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Merge tag 'pinctrl-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[linux-2.6-block.git] / drivers / pinctrl / mvebu / pinctrl-armada-37xx.c
CommitLineData
87466ccd
GC		 1/*
2 * Marvell 37xx SoC pinctrl driver
3 *
4 * Copyright (C) 2017 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
11 */
12
5715092a 13#include <linux/gpio/driver.h>
87466ccd
GC		 14#include <linux/mfd/syscon.h>
15#include <linux/of.h>
4316397c 16#include <linux/of_irq.h>
87466ccd
GC		 17#include <linux/pinctrl/pinconf-generic.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/platform_device.h>
2954ce1e 22#include <linux/property.h>
87466ccd 23#include <linux/regmap.h>
dccdc091 24#include <linux/seq_file.h>
87466ccd 25#include <linux/slab.h>
b32b195d 26#include <linux/string_helpers.h>
87466ccd
GC		 27
28#include "../pinctrl-utils.h"
29
30#define OUTPUT_EN 0x0
5715092a
GC		 31#define INPUT_VAL 0x10
32#define OUTPUT_VAL 0x18
87466ccd
GC		 33#define OUTPUT_CTL 0x20
34#define SELECTION 0x30
35
2f227605
GC		 36#define IRQ_EN 0x0
37#define IRQ_POL 0x08
38#define IRQ_STATUS 0x10
39#define IRQ_WKUP 0x18
40
9ac6e7cc 41#define NB_FUNCS 3
87466ccd
GC		 42#define GPIO_PER_REG 32
43
44/**
45 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
46 * The pins of a pinmux groups are composed of one or two groups of contiguous
47 * pins.
48 * @name: Name of the pin group, used to lookup the group.
192b752e 49 * @start_pin: Index of the first pin of the main range of pins belonging to
87466ccd
GC		 50 * the group
51 * @npins: Number of pins included in the first range
52 * @reg_mask: Bit mask matching the group in the selection register
192b752e
LJ		 53 * @val: Value to write to the registers for a given function
54 * @extra_pin: Index of the first pin of the optional second range of pins
87466ccd 55 * belonging to the group
192b752e 56 * @extra_npins:Number of pins included in the second optional range
87466ccd
GC		 57 * @funcs: A list of pinmux functions that can be selected for this group.
58 * @pins: List of the pins included in the group
59 */
60struct armada_37xx_pin_group {
61 const char *name;
62 unsigned int start_pin;
63 unsigned int npins;
64 u32 reg_mask;
65 u32 val[NB_FUNCS];
66 unsigned int extra_pin;
67 unsigned int extra_npins;
68 const char *funcs[NB_FUNCS];
69 unsigned int *pins;
70};
71
72struct armada_37xx_pin_data {
73 u8 nr_pins;
74 char *name;
75 struct armada_37xx_pin_group *groups;
76 int ngroups;
77};
78
79struct armada_37xx_pmx_func {
80 const char *name;
81 const char **groups;
82 unsigned int ngroups;
83};
84
6a230edd
MR		 85struct armada_37xx_pm_state {
86 u32 out_en_l;
87 u32 out_en_h;
88 u32 out_val_l;
89 u32 out_val_h;
90 u32 irq_en_l;
91 u32 irq_en_h;
92 u32 irq_pol_l;
93 u32 irq_pol_h;
94 u32 selection;
95};
96
87466ccd
GC		 97struct armada_37xx_pinctrl {
98 struct regmap *regmap;
2f227605 99 void __iomem *base;
87466ccd
GC		 100 const struct armada_37xx_pin_data *data;
101 struct device *dev;
5715092a 102 struct gpio_chip gpio_chip;
984245b6 103 raw_spinlock_t irq_lock;
87466ccd
GC		 104 struct pinctrl_desc pctl;
105 struct pinctrl_dev *pctl_dev;
106 struct armada_37xx_pin_group *groups;
107 unsigned int ngroups;
108 struct armada_37xx_pmx_func *funcs;
109 unsigned int nfuncs;
6a230edd 110 struct armada_37xx_pm_state pm;
87466ccd
GC		 111};
112
0ca6e30e
PR		 113#define PIN_GRP_GPIO_0(_name, _start, _nr) \
114 { \
115 .name = _name, \
116 .start_pin = _start, \
117 .npins = _nr, \
118 .reg_mask = 0, \
119 .val = {0}, \
120 .funcs = {"gpio"} \
121 }
122
87466ccd
GC		 123#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
124 { \
125 .name = _name, \
126 .start_pin = _start, \
127 .npins = _nr, \
128 .reg_mask = _mask, \
129 .val = {0, _mask}, \
130 .funcs = {_func1, "gpio"} \
131 }
132
133#define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
134 { \
135 .name = _name, \
136 .start_pin = _start, \
137 .npins = _nr, \
138 .reg_mask = _mask, \
139 .val = {_val1, _val2}, \
140 .funcs = {_func1, "gpio"} \
141 }
142
9ac6e7cc
GC		 143#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
144 { \
145 .name = _name, \
146 .start_pin = _start, \
147 .npins = _nr, \
148 .reg_mask = _mask, \
149 .val = {_v1, _v2, _v3}, \
150 .funcs = {_f1, _f2, "gpio"} \
151 }
152
87466ccd
GC		 153#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
154 _f1, _f2) \
155 { \
156 .name = _name, \
157 .start_pin = _start, \
158 .npins = _nr, \
159 .reg_mask = _mask, \
160 .val = {_v1, _v2}, \
161 .extra_pin = _start2, \
162 .extra_npins = _nr2, \
163 .funcs = {_f1, _f2} \
164 }
165
166static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
167 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
168 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
169 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
baf8d689
MB		 170 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
171 "pwm", "led"),
172 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
173 "pwm", "led"),
174 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
175 "pwm", "led"),
176 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
177 "pwm", "led"),
823868fc
MB		 178 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
179 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
0ca6e30e 180 PIN_GRP_GPIO_0("gpio1_5", 5, 1),
87466ccd
GC		 181 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
182 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
183 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
184 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
185 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
186 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
187 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
188 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
ce8a4a38
KM		 189 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
190 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
191 18, 2, "gpio", "uart"),
87466ccd
GC		 192};
193
194static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
195 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
196 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
0ca6e30e 197 PIN_GRP_GPIO_0("gpio2_2", 2, 1),
8137f78a 198 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
9ac6e7cc 199 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
823868fc 200 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
0c0a41fb 201 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
823868fc 202 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
4d98fbaa 203 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
2fa9933d
PR		 204 PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"),
205 PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12),
206 "ptp", "mii"),
207 PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13),
208 "ptp", "mii"),
9ac6e7cc
GC		 209 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
210 "mii", "mii_err"),
87466ccd
GC		 211};
212
aea1dd4b 213static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
87466ccd
GC		 214 .nr_pins = 36,
215 .name = "GPIO1",
216 .groups = armada_37xx_nb_groups,
217 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
218};
219
aea1dd4b 220static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
6b67c390 221 .nr_pins = 30,
87466ccd
GC		 222 .name = "GPIO2",
223 .groups = armada_37xx_sb_groups,
224 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
225};
226
5715092a 227static inline void armada_37xx_update_reg(unsigned int *reg,
20504fa1 228 unsigned int *offset)
5715092a
GC		 229{
230 /* We never have more than 2 registers */
20504fa1
PW		 231 if (*offset >= GPIO_PER_REG) {
232 *offset -= GPIO_PER_REG;
5715092a
GC		 233 *reg += sizeof(u32);
234 }
235}
236
87466ccd
GC		 237static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
238 struct armada_37xx_pinctrl *info, int pin, int *grp)
239{
240 while (*grp < info->ngroups) {
241 struct armada_37xx_pin_group *group = &info->groups[*grp];
242 int j;
243
244 *grp = *grp + 1;
245 for (j = 0; j < (group->npins + group->extra_npins); j++)
246 if (group->pins[j] == pin)
247 return group;
248 }
249 return NULL;
250}
251
252static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
253 unsigned int selector, unsigned long *config)
254{
255 return -ENOTSUPP;
256}
257
258static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
259 unsigned int selector, unsigned long *configs,
260 unsigned int num_configs)
261{
262 return -ENOTSUPP;
263}
264
9b4e2ba4 265static const struct pinconf_ops armada_37xx_pinconf_ops = {
87466ccd
GC		 266 .is_generic = true,
267 .pin_config_group_get = armada_37xx_pin_config_group_get,
268 .pin_config_group_set = armada_37xx_pin_config_group_set,
269};
270
271static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
272{
273 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
274
275 return info->ngroups;
276}
277
278static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
279 unsigned int group)
280{
281 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
282
283 return info->groups[group].name;
284}
285
286static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
287 unsigned int selector,
288 const unsigned int **pins,
289 unsigned int *npins)
290{
291 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
292
293 if (selector >= info->ngroups)
294 return -EINVAL;
295
296 *pins = info->groups[selector].pins;
297 *npins = info->groups[selector].npins +
298 info->groups[selector].extra_npins;
299
300 return 0;
301}
302
303static const struct pinctrl_ops armada_37xx_pctrl_ops = {
304 .get_groups_count = armada_37xx_get_groups_count,
305 .get_group_name = armada_37xx_get_group_name,
306 .get_group_pins = armada_37xx_get_group_pins,
307 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
308 .dt_free_map = pinctrl_utils_free_map,
309};
310
311/*
312 * Pinmux_ops handling
313 */
314
315static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
316{
317 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
318
319 return info->nfuncs;
320}
321
322static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
323 unsigned int selector)
324{
325 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
326
327 return info->funcs[selector].name;
328}
329
330static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
331 unsigned int selector,
332 const char * const **groups,
333 unsigned int * const num_groups)
334{
335 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
336
337 *groups = info->funcs[selector].groups;
338 *num_groups = info->funcs[selector].ngroups;
339
340 return 0;
341}
342
343static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
344 const char *name,
345 struct armada_37xx_pin_group *grp)
346{
347 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
50cf2ed2 348 struct device *dev = info->dev;
87466ccd
GC		 349 unsigned int reg = SELECTION;
350 unsigned int mask = grp->reg_mask;
351 int func, val;
352
50cf2ed2 353 dev_dbg(dev, "enable function %s group %s\n", name, grp->name);
87466ccd 354
59837002 355 func = match_string(grp->funcs, NB_FUNCS, name);
87466ccd 356 if (func < 0)
59837002 357 return -ENOTSUPP;
87466ccd
GC		 358
359 val = grp->val[func];
360
361 regmap_update_bits(info->regmap, reg, mask, val);
362
363 return 0;
364}
365
366static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
367 unsigned int selector,
368 unsigned int group)
369{
370
371 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
372 struct armada_37xx_pin_group *grp = &info->groups[group];
373 const char *name = info->funcs[selector].name;
374
375 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
376}
377
2f227605
GC		 378static inline void armada_37xx_irq_update_reg(unsigned int *reg,
379 struct irq_data *d)
380{
381 int offset = irqd_to_hwirq(d);
382
20504fa1 383 armada_37xx_update_reg(reg, &offset);
2f227605
GC		 384}
385
5715092a
GC		 386static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
387 unsigned int offset)
87466ccd 388{
5715092a 389 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
87466ccd
GC		 390 unsigned int reg = OUTPUT_EN;
391 unsigned int mask;
392
20504fa1 393 armada_37xx_update_reg(&reg, &offset);
87466ccd
GC		 394 mask = BIT(offset);
395
396 return regmap_update_bits(info->regmap, reg, mask, 0);
397}
398
5715092a
GC		 399static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
400 unsigned int offset)
87466ccd 401{
5715092a
GC		 402 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
403 unsigned int reg = OUTPUT_EN;
404 unsigned int val, mask;
405
20504fa1 406 armada_37xx_update_reg(&reg, &offset);
5715092a
GC		 407 mask = BIT(offset);
408 regmap_read(info->regmap, reg, &val);
409
3c827873
MV		 410 if (val & mask)
411 return GPIO_LINE_DIRECTION_OUT;
412
413 return GPIO_LINE_DIRECTION_IN;
5715092a
GC		 414}
415
416static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
417 unsigned int offset, int value)
418{
419 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
87466ccd 420 unsigned int reg = OUTPUT_EN;
6702abb3 421 unsigned int mask, val, ret;
87466ccd 422
20504fa1 423 armada_37xx_update_reg(&reg, &offset);
87466ccd
GC		 424 mask = BIT(offset);
425
6702abb3
GC		 426 ret = regmap_update_bits(info->regmap, reg, mask, mask);
427
428 if (ret)
429 return ret;
430
431 reg = OUTPUT_VAL;
432 val = value ? mask : 0;
433 regmap_update_bits(info->regmap, reg, mask, val);
434
435 return 0;
87466ccd
GC		 436}
437
5715092a
GC		 438static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
439{
440 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
441 unsigned int reg = INPUT_VAL;
442 unsigned int val, mask;
443
20504fa1 444 armada_37xx_update_reg(&reg, &offset);
5715092a
GC		 445 mask = BIT(offset);
446
447 regmap_read(info->regmap, reg, &val);
448
449 return (val & mask) != 0;
450}
451
452static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
453 int value)
454{
455 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
456 unsigned int reg = OUTPUT_VAL;
457 unsigned int mask, val;
458
20504fa1 459 armada_37xx_update_reg(&reg, &offset);
5715092a
GC		 460 mask = BIT(offset);
461 val = value ? mask : 0;
462
463 regmap_update_bits(info->regmap, reg, mask, val);
464}
465
87466ccd
GC		 466static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
467 struct pinctrl_gpio_range *range,
468 unsigned int offset, bool input)
469{
470 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
5715092a 471 struct gpio_chip *chip = range->gc;
87466ccd
GC		 472
473 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
474 offset, range->name, offset, input ? "input" : "output");
475
476 if (input)
5715092a 477 armada_37xx_gpio_direction_input(chip, offset);
87466ccd 478 else
5715092a 479 armada_37xx_gpio_direction_output(chip, offset, 0);
87466ccd
GC		 480
481 return 0;
482}
483
484static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
485 struct pinctrl_gpio_range *range,
486 unsigned int offset)
487{
488 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
489 struct armada_37xx_pin_group *group;
490 int grp = 0;
6b262b32 491 int ret;
87466ccd
GC		 492
493 dev_dbg(info->dev, "requesting gpio %d\n", offset);
494
6b262b32
PR		 495 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) {
496 ret = armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
497 if (ret)
498 return ret;
499 }
87466ccd
GC		 500
501 return 0;
502}
503
504static const struct pinmux_ops armada_37xx_pmx_ops = {
505 .get_functions_count = armada_37xx_pmx_get_funcs_count,
506 .get_function_name = armada_37xx_pmx_get_func_name,
507 .get_function_groups = armada_37xx_pmx_get_groups,
508 .set_mux = armada_37xx_pmx_set,
509 .gpio_request_enable = armada_37xx_gpio_request_enable,
510 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
511};
512
5715092a
GC		 513static const struct gpio_chip armada_37xx_gpiolib_chip = {
514 .request = gpiochip_generic_request,
515 .free = gpiochip_generic_free,
516 .set = armada_37xx_gpio_set,
517 .get = armada_37xx_gpio_get,
518 .get_direction = armada_37xx_gpio_get_direction,
519 .direction_input = armada_37xx_gpio_direction_input,
520 .direction_output = armada_37xx_gpio_direction_output,
521 .owner = THIS_MODULE,
522};
523
2f227605
GC		 524static void armada_37xx_irq_ack(struct irq_data *d)
525{
526 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
527 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
528 u32 reg = IRQ_STATUS;
529 unsigned long flags;
530
531 armada_37xx_irq_update_reg(&reg, d);
984245b6 532 raw_spin_lock_irqsave(&info->irq_lock, flags);
2f227605 533 writel(d->mask, info->base + reg);
984245b6 534 raw_spin_unlock_irqrestore(&info->irq_lock, flags);
2f227605
GC		 535}
536
537static void armada_37xx_irq_mask(struct irq_data *d)
538{
539 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
540 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
541 u32 val, reg = IRQ_EN;
542 unsigned long flags;
543
544 armada_37xx_irq_update_reg(&reg, d);
984245b6 545 raw_spin_lock_irqsave(&info->irq_lock, flags);
2f227605
GC		 546 val = readl(info->base + reg);
547 writel(val & ~d->mask, info->base + reg);
984245b6 548 raw_spin_unlock_irqrestore(&info->irq_lock, flags);
dccdc091 549 gpiochip_disable_irq(chip, irqd_to_hwirq(d));
2f227605
GC		 550}
551
552static void armada_37xx_irq_unmask(struct irq_data *d)
553{
554 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
555 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
556 u32 val, reg = IRQ_EN;
557 unsigned long flags;
558
dccdc091 559 gpiochip_enable_irq(chip, irqd_to_hwirq(d));
2f227605 560 armada_37xx_irq_update_reg(&reg, d);
984245b6 561 raw_spin_lock_irqsave(&info->irq_lock, flags);
2f227605
GC		 562 val = readl(info->base + reg);
563 writel(val | d->mask, info->base + reg);
984245b6 564 raw_spin_unlock_irqrestore(&info->irq_lock, flags);
2f227605
GC		 565}
566
567static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
568{
569 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
570 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
571 u32 val, reg = IRQ_WKUP;
572 unsigned long flags;
573
574 armada_37xx_irq_update_reg(&reg, d);
984245b6 575 raw_spin_lock_irqsave(&info->irq_lock, flags);
2f227605
GC		 576 val = readl(info->base + reg);
577 if (on)
a9a1a483 578 val |= (BIT(d->hwirq % GPIO_PER_REG));
2f227605 579 else
a9a1a483 580 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
2f227605 581 writel(val, info->base + reg);
984245b6 582 raw_spin_unlock_irqrestore(&info->irq_lock, flags);
2f227605
GC		 583
584 return 0;
585}
586
587static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
588{
589 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
590 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
591 u32 val, reg = IRQ_POL;
592 unsigned long flags;
593
984245b6 594 raw_spin_lock_irqsave(&info->irq_lock, flags);
2f227605
GC		 595 armada_37xx_irq_update_reg(&reg, d);
596 val = readl(info->base + reg);
597 switch (type) {
598 case IRQ_TYPE_EDGE_RISING:
a9a1a483 599 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
2f227605
GC		 600 break;
601 case IRQ_TYPE_EDGE_FALLING:
a9a1a483 602 val |= (BIT(d->hwirq % GPIO_PER_REG));
2f227605 603 break;
30ac0d3b
KM		 604 case IRQ_TYPE_EDGE_BOTH: {
605 u32 in_val, in_reg = INPUT_VAL;
606
607 armada_37xx_irq_update_reg(&in_reg, d);
608 regmap_read(info->regmap, in_reg, &in_val);
609
610 /* Set initial polarity based on current input level. */
04fb0275
GC		 611 if (in_val & BIT(d->hwirq % GPIO_PER_REG))
612 val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */
30ac0d3b 613 else
04fb0275 614 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
30ac0d3b
KM		 615 break;
616 }
2f227605 617 default:
984245b6 618 raw_spin_unlock_irqrestore(&info->irq_lock, flags);
2f227605
GC		 619 return -EINVAL;
620 }
621 writel(val, info->base + reg);
984245b6 622 raw_spin_unlock_irqrestore(&info->irq_lock, flags);
2f227605
GC		 623
624 return 0;
625}
626
30ac0d3b
KM		 627static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
628 u32 pin_idx)
629{
630 u32 reg_idx = pin_idx / GPIO_PER_REG;
631 u32 bit_num = pin_idx % GPIO_PER_REG;
632 u32 p, l, ret;
633 unsigned long flags;
634
635 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
636
984245b6 637 raw_spin_lock_irqsave(&info->irq_lock, flags);
30ac0d3b
KM		 638 p = readl(info->base + IRQ_POL + 4 * reg_idx);
639 if ((p ^ l) & (1 << bit_num)) {
640 /*
641 * For the gpios which are used for both-edge irqs, when their
642 * interrupts happen, their input levels are changed,
643 * yet their interrupt polarities are kept in old values, we
644 * should synchronize their interrupt polarities; for example,
645 * at first a gpio's input level is low and its interrupt
646 * polarity control is "Detect rising edge", then the gpio has
647 * a interrupt , its level turns to high, we should change its
648 * polarity control to "Detect falling edge" correspondingly.
649 */
650 p ^= 1 << bit_num;
651 writel(p, info->base + IRQ_POL + 4 * reg_idx);
652 ret = 0;
653 } else {
654 /* Spurious irq */
655 ret = -1;
656 }
657
984245b6 658 raw_spin_unlock_irqrestore(&info->irq_lock, flags);
30ac0d3b
KM		 659 return ret;
660}
2f227605
GC		 661
662static void armada_37xx_irq_handler(struct irq_desc *desc)
663{
664 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
665 struct irq_chip *chip = irq_desc_get_chip(desc);
666 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
f0fbe7bc 667 struct irq_domain *d = gc->irq.domain;
2f227605
GC		 668 int i;
669
670 chained_irq_enter(chip, desc);
671 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
672 u32 status;
673 unsigned long flags;
674
984245b6 675 raw_spin_lock_irqsave(&info->irq_lock, flags);
2f227605
GC		 676 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
677 /* Manage only the interrupt that was enabled */
678 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
984245b6 679 raw_spin_unlock_irqrestore(&info->irq_lock, flags);
2f227605
GC		 680 while (status) {
681 u32 hwirq = ffs(status) - 1;
682 u32 virq = irq_find_mapping(d, hwirq +
683 i * GPIO_PER_REG);
30ac0d3b
KM		 684 u32 t = irq_get_trigger_type(virq);
685
686 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
687 /* Swap polarity (race with GPIO line) */
688 if (armada_37xx_edge_both_irq_swap_pol(info,
689 hwirq + i * GPIO_PER_REG)) {
690 /*
691 * For spurious irq, which gpio level
692 * is not as expected after incoming
693 * edge, just ack the gpio irq.
694 */
695 writel(1 << hwirq,
696 info->base +
697 IRQ_STATUS + 4 * i);
702d1e81 698 goto update_status;
30ac0d3b
KM		 699 }
700 }
2f227605
GC		 701
702 generic_handle_irq(virq);
703
702d1e81 704update_status:
2f227605 705 /* Update status in case a new IRQ appears */
984245b6 706 raw_spin_lock_irqsave(&info->irq_lock, flags);
2f227605
GC		 707 status = readl_relaxed(info->base +
708 IRQ_STATUS + 4 * i);
709 /* Manage only the interrupt that was enabled */
710 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
984245b6 711 raw_spin_unlock_irqrestore(&info->irq_lock, flags);
2f227605
GC		 712 }
713 }
714 chained_irq_exit(chip, desc);
715}
716
a9a1a483
GC		 717static unsigned int armada_37xx_irq_startup(struct irq_data *d)
718{
a9a1a483
GC		 719 /*
720 * The mask field is a "precomputed bitmask for accessing the
721 * chip registers" which was introduced for the generic
722 * irqchip framework. As we don't use this framework, we can
723 * reuse this field for our own usage.
724 */
3ee9e605 725 d->mask = BIT(d->hwirq % GPIO_PER_REG);
a9a1a483
GC		 726
727 armada_37xx_irq_unmask(d);
728
729 return 0;
730}
731
dccdc091
LW		 732static void armada_37xx_irq_print_chip(struct irq_data *d, struct seq_file *p)
733{
734 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
735 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
736
737 seq_printf(p, info->data->name);
738}
739
740static const struct irq_chip armada_37xx_irqchip = {
741 .irq_ack = armada_37xx_irq_ack,
742 .irq_mask = armada_37xx_irq_mask,
743 .irq_unmask = armada_37xx_irq_unmask,
744 .irq_set_wake = armada_37xx_irq_set_wake,
745 .irq_set_type = armada_37xx_irq_set_type,
746 .irq_startup = armada_37xx_irq_startup,
747 .irq_print_chip = armada_37xx_irq_print_chip,
748 .flags = IRQCHIP_IMMUTABLE,
749 GPIOCHIP_IRQ_RESOURCE_HELPERS,
750};
751
2f227605
GC		 752static int armada_37xx_irqchip_register(struct platform_device *pdev,
753 struct armada_37xx_pinctrl *info)
754{
2f227605 755 struct gpio_chip *gc = &info->gpio_chip;
2851ef52 756 struct gpio_irq_chip *girq = &gc->irq;
46d34d4d 757 struct device_node *np = to_of_node(gc->fwnode);
2851ef52 758 struct device *dev = &pdev->dev;
46d34d4d 759 unsigned int i, nr_irq_parent;
2f227605 760
984245b6 761 raw_spin_lock_init(&info->irq_lock);
2f227605 762
46d34d4d 763 nr_irq_parent = of_irq_count(np);
2f227605 764 if (!nr_irq_parent) {
2851ef52 765 dev_err(dev, "invalid or no IRQ\n");
2f227605
GC		 766 return 0;
767 }
768
49bdef50 769 info->base = devm_platform_ioremap_resource(pdev, 1);
2f227605
GC		 770 if (IS_ERR(info->base))
771 return PTR_ERR(info->base);
772
dccdc091 773 gpio_irq_chip_set_chip(girq, &armada_37xx_irqchip);
2851ef52 774 girq->parent_handler = armada_37xx_irq_handler;
2f227605
GC		 775 /*
776 * Many interrupts are connected to the parent interrupt
777 * controller. But we do not take advantage of this and use
778 * the chained irq with all of them.
779 */
2851ef52 780 girq->num_parents = nr_irq_parent;
50cf2ed2 781 girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL);
2851ef52
LW		 782 if (!girq->parents)
783 return -ENOMEM;
2f227605 784 for (i = 0; i < nr_irq_parent; i++) {
4316397c 785 int irq = irq_of_parse_and_map(np, i);
2f227605 786
71bc7cf3 787 if (!irq)
2f227605 788 continue;
2851ef52 789 girq->parents[i] = irq;
2f227605 790 }
2851ef52
LW		 791 girq->default_type = IRQ_TYPE_NONE;
792 girq->handler = handle_edge_irq;
2f227605
GC		 793
794 return 0;
795}
796
5715092a
GC		 797static int armada_37xx_gpiochip_register(struct platform_device *pdev,
798 struct armada_37xx_pinctrl *info)
799{
50cf2ed2 800 struct device *dev = &pdev->dev;
2954ce1e 801 struct fwnode_handle *fwnode;
5715092a 802 struct gpio_chip *gc;
2954ce1e 803 int ret;
5715092a 804
2954ce1e
AS		 805 fwnode = gpiochip_node_get_first(dev);
806 if (!fwnode)
807 return -ENODEV;
5715092a
GC		 808
809 info->gpio_chip = armada_37xx_gpiolib_chip;
810
811 gc = &info->gpio_chip;
812 gc->ngpio = info->data->nr_pins;
50cf2ed2 813 gc->parent = dev;
5715092a 814 gc->base = -1;
2954ce1e 815 gc->fwnode = fwnode;
5715092a
GC		 816 gc->label = info->data->name;
817
2851ef52 818 ret = armada_37xx_irqchip_register(pdev, info);
5715092a
GC		 819 if (ret)
820 return ret;
821
50cf2ed2 822 return devm_gpiochip_add_data(dev, gc, info);
5715092a
GC		 823}
824
87466ccd
GC		 825/**
826 * armada_37xx_add_function() - Add a new function to the list
827 * @funcs: array of function to add the new one
828 * @funcsize: size of the remaining space for the function
829 * @name: name of the function to add
830 *
831 * If it is a new function then create it by adding its name else
832 * increment the number of group associated to this function.
833 */
834static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
835 int *funcsize, const char *name)
836{
87466ccd
GC		 837 if (*funcsize <= 0)
838 return -EOVERFLOW;
839
840 while (funcs->ngroups) {
841 /* function already there */
842 if (strcmp(funcs->name, name) == 0) {
843 funcs->ngroups++;
844
845 return -EEXIST;
846 }
847 funcs++;
87466ccd
GC		 848 }
849
850 /* append new unique function */
851 funcs->name = name;
852 funcs->ngroups = 1;
853 (*funcsize)--;
854
855 return 0;
856}
857
858/**
859 * armada_37xx_fill_group() - complete the group array
860 * @info: info driver instance
861 *
862 * Based on the data available from the armada_37xx_pin_group array
863 * completes the last member of the struct for each function: the list
864 * of the groups associated to this function.
865 *
866 */
867static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
868{
869 int n, num = 0, funcsize = info->data->nr_pins;
50cf2ed2 870 struct device *dev = info->dev;
87466ccd
GC		 871
872 for (n = 0; n < info->ngroups; n++) {
873 struct armada_37xx_pin_group *grp = &info->groups[n];
874 int i, j, f;
875
50cf2ed2 876 grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins,
a86854d0
KC		 877 sizeof(*grp->pins),
878 GFP_KERNEL);
87466ccd
GC		 879 if (!grp->pins)
880 return -ENOMEM;
881
882 for (i = 0; i < grp->npins; i++)
883 grp->pins[i] = grp->start_pin + i;
884
885 for (j = 0; j < grp->extra_npins; j++)
886 grp->pins[i+j] = grp->extra_pin + j;
887
9ac6e7cc 888 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
87466ccd
GC		 889 int ret;
890 /* check for unique functions and count groups */
891 ret = armada_37xx_add_function(info->funcs, &funcsize,
892 grp->funcs[f]);
893 if (ret == -EOVERFLOW)
50cf2ed2 894 dev_err(dev, "More functions than pins(%d)\n",
87466ccd
GC		 895 info->data->nr_pins);
896 if (ret < 0)
897 continue;
898 num++;
899 }
900 }
901
902 info->nfuncs = num;
903
904 return 0;
905}
906
907/**
a6d93da4 908 * armada_37xx_fill_func() - complete the funcs array
87466ccd
GC		 909 * @info: info driver instance
910 *
911 * Based on the data available from the armada_37xx_pin_group array
912 * completes the last two member of the struct for each group:
913 * - the list of the pins included in the group
914 * - the list of pinmux functions that can be selected for this group
915 *
916 */
917static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
918{
919 struct armada_37xx_pmx_func *funcs = info->funcs;
50cf2ed2 920 struct device *dev = info->dev;
87466ccd
GC		 921 int n;
922
923 for (n = 0; n < info->nfuncs; n++) {
924 const char *name = funcs[n].name;
925 const char **groups;
926 int g;
927
50cf2ed2 928 funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups,
87466ccd
GC		 929 sizeof(*(funcs[n].groups)),
930 GFP_KERNEL);
931 if (!funcs[n].groups)
932 return -ENOMEM;
933
934 groups = funcs[n].groups;
935
936 for (g = 0; g < info->ngroups; g++) {
937 struct armada_37xx_pin_group *gp = &info->groups[g];
938 int f;
939
59837002
AS		 940 f = match_string(gp->funcs, NB_FUNCS, name);
941 if (f < 0)
942 continue;
943
944 *groups = gp->name;
945 groups++;
87466ccd
GC		 946 }
947 }
948 return 0;
949}
950
951static int armada_37xx_pinctrl_register(struct platform_device *pdev,
952 struct armada_37xx_pinctrl *info)
953{
954 const struct armada_37xx_pin_data *pin_data = info->data;
955 struct pinctrl_desc *ctrldesc = &info->pctl;
956 struct pinctrl_pin_desc *pindesc, *pdesc;
50cf2ed2 957 struct device *dev = &pdev->dev;
b32b195d 958 char **pin_names;
87466ccd
GC		 959 int pin, ret;
960
961 info->groups = pin_data->groups;
962 info->ngroups = pin_data->ngroups;
963
964 ctrldesc->name = "armada_37xx-pinctrl";
965 ctrldesc->owner = THIS_MODULE;
966 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
967 ctrldesc->pmxops = &armada_37xx_pmx_ops;
968 ctrldesc->confops = &armada_37xx_pinconf_ops;
969
50cf2ed2 970 pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL);
87466ccd
GC		 971 if (!pindesc)
972 return -ENOMEM;
973
974 ctrldesc->pins = pindesc;
975 ctrldesc->npins = pin_data->nr_pins;
976
b32b195d
AS		 977 pin_names = devm_kasprintf_strarray(dev, pin_data->name, pin_data->nr_pins);
978 if (IS_ERR(pin_names))
979 return PTR_ERR(pin_names);
980
87466ccd
GC		 981 pdesc = pindesc;
982 for (pin = 0; pin < pin_data->nr_pins; pin++) {
983 pdesc->number = pin;
b32b195d 984 pdesc->name = pin_names[pin];
87466ccd
GC		 985 pdesc++;
986 }
987
988 /*
989 * we allocate functions for number of pins and hope there are
990 * fewer unique functions than pins available
991 */
50cf2ed2 992 info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL);
87466ccd
GC		 993 if (!info->funcs)
994 return -ENOMEM;
995
87466ccd
GC		 996 ret = armada_37xx_fill_group(info);
997 if (ret)
998 return ret;
999
1000 ret = armada_37xx_fill_func(info);
1001 if (ret)
1002 return ret;
1003
50cf2ed2 1004 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
06cb10ea
AS		 1005 if (IS_ERR(info->pctl_dev))
1006 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
87466ccd
GC		 1007
1008 return 0;
1009}
1010
6a230edd
MR		 1011static int armada_3700_pinctrl_suspend(struct device *dev)
1012{
1013 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1014
1015 /* Save GPIO state */
1016 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
1017 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
1018 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
1019 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
1020 &info->pm.out_val_h);
1021
1022 info->pm.irq_en_l = readl(info->base + IRQ_EN);
1023 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
1024 info->pm.irq_pol_l = readl(info->base + IRQ_POL);
1025 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
1026
1027 /* Save pinctrl state */
1028 regmap_read(info->regmap, SELECTION, &info->pm.selection);
1029
1030 return 0;
1031}
1032
1033static int armada_3700_pinctrl_resume(struct device *dev)
1034{
1035 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1036 struct gpio_chip *gc;
1037 struct irq_domain *d;
1038 int i;
1039
1040 /* Restore GPIO state */
1041 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
1042 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
1043 info->pm.out_en_h);
1044 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
1045 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
1046 info->pm.out_val_h);
1047
1048 /*
1049 * Input levels may change during suspend, which is not monitored at
1050 * that time. GPIOs used for both-edge IRQs may not be synchronized
1051 * anymore with their polarities (rising/falling edge) and must be
1052 * re-configured manually.
1053 */
1054 gc = &info->gpio_chip;
1055 d = gc->irq.domain;
1056 for (i = 0; i < gc->ngpio; i++) {
1057 u32 irq_bit = BIT(i % GPIO_PER_REG);
1058 u32 mask, *irq_pol, input_reg, virq, type, level;
1059
1060 if (i < GPIO_PER_REG) {
1061 mask = info->pm.irq_en_l;
1062 irq_pol = &info->pm.irq_pol_l;
1063 input_reg = INPUT_VAL;
1064 } else {
1065 mask = info->pm.irq_en_h;
1066 irq_pol = &info->pm.irq_pol_h;
1067 input_reg = INPUT_VAL + sizeof(u32);
1068 }
1069
1070 if (!(mask & irq_bit))
1071 continue;
1072
1073 virq = irq_find_mapping(d, i);
1074 type = irq_get_trigger_type(virq);
1075
1076 /*
1077 * Synchronize level and polarity for both-edge irqs:
1078 * - a high input level expects a falling edge,
1079 * - a low input level exepects a rising edge.
1080 */
1081 if ((type & IRQ_TYPE_SENSE_MASK) ==
1082 IRQ_TYPE_EDGE_BOTH) {
1083 regmap_read(info->regmap, input_reg, &level);
1084 if ((*irq_pol ^ level) & irq_bit)
1085 *irq_pol ^= irq_bit;
1086 }
1087 }
1088
1089 writel(info->pm.irq_en_l, info->base + IRQ_EN);
1090 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
1091 writel(info->pm.irq_pol_l, info->base + IRQ_POL);
1092 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
1093
1094 /* Restore pinctrl state */
1095 regmap_write(info->regmap, SELECTION, info->pm.selection);
1096
1097 return 0;
1098}
1099
1100/*
1101 * Since pinctrl is an infrastructure module, its resume should be issued prior
1102 * to other IO drivers.
1103 */
c9008b71
AS		 1104static DEFINE_NOIRQ_DEV_PM_OPS(armada_3700_pinctrl_pm_ops,
1105 armada_3700_pinctrl_suspend, armada_3700_pinctrl_resume);
6a230edd 1106
87466ccd
GC		 1107static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1108 {
1109 .compatible = "marvell,armada3710-sb-pinctrl",
924f5494 1110 .data = &armada_37xx_pin_sb,
87466ccd
GC		 1111 },
1112 {
1113 .compatible = "marvell,armada3710-nb-pinctrl",
924f5494 1114 .data = &armada_37xx_pin_nb,
87466ccd
GC		 1115 },
1116 { },
1117};
1118
45467606
VO		 1119static const struct regmap_config armada_37xx_pinctrl_regmap_config = {
1120 .reg_bits = 32,
1121 .val_bits = 32,
1122 .reg_stride = 4,
1123 .use_raw_spinlock = true,
1124};
1125
87466ccd
GC		 1126static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1127{
1128 struct armada_37xx_pinctrl *info;
1129 struct device *dev = &pdev->dev;
87466ccd 1130 struct regmap *regmap;
45467606 1131 void __iomem *base;
87466ccd
GC		 1132 int ret;
1133
45467606
VO		 1134 base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1135 if (IS_ERR(base)) {
1136 dev_err(dev, "failed to ioremap base address: %pe\n", base);
1137 return PTR_ERR(base);
1138 }
1139
1140 regmap = devm_regmap_init_mmio(dev, base,
1141 &armada_37xx_pinctrl_regmap_config);
1142 if (IS_ERR(regmap)) {
1143 dev_err(dev, "failed to create regmap: %pe\n", regmap);
1144 return PTR_ERR(regmap);
1145 }
1146
50cf2ed2 1147 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
87466ccd
GC		 1148 if (!info)
1149 return -ENOMEM;
1150
1151 info->dev = dev;
87466ccd 1152 info->regmap = regmap;
87466ccd
GC		 1153 info->data = of_device_get_match_data(dev);
1154
1155 ret = armada_37xx_pinctrl_register(pdev, info);
1156 if (ret)
1157 return ret;
1158
5715092a
GC		 1159 ret = armada_37xx_gpiochip_register(pdev, info);
1160 if (ret)
1161 return ret;
1162
87466ccd
GC		 1163 platform_set_drvdata(pdev, info);
1164
1165 return 0;
1166}
1167
1168static struct platform_driver armada_37xx_pinctrl_driver = {
1169 .driver = {
1170 .name = "armada-37xx-pinctrl",
1171 .of_match_table = armada_37xx_pinctrl_of_match,
c9008b71 1172 .pm = pm_sleep_ptr(&armada_3700_pinctrl_pm_ops),
87466ccd
GC		 1173 },
1174};
1175
1176builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1177 armada_37xx_pinctrl_probe);
Linux 6.x block layer and io_uring tree(s)