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6ac73095 BG |
1 | /* |
2 | * Pin controller and GPIO driver for Amlogic Meson SoCs | |
3 | * | |
4 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * You should have received a copy of the GNU General Public License | |
11 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
12 | */ | |
13 | ||
1c5fb66a | 14 | #include <linux/gpio/driver.h> |
6ac73095 | 15 | #include <linux/pinctrl/pinctrl.h> |
277d14eb | 16 | #include <linux/platform_device.h> |
6ac73095 BG |
17 | #include <linux/regmap.h> |
18 | #include <linux/types.h> | |
19 | ||
20 | /** | |
21 | * struct meson_pmx_group - a pinmux group | |
22 | * | |
23 | * @name: group name | |
24 | * @pins: pins in the group | |
25 | * @num_pins: number of pins in the group | |
26 | * @is_gpio: whether the group is a single GPIO group | |
27 | * @reg: register offset for the group in the domain mux registers | |
28 | * @bit bit index enabling the group | |
29 | * @domain: index of the domain this group belongs to | |
30 | */ | |
31 | struct meson_pmx_group { | |
32 | const char *name; | |
33 | const unsigned int *pins; | |
34 | unsigned int num_pins; | |
ce385aa2 | 35 | const void *data; |
6ac73095 BG |
36 | }; |
37 | ||
38 | /** | |
39 | * struct meson_pmx_func - a pinmux function | |
40 | * | |
41 | * @name: function name | |
42 | * @groups: groups in the function | |
43 | * @num_groups: number of groups in the function | |
44 | */ | |
45 | struct meson_pmx_func { | |
46 | const char *name; | |
47 | const char * const *groups; | |
48 | unsigned int num_groups; | |
49 | }; | |
50 | ||
51 | /** | |
52 | * struct meson_reg_desc - a register descriptor | |
53 | * | |
54 | * @reg: register offset in the regmap | |
55 | * @bit: bit index in register | |
56 | * | |
57 | * The structure describes the information needed to control pull, | |
58 | * pull-enable, direction, etc. for a single pin | |
59 | */ | |
60 | struct meson_reg_desc { | |
61 | unsigned int reg; | |
62 | unsigned int bit; | |
63 | }; | |
64 | ||
65 | /** | |
66 | * enum meson_reg_type - type of registers encoded in @meson_reg_desc | |
67 | */ | |
68 | enum meson_reg_type { | |
69 | REG_PULLEN, | |
70 | REG_PULL, | |
71 | REG_DIR, | |
72 | REG_OUT, | |
73 | REG_IN, | |
74 | NUM_REG, | |
75 | }; | |
76 | ||
77 | /** | |
78 | * struct meson bank | |
79 | * | |
80 | * @name: bank name | |
81 | * @first: first pin of the bank | |
82 | * @last: last pin of the bank | |
6c9dc843 | 83 | * @irq: hwirq base number of the bank |
6ac73095 BG |
84 | * @regs: array of register descriptors |
85 | * | |
86 | * A bank represents a set of pins controlled by a contiguous set of | |
87 | * bits in the domain registers. The structure specifies which bits in | |
88 | * the regmap control the different functionalities. Each member of | |
89 | * the @regs array refers to the first pin of the bank. | |
90 | */ | |
91 | struct meson_bank { | |
92 | const char *name; | |
93 | unsigned int first; | |
94 | unsigned int last; | |
6c9dc843 JB |
95 | int irq_first; |
96 | int irq_last; | |
6ac73095 BG |
97 | struct meson_reg_desc regs[NUM_REG]; |
98 | }; | |
99 | ||
6ac73095 | 100 | struct meson_pinctrl_data { |
db80f0e1 | 101 | const char *name; |
6ac73095 BG |
102 | const struct pinctrl_pin_desc *pins; |
103 | struct meson_pmx_group *groups; | |
104 | struct meson_pmx_func *funcs; | |
6ac73095 BG |
105 | unsigned int num_pins; |
106 | unsigned int num_groups; | |
107 | unsigned int num_funcs; | |
db80f0e1 BG |
108 | struct meson_bank *banks; |
109 | unsigned int num_banks; | |
ce385aa2 | 110 | const struct pinmux_ops *pmx_ops; |
0fabe43f | 111 | void *pmx_data; |
6ac73095 BG |
112 | }; |
113 | ||
114 | struct meson_pinctrl { | |
115 | struct device *dev; | |
116 | struct pinctrl_dev *pcdev; | |
117 | struct pinctrl_desc desc; | |
118 | struct meson_pinctrl_data *data; | |
db80f0e1 BG |
119 | struct regmap *reg_mux; |
120 | struct regmap *reg_pullen; | |
121 | struct regmap *reg_pull; | |
122 | struct regmap *reg_gpio; | |
123 | struct gpio_chip chip; | |
124 | struct device_node *of_node; | |
6ac73095 BG |
125 | }; |
126 | ||
6ac73095 BG |
127 | #define FUNCTION(fn) \ |
128 | { \ | |
129 | .name = #fn, \ | |
130 | .groups = fn ## _groups, \ | |
131 | .num_groups = ARRAY_SIZE(fn ## _groups), \ | |
132 | } | |
133 | ||
6c9dc843 | 134 | #define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ |
6ac73095 | 135 | { \ |
6c9dc843 JB |
136 | .name = n, \ |
137 | .first = f, \ | |
138 | .last = l, \ | |
139 | .irq_first = fi, \ | |
140 | .irq_last = li, \ | |
141 | .regs = { \ | |
6ac73095 BG |
142 | [REG_PULLEN] = { per, peb }, \ |
143 | [REG_PULL] = { pr, pb }, \ | |
144 | [REG_DIR] = { dr, db }, \ | |
145 | [REG_OUT] = { or, ob }, \ | |
146 | [REG_IN] = { ir, ib }, \ | |
147 | }, \ | |
148 | } | |
149 | ||
634e40b0 | 150 | #define MESON_PIN(x) PINCTRL_PIN(x, #x) |
6ac73095 | 151 | |
ce385aa2 JB |
152 | /* Common pmx functions */ |
153 | int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev); | |
154 | const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, | |
155 | unsigned selector); | |
156 | int meson_pmx_get_groups(struct pinctrl_dev *pcdev, | |
157 | unsigned selector, | |
158 | const char * const **groups, | |
159 | unsigned * const num_groups); | |
160 | ||
277d14eb JB |
161 | /* Common probe function */ |
162 | int meson_pinctrl_probe(struct platform_device *pdev); |