Commit | Line | Data |
---|---|---|
3c910ecb | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
6ac73095 BG |
2 | /* |
3 | * Pin controller and GPIO driver for Amlogic Meson SoCs | |
4 | * | |
5 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
6ac73095 BG |
6 | */ |
7 | ||
1c5fb66a | 8 | #include <linux/gpio/driver.h> |
6ac73095 | 9 | #include <linux/pinctrl/pinctrl.h> |
277d14eb | 10 | #include <linux/platform_device.h> |
6ac73095 BG |
11 | #include <linux/regmap.h> |
12 | #include <linux/types.h> | |
13 | ||
14 | /** | |
15 | * struct meson_pmx_group - a pinmux group | |
16 | * | |
17 | * @name: group name | |
18 | * @pins: pins in the group | |
19 | * @num_pins: number of pins in the group | |
20 | * @is_gpio: whether the group is a single GPIO group | |
21 | * @reg: register offset for the group in the domain mux registers | |
22 | * @bit bit index enabling the group | |
23 | * @domain: index of the domain this group belongs to | |
24 | */ | |
25 | struct meson_pmx_group { | |
26 | const char *name; | |
27 | const unsigned int *pins; | |
28 | unsigned int num_pins; | |
ce385aa2 | 29 | const void *data; |
6ac73095 BG |
30 | }; |
31 | ||
32 | /** | |
33 | * struct meson_pmx_func - a pinmux function | |
34 | * | |
35 | * @name: function name | |
36 | * @groups: groups in the function | |
37 | * @num_groups: number of groups in the function | |
38 | */ | |
39 | struct meson_pmx_func { | |
40 | const char *name; | |
41 | const char * const *groups; | |
42 | unsigned int num_groups; | |
43 | }; | |
44 | ||
45 | /** | |
46 | * struct meson_reg_desc - a register descriptor | |
47 | * | |
48 | * @reg: register offset in the regmap | |
49 | * @bit: bit index in register | |
50 | * | |
51 | * The structure describes the information needed to control pull, | |
52 | * pull-enable, direction, etc. for a single pin | |
53 | */ | |
54 | struct meson_reg_desc { | |
55 | unsigned int reg; | |
56 | unsigned int bit; | |
57 | }; | |
58 | ||
59 | /** | |
60 | * enum meson_reg_type - type of registers encoded in @meson_reg_desc | |
61 | */ | |
62 | enum meson_reg_type { | |
63 | REG_PULLEN, | |
64 | REG_PULL, | |
65 | REG_DIR, | |
66 | REG_OUT, | |
67 | REG_IN, | |
6ea3e3bb | 68 | REG_DS, |
6ac73095 BG |
69 | NUM_REG, |
70 | }; | |
71 | ||
6ea3e3bb GLR |
72 | /** |
73 | * enum meson_pinconf_drv - value of drive-strength supported | |
74 | */ | |
75 | enum meson_pinconf_drv { | |
76 | MESON_PINCONF_DRV_500UA, | |
77 | MESON_PINCONF_DRV_2500UA, | |
78 | MESON_PINCONF_DRV_3000UA, | |
79 | MESON_PINCONF_DRV_4000UA, | |
80 | }; | |
81 | ||
6ac73095 BG |
82 | /** |
83 | * struct meson bank | |
84 | * | |
85 | * @name: bank name | |
86 | * @first: first pin of the bank | |
87 | * @last: last pin of the bank | |
6c9dc843 | 88 | * @irq: hwirq base number of the bank |
6ac73095 BG |
89 | * @regs: array of register descriptors |
90 | * | |
91 | * A bank represents a set of pins controlled by a contiguous set of | |
92 | * bits in the domain registers. The structure specifies which bits in | |
93 | * the regmap control the different functionalities. Each member of | |
94 | * the @regs array refers to the first pin of the bank. | |
95 | */ | |
96 | struct meson_bank { | |
97 | const char *name; | |
98 | unsigned int first; | |
99 | unsigned int last; | |
6c9dc843 JB |
100 | int irq_first; |
101 | int irq_last; | |
6ac73095 BG |
102 | struct meson_reg_desc regs[NUM_REG]; |
103 | }; | |
104 | ||
6ac73095 | 105 | struct meson_pinctrl_data { |
db80f0e1 | 106 | const char *name; |
6ac73095 BG |
107 | const struct pinctrl_pin_desc *pins; |
108 | struct meson_pmx_group *groups; | |
109 | struct meson_pmx_func *funcs; | |
6ac73095 BG |
110 | unsigned int num_pins; |
111 | unsigned int num_groups; | |
112 | unsigned int num_funcs; | |
db80f0e1 BG |
113 | struct meson_bank *banks; |
114 | unsigned int num_banks; | |
ce385aa2 | 115 | const struct pinmux_ops *pmx_ops; |
0fabe43f | 116 | void *pmx_data; |
6ac73095 BG |
117 | }; |
118 | ||
119 | struct meson_pinctrl { | |
120 | struct device *dev; | |
121 | struct pinctrl_dev *pcdev; | |
122 | struct pinctrl_desc desc; | |
123 | struct meson_pinctrl_data *data; | |
db80f0e1 BG |
124 | struct regmap *reg_mux; |
125 | struct regmap *reg_pullen; | |
126 | struct regmap *reg_pull; | |
127 | struct regmap *reg_gpio; | |
64856974 | 128 | struct regmap *reg_ds; |
db80f0e1 BG |
129 | struct gpio_chip chip; |
130 | struct device_node *of_node; | |
6ac73095 BG |
131 | }; |
132 | ||
6ac73095 BG |
133 | #define FUNCTION(fn) \ |
134 | { \ | |
135 | .name = #fn, \ | |
136 | .groups = fn ## _groups, \ | |
137 | .num_groups = ARRAY_SIZE(fn ## _groups), \ | |
138 | } | |
139 | ||
6ea3e3bb GLR |
140 | #define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, \ |
141 | dsr, dsb) \ | |
6ac73095 | 142 | { \ |
6c9dc843 JB |
143 | .name = n, \ |
144 | .first = f, \ | |
145 | .last = l, \ | |
146 | .irq_first = fi, \ | |
147 | .irq_last = li, \ | |
148 | .regs = { \ | |
6ac73095 BG |
149 | [REG_PULLEN] = { per, peb }, \ |
150 | [REG_PULL] = { pr, pb }, \ | |
151 | [REG_DIR] = { dr, db }, \ | |
152 | [REG_OUT] = { or, ob }, \ | |
153 | [REG_IN] = { ir, ib }, \ | |
6ea3e3bb | 154 | [REG_DS] = { dsr, dsb }, \ |
6ac73095 BG |
155 | }, \ |
156 | } | |
157 | ||
6ea3e3bb GLR |
158 | #define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ |
159 | BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0) | |
160 | ||
634e40b0 | 161 | #define MESON_PIN(x) PINCTRL_PIN(x, #x) |
6ac73095 | 162 | |
ce385aa2 JB |
163 | /* Common pmx functions */ |
164 | int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev); | |
165 | const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, | |
166 | unsigned selector); | |
167 | int meson_pmx_get_groups(struct pinctrl_dev *pcdev, | |
168 | unsigned selector, | |
169 | const char * const **groups, | |
170 | unsigned * const num_groups); | |
171 | ||
277d14eb JB |
172 | /* Common probe function */ |
173 | int meson_pinctrl_probe(struct platform_device *pdev); |