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6ac73095 BG |
1 | /* |
2 | * Pin controller and GPIO driver for Amlogic Meson SoCs | |
3 | * | |
4 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * You should have received a copy of the GNU General Public License | |
11 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
12 | */ | |
13 | ||
14 | /* | |
15 | * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, | |
faa246de CC |
16 | * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and |
17 | * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a | |
18 | * variable number of pins. | |
6ac73095 BG |
19 | * |
20 | * The AO bank is special because it belongs to the Always-On power | |
21 | * domain which can't be powered off; the bank also uses a set of | |
22 | * registers different from the other banks. | |
23 | * | |
db80f0e1 BG |
24 | * For each pin controller there are 4 different register ranges that |
25 | * control the following properties of the pins: | |
6ac73095 BG |
26 | * 1) pin muxing |
27 | * 2) pull enable/disable | |
28 | * 3) pull up/down | |
29 | * 4) GPIO direction, output value, input value | |
30 | * | |
31 | * In some cases the register ranges for pull enable and pull | |
32 | * direction are the same and thus there are only 3 register ranges. | |
33 | * | |
34 | * Every pinmux group can be enabled by a specific bit in the first | |
db80f0e1 BG |
35 | * register range; when all groups for a given pin are disabled the |
36 | * pin acts as a GPIO. | |
6ac73095 BG |
37 | * |
38 | * For the pull and GPIO configuration every bank uses a contiguous | |
39 | * set of bits in the register sets described above; the same register | |
40 | * can be shared by more banks with different offsets. | |
41 | * | |
42 | * In addition to this there are some registers shared between all | |
43 | * banks that control the IRQ functionality. This feature is not | |
44 | * supported at the moment by the driver. | |
45 | */ | |
46 | ||
47 | #include <linux/device.h> | |
48 | #include <linux/gpio.h> | |
49 | #include <linux/init.h> | |
50 | #include <linux/io.h> | |
6ac73095 BG |
51 | #include <linux/of.h> |
52 | #include <linux/of_address.h> | |
53 | #include <linux/pinctrl/pinconf-generic.h> | |
54 | #include <linux/pinctrl/pinconf.h> | |
55 | #include <linux/pinctrl/pinctrl.h> | |
56 | #include <linux/pinctrl/pinmux.h> | |
57 | #include <linux/platform_device.h> | |
58 | #include <linux/regmap.h> | |
59 | #include <linux/seq_file.h> | |
60 | ||
61 | #include "../core.h" | |
62 | #include "../pinctrl-utils.h" | |
63 | #include "pinctrl-meson.h" | |
64 | ||
65 | /** | |
66 | * meson_get_bank() - find the bank containing a given pin | |
67 | * | |
db80f0e1 | 68 | * @pc: the pinctrl instance |
6ac73095 BG |
69 | * @pin: the pin number |
70 | * @bank: the found bank | |
71 | * | |
72 | * Return: 0 on success, a negative value on error | |
73 | */ | |
db80f0e1 | 74 | static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, |
6ac73095 BG |
75 | struct meson_bank **bank) |
76 | { | |
77 | int i; | |
78 | ||
db80f0e1 BG |
79 | for (i = 0; i < pc->data->num_banks; i++) { |
80 | if (pin >= pc->data->banks[i].first && | |
81 | pin <= pc->data->banks[i].last) { | |
82 | *bank = &pc->data->banks[i]; | |
6ac73095 BG |
83 | return 0; |
84 | } | |
85 | } | |
86 | ||
87 | return -EINVAL; | |
88 | } | |
89 | ||
6ac73095 BG |
90 | /** |
91 | * meson_calc_reg_and_bit() - calculate register and bit for a pin | |
92 | * | |
93 | * @bank: the bank containing the pin | |
94 | * @pin: the pin number | |
95 | * @reg_type: the type of register needed (pull-enable, pull, etc...) | |
96 | * @reg: the computed register offset | |
97 | * @bit: the computed bit | |
98 | */ | |
99 | static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, | |
100 | enum meson_reg_type reg_type, | |
101 | unsigned int *reg, unsigned int *bit) | |
102 | { | |
103 | struct meson_reg_desc *desc = &bank->regs[reg_type]; | |
104 | ||
105 | *reg = desc->reg * 4; | |
106 | *bit = desc->bit + pin - bank->first; | |
107 | } | |
108 | ||
109 | static int meson_get_groups_count(struct pinctrl_dev *pcdev) | |
110 | { | |
111 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
112 | ||
113 | return pc->data->num_groups; | |
114 | } | |
115 | ||
116 | static const char *meson_get_group_name(struct pinctrl_dev *pcdev, | |
117 | unsigned selector) | |
118 | { | |
119 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
120 | ||
121 | return pc->data->groups[selector].name; | |
122 | } | |
123 | ||
124 | static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, | |
125 | const unsigned **pins, unsigned *num_pins) | |
126 | { | |
127 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
128 | ||
129 | *pins = pc->data->groups[selector].pins; | |
130 | *num_pins = pc->data->groups[selector].num_pins; | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
135 | static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, | |
136 | unsigned offset) | |
137 | { | |
138 | seq_printf(s, " %s", dev_name(pcdev->dev)); | |
139 | } | |
140 | ||
141 | static const struct pinctrl_ops meson_pctrl_ops = { | |
142 | .get_groups_count = meson_get_groups_count, | |
143 | .get_group_name = meson_get_group_name, | |
144 | .get_group_pins = meson_get_group_pins, | |
145 | .dt_node_to_map = pinconf_generic_dt_node_to_map_all, | |
d32f7fd3 | 146 | .dt_free_map = pinctrl_utils_free_map, |
6ac73095 BG |
147 | .pin_dbg_show = meson_pin_dbg_show, |
148 | }; | |
149 | ||
150 | /** | |
151 | * meson_pmx_disable_other_groups() - disable other groups using a given pin | |
152 | * | |
153 | * @pc: meson pin controller device | |
154 | * @pin: number of the pin | |
155 | * @sel_group: index of the selected group, or -1 if none | |
156 | * | |
157 | * The function disables all pinmux groups using a pin except the | |
158 | * selected one. If @sel_group is -1 all groups are disabled, leaving | |
159 | * the pin in GPIO mode. | |
160 | */ | |
161 | static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc, | |
162 | unsigned int pin, int sel_group) | |
163 | { | |
164 | struct meson_pmx_group *group; | |
6ac73095 BG |
165 | int i, j; |
166 | ||
167 | for (i = 0; i < pc->data->num_groups; i++) { | |
168 | group = &pc->data->groups[i]; | |
169 | if (group->is_gpio || i == sel_group) | |
170 | continue; | |
171 | ||
172 | for (j = 0; j < group->num_pins; j++) { | |
173 | if (group->pins[j] == pin) { | |
174 | /* We have found a group using the pin */ | |
db80f0e1 | 175 | regmap_update_bits(pc->reg_mux, |
6ac73095 BG |
176 | group->reg * 4, |
177 | BIT(group->bit), 0); | |
178 | } | |
179 | } | |
180 | } | |
181 | } | |
182 | ||
183 | static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, | |
184 | unsigned group_num) | |
185 | { | |
186 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
187 | struct meson_pmx_func *func = &pc->data->funcs[func_num]; | |
188 | struct meson_pmx_group *group = &pc->data->groups[group_num]; | |
6ac73095 BG |
189 | int i, ret = 0; |
190 | ||
191 | dev_dbg(pc->dev, "enable function %s, group %s\n", func->name, | |
192 | group->name); | |
193 | ||
194 | /* | |
195 | * Disable groups using the same pin. | |
196 | * The selected group is not disabled to avoid glitches. | |
197 | */ | |
198 | for (i = 0; i < group->num_pins; i++) | |
199 | meson_pmx_disable_other_groups(pc, group->pins[i], group_num); | |
200 | ||
201 | /* Function 0 (GPIO) doesn't need any additional setting */ | |
202 | if (func_num) | |
db80f0e1 | 203 | ret = regmap_update_bits(pc->reg_mux, group->reg * 4, |
6ac73095 BG |
204 | BIT(group->bit), BIT(group->bit)); |
205 | ||
206 | return ret; | |
207 | } | |
208 | ||
209 | static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev, | |
210 | struct pinctrl_gpio_range *range, | |
211 | unsigned offset) | |
212 | { | |
213 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
214 | ||
f24d311f | 215 | meson_pmx_disable_other_groups(pc, offset, -1); |
6ac73095 BG |
216 | |
217 | return 0; | |
218 | } | |
219 | ||
220 | static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) | |
221 | { | |
222 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
223 | ||
224 | return pc->data->num_funcs; | |
225 | } | |
226 | ||
227 | static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, | |
228 | unsigned selector) | |
229 | { | |
230 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
231 | ||
232 | return pc->data->funcs[selector].name; | |
233 | } | |
234 | ||
235 | static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, | |
236 | const char * const **groups, | |
237 | unsigned * const num_groups) | |
238 | { | |
239 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
240 | ||
241 | *groups = pc->data->funcs[selector].groups; | |
242 | *num_groups = pc->data->funcs[selector].num_groups; | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
247 | static const struct pinmux_ops meson_pmx_ops = { | |
248 | .set_mux = meson_pmx_set_mux, | |
249 | .get_functions_count = meson_pmx_get_funcs_count, | |
250 | .get_function_name = meson_pmx_get_func_name, | |
251 | .get_function_groups = meson_pmx_get_groups, | |
252 | .gpio_request_enable = meson_pmx_request_gpio, | |
253 | }; | |
254 | ||
255 | static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, | |
256 | unsigned long *configs, unsigned num_configs) | |
257 | { | |
258 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
6ac73095 BG |
259 | struct meson_bank *bank; |
260 | enum pin_config_param param; | |
261 | unsigned int reg, bit; | |
262 | int i, ret; | |
263 | u16 arg; | |
264 | ||
db80f0e1 | 265 | ret = meson_get_bank(pc, pin, &bank); |
6ac73095 BG |
266 | if (ret) |
267 | return ret; | |
268 | ||
269 | for (i = 0; i < num_configs; i++) { | |
270 | param = pinconf_to_config_param(configs[i]); | |
271 | arg = pinconf_to_config_argument(configs[i]); | |
272 | ||
273 | switch (param) { | |
274 | case PIN_CONFIG_BIAS_DISABLE: | |
275 | dev_dbg(pc->dev, "pin %u: disable bias\n", pin); | |
276 | ||
277 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); | |
db80f0e1 | 278 | ret = regmap_update_bits(pc->reg_pull, reg, |
6ac73095 BG |
279 | BIT(bit), 0); |
280 | if (ret) | |
281 | return ret; | |
282 | break; | |
283 | case PIN_CONFIG_BIAS_PULL_UP: | |
284 | dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin); | |
285 | ||
286 | meson_calc_reg_and_bit(bank, pin, REG_PULLEN, | |
287 | ®, &bit); | |
db80f0e1 | 288 | ret = regmap_update_bits(pc->reg_pullen, reg, |
6ac73095 BG |
289 | BIT(bit), BIT(bit)); |
290 | if (ret) | |
291 | return ret; | |
292 | ||
293 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); | |
db80f0e1 | 294 | ret = regmap_update_bits(pc->reg_pull, reg, |
6ac73095 BG |
295 | BIT(bit), BIT(bit)); |
296 | if (ret) | |
297 | return ret; | |
298 | break; | |
299 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
300 | dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin); | |
301 | ||
302 | meson_calc_reg_and_bit(bank, pin, REG_PULLEN, | |
303 | ®, &bit); | |
db80f0e1 | 304 | ret = regmap_update_bits(pc->reg_pullen, reg, |
6ac73095 BG |
305 | BIT(bit), BIT(bit)); |
306 | if (ret) | |
307 | return ret; | |
308 | ||
309 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); | |
db80f0e1 | 310 | ret = regmap_update_bits(pc->reg_pull, reg, |
6ac73095 BG |
311 | BIT(bit), 0); |
312 | if (ret) | |
313 | return ret; | |
314 | break; | |
315 | default: | |
316 | return -ENOTSUPP; | |
317 | } | |
318 | } | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
323 | static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) | |
324 | { | |
6ac73095 BG |
325 | struct meson_bank *bank; |
326 | unsigned int reg, bit, val; | |
327 | int ret, conf; | |
328 | ||
db80f0e1 | 329 | ret = meson_get_bank(pc, pin, &bank); |
6ac73095 BG |
330 | if (ret) |
331 | return ret; | |
332 | ||
333 | meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); | |
334 | ||
db80f0e1 | 335 | ret = regmap_read(pc->reg_pullen, reg, &val); |
6ac73095 BG |
336 | if (ret) |
337 | return ret; | |
338 | ||
339 | if (!(val & BIT(bit))) { | |
340 | conf = PIN_CONFIG_BIAS_DISABLE; | |
341 | } else { | |
342 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); | |
343 | ||
db80f0e1 | 344 | ret = regmap_read(pc->reg_pull, reg, &val); |
6ac73095 BG |
345 | if (ret) |
346 | return ret; | |
347 | ||
348 | if (val & BIT(bit)) | |
349 | conf = PIN_CONFIG_BIAS_PULL_UP; | |
350 | else | |
351 | conf = PIN_CONFIG_BIAS_PULL_DOWN; | |
352 | } | |
353 | ||
354 | return conf; | |
355 | } | |
356 | ||
357 | static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, | |
358 | unsigned long *config) | |
359 | { | |
360 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
361 | enum pin_config_param param = pinconf_to_config_param(*config); | |
362 | u16 arg; | |
363 | ||
364 | switch (param) { | |
365 | case PIN_CONFIG_BIAS_DISABLE: | |
366 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
367 | case PIN_CONFIG_BIAS_PULL_UP: | |
368 | if (meson_pinconf_get_pull(pc, pin) == param) | |
369 | arg = 1; | |
370 | else | |
371 | return -EINVAL; | |
372 | break; | |
373 | default: | |
374 | return -ENOTSUPP; | |
375 | } | |
376 | ||
377 | *config = pinconf_to_config_packed(param, arg); | |
378 | dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, | |
384 | unsigned int num_group, | |
385 | unsigned long *configs, unsigned num_configs) | |
386 | { | |
387 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
388 | struct meson_pmx_group *group = &pc->data->groups[num_group]; | |
389 | int i; | |
390 | ||
391 | dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); | |
392 | ||
393 | for (i = 0; i < group->num_pins; i++) { | |
394 | meson_pinconf_set(pcdev, group->pins[i], configs, | |
395 | num_configs); | |
396 | } | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, | |
402 | unsigned int group, unsigned long *config) | |
403 | { | |
404 | return -ENOSYS; | |
405 | } | |
406 | ||
407 | static const struct pinconf_ops meson_pinconf_ops = { | |
408 | .pin_config_get = meson_pinconf_get, | |
409 | .pin_config_set = meson_pinconf_set, | |
410 | .pin_config_group_get = meson_pinconf_group_get, | |
411 | .pin_config_group_set = meson_pinconf_group_set, | |
412 | .is_generic = true, | |
413 | }; | |
414 | ||
6ac73095 BG |
415 | static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio) |
416 | { | |
417 | return pinctrl_request_gpio(chip->base + gpio); | |
418 | } | |
419 | ||
420 | static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio) | |
421 | { | |
db80f0e1 | 422 | struct meson_pinctrl *pc = gpiochip_get_data(chip); |
6ac73095 | 423 | |
db80f0e1 | 424 | pinctrl_free_gpio(pc->data->pin_base + gpio); |
6ac73095 BG |
425 | } |
426 | ||
427 | static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | |
428 | { | |
db80f0e1 | 429 | struct meson_pinctrl *pc = gpiochip_get_data(chip); |
6ac73095 BG |
430 | unsigned int reg, bit, pin; |
431 | struct meson_bank *bank; | |
432 | int ret; | |
433 | ||
db80f0e1 BG |
434 | pin = pc->data->pin_base + gpio; |
435 | ret = meson_get_bank(pc, pin, &bank); | |
6ac73095 BG |
436 | if (ret) |
437 | return ret; | |
438 | ||
439 | meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); | |
440 | ||
db80f0e1 | 441 | return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit)); |
6ac73095 BG |
442 | } |
443 | ||
444 | static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, | |
445 | int value) | |
446 | { | |
db80f0e1 | 447 | struct meson_pinctrl *pc = gpiochip_get_data(chip); |
6ac73095 BG |
448 | unsigned int reg, bit, pin; |
449 | struct meson_bank *bank; | |
450 | int ret; | |
451 | ||
db80f0e1 BG |
452 | pin = pc->data->pin_base + gpio; |
453 | ret = meson_get_bank(pc, pin, &bank); | |
6ac73095 BG |
454 | if (ret) |
455 | return ret; | |
456 | ||
457 | meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); | |
db80f0e1 | 458 | ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0); |
6ac73095 BG |
459 | if (ret) |
460 | return ret; | |
461 | ||
462 | meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); | |
db80f0e1 | 463 | return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), |
6ac73095 BG |
464 | value ? BIT(bit) : 0); |
465 | } | |
466 | ||
467 | static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) | |
468 | { | |
db80f0e1 | 469 | struct meson_pinctrl *pc = gpiochip_get_data(chip); |
6ac73095 BG |
470 | unsigned int reg, bit, pin; |
471 | struct meson_bank *bank; | |
472 | int ret; | |
473 | ||
db80f0e1 BG |
474 | pin = pc->data->pin_base + gpio; |
475 | ret = meson_get_bank(pc, pin, &bank); | |
6ac73095 BG |
476 | if (ret) |
477 | return; | |
478 | ||
479 | meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); | |
db80f0e1 | 480 | regmap_update_bits(pc->reg_gpio, reg, BIT(bit), |
6ac73095 BG |
481 | value ? BIT(bit) : 0); |
482 | } | |
483 | ||
484 | static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) | |
485 | { | |
db80f0e1 | 486 | struct meson_pinctrl *pc = gpiochip_get_data(chip); |
6ac73095 BG |
487 | unsigned int reg, bit, val, pin; |
488 | struct meson_bank *bank; | |
489 | int ret; | |
490 | ||
db80f0e1 BG |
491 | pin = pc->data->pin_base + gpio; |
492 | ret = meson_get_bank(pc, pin, &bank); | |
6ac73095 BG |
493 | if (ret) |
494 | return ret; | |
495 | ||
496 | meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit); | |
db80f0e1 | 497 | regmap_read(pc->reg_gpio, reg, &val); |
6ac73095 BG |
498 | |
499 | return !!(val & BIT(bit)); | |
500 | } | |
501 | ||
502 | static const struct of_device_id meson_pinctrl_dt_match[] = { | |
503 | { | |
9dab1868 CC |
504 | .compatible = "amlogic,meson8-cbus-pinctrl", |
505 | .data = &meson8_cbus_pinctrl_data, | |
506 | }, | |
507 | { | |
508 | .compatible = "amlogic,meson8b-cbus-pinctrl", | |
509 | .data = &meson8b_cbus_pinctrl_data, | |
510 | }, | |
511 | { | |
512 | .compatible = "amlogic,meson8-aobus-pinctrl", | |
513 | .data = &meson8_aobus_pinctrl_data, | |
6ac73095 | 514 | }, |
0fefcb68 | 515 | { |
9dab1868 CC |
516 | .compatible = "amlogic,meson8b-aobus-pinctrl", |
517 | .data = &meson8b_aobus_pinctrl_data, | |
0fefcb68 | 518 | }, |
468c234f CC |
519 | { |
520 | .compatible = "amlogic,meson-gxbb-periphs-pinctrl", | |
521 | .data = &meson_gxbb_periphs_pinctrl_data, | |
522 | }, | |
523 | { | |
524 | .compatible = "amlogic,meson-gxbb-aobus-pinctrl", | |
525 | .data = &meson_gxbb_aobus_pinctrl_data, | |
0f15f500 NA |
526 | }, |
527 | { | |
528 | .compatible = "amlogic,meson-gxl-periphs-pinctrl", | |
529 | .data = &meson_gxl_periphs_pinctrl_data, | |
530 | }, | |
531 | { | |
532 | .compatible = "amlogic,meson-gxl-aobus-pinctrl", | |
533 | .data = &meson_gxl_aobus_pinctrl_data, | |
468c234f | 534 | }, |
6ac73095 BG |
535 | { }, |
536 | }; | |
6ac73095 BG |
537 | |
538 | static int meson_gpiolib_register(struct meson_pinctrl *pc) | |
539 | { | |
9dab1868 | 540 | int ret; |
6ac73095 | 541 | |
db80f0e1 BG |
542 | pc->chip.label = pc->data->name; |
543 | pc->chip.parent = pc->dev; | |
544 | pc->chip.request = meson_gpio_request; | |
545 | pc->chip.free = meson_gpio_free; | |
546 | pc->chip.direction_input = meson_gpio_direction_input; | |
547 | pc->chip.direction_output = meson_gpio_direction_output; | |
548 | pc->chip.get = meson_gpio_get; | |
549 | pc->chip.set = meson_gpio_set; | |
550 | pc->chip.base = pc->data->pin_base; | |
551 | pc->chip.ngpio = pc->data->num_pins; | |
552 | pc->chip.can_sleep = false; | |
553 | pc->chip.of_node = pc->of_node; | |
554 | pc->chip.of_gpio_n_cells = 2; | |
555 | ||
556 | ret = gpiochip_add_data(&pc->chip, pc); | |
9dab1868 CC |
557 | if (ret) { |
558 | dev_err(pc->dev, "can't add gpio chip %s\n", | |
db80f0e1 | 559 | pc->data->name); |
9dab1868 CC |
560 | goto fail; |
561 | } | |
6ac73095 | 562 | |
db80f0e1 BG |
563 | ret = gpiochip_add_pin_range(&pc->chip, dev_name(pc->dev), |
564 | 0, pc->data->pin_base, | |
565 | pc->chip.ngpio); | |
9dab1868 CC |
566 | if (ret) { |
567 | dev_err(pc->dev, "can't add pin range\n"); | |
568 | goto fail; | |
6ac73095 BG |
569 | } |
570 | ||
571 | return 0; | |
572 | fail: | |
db80f0e1 | 573 | gpiochip_remove(&pc->chip); |
6ac73095 BG |
574 | |
575 | return ret; | |
576 | } | |
577 | ||
6ac73095 BG |
578 | static struct regmap_config meson_regmap_config = { |
579 | .reg_bits = 32, | |
580 | .val_bits = 32, | |
581 | .reg_stride = 4, | |
582 | }; | |
583 | ||
584 | static struct regmap *meson_map_resource(struct meson_pinctrl *pc, | |
585 | struct device_node *node, char *name) | |
586 | { | |
587 | struct resource res; | |
588 | void __iomem *base; | |
589 | int i; | |
590 | ||
591 | i = of_property_match_string(node, "reg-names", name); | |
592 | if (of_address_to_resource(node, i, &res)) | |
593 | return ERR_PTR(-ENOENT); | |
594 | ||
595 | base = devm_ioremap_resource(pc->dev, &res); | |
596 | if (IS_ERR(base)) | |
597 | return ERR_CAST(base); | |
598 | ||
599 | meson_regmap_config.max_register = resource_size(&res) - 4; | |
600 | meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, | |
601 | "%s-%s", node->name, | |
602 | name); | |
603 | if (!meson_regmap_config.name) | |
604 | return ERR_PTR(-ENOMEM); | |
605 | ||
606 | return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); | |
607 | } | |
608 | ||
609 | static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, | |
610 | struct device_node *node) | |
611 | { | |
db80f0e1 | 612 | struct device_node *np, *gpio_np = NULL; |
6ac73095 BG |
613 | |
614 | for_each_child_of_node(node, np) { | |
615 | if (!of_find_property(np, "gpio-controller", NULL)) | |
616 | continue; | |
db80f0e1 BG |
617 | if (gpio_np) { |
618 | dev_err(pc->dev, "multiple gpio nodes\n"); | |
619 | return -EINVAL; | |
620 | } | |
621 | gpio_np = np; | |
6ac73095 BG |
622 | } |
623 | ||
db80f0e1 BG |
624 | if (!gpio_np) { |
625 | dev_err(pc->dev, "no gpio node found\n"); | |
6ac73095 BG |
626 | return -EINVAL; |
627 | } | |
628 | ||
db80f0e1 | 629 | pc->of_node = gpio_np; |
6ac73095 | 630 | |
db80f0e1 BG |
631 | pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); |
632 | if (IS_ERR(pc->reg_mux)) { | |
633 | dev_err(pc->dev, "mux registers not found\n"); | |
634 | return PTR_ERR(pc->reg_mux); | |
635 | } | |
6ac73095 | 636 | |
db80f0e1 BG |
637 | pc->reg_pull = meson_map_resource(pc, gpio_np, "pull"); |
638 | if (IS_ERR(pc->reg_pull)) { | |
639 | dev_err(pc->dev, "pull registers not found\n"); | |
640 | return PTR_ERR(pc->reg_pull); | |
641 | } | |
6ac73095 | 642 | |
db80f0e1 BG |
643 | pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable"); |
644 | /* Use pull region if pull-enable one is not present */ | |
645 | if (IS_ERR(pc->reg_pullen)) | |
646 | pc->reg_pullen = pc->reg_pull; | |
6ac73095 | 647 | |
db80f0e1 BG |
648 | pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio"); |
649 | if (IS_ERR(pc->reg_gpio)) { | |
650 | dev_err(pc->dev, "gpio registers not found\n"); | |
651 | return PTR_ERR(pc->reg_gpio); | |
6ac73095 BG |
652 | } |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
657 | static int meson_pinctrl_probe(struct platform_device *pdev) | |
658 | { | |
659 | const struct of_device_id *match; | |
660 | struct device *dev = &pdev->dev; | |
661 | struct meson_pinctrl *pc; | |
662 | int ret; | |
663 | ||
664 | pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); | |
665 | if (!pc) | |
666 | return -ENOMEM; | |
667 | ||
668 | pc->dev = dev; | |
669 | match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node); | |
9dab1868 | 670 | pc->data = (struct meson_pinctrl_data *) match->data; |
6ac73095 BG |
671 | |
672 | ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node); | |
673 | if (ret) | |
674 | return ret; | |
675 | ||
676 | pc->desc.name = "pinctrl-meson"; | |
677 | pc->desc.owner = THIS_MODULE; | |
678 | pc->desc.pctlops = &meson_pctrl_ops; | |
679 | pc->desc.pmxops = &meson_pmx_ops; | |
680 | pc->desc.confops = &meson_pinconf_ops; | |
681 | pc->desc.pins = pc->data->pins; | |
682 | pc->desc.npins = pc->data->num_pins; | |
683 | ||
e649f7ec | 684 | pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc); |
323de9ef | 685 | if (IS_ERR(pc->pcdev)) { |
6ac73095 | 686 | dev_err(pc->dev, "can't register pinctrl device"); |
323de9ef | 687 | return PTR_ERR(pc->pcdev); |
6ac73095 BG |
688 | } |
689 | ||
5b236d0f | 690 | return meson_gpiolib_register(pc); |
6ac73095 BG |
691 | } |
692 | ||
693 | static struct platform_driver meson_pinctrl_driver = { | |
694 | .probe = meson_pinctrl_probe, | |
695 | .driver = { | |
696 | .name = "meson-pinctrl", | |
697 | .of_match_table = meson_pinctrl_dt_match, | |
698 | }, | |
699 | }; | |
2496eb32 | 700 | builtin_platform_driver(meson_pinctrl_driver); |