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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a6df410d HY |
2 | /* |
3 | * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver. | |
4 | * Copyright (c) 2014 MediaTek Inc. | |
5 | * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> | |
a6df410d HY |
6 | */ |
7 | ||
8 | #include <linux/io.h> | |
11aa679a | 9 | #include <linux/gpio/driver.h> |
a6df410d HY |
10 | #include <linux/of.h> |
11 | #include <linux/of_address.h> | |
12 | #include <linux/of_device.h> | |
13 | #include <linux/of_irq.h> | |
14 | #include <linux/pinctrl/consumer.h> | |
15 | #include <linux/pinctrl/machine.h> | |
16 | #include <linux/pinctrl/pinconf.h> | |
17 | #include <linux/pinctrl/pinconf-generic.h> | |
18 | #include <linux/pinctrl/pinctrl.h> | |
19 | #include <linux/pinctrl/pinmux.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/bitops.h> | |
23 | #include <linux/regmap.h> | |
24 | #include <linux/mfd/syscon.h> | |
d9819eb9 | 25 | #include <linux/delay.h> |
30f010f5 | 26 | #include <linux/interrupt.h> |
58a5e1b6 | 27 | #include <linux/pm.h> |
a6df410d HY |
28 | #include <dt-bindings/pinctrl/mt65xx.h> |
29 | ||
30 | #include "../core.h" | |
31 | #include "../pinconf.h" | |
32 | #include "../pinctrl-utils.h" | |
e46df235 | 33 | #include "mtk-eint.h" |
a6df410d HY |
34 | #include "pinctrl-mtk-common.h" |
35 | ||
36 | #define MAX_GPIO_MODE_PER_REG 5 | |
37 | #define GPIO_MODE_BITS 3 | |
59ee9c96 | 38 | #define GPIO_MODE_PREFIX "GPIO" |
a6df410d HY |
39 | |
40 | static const char * const mtk_gpio_functions[] = { | |
41 | "func0", "func1", "func2", "func3", | |
42 | "func4", "func5", "func6", "func7", | |
148b95ee BH |
43 | "func8", "func9", "func10", "func11", |
44 | "func12", "func13", "func14", "func15", | |
a6df410d HY |
45 | }; |
46 | ||
47 | /* | |
48 | * There are two base address for pull related configuration | |
49 | * in mt8135, and different GPIO pins use different base address. | |
50 | * When pin number greater than type1_start and less than type1_end, | |
51 | * should use the second base address. | |
52 | */ | |
53 | static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, | |
54 | unsigned long pin) | |
55 | { | |
56 | if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) | |
57 | return pctl->regmap2; | |
58 | return pctl->regmap1; | |
59 | } | |
60 | ||
61 | static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) | |
62 | { | |
63 | /* Different SoC has different mask and port shift. */ | |
64 | return ((pin >> 4) & pctl->devdata->port_mask) | |
65 | << pctl->devdata->port_shf; | |
66 | } | |
67 | ||
68 | static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
69 | struct pinctrl_gpio_range *range, unsigned offset, | |
70 | bool input) | |
71 | { | |
72 | unsigned int reg_addr; | |
73 | unsigned int bit; | |
74 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
75 | ||
76 | reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; | |
77 | bit = BIT(offset & 0xf); | |
78 | ||
148b95ee BH |
79 | if (pctl->devdata->spec_dir_set) |
80 | pctl->devdata->spec_dir_set(®_addr, offset); | |
81 | ||
a6df410d HY |
82 | if (input) |
83 | /* Different SoC has different alignment offset. */ | |
84 | reg_addr = CLR_ADDR(reg_addr, pctl); | |
85 | else | |
86 | reg_addr = SET_ADDR(reg_addr, pctl); | |
87 | ||
88 | regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); | |
89 | return 0; | |
90 | } | |
91 | ||
92 | static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
93 | { | |
94 | unsigned int reg_addr; | |
95 | unsigned int bit; | |
11aa679a | 96 | struct mtk_pinctrl *pctl = gpiochip_get_data(chip); |
a6df410d HY |
97 | |
98 | reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; | |
99 | bit = BIT(offset & 0xf); | |
100 | ||
101 | if (value) | |
102 | reg_addr = SET_ADDR(reg_addr, pctl); | |
103 | else | |
104 | reg_addr = CLR_ADDR(reg_addr, pctl); | |
105 | ||
106 | regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); | |
107 | } | |
108 | ||
25d76b21 HY |
109 | static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, |
110 | int value, enum pin_config_param arg) | |
a6df410d HY |
111 | { |
112 | unsigned int reg_addr, offset; | |
113 | unsigned int bit; | |
25d76b21 HY |
114 | |
115 | /** | |
116 | * Due to some soc are not support ies/smt config, add this special | |
117 | * control to handle it. | |
118 | */ | |
119 | if (!pctl->devdata->spec_ies_smt_set && | |
120 | pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT && | |
121 | arg == PIN_CONFIG_INPUT_ENABLE) | |
122 | return -EINVAL; | |
123 | ||
124 | if (!pctl->devdata->spec_ies_smt_set && | |
125 | pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT && | |
126 | arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) | |
127 | return -EINVAL; | |
30f010f5 HY |
128 | |
129 | /* | |
130 | * Due to some pins are irregular, their input enable and smt | |
25d76b21 | 131 | * control register are discontinuous, so we need this special handle. |
30f010f5 HY |
132 | */ |
133 | if (pctl->devdata->spec_ies_smt_set) { | |
25d76b21 HY |
134 | return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), |
135 | pin, pctl->devdata->port_align, value, arg); | |
30f010f5 | 136 | } |
a6df410d HY |
137 | |
138 | bit = BIT(pin & 0xf); | |
139 | ||
25d76b21 | 140 | if (arg == PIN_CONFIG_INPUT_ENABLE) |
a6df410d HY |
141 | offset = pctl->devdata->ies_offset; |
142 | else | |
143 | offset = pctl->devdata->smt_offset; | |
144 | ||
145 | if (value) | |
146 | reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); | |
147 | else | |
148 | reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); | |
149 | ||
150 | regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); | |
25d76b21 HY |
151 | return 0; |
152 | } | |
153 | ||
154 | int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, | |
155 | const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, | |
156 | unsigned int pin, unsigned char align, int value) | |
157 | { | |
158 | unsigned int i, reg_addr, bit; | |
159 | ||
160 | for (i = 0; i < info_num; i++) { | |
161 | if (pin >= ies_smt_infos[i].start && | |
162 | pin <= ies_smt_infos[i].end) { | |
163 | break; | |
164 | } | |
165 | } | |
166 | ||
167 | if (i == info_num) | |
168 | return -EINVAL; | |
169 | ||
170 | if (value) | |
171 | reg_addr = ies_smt_infos[i].offset + align; | |
172 | else | |
173 | reg_addr = ies_smt_infos[i].offset + (align << 1); | |
174 | ||
175 | bit = BIT(ies_smt_infos[i].bit); | |
176 | regmap_write(regmap, reg_addr, bit); | |
177 | return 0; | |
a6df410d HY |
178 | } |
179 | ||
180 | static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( | |
181 | struct mtk_pinctrl *pctl, unsigned long pin) { | |
182 | int i; | |
183 | ||
184 | for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) { | |
185 | const struct mtk_pin_drv_grp *pin_drv = | |
186 | pctl->devdata->pin_drv_grp + i; | |
187 | if (pin == pin_drv->pin) | |
188 | return pin_drv; | |
189 | } | |
190 | ||
191 | return NULL; | |
192 | } | |
193 | ||
194 | static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, | |
195 | unsigned int pin, unsigned char driving) | |
196 | { | |
197 | const struct mtk_pin_drv_grp *pin_drv; | |
198 | unsigned int val; | |
199 | unsigned int bits, mask, shift; | |
200 | const struct mtk_drv_group_desc *drv_grp; | |
201 | ||
202 | if (pin >= pctl->devdata->npins) | |
203 | return -EINVAL; | |
204 | ||
205 | pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin); | |
206 | if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls) | |
207 | return -EINVAL; | |
208 | ||
209 | drv_grp = pctl->devdata->grp_desc + pin_drv->grp; | |
210 | if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv | |
211 | && !(driving % drv_grp->step)) { | |
212 | val = driving / drv_grp->step - 1; | |
213 | bits = drv_grp->high_bit - drv_grp->low_bit + 1; | |
214 | mask = BIT(bits) - 1; | |
215 | shift = pin_drv->bit + drv_grp->low_bit; | |
216 | mask <<= shift; | |
217 | val <<= shift; | |
218 | return regmap_update_bits(mtk_get_regmap(pctl, pin), | |
219 | pin_drv->offset, mask, val); | |
220 | } | |
221 | ||
222 | return -EINVAL; | |
223 | } | |
224 | ||
e73fe271 YC |
225 | int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, |
226 | const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, | |
227 | unsigned int info_num, unsigned int pin, | |
228 | unsigned char align, bool isup, unsigned int r1r0) | |
229 | { | |
230 | unsigned int i; | |
231 | unsigned int reg_pupd, reg_set, reg_rst; | |
232 | unsigned int bit_pupd, bit_r0, bit_r1; | |
233 | const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; | |
234 | bool find = false; | |
235 | ||
236 | for (i = 0; i < info_num; i++) { | |
237 | if (pin == pupd_infos[i].pin) { | |
238 | find = true; | |
239 | break; | |
240 | } | |
241 | } | |
242 | ||
243 | if (!find) | |
244 | return -EINVAL; | |
245 | ||
246 | spec_pupd_pin = pupd_infos + i; | |
247 | reg_set = spec_pupd_pin->offset + align; | |
248 | reg_rst = spec_pupd_pin->offset + (align << 1); | |
249 | ||
250 | if (isup) | |
251 | reg_pupd = reg_rst; | |
252 | else | |
253 | reg_pupd = reg_set; | |
254 | ||
255 | bit_pupd = BIT(spec_pupd_pin->pupd_bit); | |
256 | regmap_write(regmap, reg_pupd, bit_pupd); | |
257 | ||
258 | bit_r0 = BIT(spec_pupd_pin->r0_bit); | |
259 | bit_r1 = BIT(spec_pupd_pin->r1_bit); | |
260 | ||
261 | switch (r1r0) { | |
262 | case MTK_PUPD_SET_R1R0_00: | |
263 | regmap_write(regmap, reg_rst, bit_r0); | |
264 | regmap_write(regmap, reg_rst, bit_r1); | |
265 | break; | |
266 | case MTK_PUPD_SET_R1R0_01: | |
267 | regmap_write(regmap, reg_set, bit_r0); | |
268 | regmap_write(regmap, reg_rst, bit_r1); | |
269 | break; | |
270 | case MTK_PUPD_SET_R1R0_10: | |
271 | regmap_write(regmap, reg_rst, bit_r0); | |
272 | regmap_write(regmap, reg_set, bit_r1); | |
273 | break; | |
274 | case MTK_PUPD_SET_R1R0_11: | |
275 | regmap_write(regmap, reg_set, bit_r0); | |
276 | regmap_write(regmap, reg_set, bit_r1); | |
277 | break; | |
278 | default: | |
279 | return -EINVAL; | |
280 | } | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
a6df410d HY |
285 | static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, |
286 | unsigned int pin, bool enable, bool isup, unsigned int arg) | |
287 | { | |
288 | unsigned int bit; | |
6af8df4c | 289 | unsigned int reg_pullen, reg_pullsel, r1r0; |
a6df410d HY |
290 | int ret; |
291 | ||
292 | /* Some pins' pull setting are very different, | |
293 | * they have separate pull up/down bit, R0 and R1 | |
294 | * resistor bit, so we need this special handle. | |
295 | */ | |
296 | if (pctl->devdata->spec_pull_set) { | |
6af8df4c ZT |
297 | /* For special pins, bias-disable is set by R1R0, |
298 | * the parameter should be "MTK_PUPD_SET_R1R0_00". | |
299 | */ | |
300 | r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00; | |
a6df410d | 301 | ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), |
6af8df4c | 302 | pin, pctl->devdata->port_align, isup, r1r0); |
a6df410d HY |
303 | if (!ret) |
304 | return 0; | |
305 | } | |
306 | ||
307 | /* For generic pull config, default arg value should be 0 or 1. */ | |
308 | if (arg != 0 && arg != 1) { | |
309 | dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", | |
310 | arg, pin); | |
311 | return -EINVAL; | |
312 | } | |
313 | ||
314 | bit = BIT(pin & 0xf); | |
315 | if (enable) | |
316 | reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + | |
317 | pctl->devdata->pullen_offset, pctl); | |
318 | else | |
319 | reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + | |
320 | pctl->devdata->pullen_offset, pctl); | |
321 | ||
322 | if (isup) | |
323 | reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + | |
324 | pctl->devdata->pullsel_offset, pctl); | |
325 | else | |
326 | reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + | |
327 | pctl->devdata->pullsel_offset, pctl); | |
328 | ||
329 | regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); | |
330 | regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); | |
331 | return 0; | |
332 | } | |
333 | ||
334 | static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, | |
335 | unsigned int pin, enum pin_config_param param, | |
336 | enum pin_config_param arg) | |
337 | { | |
25d76b21 | 338 | int ret = 0; |
a6df410d HY |
339 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
340 | ||
341 | switch (param) { | |
342 | case PIN_CONFIG_BIAS_DISABLE: | |
25d76b21 | 343 | ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg); |
a6df410d HY |
344 | break; |
345 | case PIN_CONFIG_BIAS_PULL_UP: | |
25d76b21 | 346 | ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg); |
a6df410d HY |
347 | break; |
348 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
25d76b21 | 349 | ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg); |
a6df410d HY |
350 | break; |
351 | case PIN_CONFIG_INPUT_ENABLE: | |
eceb3e61 | 352 | mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true); |
25d76b21 | 353 | ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); |
a6df410d HY |
354 | break; |
355 | case PIN_CONFIG_OUTPUT: | |
356 | mtk_gpio_set(pctl->chip, pin, arg); | |
25d76b21 | 357 | ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); |
a6df410d HY |
358 | break; |
359 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
eceb3e61 | 360 | mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true); |
25d76b21 | 361 | ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); |
a6df410d HY |
362 | break; |
363 | case PIN_CONFIG_DRIVE_STRENGTH: | |
25d76b21 | 364 | ret = mtk_pconf_set_driving(pctl, pin, arg); |
a6df410d HY |
365 | break; |
366 | default: | |
25d76b21 | 367 | ret = -EINVAL; |
a6df410d HY |
368 | } |
369 | ||
25d76b21 | 370 | return ret; |
a6df410d HY |
371 | } |
372 | ||
373 | static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, | |
374 | unsigned group, | |
375 | unsigned long *config) | |
376 | { | |
377 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
378 | ||
379 | *config = pctl->groups[group].config; | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
384 | static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, | |
385 | unsigned long *configs, unsigned num_configs) | |
386 | { | |
387 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
388 | struct mtk_pinctrl_group *g = &pctl->groups[group]; | |
25d76b21 | 389 | int i, ret; |
a6df410d HY |
390 | |
391 | for (i = 0; i < num_configs; i++) { | |
25d76b21 | 392 | ret = mtk_pconf_parse_conf(pctldev, g->pin, |
a6df410d HY |
393 | pinconf_to_config_param(configs[i]), |
394 | pinconf_to_config_argument(configs[i])); | |
25d76b21 HY |
395 | if (ret < 0) |
396 | return ret; | |
a6df410d HY |
397 | |
398 | g->config = configs[i]; | |
399 | } | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
404 | static const struct pinconf_ops mtk_pconf_ops = { | |
405 | .pin_config_group_get = mtk_pconf_group_get, | |
406 | .pin_config_group_set = mtk_pconf_group_set, | |
407 | }; | |
408 | ||
409 | static struct mtk_pinctrl_group * | |
410 | mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin) | |
411 | { | |
412 | int i; | |
413 | ||
414 | for (i = 0; i < pctl->ngroups; i++) { | |
415 | struct mtk_pinctrl_group *grp = pctl->groups + i; | |
416 | ||
417 | if (grp->pin == pin) | |
418 | return grp; | |
419 | } | |
420 | ||
421 | return NULL; | |
422 | } | |
423 | ||
424 | static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin( | |
425 | struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum) | |
426 | { | |
427 | const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num; | |
428 | const struct mtk_desc_function *func = pin->functions; | |
429 | ||
430 | while (func && func->name) { | |
431 | if (func->muxval == fnum) | |
432 | return func; | |
433 | func++; | |
434 | } | |
435 | ||
436 | return NULL; | |
437 | } | |
438 | ||
439 | static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl, | |
440 | u32 pin_num, u32 fnum) | |
441 | { | |
442 | int i; | |
443 | ||
444 | for (i = 0; i < pctl->devdata->npins; i++) { | |
445 | const struct mtk_desc_pin *pin = pctl->devdata->pins + i; | |
446 | ||
447 | if (pin->pin.number == pin_num) { | |
448 | const struct mtk_desc_function *func = | |
449 | pin->functions; | |
450 | ||
451 | while (func && func->name) { | |
452 | if (func->muxval == fnum) | |
453 | return true; | |
454 | func++; | |
455 | } | |
456 | ||
457 | break; | |
458 | } | |
459 | } | |
460 | ||
461 | return false; | |
462 | } | |
463 | ||
464 | static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, | |
465 | u32 pin, u32 fnum, struct mtk_pinctrl_group *grp, | |
466 | struct pinctrl_map **map, unsigned *reserved_maps, | |
467 | unsigned *num_maps) | |
468 | { | |
469 | bool ret; | |
470 | ||
471 | if (*num_maps == *reserved_maps) | |
472 | return -ENOSPC; | |
473 | ||
474 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
475 | (*map)[*num_maps].data.mux.group = grp->name; | |
476 | ||
477 | ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); | |
478 | if (!ret) { | |
479 | dev_err(pctl->dev, "invalid function %d on pin %d .\n", | |
480 | fnum, pin); | |
481 | return -EINVAL; | |
482 | } | |
483 | ||
484 | (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; | |
485 | (*num_maps)++; | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
490 | static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
491 | struct device_node *node, | |
492 | struct pinctrl_map **map, | |
493 | unsigned *reserved_maps, | |
494 | unsigned *num_maps) | |
495 | { | |
496 | struct property *pins; | |
497 | u32 pinfunc, pin, func; | |
498 | int num_pins, num_funcs, maps_per_pin; | |
499 | unsigned long *configs; | |
500 | unsigned int num_configs; | |
b2f78906 | 501 | bool has_config = false; |
a6df410d HY |
502 | int i, err; |
503 | unsigned reserve = 0; | |
504 | struct mtk_pinctrl_group *grp; | |
505 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
506 | ||
507 | pins = of_find_property(node, "pinmux", NULL); | |
508 | if (!pins) { | |
94f4e54c RH |
509 | dev_err(pctl->dev, "missing pins property in node %pOFn .\n", |
510 | node); | |
a6df410d HY |
511 | return -EINVAL; |
512 | } | |
513 | ||
c445cac3 HY |
514 | err = pinconf_generic_parse_dt_config(node, pctldev, &configs, |
515 | &num_configs); | |
b04a23b0 HY |
516 | if (err) |
517 | return err; | |
518 | ||
a6df410d | 519 | if (num_configs) |
b2f78906 | 520 | has_config = true; |
a6df410d HY |
521 | |
522 | num_pins = pins->length / sizeof(u32); | |
523 | num_funcs = num_pins; | |
524 | maps_per_pin = 0; | |
525 | if (num_funcs) | |
526 | maps_per_pin++; | |
527 | if (has_config && num_pins >= 1) | |
528 | maps_per_pin++; | |
529 | ||
b04a23b0 HY |
530 | if (!num_pins || !maps_per_pin) { |
531 | err = -EINVAL; | |
532 | goto exit; | |
533 | } | |
a6df410d HY |
534 | |
535 | reserve = num_pins * maps_per_pin; | |
536 | ||
537 | err = pinctrl_utils_reserve_map(pctldev, map, | |
538 | reserved_maps, num_maps, reserve); | |
539 | if (err < 0) | |
b04a23b0 | 540 | goto exit; |
a6df410d HY |
541 | |
542 | for (i = 0; i < num_pins; i++) { | |
543 | err = of_property_read_u32_index(node, "pinmux", | |
544 | i, &pinfunc); | |
545 | if (err) | |
b04a23b0 | 546 | goto exit; |
a6df410d HY |
547 | |
548 | pin = MTK_GET_PIN_NO(pinfunc); | |
549 | func = MTK_GET_PIN_FUNC(pinfunc); | |
550 | ||
551 | if (pin >= pctl->devdata->npins || | |
552 | func >= ARRAY_SIZE(mtk_gpio_functions)) { | |
553 | dev_err(pctl->dev, "invalid pins value.\n"); | |
554 | err = -EINVAL; | |
b04a23b0 | 555 | goto exit; |
a6df410d HY |
556 | } |
557 | ||
558 | grp = mtk_pctrl_find_group_by_pin(pctl, pin); | |
559 | if (!grp) { | |
560 | dev_err(pctl->dev, "unable to match pin %d to group\n", | |
561 | pin); | |
b04a23b0 HY |
562 | err = -EINVAL; |
563 | goto exit; | |
a6df410d HY |
564 | } |
565 | ||
566 | err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, | |
567 | reserved_maps, num_maps); | |
568 | if (err < 0) | |
b04a23b0 | 569 | goto exit; |
a6df410d HY |
570 | |
571 | if (has_config) { | |
572 | err = pinctrl_utils_add_map_configs(pctldev, map, | |
573 | reserved_maps, num_maps, grp->name, | |
574 | configs, num_configs, | |
575 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
576 | if (err < 0) | |
b04a23b0 | 577 | goto exit; |
a6df410d HY |
578 | } |
579 | } | |
580 | ||
b04a23b0 | 581 | err = 0; |
a6df410d | 582 | |
b04a23b0 HY |
583 | exit: |
584 | kfree(configs); | |
a6df410d HY |
585 | return err; |
586 | } | |
587 | ||
588 | static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
589 | struct device_node *np_config, | |
590 | struct pinctrl_map **map, unsigned *num_maps) | |
591 | { | |
592 | struct device_node *np; | |
593 | unsigned reserved_maps; | |
594 | int ret; | |
595 | ||
596 | *map = NULL; | |
597 | *num_maps = 0; | |
598 | reserved_maps = 0; | |
599 | ||
600 | for_each_child_of_node(np_config, np) { | |
601 | ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map, | |
602 | &reserved_maps, num_maps); | |
603 | if (ret < 0) { | |
d32f7fd3 | 604 | pinctrl_utils_free_map(pctldev, *map, *num_maps); |
4fc8a4b2 | 605 | of_node_put(np); |
a6df410d HY |
606 | return ret; |
607 | } | |
608 | } | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
613 | static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
614 | { | |
615 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
616 | ||
617 | return pctl->ngroups; | |
618 | } | |
619 | ||
620 | static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, | |
621 | unsigned group) | |
622 | { | |
623 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
624 | ||
625 | return pctl->groups[group].name; | |
626 | } | |
627 | ||
628 | static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
629 | unsigned group, | |
630 | const unsigned **pins, | |
631 | unsigned *num_pins) | |
632 | { | |
633 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
634 | ||
635 | *pins = (unsigned *)&pctl->groups[group].pin; | |
636 | *num_pins = 1; | |
637 | ||
638 | return 0; | |
639 | } | |
640 | ||
641 | static const struct pinctrl_ops mtk_pctrl_ops = { | |
642 | .dt_node_to_map = mtk_pctrl_dt_node_to_map, | |
d32f7fd3 | 643 | .dt_free_map = pinctrl_utils_free_map, |
a6df410d HY |
644 | .get_groups_count = mtk_pctrl_get_groups_count, |
645 | .get_group_name = mtk_pctrl_get_group_name, | |
646 | .get_group_pins = mtk_pctrl_get_group_pins, | |
647 | }; | |
648 | ||
649 | static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) | |
650 | { | |
651 | return ARRAY_SIZE(mtk_gpio_functions); | |
652 | } | |
653 | ||
654 | static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
655 | unsigned selector) | |
656 | { | |
657 | return mtk_gpio_functions[selector]; | |
658 | } | |
659 | ||
660 | static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
661 | unsigned function, | |
662 | const char * const **groups, | |
663 | unsigned * const num_groups) | |
664 | { | |
665 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
666 | ||
667 | *groups = pctl->grp_names; | |
668 | *num_groups = pctl->ngroups; | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
673 | static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, | |
674 | unsigned long pin, unsigned long mode) | |
675 | { | |
676 | unsigned int reg_addr; | |
677 | unsigned char bit; | |
678 | unsigned int val; | |
679 | unsigned int mask = (1L << GPIO_MODE_BITS) - 1; | |
680 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
681 | ||
148b95ee BH |
682 | if (pctl->devdata->spec_pinmux_set) |
683 | pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin), | |
684 | pin, mode); | |
685 | ||
a6df410d HY |
686 | reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf) |
687 | + pctl->devdata->pinmux_offset; | |
688 | ||
148b95ee | 689 | mode &= mask; |
a6df410d HY |
690 | bit = pin % MAX_GPIO_MODE_PER_REG; |
691 | mask <<= (GPIO_MODE_BITS * bit); | |
692 | val = (mode << (GPIO_MODE_BITS * bit)); | |
693 | return regmap_update_bits(mtk_get_regmap(pctl, pin), | |
694 | reg_addr, mask, val); | |
695 | } | |
696 | ||
d9819eb9 MM |
697 | static const struct mtk_desc_pin * |
698 | mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num) | |
699 | { | |
700 | int i; | |
701 | const struct mtk_desc_pin *pin; | |
702 | ||
703 | for (i = 0; i < pctl->devdata->npins; i++) { | |
704 | pin = pctl->devdata->pins + i; | |
705 | if (pin->eint.eintnum == eint_num) | |
706 | return pin; | |
707 | } | |
708 | ||
709 | return NULL; | |
710 | } | |
711 | ||
a6df410d HY |
712 | static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, |
713 | unsigned function, | |
714 | unsigned group) | |
715 | { | |
716 | bool ret; | |
717 | const struct mtk_desc_function *desc; | |
718 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
719 | struct mtk_pinctrl_group *g = pctl->groups + group; | |
720 | ||
721 | ret = mtk_pctrl_is_function_valid(pctl, g->pin, function); | |
722 | if (!ret) { | |
c70336cc | 723 | dev_err(pctl->dev, "invalid function %d on group %d .\n", |
a6df410d HY |
724 | function, group); |
725 | return -EINVAL; | |
726 | } | |
727 | ||
728 | desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function); | |
729 | if (!desc) | |
730 | return -EINVAL; | |
731 | mtk_pmx_set_mode(pctldev, g->pin, desc->muxval); | |
732 | return 0; | |
733 | } | |
734 | ||
59ee9c96 BH |
735 | static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl, |
736 | unsigned offset) | |
737 | { | |
738 | const struct mtk_desc_pin *pin = pctl->devdata->pins + offset; | |
739 | const struct mtk_desc_function *func = pin->functions; | |
740 | ||
741 | while (func && func->name) { | |
742 | if (!strncmp(func->name, GPIO_MODE_PREFIX, | |
743 | sizeof(GPIO_MODE_PREFIX)-1)) | |
744 | return func->muxval; | |
745 | func++; | |
746 | } | |
747 | return -EINVAL; | |
748 | } | |
749 | ||
750 | static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, | |
751 | struct pinctrl_gpio_range *range, | |
752 | unsigned offset) | |
753 | { | |
740f5b08 | 754 | int muxval; |
59ee9c96 BH |
755 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
756 | ||
757 | muxval = mtk_pmx_find_gpio_mode(pctl, offset); | |
758 | ||
759 | if (muxval < 0) { | |
760 | dev_err(pctl->dev, "invalid gpio pin %d.\n", offset); | |
761 | return -EINVAL; | |
762 | } | |
763 | ||
764 | mtk_pmx_set_mode(pctldev, offset, muxval); | |
31763d3b | 765 | mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE); |
59ee9c96 BH |
766 | |
767 | return 0; | |
768 | } | |
769 | ||
a6df410d HY |
770 | static const struct pinmux_ops mtk_pmx_ops = { |
771 | .get_functions_count = mtk_pmx_get_funcs_cnt, | |
772 | .get_function_name = mtk_pmx_get_func_name, | |
773 | .get_function_groups = mtk_pmx_get_func_groups, | |
774 | .set_mux = mtk_pmx_set_mux, | |
775 | .gpio_set_direction = mtk_pmx_gpio_set_direction, | |
59ee9c96 | 776 | .gpio_request_enable = mtk_pmx_gpio_request_enable, |
a6df410d HY |
777 | }; |
778 | ||
a6df410d HY |
779 | static int mtk_gpio_direction_input(struct gpio_chip *chip, |
780 | unsigned offset) | |
781 | { | |
782 | return pinctrl_gpio_direction_input(chip->base + offset); | |
783 | } | |
784 | ||
785 | static int mtk_gpio_direction_output(struct gpio_chip *chip, | |
786 | unsigned offset, int value) | |
787 | { | |
788 | mtk_gpio_set(chip, offset, value); | |
789 | return pinctrl_gpio_direction_output(chip->base + offset); | |
790 | } | |
791 | ||
792 | static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) | |
793 | { | |
794 | unsigned int reg_addr; | |
795 | unsigned int bit; | |
796 | unsigned int read_val = 0; | |
797 | ||
11aa679a | 798 | struct mtk_pinctrl *pctl = gpiochip_get_data(chip); |
a6df410d HY |
799 | |
800 | reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; | |
801 | bit = BIT(offset & 0xf); | |
148b95ee BH |
802 | |
803 | if (pctl->devdata->spec_dir_set) | |
804 | pctl->devdata->spec_dir_set(®_addr, offset); | |
805 | ||
a6df410d | 806 | regmap_read(pctl->regmap1, reg_addr, &read_val); |
3c827873 MV |
807 | if (read_val & bit) |
808 | return GPIO_LINE_DIRECTION_OUT; | |
809 | ||
810 | return GPIO_LINE_DIRECTION_IN; | |
a6df410d HY |
811 | } |
812 | ||
813 | static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) | |
814 | { | |
815 | unsigned int reg_addr; | |
816 | unsigned int bit; | |
817 | unsigned int read_val = 0; | |
11aa679a | 818 | struct mtk_pinctrl *pctl = gpiochip_get_data(chip); |
a6df410d | 819 | |
f97c2309 HY |
820 | reg_addr = mtk_get_port(pctl, offset) + |
821 | pctl->devdata->din_offset; | |
a6df410d HY |
822 | |
823 | bit = BIT(offset & 0xf); | |
824 | regmap_read(pctl->regmap1, reg_addr, &read_val); | |
825 | return !!(read_val & bit); | |
826 | } | |
827 | ||
d9819eb9 MM |
828 | static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
829 | { | |
11aa679a | 830 | struct mtk_pinctrl *pctl = gpiochip_get_data(chip); |
d9819eb9 | 831 | const struct mtk_desc_pin *pin; |
e46df235 | 832 | unsigned long eint_n; |
d9819eb9 MM |
833 | |
834 | pin = pctl->devdata->pins + offset; | |
835 | if (pin->eint.eintnum == NO_EINT_SUPPORT) | |
836 | return -EINVAL; | |
837 | ||
e46df235 | 838 | eint_n = pin->eint.eintnum; |
d9819eb9 | 839 | |
e46df235 | 840 | return mtk_eint_find_irq(pctl->eint, eint_n); |
d9819eb9 MM |
841 | } |
842 | ||
2956b5d9 MW |
843 | static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
844 | unsigned long config) | |
845 | { | |
e46df235 SW |
846 | struct mtk_pinctrl *pctl = gpiochip_get_data(chip); |
847 | const struct mtk_desc_pin *pin; | |
848 | unsigned long eint_n; | |
2956b5d9 MW |
849 | u32 debounce; |
850 | ||
851 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
852 | return -ENOTSUPP; | |
853 | ||
e46df235 SW |
854 | pin = pctl->devdata->pins + offset; |
855 | if (pin->eint.eintnum == NO_EINT_SUPPORT) | |
856 | return -EINVAL; | |
857 | ||
2956b5d9 | 858 | debounce = pinconf_to_config_argument(config); |
e46df235 SW |
859 | eint_n = pin->eint.eintnum; |
860 | ||
861 | return mtk_eint_set_debounce(pctl->eint, eint_n, debounce); | |
2956b5d9 MW |
862 | } |
863 | ||
03e9888f | 864 | static const struct gpio_chip mtk_gpio_chip = { |
a6df410d | 865 | .owner = THIS_MODULE, |
98c85d58 JG |
866 | .request = gpiochip_generic_request, |
867 | .free = gpiochip_generic_free, | |
f97c2309 | 868 | .get_direction = mtk_gpio_get_direction, |
a6df410d HY |
869 | .direction_input = mtk_gpio_direction_input, |
870 | .direction_output = mtk_gpio_direction_output, | |
871 | .get = mtk_gpio_get, | |
872 | .set = mtk_gpio_set, | |
d9819eb9 | 873 | .to_irq = mtk_gpio_to_irq, |
2956b5d9 | 874 | .set_config = mtk_gpio_set_config, |
a6df410d HY |
875 | .of_gpio_n_cells = 2, |
876 | }; | |
877 | ||
58a5e1b6 MM |
878 | static int mtk_eint_suspend(struct device *device) |
879 | { | |
58a5e1b6 | 880 | struct mtk_pinctrl *pctl = dev_get_drvdata(device); |
58a5e1b6 | 881 | |
e46df235 | 882 | return mtk_eint_do_suspend(pctl->eint); |
58a5e1b6 MM |
883 | } |
884 | ||
885 | static int mtk_eint_resume(struct device *device) | |
886 | { | |
887 | struct mtk_pinctrl *pctl = dev_get_drvdata(device); | |
58a5e1b6 | 888 | |
e46df235 | 889 | return mtk_eint_do_resume(pctl->eint); |
58a5e1b6 MM |
890 | } |
891 | ||
892 | const struct dev_pm_ops mtk_eint_pm_ops = { | |
d2fcd62a | 893 | .suspend_noirq = mtk_eint_suspend, |
894 | .resume_noirq = mtk_eint_resume, | |
58a5e1b6 MM |
895 | }; |
896 | ||
a6df410d HY |
897 | static int mtk_pctrl_build_state(struct platform_device *pdev) |
898 | { | |
899 | struct mtk_pinctrl *pctl = platform_get_drvdata(pdev); | |
900 | int i; | |
901 | ||
902 | pctl->ngroups = pctl->devdata->npins; | |
903 | ||
904 | /* Allocate groups */ | |
0206caa8 AL |
905 | pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, |
906 | sizeof(*pctl->groups), GFP_KERNEL); | |
a6df410d HY |
907 | if (!pctl->groups) |
908 | return -ENOMEM; | |
909 | ||
910 | /* We assume that one pin is one group, use pin name as group name. */ | |
0206caa8 AL |
911 | pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, |
912 | sizeof(*pctl->grp_names), GFP_KERNEL); | |
a6df410d HY |
913 | if (!pctl->grp_names) |
914 | return -ENOMEM; | |
915 | ||
916 | for (i = 0; i < pctl->devdata->npins; i++) { | |
917 | const struct mtk_desc_pin *pin = pctl->devdata->pins + i; | |
918 | struct mtk_pinctrl_group *group = pctl->groups + i; | |
919 | ||
920 | group->name = pin->pin.name; | |
921 | group->pin = pin->pin.number; | |
922 | ||
923 | pctl->grp_names[i] = pin->pin.name; | |
924 | } | |
925 | ||
926 | return 0; | |
927 | } | |
928 | ||
e46df235 SW |
929 | static int |
930 | mtk_xt_get_gpio_n(void *data, unsigned long eint_n, unsigned int *gpio_n, | |
931 | struct gpio_chip **gpio_chip) | |
932 | { | |
933 | struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data; | |
934 | const struct mtk_desc_pin *pin; | |
935 | ||
936 | pin = mtk_find_pin_by_eint_num(pctl, eint_n); | |
937 | if (!pin) | |
938 | return -EINVAL; | |
939 | ||
940 | *gpio_chip = pctl->chip; | |
941 | *gpio_n = pin->pin.number; | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
946 | static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n) | |
947 | { | |
948 | struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data; | |
949 | const struct mtk_desc_pin *pin; | |
950 | ||
951 | pin = mtk_find_pin_by_eint_num(pctl, eint_n); | |
952 | if (!pin) | |
953 | return -EINVAL; | |
954 | ||
955 | return mtk_gpio_get(pctl->chip, pin->pin.number); | |
956 | } | |
957 | ||
958 | static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n) | |
959 | { | |
960 | struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data; | |
961 | const struct mtk_desc_pin *pin; | |
962 | ||
963 | pin = mtk_find_pin_by_eint_num(pctl, eint_n); | |
964 | if (!pin) | |
965 | return -EINVAL; | |
966 | ||
967 | /* set mux to INT mode */ | |
968 | mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux); | |
969 | /* set gpio direction to input */ | |
970 | mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, | |
971 | true); | |
972 | /* set input-enable */ | |
973 | mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, | |
974 | PIN_CONFIG_INPUT_ENABLE); | |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
979 | static const struct mtk_eint_xt mtk_eint_xt = { | |
980 | .get_gpio_n = mtk_xt_get_gpio_n, | |
981 | .get_gpio_state = mtk_xt_get_gpio_state, | |
982 | .set_gpio_as_eint = mtk_xt_set_gpio_as_eint, | |
983 | }; | |
984 | ||
985 | static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev) | |
986 | { | |
987 | struct device_node *np = pdev->dev.of_node; | |
e46df235 SW |
988 | |
989 | if (!of_property_read_bool(np, "interrupt-controller")) | |
990 | return -ENODEV; | |
991 | ||
992 | pctl->eint = devm_kzalloc(pctl->dev, sizeof(*pctl->eint), GFP_KERNEL); | |
993 | if (!pctl->eint) | |
994 | return -ENOMEM; | |
995 | ||
65713177 | 996 | pctl->eint->base = devm_platform_ioremap_resource(pdev, 0); |
e46df235 SW |
997 | if (IS_ERR(pctl->eint->base)) |
998 | return PTR_ERR(pctl->eint->base); | |
999 | ||
1000 | pctl->eint->irq = irq_of_parse_and_map(np, 0); | |
1001 | if (!pctl->eint->irq) | |
1002 | return -EINVAL; | |
1003 | ||
1004 | pctl->eint->dev = &pdev->dev; | |
e6612a69 SW |
1005 | /* |
1006 | * If pctl->eint->regs == NULL, it would fall back into using a generic | |
1007 | * register map in mtk_eint_do_init calls. | |
1008 | */ | |
1009 | pctl->eint->regs = pctl->devdata->eint_regs; | |
e46df235 SW |
1010 | pctl->eint->hw = &pctl->devdata->eint_hw; |
1011 | pctl->eint->pctl = pctl; | |
1012 | pctl->eint->gpio_xlate = &mtk_eint_xt; | |
1013 | ||
1014 | return mtk_eint_do_init(pctl->eint); | |
1015 | } | |
1016 | ||
a6df410d | 1017 | int mtk_pctrl_init(struct platform_device *pdev, |
fc59e66c HY |
1018 | const struct mtk_pinctrl_devdata *data, |
1019 | struct regmap *regmap) | |
a6df410d HY |
1020 | { |
1021 | struct pinctrl_pin_desc *pins; | |
1022 | struct mtk_pinctrl *pctl; | |
1023 | struct device_node *np = pdev->dev.of_node, *node; | |
1024 | struct property *prop; | |
e46df235 | 1025 | int ret, i; |
a6df410d HY |
1026 | |
1027 | pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); | |
1028 | if (!pctl) | |
1029 | return -ENOMEM; | |
1030 | ||
1031 | platform_set_drvdata(pdev, pctl); | |
1032 | ||
1033 | prop = of_find_property(np, "pins-are-numbered", NULL); | |
1034 | if (!prop) { | |
c445cac3 | 1035 | dev_err(&pdev->dev, "only support pins-are-numbered format\n"); |
a6df410d HY |
1036 | return -EINVAL; |
1037 | } | |
1038 | ||
1039 | node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); | |
1040 | if (node) { | |
1041 | pctl->regmap1 = syscon_node_to_regmap(node); | |
1042 | if (IS_ERR(pctl->regmap1)) | |
1043 | return PTR_ERR(pctl->regmap1); | |
fc59e66c HY |
1044 | } else if (regmap) { |
1045 | pctl->regmap1 = regmap; | |
1046 | } else { | |
1047 | dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n"); | |
1048 | return -EINVAL; | |
a6df410d HY |
1049 | } |
1050 | ||
1051 | /* Only 8135 has two base addr, other SoCs have only one. */ | |
1052 | node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); | |
1053 | if (node) { | |
1054 | pctl->regmap2 = syscon_node_to_regmap(node); | |
1055 | if (IS_ERR(pctl->regmap2)) | |
1056 | return PTR_ERR(pctl->regmap2); | |
1057 | } | |
1058 | ||
1059 | pctl->devdata = data; | |
1060 | ret = mtk_pctrl_build_state(pdev); | |
1061 | if (ret) { | |
1062 | dev_err(&pdev->dev, "build state failed: %d\n", ret); | |
1063 | return -EINVAL; | |
1064 | } | |
1065 | ||
0206caa8 | 1066 | pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins), |
a6df410d HY |
1067 | GFP_KERNEL); |
1068 | if (!pins) | |
1069 | return -ENOMEM; | |
1070 | ||
1071 | for (i = 0; i < pctl->devdata->npins; i++) | |
1072 | pins[i] = pctl->devdata->pins[i].pin; | |
d48c2c02 HY |
1073 | |
1074 | pctl->pctl_desc.name = dev_name(&pdev->dev); | |
1075 | pctl->pctl_desc.owner = THIS_MODULE; | |
1076 | pctl->pctl_desc.pins = pins; | |
1077 | pctl->pctl_desc.npins = pctl->devdata->npins; | |
1078 | pctl->pctl_desc.confops = &mtk_pconf_ops; | |
1079 | pctl->pctl_desc.pctlops = &mtk_pctrl_ops; | |
1080 | pctl->pctl_desc.pmxops = &mtk_pmx_ops; | |
a6df410d | 1081 | pctl->dev = &pdev->dev; |
d48c2c02 | 1082 | |
03a3a558 LD |
1083 | pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, |
1084 | pctl); | |
323de9ef | 1085 | if (IS_ERR(pctl->pctl_dev)) { |
a6df410d | 1086 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); |
323de9ef | 1087 | return PTR_ERR(pctl->pctl_dev); |
a6df410d HY |
1088 | } |
1089 | ||
1090 | pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); | |
03a3a558 LD |
1091 | if (!pctl->chip) |
1092 | return -ENOMEM; | |
a6df410d | 1093 | |
fc63d854 | 1094 | *pctl->chip = mtk_gpio_chip; |
a6df410d HY |
1095 | pctl->chip->ngpio = pctl->devdata->npins; |
1096 | pctl->chip->label = dev_name(&pdev->dev); | |
58383c78 | 1097 | pctl->chip->parent = &pdev->dev; |
fc59e66c | 1098 | pctl->chip->base = -1; |
a6df410d | 1099 | |
11aa679a | 1100 | ret = gpiochip_add_data(pctl->chip, pctl); |
03a3a558 LD |
1101 | if (ret) |
1102 | return -EINVAL; | |
a6df410d HY |
1103 | |
1104 | /* Register the GPIO to pin mappings. */ | |
1105 | ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), | |
1106 | 0, 0, pctl->devdata->npins); | |
1107 | if (ret) { | |
1108 | ret = -EINVAL; | |
1109 | goto chip_error; | |
1110 | } | |
1111 | ||
e46df235 SW |
1112 | ret = mtk_eint_init(pctl, pdev); |
1113 | if (ret) | |
61a35576 | 1114 | goto chip_error; |
d9819eb9 | 1115 | |
a6df410d HY |
1116 | return 0; |
1117 | ||
1118 | chip_error: | |
1119 | gpiochip_remove(pctl->chip); | |
a6df410d HY |
1120 | return ret; |
1121 | } |