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pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq()
[linux-2.6-block.git] / drivers / pinctrl / mediatek / pinctrl-mtk-common.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
a6df410d
HY		 2/*
3 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
4 * Copyright (c) 2014 MediaTek Inc.
5 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
a6df410d
HY		 6 */
7
8#include <linux/io.h>
11aa679a 9#include <linux/gpio/driver.h>
a6df410d
HY		 10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/of_device.h>
13#include <linux/of_irq.h>
14#include <linux/pinctrl/consumer.h>
15#include <linux/pinctrl/machine.h>
16#include <linux/pinctrl/pinconf.h>
17#include <linux/pinctrl/pinconf-generic.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/platform_device.h>
21#include <linux/slab.h>
22#include <linux/bitops.h>
23#include <linux/regmap.h>
24#include <linux/mfd/syscon.h>
d9819eb9 25#include <linux/delay.h>
30f010f5 26#include <linux/interrupt.h>
58a5e1b6 27#include <linux/pm.h>
a6df410d
HY		 28#include <dt-bindings/pinctrl/mt65xx.h>
29
30#include "../core.h"
31#include "../pinconf.h"
32#include "../pinctrl-utils.h"
e46df235 33#include "mtk-eint.h"
a6df410d
HY		 34#include "pinctrl-mtk-common.h"
35
a6df410d 36#define GPIO_MODE_BITS 3
59ee9c96 37#define GPIO_MODE_PREFIX "GPIO"
a6df410d
HY		 38
39static const char * const mtk_gpio_functions[] = {
40 "func0", "func1", "func2", "func3",
41 "func4", "func5", "func6", "func7",
148b95ee
BH		 42 "func8", "func9", "func10", "func11",
43 "func12", "func13", "func14", "func15",
a6df410d
HY		 44};
45
46/*
47 * There are two base address for pull related configuration
48 * in mt8135, and different GPIO pins use different base address.
49 * When pin number greater than type1_start and less than type1_end,
50 * should use the second base address.
51 */
52static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
53 unsigned long pin)
54{
55 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
56 return pctl->regmap2;
57 return pctl->regmap1;
58}
59
60static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
61{
62 /* Different SoC has different mask and port shift. */
9f940d8e 63 return ((pin >> pctl->devdata->mode_shf) & pctl->devdata->port_mask)
a6df410d
HY		 64 << pctl->devdata->port_shf;
65}
66
67static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
68 struct pinctrl_gpio_range *range, unsigned offset,
69 bool input)
70{
71 unsigned int reg_addr;
72 unsigned int bit;
73 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
74
75 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
9f940d8e 76 bit = BIT(offset & pctl->devdata->mode_mask);
a6df410d 77
148b95ee
BH		 78 if (pctl->devdata->spec_dir_set)
79 pctl->devdata->spec_dir_set(&reg_addr, offset);
80
a6df410d
HY		 81 if (input)
82 /* Different SoC has different alignment offset. */
83 reg_addr = CLR_ADDR(reg_addr, pctl);
84 else
85 reg_addr = SET_ADDR(reg_addr, pctl);
86
87 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
88 return 0;
89}
90
91static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
92{
93 unsigned int reg_addr;
94 unsigned int bit;
11aa679a 95 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d
HY		 96
97 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
9f940d8e 98 bit = BIT(offset & pctl->devdata->mode_mask);
a6df410d
HY		 99
100 if (value)
101 reg_addr = SET_ADDR(reg_addr, pctl);
102 else
103 reg_addr = CLR_ADDR(reg_addr, pctl);
104
105 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
106}
107
25d76b21
HY		 108static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
109 int value, enum pin_config_param arg)
a6df410d
HY		 110{
111 unsigned int reg_addr, offset;
112 unsigned int bit;
25d76b21
HY		 113
114 /**
115 * Due to some soc are not support ies/smt config, add this special
116 * control to handle it.
117 */
118 if (!pctl->devdata->spec_ies_smt_set &&
119 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
120 arg == PIN_CONFIG_INPUT_ENABLE)
121 return -EINVAL;
122
123 if (!pctl->devdata->spec_ies_smt_set &&
124 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
125 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
126 return -EINVAL;
30f010f5
HY		 127
128 /*
129 * Due to some pins are irregular, their input enable and smt
25d76b21 130 * control register are discontinuous, so we need this special handle.
30f010f5
HY		 131 */
132 if (pctl->devdata->spec_ies_smt_set) {
25d76b21
HY		 133 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
134 pin, pctl->devdata->port_align, value, arg);
30f010f5 135 }
a6df410d 136
696beef7 137 bit = BIT(pin & 0xf);
a6df410d 138
25d76b21 139 if (arg == PIN_CONFIG_INPUT_ENABLE)
a6df410d
HY		 140 offset = pctl->devdata->ies_offset;
141 else
142 offset = pctl->devdata->smt_offset;
143
144 if (value)
145 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
146 else
147 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
148
149 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
25d76b21
HY		 150 return 0;
151}
152
153int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
154 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
155 unsigned int pin, unsigned char align, int value)
156{
157 unsigned int i, reg_addr, bit;
158
159 for (i = 0; i < info_num; i++) {
160 if (pin >= ies_smt_infos[i].start &&
161 pin <= ies_smt_infos[i].end) {
162 break;
163 }
164 }
165
166 if (i == info_num)
167 return -EINVAL;
168
169 if (value)
170 reg_addr = ies_smt_infos[i].offset + align;
171 else
172 reg_addr = ies_smt_infos[i].offset + (align << 1);
173
174 bit = BIT(ies_smt_infos[i].bit);
175 regmap_write(regmap, reg_addr, bit);
176 return 0;
a6df410d
HY		 177}
178
179static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
180 struct mtk_pinctrl *pctl, unsigned long pin) {
181 int i;
182
183 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
184 const struct mtk_pin_drv_grp *pin_drv =
185 pctl->devdata->pin_drv_grp + i;
186 if (pin == pin_drv->pin)
187 return pin_drv;
188 }
189
190 return NULL;
191}
192
193static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
194 unsigned int pin, unsigned char driving)
195{
196 const struct mtk_pin_drv_grp *pin_drv;
197 unsigned int val;
198 unsigned int bits, mask, shift;
199 const struct mtk_drv_group_desc *drv_grp;
200
201 if (pin >= pctl->devdata->npins)
202 return -EINVAL;
203
204 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
205 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
206 return -EINVAL;
207
208 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
209 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
210 && !(driving % drv_grp->step)) {
211 val = driving / drv_grp->step - 1;
212 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
213 mask = BIT(bits) - 1;
214 shift = pin_drv->bit + drv_grp->low_bit;
215 mask <<= shift;
216 val <<= shift;
217 return regmap_update_bits(mtk_get_regmap(pctl, pin),
218 pin_drv->offset, mask, val);
219 }
220
221 return -EINVAL;
222}
223
e73fe271
YC		 224int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
225 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
226 unsigned int info_num, unsigned int pin,
227 unsigned char align, bool isup, unsigned int r1r0)
228{
229 unsigned int i;
230 unsigned int reg_pupd, reg_set, reg_rst;
231 unsigned int bit_pupd, bit_r0, bit_r1;
232 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
233 bool find = false;
234
235 for (i = 0; i < info_num; i++) {
236 if (pin == pupd_infos[i].pin) {
237 find = true;
238 break;
239 }
240 }
241
242 if (!find)
243 return -EINVAL;
244
245 spec_pupd_pin = pupd_infos + i;
246 reg_set = spec_pupd_pin->offset + align;
247 reg_rst = spec_pupd_pin->offset + (align << 1);
248
249 if (isup)
250 reg_pupd = reg_rst;
251 else
252 reg_pupd = reg_set;
253
254 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
255 regmap_write(regmap, reg_pupd, bit_pupd);
256
257 bit_r0 = BIT(spec_pupd_pin->r0_bit);
258 bit_r1 = BIT(spec_pupd_pin->r1_bit);
259
260 switch (r1r0) {
261 case MTK_PUPD_SET_R1R0_00:
262 regmap_write(regmap, reg_rst, bit_r0);
263 regmap_write(regmap, reg_rst, bit_r1);
264 break;
265 case MTK_PUPD_SET_R1R0_01:
266 regmap_write(regmap, reg_set, bit_r0);
267 regmap_write(regmap, reg_rst, bit_r1);
268 break;
269 case MTK_PUPD_SET_R1R0_10:
270 regmap_write(regmap, reg_rst, bit_r0);
271 regmap_write(regmap, reg_set, bit_r1);
272 break;
273 case MTK_PUPD_SET_R1R0_11:
274 regmap_write(regmap, reg_set, bit_r0);
275 regmap_write(regmap, reg_set, bit_r1);
276 break;
277 default:
278 return -EINVAL;
279 }
280
281 return 0;
282}
283
a6df410d
HY		 284static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
285 unsigned int pin, bool enable, bool isup, unsigned int arg)
286{
287 unsigned int bit;
6af8df4c 288 unsigned int reg_pullen, reg_pullsel, r1r0;
a6df410d
HY		 289 int ret;
290
291 /* Some pins' pull setting are very different,
292 * they have separate pull up/down bit, R0 and R1
293 * resistor bit, so we need this special handle.
294 */
295 if (pctl->devdata->spec_pull_set) {
6af8df4c
ZT		 296 /* For special pins, bias-disable is set by R1R0,
297 * the parameter should be "MTK_PUPD_SET_R1R0_00".
298 */
299 r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
a6df410d 300 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
6af8df4c 301 pin, pctl->devdata->port_align, isup, r1r0);
a6df410d
HY		 302 if (!ret)
303 return 0;
304 }
305
306 /* For generic pull config, default arg value should be 0 or 1. */
307 if (arg != 0 && arg != 1) {
308 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
309 arg, pin);
310 return -EINVAL;
311 }
312
9f940d8e 313 bit = BIT(pin & pctl->devdata->mode_mask);
a6df410d
HY		 314 if (enable)
315 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
316 pctl->devdata->pullen_offset, pctl);
317 else
318 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
319 pctl->devdata->pullen_offset, pctl);
320
321 if (isup)
322 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
323 pctl->devdata->pullsel_offset, pctl);
324 else
325 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
326 pctl->devdata->pullsel_offset, pctl);
327
328 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
329 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
330 return 0;
331}
332
333static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
334 unsigned int pin, enum pin_config_param param,
335 enum pin_config_param arg)
336{
25d76b21 337 int ret = 0;
a6df410d
HY		 338 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
339
340 switch (param) {
341 case PIN_CONFIG_BIAS_DISABLE:
25d76b21 342 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
a6df410d
HY		 343 break;
344 case PIN_CONFIG_BIAS_PULL_UP:
25d76b21 345 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
a6df410d
HY		 346 break;
347 case PIN_CONFIG_BIAS_PULL_DOWN:
25d76b21 348 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
a6df410d
HY		 349 break;
350 case PIN_CONFIG_INPUT_ENABLE:
eceb3e61 351 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
25d76b21 352 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 353 break;
354 case PIN_CONFIG_OUTPUT:
355 mtk_gpio_set(pctl->chip, pin, arg);
25d76b21 356 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
a6df410d
HY		 357 break;
358 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
eceb3e61 359 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
25d76b21 360 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 361 break;
362 case PIN_CONFIG_DRIVE_STRENGTH:
25d76b21 363 ret = mtk_pconf_set_driving(pctl, pin, arg);
a6df410d
HY		 364 break;
365 default:
25d76b21 366 ret = -EINVAL;
a6df410d
HY		 367 }
368
25d76b21 369 return ret;
a6df410d
HY		 370}
371
372static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
373 unsigned group,
374 unsigned long *config)
375{
376 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
377
378 *config = pctl->groups[group].config;
379
380 return 0;
381}
382
383static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
384 unsigned long *configs, unsigned num_configs)
385{
386 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
387 struct mtk_pinctrl_group *g = &pctl->groups[group];
25d76b21 388 int i, ret;
a6df410d
HY		 389
390 for (i = 0; i < num_configs; i++) {
25d76b21 391 ret = mtk_pconf_parse_conf(pctldev, g->pin,
a6df410d
HY		 392 pinconf_to_config_param(configs[i]),
393 pinconf_to_config_argument(configs[i]));
25d76b21
HY		 394 if (ret < 0)
395 return ret;
a6df410d
HY		 396
397 g->config = configs[i];
398 }
399
400 return 0;
401}
402
403static const struct pinconf_ops mtk_pconf_ops = {
404 .pin_config_group_get = mtk_pconf_group_get,
405 .pin_config_group_set = mtk_pconf_group_set,
406};
407
408static struct mtk_pinctrl_group *
409mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
410{
411 int i;
412
413 for (i = 0; i < pctl->ngroups; i++) {
414 struct mtk_pinctrl_group *grp = pctl->groups + i;
415
416 if (grp->pin == pin)
417 return grp;
418 }
419
420 return NULL;
421}
422
423static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
424 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
425{
426 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
427 const struct mtk_desc_function *func = pin->functions;
428
429 while (func && func->name) {
430 if (func->muxval == fnum)
431 return func;
432 func++;
433 }
434
435 return NULL;
436}
437
438static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
439 u32 pin_num, u32 fnum)
440{
441 int i;
442
443 for (i = 0; i < pctl->devdata->npins; i++) {
444 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
445
446 if (pin->pin.number == pin_num) {
447 const struct mtk_desc_function *func =
448 pin->functions;
449
450 while (func && func->name) {
451 if (func->muxval == fnum)
452 return true;
453 func++;
454 }
455
456 break;
457 }
458 }
459
460 return false;
461}
462
463static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
464 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
465 struct pinctrl_map **map, unsigned *reserved_maps,
466 unsigned *num_maps)
467{
468 bool ret;
469
470 if (*num_maps == *reserved_maps)
471 return -ENOSPC;
472
473 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
474 (*map)[*num_maps].data.mux.group = grp->name;
475
476 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
477 if (!ret) {
478 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
479 fnum, pin);
480 return -EINVAL;
481 }
482
483 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
484 (*num_maps)++;
485
486 return 0;
487}
488
489static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
490 struct device_node *node,
491 struct pinctrl_map **map,
492 unsigned *reserved_maps,
493 unsigned *num_maps)
494{
495 struct property *pins;
496 u32 pinfunc, pin, func;
497 int num_pins, num_funcs, maps_per_pin;
498 unsigned long *configs;
499 unsigned int num_configs;
b2f78906 500 bool has_config = false;
a6df410d
HY		 501 int i, err;
502 unsigned reserve = 0;
503 struct mtk_pinctrl_group *grp;
504 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
505
506 pins = of_find_property(node, "pinmux", NULL);
507 if (!pins) {
94f4e54c
RH		 508 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
509 node);
a6df410d
HY		 510 return -EINVAL;
511 }
512
c445cac3
HY		 513 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
514 &num_configs);
b04a23b0
HY		 515 if (err)
516 return err;
517
a6df410d 518 if (num_configs)
b2f78906 519 has_config = true;
a6df410d
HY		 520
521 num_pins = pins->length / sizeof(u32);
522 num_funcs = num_pins;
523 maps_per_pin = 0;
524 if (num_funcs)
525 maps_per_pin++;
526 if (has_config && num_pins >= 1)
527 maps_per_pin++;
528
b04a23b0
HY		 529 if (!num_pins || !maps_per_pin) {
530 err = -EINVAL;
531 goto exit;
532 }
a6df410d
HY		 533
534 reserve = num_pins * maps_per_pin;
535
536 err = pinctrl_utils_reserve_map(pctldev, map,
537 reserved_maps, num_maps, reserve);
538 if (err < 0)
b04a23b0 539 goto exit;
a6df410d
HY		 540
541 for (i = 0; i < num_pins; i++) {
542 err = of_property_read_u32_index(node, "pinmux",
543 i, &pinfunc);
544 if (err)
b04a23b0 545 goto exit;
a6df410d
HY		 546
547 pin = MTK_GET_PIN_NO(pinfunc);
548 func = MTK_GET_PIN_FUNC(pinfunc);
549
550 if (pin >= pctl->devdata->npins ||
551 func >= ARRAY_SIZE(mtk_gpio_functions)) {
552 dev_err(pctl->dev, "invalid pins value.\n");
553 err = -EINVAL;
b04a23b0 554 goto exit;
a6df410d
HY		 555 }
556
557 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
558 if (!grp) {
559 dev_err(pctl->dev, "unable to match pin %d to group\n",
560 pin);
b04a23b0
HY		 561 err = -EINVAL;
562 goto exit;
a6df410d
HY		 563 }
564
565 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
566 reserved_maps, num_maps);
567 if (err < 0)
b04a23b0 568 goto exit;
a6df410d
HY		 569
570 if (has_config) {
571 err = pinctrl_utils_add_map_configs(pctldev, map,
572 reserved_maps, num_maps, grp->name,
573 configs, num_configs,
574 PIN_MAP_TYPE_CONFIGS_GROUP);
575 if (err < 0)
b04a23b0 576 goto exit;
a6df410d
HY		 577 }
578 }
579
b04a23b0 580 err = 0;
a6df410d 581
b04a23b0
HY		 582exit:
583 kfree(configs);
a6df410d
HY		 584 return err;
585}
586
587static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
588 struct device_node *np_config,
589 struct pinctrl_map **map, unsigned *num_maps)
590{
591 struct device_node *np;
592 unsigned reserved_maps;
593 int ret;
594
595 *map = NULL;
596 *num_maps = 0;
597 reserved_maps = 0;
598
599 for_each_child_of_node(np_config, np) {
600 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
601 &reserved_maps, num_maps);
602 if (ret < 0) {
d32f7fd3 603 pinctrl_utils_free_map(pctldev, *map, *num_maps);
4fc8a4b2 604 of_node_put(np);
a6df410d
HY		 605 return ret;
606 }
607 }
608
609 return 0;
610}
611
612static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
613{
614 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
615
616 return pctl->ngroups;
617}
618
619static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
620 unsigned group)
621{
622 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
623
624 return pctl->groups[group].name;
625}
626
627static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
628 unsigned group,
629 const unsigned **pins,
630 unsigned *num_pins)
631{
632 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
633
634 *pins = (unsigned *)&pctl->groups[group].pin;
635 *num_pins = 1;
636
637 return 0;
638}
639
640static const struct pinctrl_ops mtk_pctrl_ops = {
641 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
d32f7fd3 642 .dt_free_map = pinctrl_utils_free_map,
a6df410d
HY		 643 .get_groups_count = mtk_pctrl_get_groups_count,
644 .get_group_name = mtk_pctrl_get_group_name,
645 .get_group_pins = mtk_pctrl_get_group_pins,
646};
647
648static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
649{
650 return ARRAY_SIZE(mtk_gpio_functions);
651}
652
653static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
654 unsigned selector)
655{
656 return mtk_gpio_functions[selector];
657}
658
659static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
660 unsigned function,
661 const char * const **groups,
662 unsigned * const num_groups)
663{
664 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
665
666 *groups = pctl->grp_names;
667 *num_groups = pctl->ngroups;
668
669 return 0;
670}
671
672static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
673 unsigned long pin, unsigned long mode)
674{
675 unsigned int reg_addr;
676 unsigned char bit;
677 unsigned int val;
678 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
679 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
680
148b95ee
BH		 681 if (pctl->devdata->spec_pinmux_set)
682 pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
683 pin, mode);
684
9f940d8e 685 reg_addr = ((pin / pctl->devdata->mode_per_reg) << pctl->devdata->port_shf)
a6df410d
HY		 686 + pctl->devdata->pinmux_offset;
687
148b95ee 688 mode &= mask;
9f940d8e 689 bit = pin % pctl->devdata->mode_per_reg;
a6df410d
HY		 690 mask <<= (GPIO_MODE_BITS * bit);
691 val = (mode << (GPIO_MODE_BITS * bit));
692 return regmap_update_bits(mtk_get_regmap(pctl, pin),
693 reg_addr, mask, val);
694}
695
d9819eb9
MM		 696static const struct mtk_desc_pin *
697mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
698{
699 int i;
700 const struct mtk_desc_pin *pin;
701
702 for (i = 0; i < pctl->devdata->npins; i++) {
703 pin = pctl->devdata->pins + i;
704 if (pin->eint.eintnum == eint_num)
705 return pin;
706 }
707
708 return NULL;
709}
710
a6df410d
HY		 711static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
712 unsigned function,
713 unsigned group)
714{
715 bool ret;
716 const struct mtk_desc_function *desc;
717 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
718 struct mtk_pinctrl_group *g = pctl->groups + group;
719
720 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
721 if (!ret) {
c70336cc 722 dev_err(pctl->dev, "invalid function %d on group %d .\n",
a6df410d
HY		 723 function, group);
724 return -EINVAL;
725 }
726
727 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
728 if (!desc)
729 return -EINVAL;
730 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
731 return 0;
732}
733
59ee9c96
BH		 734static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
735 unsigned offset)
736{
737 const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
738 const struct mtk_desc_function *func = pin->functions;
739
740 while (func && func->name) {
741 if (!strncmp(func->name, GPIO_MODE_PREFIX,
742 sizeof(GPIO_MODE_PREFIX)-1))
743 return func->muxval;
744 func++;
745 }
746 return -EINVAL;
747}
748
749static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
750 struct pinctrl_gpio_range *range,
751 unsigned offset)
752{
740f5b08 753 int muxval;
59ee9c96
BH		 754 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
755
756 muxval = mtk_pmx_find_gpio_mode(pctl, offset);
757
758 if (muxval < 0) {
759 dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
760 return -EINVAL;
761 }
762
763 mtk_pmx_set_mode(pctldev, offset, muxval);
31763d3b 764 mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
59ee9c96
BH		 765
766 return 0;
767}
768
a6df410d
HY		 769static const struct pinmux_ops mtk_pmx_ops = {
770 .get_functions_count = mtk_pmx_get_funcs_cnt,
771 .get_function_name = mtk_pmx_get_func_name,
772 .get_function_groups = mtk_pmx_get_func_groups,
773 .set_mux = mtk_pmx_set_mux,
774 .gpio_set_direction = mtk_pmx_gpio_set_direction,
59ee9c96 775 .gpio_request_enable = mtk_pmx_gpio_request_enable,
a6df410d
HY		 776};
777
a6df410d
HY		 778static int mtk_gpio_direction_input(struct gpio_chip *chip,
779 unsigned offset)
780{
781 return pinctrl_gpio_direction_input(chip->base + offset);
782}
783
784static int mtk_gpio_direction_output(struct gpio_chip *chip,
785 unsigned offset, int value)
786{
787 mtk_gpio_set(chip, offset, value);
788 return pinctrl_gpio_direction_output(chip->base + offset);
789}
790
791static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
792{
793 unsigned int reg_addr;
794 unsigned int bit;
795 unsigned int read_val = 0;
796
11aa679a 797 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d
HY		 798
799 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
9f940d8e 800 bit = BIT(offset & pctl->devdata->mode_mask);
148b95ee
BH		 801
802 if (pctl->devdata->spec_dir_set)
803 pctl->devdata->spec_dir_set(&reg_addr, offset);
804
a6df410d 805 regmap_read(pctl->regmap1, reg_addr, &read_val);
3c827873
MV		 806 if (read_val & bit)
807 return GPIO_LINE_DIRECTION_OUT;
808
809 return GPIO_LINE_DIRECTION_IN;
a6df410d
HY		 810}
811
812static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
813{
814 unsigned int reg_addr;
815 unsigned int bit;
816 unsigned int read_val = 0;
11aa679a 817 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d 818
f97c2309
HY		 819 reg_addr = mtk_get_port(pctl, offset) +
820 pctl->devdata->din_offset;
a6df410d 821
9f940d8e 822 bit = BIT(offset & pctl->devdata->mode_mask);
a6df410d
HY		 823 regmap_read(pctl->regmap1, reg_addr, &read_val);
824 return !!(read_val & bit);
825}
826
d9819eb9
MM		 827static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
828{
11aa679a 829 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
d9819eb9 830 const struct mtk_desc_pin *pin;
e46df235 831 unsigned long eint_n;
d9819eb9
MM		 832
833 pin = pctl->devdata->pins + offset;
834 if (pin->eint.eintnum == NO_EINT_SUPPORT)
835 return -EINVAL;
836
e46df235 837 eint_n = pin->eint.eintnum;
d9819eb9 838
e46df235 839 return mtk_eint_find_irq(pctl->eint, eint_n);
d9819eb9
MM		 840}
841
2956b5d9
MW		 842static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset,
843 unsigned long config)
844{
e46df235
SW		 845 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
846 const struct mtk_desc_pin *pin;
847 unsigned long eint_n;
2956b5d9
MW		 848 u32 debounce;
849
850 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
851 return -ENOTSUPP;
852
e46df235
SW		 853 pin = pctl->devdata->pins + offset;
854 if (pin->eint.eintnum == NO_EINT_SUPPORT)
855 return -EINVAL;
856
2956b5d9 857 debounce = pinconf_to_config_argument(config);
e46df235
SW		 858 eint_n = pin->eint.eintnum;
859
860 return mtk_eint_set_debounce(pctl->eint, eint_n, debounce);
2956b5d9
MW		 861}
862
03e9888f 863static const struct gpio_chip mtk_gpio_chip = {
a6df410d 864 .owner = THIS_MODULE,
98c85d58
JG		 865 .request = gpiochip_generic_request,
866 .free = gpiochip_generic_free,
f97c2309 867 .get_direction = mtk_gpio_get_direction,
a6df410d
HY		 868 .direction_input = mtk_gpio_direction_input,
869 .direction_output = mtk_gpio_direction_output,
870 .get = mtk_gpio_get,
871 .set = mtk_gpio_set,
d9819eb9 872 .to_irq = mtk_gpio_to_irq,
2956b5d9 873 .set_config = mtk_gpio_set_config,
a6df410d
HY		 874 .of_gpio_n_cells = 2,
875};
876
58a5e1b6
MM		 877static int mtk_eint_suspend(struct device *device)
878{
58a5e1b6 879 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
58a5e1b6 880
e46df235 881 return mtk_eint_do_suspend(pctl->eint);
58a5e1b6
MM		 882}
883
884static int mtk_eint_resume(struct device *device)
885{
886 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
58a5e1b6 887
e46df235 888 return mtk_eint_do_resume(pctl->eint);
58a5e1b6
MM		 889}
890
891const struct dev_pm_ops mtk_eint_pm_ops = {
d2fcd62a 892 .suspend_noirq = mtk_eint_suspend,
893 .resume_noirq = mtk_eint_resume,
58a5e1b6
MM		 894};
895
a6df410d
HY		 896static int mtk_pctrl_build_state(struct platform_device *pdev)
897{
898 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
899 int i;
900
901 pctl->ngroups = pctl->devdata->npins;
902
903 /* Allocate groups */
0206caa8
AL		 904 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
905 sizeof(*pctl->groups), GFP_KERNEL);
a6df410d
HY		 906 if (!pctl->groups)
907 return -ENOMEM;
908
909 /* We assume that one pin is one group, use pin name as group name. */
0206caa8
AL		 910 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
911 sizeof(*pctl->grp_names), GFP_KERNEL);
a6df410d
HY		 912 if (!pctl->grp_names)
913 return -ENOMEM;
914
915 for (i = 0; i < pctl->devdata->npins; i++) {
916 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
917 struct mtk_pinctrl_group *group = pctl->groups + i;
918
919 group->name = pin->pin.name;
920 group->pin = pin->pin.number;
921
922 pctl->grp_names[i] = pin->pin.name;
923 }
924
925 return 0;
926}
927
e46df235
SW		 928static int
929mtk_xt_get_gpio_n(void *data, unsigned long eint_n, unsigned int *gpio_n,
930 struct gpio_chip **gpio_chip)
931{
932 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
933 const struct mtk_desc_pin *pin;
934
935 pin = mtk_find_pin_by_eint_num(pctl, eint_n);
936 if (!pin)
937 return -EINVAL;
938
939 *gpio_chip = pctl->chip;
940 *gpio_n = pin->pin.number;
941
942 return 0;
943}
944
945static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
946{
947 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
948 const struct mtk_desc_pin *pin;
949
950 pin = mtk_find_pin_by_eint_num(pctl, eint_n);
951 if (!pin)
952 return -EINVAL;
953
954 return mtk_gpio_get(pctl->chip, pin->pin.number);
955}
956
957static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
958{
959 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
960 const struct mtk_desc_pin *pin;
961
962 pin = mtk_find_pin_by_eint_num(pctl, eint_n);
963 if (!pin)
964 return -EINVAL;
965
966 /* set mux to INT mode */
967 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
968 /* set gpio direction to input */
969 mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number,
970 true);
971 /* set input-enable */
972 mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1,
973 PIN_CONFIG_INPUT_ENABLE);
974
975 return 0;
976}
977
978static const struct mtk_eint_xt mtk_eint_xt = {
979 .get_gpio_n = mtk_xt_get_gpio_n,
980 .get_gpio_state = mtk_xt_get_gpio_state,
981 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
982};
983
984static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev)
985{
986 struct device_node *np = pdev->dev.of_node;
e46df235
SW		 987
988 if (!of_property_read_bool(np, "interrupt-controller"))
989 return -ENODEV;
990
991 pctl->eint = devm_kzalloc(pctl->dev, sizeof(*pctl->eint), GFP_KERNEL);
992 if (!pctl->eint)
993 return -ENOMEM;
994
65713177 995 pctl->eint->base = devm_platform_ioremap_resource(pdev, 0);
e46df235
SW		 996 if (IS_ERR(pctl->eint->base))
997 return PTR_ERR(pctl->eint->base);
998
999 pctl->eint->irq = irq_of_parse_and_map(np, 0);
1000 if (!pctl->eint->irq)
1001 return -EINVAL;
1002
1003 pctl->eint->dev = &pdev->dev;
e6612a69
SW		 1004 /*
1005 * If pctl->eint->regs == NULL, it would fall back into using a generic
1006 * register map in mtk_eint_do_init calls.
1007 */
1008 pctl->eint->regs = pctl->devdata->eint_regs;
e46df235
SW		 1009 pctl->eint->hw = &pctl->devdata->eint_hw;
1010 pctl->eint->pctl = pctl;
1011 pctl->eint->gpio_xlate = &mtk_eint_xt;
1012
1013 return mtk_eint_do_init(pctl->eint);
1014}
1015
a6df410d 1016int mtk_pctrl_init(struct platform_device *pdev,
fc59e66c
HY		 1017 const struct mtk_pinctrl_devdata *data,
1018 struct regmap *regmap)
a6df410d
HY		 1019{
1020 struct pinctrl_pin_desc *pins;
1021 struct mtk_pinctrl *pctl;
1022 struct device_node *np = pdev->dev.of_node, *node;
1023 struct property *prop;
e46df235 1024 int ret, i;
a6df410d
HY		 1025
1026 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1027 if (!pctl)
1028 return -ENOMEM;
1029
1030 platform_set_drvdata(pdev, pctl);
1031
1032 prop = of_find_property(np, "pins-are-numbered", NULL);
1033 if (!prop) {
c445cac3 1034 dev_err(&pdev->dev, "only support pins-are-numbered format\n");
a6df410d
HY		 1035 return -EINVAL;
1036 }
1037
1038 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1039 if (node) {
1040 pctl->regmap1 = syscon_node_to_regmap(node);
1041 if (IS_ERR(pctl->regmap1))
1042 return PTR_ERR(pctl->regmap1);
fc59e66c
HY		 1043 } else if (regmap) {
1044 pctl->regmap1 = regmap;
1045 } else {
1046 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1047 return -EINVAL;
a6df410d
HY		 1048 }
1049
1050 /* Only 8135 has two base addr, other SoCs have only one. */
1051 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1052 if (node) {
1053 pctl->regmap2 = syscon_node_to_regmap(node);
1054 if (IS_ERR(pctl->regmap2))
1055 return PTR_ERR(pctl->regmap2);
1056 }
1057
1058 pctl->devdata = data;
1059 ret = mtk_pctrl_build_state(pdev);
1060 if (ret) {
1061 dev_err(&pdev->dev, "build state failed: %d\n", ret);
1062 return -EINVAL;
1063 }
1064
0206caa8 1065 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
a6df410d
HY		 1066 GFP_KERNEL);
1067 if (!pins)
1068 return -ENOMEM;
1069
1070 for (i = 0; i < pctl->devdata->npins; i++)
1071 pins[i] = pctl->devdata->pins[i].pin;
d48c2c02
HY		 1072
1073 pctl->pctl_desc.name = dev_name(&pdev->dev);
1074 pctl->pctl_desc.owner = THIS_MODULE;
1075 pctl->pctl_desc.pins = pins;
1076 pctl->pctl_desc.npins = pctl->devdata->npins;
1077 pctl->pctl_desc.confops = &mtk_pconf_ops;
1078 pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1079 pctl->pctl_desc.pmxops = &mtk_pmx_ops;
a6df410d 1080 pctl->dev = &pdev->dev;
d48c2c02 1081
03a3a558
LD		 1082 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1083 pctl);
323de9ef 1084 if (IS_ERR(pctl->pctl_dev)) {
a6df410d 1085 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
323de9ef 1086 return PTR_ERR(pctl->pctl_dev);
a6df410d
HY		 1087 }
1088
1089 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
03a3a558
LD		 1090 if (!pctl->chip)
1091 return -ENOMEM;
a6df410d 1092
fc63d854 1093 *pctl->chip = mtk_gpio_chip;
a6df410d
HY		 1094 pctl->chip->ngpio = pctl->devdata->npins;
1095 pctl->chip->label = dev_name(&pdev->dev);
58383c78 1096 pctl->chip->parent = &pdev->dev;
fc59e66c 1097 pctl->chip->base = -1;
a6df410d 1098
11aa679a 1099 ret = gpiochip_add_data(pctl->chip, pctl);
03a3a558
LD		 1100 if (ret)
1101 return -EINVAL;
a6df410d
HY		 1102
1103 /* Register the GPIO to pin mappings. */
1104 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1105 0, 0, pctl->devdata->npins);
1106 if (ret) {
1107 ret = -EINVAL;
1108 goto chip_error;
1109 }
1110
e46df235
SW		 1111 ret = mtk_eint_init(pctl, pdev);
1112 if (ret)
61a35576 1113 goto chip_error;
d9819eb9 1114
a6df410d
HY		 1115 return 0;
1116
1117chip_error:
1118 gpiochip_remove(pctl->chip);
a6df410d
HY		 1119 return ret;
1120}
Linux 6.x block layer and io_uring tree(s)