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Merge tag 'nfsd-6.3-6' of git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux
[linux-2.6-block.git] / drivers / pinctrl / mediatek / pinctrl-mtk-common.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
a6df410d
HY		 2/*
3 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
4 * Copyright (c) 2014 MediaTek Inc.
5 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
a6df410d
HY		 6 */
7
8#include <linux/io.h>
11aa679a 9#include <linux/gpio/driver.h>
a6df410d
HY		 10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/of_device.h>
13#include <linux/of_irq.h>
14#include <linux/pinctrl/consumer.h>
15#include <linux/pinctrl/machine.h>
16#include <linux/pinctrl/pinconf.h>
17#include <linux/pinctrl/pinconf-generic.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/platform_device.h>
21#include <linux/slab.h>
22#include <linux/bitops.h>
23#include <linux/regmap.h>
24#include <linux/mfd/syscon.h>
d9819eb9 25#include <linux/delay.h>
30f010f5 26#include <linux/interrupt.h>
58a5e1b6 27#include <linux/pm.h>
a6df410d
HY		 28#include <dt-bindings/pinctrl/mt65xx.h>
29
30#include "../core.h"
31#include "../pinconf.h"
32#include "../pinctrl-utils.h"
e46df235 33#include "mtk-eint.h"
a6df410d
HY		 34#include "pinctrl-mtk-common.h"
35
a6df410d 36#define GPIO_MODE_BITS 3
59ee9c96 37#define GPIO_MODE_PREFIX "GPIO"
a6df410d
HY		 38
39static const char * const mtk_gpio_functions[] = {
40 "func0", "func1", "func2", "func3",
41 "func4", "func5", "func6", "func7",
148b95ee
BH		 42 "func8", "func9", "func10", "func11",
43 "func12", "func13", "func14", "func15",
a6df410d
HY		 44};
45
46/*
47 * There are two base address for pull related configuration
48 * in mt8135, and different GPIO pins use different base address.
49 * When pin number greater than type1_start and less than type1_end,
50 * should use the second base address.
51 */
52static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
53 unsigned long pin)
54{
55 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
56 return pctl->regmap2;
57 return pctl->regmap1;
58}
59
60static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
61{
62 /* Different SoC has different mask and port shift. */
9f940d8e 63 return ((pin >> pctl->devdata->mode_shf) & pctl->devdata->port_mask)
a6df410d
HY		 64 << pctl->devdata->port_shf;
65}
66
67static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
68 struct pinctrl_gpio_range *range, unsigned offset,
69 bool input)
70{
71 unsigned int reg_addr;
72 unsigned int bit;
73 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
74
75 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
9f940d8e 76 bit = BIT(offset & pctl->devdata->mode_mask);
a6df410d 77
148b95ee
BH		 78 if (pctl->devdata->spec_dir_set)
79 pctl->devdata->spec_dir_set(&reg_addr, offset);
80
a6df410d
HY		 81 if (input)
82 /* Different SoC has different alignment offset. */
83 reg_addr = CLR_ADDR(reg_addr, pctl);
84 else
85 reg_addr = SET_ADDR(reg_addr, pctl);
86
87 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
88 return 0;
89}
90
91static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
92{
93 unsigned int reg_addr;
94 unsigned int bit;
11aa679a 95 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d
HY		 96
97 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
9f940d8e 98 bit = BIT(offset & pctl->devdata->mode_mask);
a6df410d
HY		 99
100 if (value)
101 reg_addr = SET_ADDR(reg_addr, pctl);
102 else
103 reg_addr = CLR_ADDR(reg_addr, pctl);
104
105 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
106}
107
25d76b21
HY		 108static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
109 int value, enum pin_config_param arg)
a6df410d
HY		 110{
111 unsigned int reg_addr, offset;
112 unsigned int bit;
25d76b21
HY		 113
114 /**
115 * Due to some soc are not support ies/smt config, add this special
116 * control to handle it.
117 */
118 if (!pctl->devdata->spec_ies_smt_set &&
119 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
120 arg == PIN_CONFIG_INPUT_ENABLE)
121 return -EINVAL;
122
123 if (!pctl->devdata->spec_ies_smt_set &&
124 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
125 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
126 return -EINVAL;
30f010f5
HY		 127
128 /*
129 * Due to some pins are irregular, their input enable and smt
25d76b21 130 * control register are discontinuous, so we need this special handle.
30f010f5
HY		 131 */
132 if (pctl->devdata->spec_ies_smt_set) {
25d76b21 133 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
156f7217 134 pctl->devdata, pin, value, arg);
30f010f5 135 }
a6df410d 136
25d76b21 137 if (arg == PIN_CONFIG_INPUT_ENABLE)
a6df410d
HY		 138 offset = pctl->devdata->ies_offset;
139 else
140 offset = pctl->devdata->smt_offset;
141
21c423a6
MB		 142 bit = BIT(offset & pctl->devdata->mode_mask);
143
a6df410d
HY		 144 if (value)
145 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
146 else
147 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
148
149 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
25d76b21
HY		 150 return 0;
151}
152
153int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
156f7217
ADR		 154 const struct mtk_pinctrl_devdata *devdata,
155 unsigned int pin, int value, enum pin_config_param arg)
25d76b21 156{
156f7217
ADR		 157 const struct mtk_pin_ies_smt_set *ies_smt_infos = NULL;
158 unsigned int i, info_num, reg_addr, bit;
159
160 switch (arg) {
161 case PIN_CONFIG_INPUT_ENABLE:
162 ies_smt_infos = devdata->spec_ies;
163 info_num = devdata->n_spec_ies;
164 break;
165 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
166 ies_smt_infos = devdata->spec_smt;
167 info_num = devdata->n_spec_smt;
168 break;
169 default:
170 break;
4a6d0149 171 }
156f7217
ADR		 172
173 if (!ies_smt_infos)
174 return -EINVAL;
25d76b21
HY		 175
176 for (i = 0; i < info_num; i++) {
177 if (pin >= ies_smt_infos[i].start &&
178 pin <= ies_smt_infos[i].end) {
179 break;
180 }
181 }
182
183 if (i == info_num)
184 return -EINVAL;
185
186 if (value)
156f7217 187 reg_addr = ies_smt_infos[i].offset + devdata->port_align;
25d76b21 188 else
156f7217 189 reg_addr = ies_smt_infos[i].offset + (devdata->port_align << 1);
25d76b21
HY		 190
191 bit = BIT(ies_smt_infos[i].bit);
192 regmap_write(regmap, reg_addr, bit);
193 return 0;
a6df410d
HY		 194}
195
196static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
197 struct mtk_pinctrl *pctl, unsigned long pin) {
198 int i;
199
200 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
201 const struct mtk_pin_drv_grp *pin_drv =
202 pctl->devdata->pin_drv_grp + i;
203 if (pin == pin_drv->pin)
204 return pin_drv;
205 }
206
207 return NULL;
208}
209
210static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
211 unsigned int pin, unsigned char driving)
212{
213 const struct mtk_pin_drv_grp *pin_drv;
214 unsigned int val;
215 unsigned int bits, mask, shift;
216 const struct mtk_drv_group_desc *drv_grp;
217
218 if (pin >= pctl->devdata->npins)
219 return -EINVAL;
220
221 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
222 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
223 return -EINVAL;
224
225 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
226 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
227 && !(driving % drv_grp->step)) {
228 val = driving / drv_grp->step - 1;
229 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
230 mask = BIT(bits) - 1;
231 shift = pin_drv->bit + drv_grp->low_bit;
232 mask <<= shift;
233 val <<= shift;
234 return regmap_update_bits(mtk_get_regmap(pctl, pin),
235 pin_drv->offset, mask, val);
236 }
237
238 return -EINVAL;
239}
240
e73fe271 241int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
c19763c3
ADR		 242 const struct mtk_pinctrl_devdata *devdata,
243 unsigned int pin, bool isup, unsigned int r1r0)
e73fe271
YC		 244{
245 unsigned int i;
246 unsigned int reg_pupd, reg_set, reg_rst;
247 unsigned int bit_pupd, bit_r0, bit_r1;
248 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
249 bool find = false;
250
c19763c3
ADR		 251 if (!devdata->spec_pupd)
252 return -EINVAL;
253
254 for (i = 0; i < devdata->n_spec_pupd; i++) {
255 if (pin == devdata->spec_pupd[i].pin) {
e73fe271
YC		 256 find = true;
257 break;
258 }
259 }
260
261 if (!find)
262 return -EINVAL;
263
c19763c3
ADR		 264 spec_pupd_pin = devdata->spec_pupd + i;
265 reg_set = spec_pupd_pin->offset + devdata->port_align;
266 reg_rst = spec_pupd_pin->offset + (devdata->port_align << 1);
e73fe271
YC		 267
268 if (isup)
269 reg_pupd = reg_rst;
270 else
271 reg_pupd = reg_set;
272
273 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
274 regmap_write(regmap, reg_pupd, bit_pupd);
275
276 bit_r0 = BIT(spec_pupd_pin->r0_bit);
277 bit_r1 = BIT(spec_pupd_pin->r1_bit);
278
279 switch (r1r0) {
280 case MTK_PUPD_SET_R1R0_00:
281 regmap_write(regmap, reg_rst, bit_r0);
282 regmap_write(regmap, reg_rst, bit_r1);
283 break;
284 case MTK_PUPD_SET_R1R0_01:
285 regmap_write(regmap, reg_set, bit_r0);
286 regmap_write(regmap, reg_rst, bit_r1);
287 break;
288 case MTK_PUPD_SET_R1R0_10:
289 regmap_write(regmap, reg_rst, bit_r0);
290 regmap_write(regmap, reg_set, bit_r1);
291 break;
292 case MTK_PUPD_SET_R1R0_11:
293 regmap_write(regmap, reg_set, bit_r0);
294 regmap_write(regmap, reg_set, bit_r1);
295 break;
296 default:
297 return -EINVAL;
298 }
299
300 return 0;
301}
302
a6df410d
HY		 303static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
304 unsigned int pin, bool enable, bool isup, unsigned int arg)
305{
306 unsigned int bit;
6af8df4c 307 unsigned int reg_pullen, reg_pullsel, r1r0;
a6df410d
HY		 308 int ret;
309
310 /* Some pins' pull setting are very different,
311 * they have separate pull up/down bit, R0 and R1
312 * resistor bit, so we need this special handle.
313 */
314 if (pctl->devdata->spec_pull_set) {
6af8df4c
ZT		 315 /* For special pins, bias-disable is set by R1R0,
316 * the parameter should be "MTK_PUPD_SET_R1R0_00".
317 */
318 r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
a6df410d 319 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
c19763c3
ADR		 320 pctl->devdata, pin, isup,
321 r1r0);
a6df410d
HY		 322 if (!ret)
323 return 0;
324 }
325
326 /* For generic pull config, default arg value should be 0 or 1. */
327 if (arg != 0 && arg != 1) {
328 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
329 arg, pin);
330 return -EINVAL;
331 }
332
d459a235
BC		 333 if (pctl->devdata->mt8365_set_clr_mode) {
334 bit = pin & pctl->devdata->mode_mask;
335 reg_pullen = mtk_get_port(pctl, pin) +
336 pctl->devdata->pullen_offset;
337 reg_pullsel = mtk_get_port(pctl, pin) +
338 pctl->devdata->pullsel_offset;
339 ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin),
340 bit, reg_pullen, reg_pullsel,
341 enable, isup);
342 if (ret)
343 return -EINVAL;
344
345 return 0;
346 }
347
9f940d8e 348 bit = BIT(pin & pctl->devdata->mode_mask);
a6df410d
HY		 349 if (enable)
350 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
351 pctl->devdata->pullen_offset, pctl);
352 else
353 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
354 pctl->devdata->pullen_offset, pctl);
355
356 if (isup)
357 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
358 pctl->devdata->pullsel_offset, pctl);
359 else
360 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
361 pctl->devdata->pullsel_offset, pctl);
362
363 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
364 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
365 return 0;
366}
367
368static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
369 unsigned int pin, enum pin_config_param param,
370 enum pin_config_param arg)
371{
25d76b21 372 int ret = 0;
a6df410d
HY		 373 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
374
375 switch (param) {
376 case PIN_CONFIG_BIAS_DISABLE:
25d76b21 377 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
a6df410d
HY		 378 break;
379 case PIN_CONFIG_BIAS_PULL_UP:
25d76b21 380 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
a6df410d
HY		 381 break;
382 case PIN_CONFIG_BIAS_PULL_DOWN:
25d76b21 383 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
a6df410d
HY		 384 break;
385 case PIN_CONFIG_INPUT_ENABLE:
eceb3e61 386 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
25d76b21 387 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 388 break;
389 case PIN_CONFIG_OUTPUT:
390 mtk_gpio_set(pctl->chip, pin, arg);
25d76b21 391 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
a6df410d
HY		 392 break;
393 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
eceb3e61 394 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
25d76b21 395 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 396 break;
397 case PIN_CONFIG_DRIVE_STRENGTH:
25d76b21 398 ret = mtk_pconf_set_driving(pctl, pin, arg);
a6df410d
HY		 399 break;
400 default:
25d76b21 401 ret = -EINVAL;
a6df410d
HY		 402 }
403
25d76b21 404 return ret;
a6df410d
HY		 405}
406
407static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
408 unsigned group,
409 unsigned long *config)
410{
411 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
412
413 *config = pctl->groups[group].config;
414
415 return 0;
416}
417
418static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
419 unsigned long *configs, unsigned num_configs)
420{
421 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
422 struct mtk_pinctrl_group *g = &pctl->groups[group];
25d76b21 423 int i, ret;
a6df410d
HY		 424
425 for (i = 0; i < num_configs; i++) {
25d76b21 426 ret = mtk_pconf_parse_conf(pctldev, g->pin,
a6df410d
HY		 427 pinconf_to_config_param(configs[i]),
428 pinconf_to_config_argument(configs[i]));
25d76b21
HY		 429 if (ret < 0)
430 return ret;
a6df410d
HY		 431
432 g->config = configs[i];
433 }
434
435 return 0;
436}
437
438static const struct pinconf_ops mtk_pconf_ops = {
439 .pin_config_group_get = mtk_pconf_group_get,
440 .pin_config_group_set = mtk_pconf_group_set,
441};
442
443static struct mtk_pinctrl_group *
444mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
445{
446 int i;
447
448 for (i = 0; i < pctl->ngroups; i++) {
449 struct mtk_pinctrl_group *grp = pctl->groups + i;
450
451 if (grp->pin == pin)
452 return grp;
453 }
454
455 return NULL;
456}
457
458static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
459 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
460{
461 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
462 const struct mtk_desc_function *func = pin->functions;
463
464 while (func && func->name) {
465 if (func->muxval == fnum)
466 return func;
467 func++;
468 }
469
470 return NULL;
471}
472
473static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
474 u32 pin_num, u32 fnum)
475{
476 int i;
477
478 for (i = 0; i < pctl->devdata->npins; i++) {
479 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
480
481 if (pin->pin.number == pin_num) {
482 const struct mtk_desc_function *func =
483 pin->functions;
484
485 while (func && func->name) {
486 if (func->muxval == fnum)
487 return true;
488 func++;
489 }
490
491 break;
492 }
493 }
494
495 return false;
496}
497
498static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
499 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
500 struct pinctrl_map **map, unsigned *reserved_maps,
501 unsigned *num_maps)
502{
503 bool ret;
504
505 if (*num_maps == *reserved_maps)
506 return -ENOSPC;
507
508 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
509 (*map)[*num_maps].data.mux.group = grp->name;
510
511 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
512 if (!ret) {
513 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
514 fnum, pin);
515 return -EINVAL;
516 }
517
518 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
519 (*num_maps)++;
520
521 return 0;
522}
523
524static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
525 struct device_node *node,
526 struct pinctrl_map **map,
527 unsigned *reserved_maps,
528 unsigned *num_maps)
529{
530 struct property *pins;
531 u32 pinfunc, pin, func;
532 int num_pins, num_funcs, maps_per_pin;
533 unsigned long *configs;
534 unsigned int num_configs;
b2f78906 535 bool has_config = false;
a6df410d
HY		 536 int i, err;
537 unsigned reserve = 0;
538 struct mtk_pinctrl_group *grp;
539 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
540
541 pins = of_find_property(node, "pinmux", NULL);
542 if (!pins) {
94f4e54c
RH		 543 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
544 node);
a6df410d
HY		 545 return -EINVAL;
546 }
547
c445cac3
HY		 548 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
549 &num_configs);
b04a23b0
HY		 550 if (err)
551 return err;
552
a6df410d 553 if (num_configs)
b2f78906 554 has_config = true;
a6df410d
HY		 555
556 num_pins = pins->length / sizeof(u32);
557 num_funcs = num_pins;
558 maps_per_pin = 0;
559 if (num_funcs)
560 maps_per_pin++;
561 if (has_config && num_pins >= 1)
562 maps_per_pin++;
563
b04a23b0
HY		 564 if (!num_pins || !maps_per_pin) {
565 err = -EINVAL;
566 goto exit;
567 }
a6df410d
HY		 568
569 reserve = num_pins * maps_per_pin;
570
571 err = pinctrl_utils_reserve_map(pctldev, map,
572 reserved_maps, num_maps, reserve);
573 if (err < 0)
b04a23b0 574 goto exit;
a6df410d
HY		 575
576 for (i = 0; i < num_pins; i++) {
577 err = of_property_read_u32_index(node, "pinmux",
578 i, &pinfunc);
579 if (err)
b04a23b0 580 goto exit;
a6df410d
HY		 581
582 pin = MTK_GET_PIN_NO(pinfunc);
583 func = MTK_GET_PIN_FUNC(pinfunc);
584
585 if (pin >= pctl->devdata->npins ||
586 func >= ARRAY_SIZE(mtk_gpio_functions)) {
587 dev_err(pctl->dev, "invalid pins value.\n");
588 err = -EINVAL;
b04a23b0 589 goto exit;
a6df410d
HY		 590 }
591
592 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
593 if (!grp) {
594 dev_err(pctl->dev, "unable to match pin %d to group\n",
595 pin);
b04a23b0
HY		 596 err = -EINVAL;
597 goto exit;
a6df410d
HY		 598 }
599
600 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
601 reserved_maps, num_maps);
602 if (err < 0)
b04a23b0 603 goto exit;
a6df410d
HY		 604
605 if (has_config) {
606 err = pinctrl_utils_add_map_configs(pctldev, map,
607 reserved_maps, num_maps, grp->name,
608 configs, num_configs,
609 PIN_MAP_TYPE_CONFIGS_GROUP);
610 if (err < 0)
b04a23b0 611 goto exit;
a6df410d
HY		 612 }
613 }
614
b04a23b0 615 err = 0;
a6df410d 616
b04a23b0
HY		 617exit:
618 kfree(configs);
a6df410d
HY		 619 return err;
620}
621
622static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
623 struct device_node *np_config,
624 struct pinctrl_map **map, unsigned *num_maps)
625{
626 struct device_node *np;
627 unsigned reserved_maps;
628 int ret;
629
630 *map = NULL;
631 *num_maps = 0;
632 reserved_maps = 0;
633
634 for_each_child_of_node(np_config, np) {
635 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
636 &reserved_maps, num_maps);
637 if (ret < 0) {
d32f7fd3 638 pinctrl_utils_free_map(pctldev, *map, *num_maps);
4fc8a4b2 639 of_node_put(np);
a6df410d
HY		 640 return ret;
641 }
642 }
643
644 return 0;
645}
646
647static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
648{
649 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
650
651 return pctl->ngroups;
652}
653
654static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
655 unsigned group)
656{
657 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
658
659 return pctl->groups[group].name;
660}
661
662static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
663 unsigned group,
664 const unsigned **pins,
665 unsigned *num_pins)
666{
667 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
668
669 *pins = (unsigned *)&pctl->groups[group].pin;
670 *num_pins = 1;
671
672 return 0;
673}
674
675static const struct pinctrl_ops mtk_pctrl_ops = {
676 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
d32f7fd3 677 .dt_free_map = pinctrl_utils_free_map,
a6df410d
HY		 678 .get_groups_count = mtk_pctrl_get_groups_count,
679 .get_group_name = mtk_pctrl_get_group_name,
680 .get_group_pins = mtk_pctrl_get_group_pins,
681};
682
683static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
684{
685 return ARRAY_SIZE(mtk_gpio_functions);
686}
687
688static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
689 unsigned selector)
690{
691 return mtk_gpio_functions[selector];
692}
693
694static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
695 unsigned function,
696 const char * const **groups,
697 unsigned * const num_groups)
698{
699 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
700
701 *groups = pctl->grp_names;
702 *num_groups = pctl->ngroups;
703
704 return 0;
705}
706
707static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
708 unsigned long pin, unsigned long mode)
709{
710 unsigned int reg_addr;
711 unsigned char bit;
712 unsigned int val;
713 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
714 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
715
148b95ee
BH		 716 if (pctl->devdata->spec_pinmux_set)
717 pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
718 pin, mode);
719
9f940d8e 720 reg_addr = ((pin / pctl->devdata->mode_per_reg) << pctl->devdata->port_shf)
a6df410d
HY		 721 + pctl->devdata->pinmux_offset;
722
148b95ee 723 mode &= mask;
9f940d8e 724 bit = pin % pctl->devdata->mode_per_reg;
a6df410d
HY		 725 mask <<= (GPIO_MODE_BITS * bit);
726 val = (mode << (GPIO_MODE_BITS * bit));
727 return regmap_update_bits(mtk_get_regmap(pctl, pin),
728 reg_addr, mask, val);
729}
730
d9819eb9
MM		 731static const struct mtk_desc_pin *
732mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
733{
734 int i;
735 const struct mtk_desc_pin *pin;
736
737 for (i = 0; i < pctl->devdata->npins; i++) {
738 pin = pctl->devdata->pins + i;
739 if (pin->eint.eintnum == eint_num)
740 return pin;
741 }
742
743 return NULL;
744}
745
a6df410d
HY		 746static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
747 unsigned function,
748 unsigned group)
749{
750 bool ret;
751 const struct mtk_desc_function *desc;
752 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
753 struct mtk_pinctrl_group *g = pctl->groups + group;
754
755 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
756 if (!ret) {
c70336cc 757 dev_err(pctl->dev, "invalid function %d on group %d .\n",
a6df410d
HY		 758 function, group);
759 return -EINVAL;
760 }
761
762 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
763 if (!desc)
764 return -EINVAL;
765 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
766 return 0;
767}
768
59ee9c96
BH		 769static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
770 unsigned offset)
771{
772 const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
773 const struct mtk_desc_function *func = pin->functions;
774
775 while (func && func->name) {
776 if (!strncmp(func->name, GPIO_MODE_PREFIX,
777 sizeof(GPIO_MODE_PREFIX)-1))
778 return func->muxval;
779 func++;
780 }
781 return -EINVAL;
782}
783
784static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
785 struct pinctrl_gpio_range *range,
786 unsigned offset)
787{
740f5b08 788 int muxval;
59ee9c96
BH		 789 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
790
791 muxval = mtk_pmx_find_gpio_mode(pctl, offset);
792
793 if (muxval < 0) {
794 dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
795 return -EINVAL;
796 }
797
798 mtk_pmx_set_mode(pctldev, offset, muxval);
31763d3b 799 mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
59ee9c96
BH		 800
801 return 0;
802}
803
a6df410d
HY		 804static const struct pinmux_ops mtk_pmx_ops = {
805 .get_functions_count = mtk_pmx_get_funcs_cnt,
806 .get_function_name = mtk_pmx_get_func_name,
807 .get_function_groups = mtk_pmx_get_func_groups,
808 .set_mux = mtk_pmx_set_mux,
809 .gpio_set_direction = mtk_pmx_gpio_set_direction,
59ee9c96 810 .gpio_request_enable = mtk_pmx_gpio_request_enable,
a6df410d
HY		 811};
812
a6df410d
HY		 813static int mtk_gpio_direction_input(struct gpio_chip *chip,
814 unsigned offset)
815{
816 return pinctrl_gpio_direction_input(chip->base + offset);
817}
818
819static int mtk_gpio_direction_output(struct gpio_chip *chip,
820 unsigned offset, int value)
821{
822 mtk_gpio_set(chip, offset, value);
823 return pinctrl_gpio_direction_output(chip->base + offset);
824}
825
826static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
827{
828 unsigned int reg_addr;
829 unsigned int bit;
830 unsigned int read_val = 0;
831
11aa679a 832 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d
HY		 833
834 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
9f940d8e 835 bit = BIT(offset & pctl->devdata->mode_mask);
148b95ee
BH		 836
837 if (pctl->devdata->spec_dir_set)
838 pctl->devdata->spec_dir_set(&reg_addr, offset);
839
a6df410d 840 regmap_read(pctl->regmap1, reg_addr, &read_val);
3c827873
MV		 841 if (read_val & bit)
842 return GPIO_LINE_DIRECTION_OUT;
843
844 return GPIO_LINE_DIRECTION_IN;
a6df410d
HY		 845}
846
847static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
848{
849 unsigned int reg_addr;
850 unsigned int bit;
851 unsigned int read_val = 0;
11aa679a 852 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d 853
f97c2309
HY		 854 reg_addr = mtk_get_port(pctl, offset) +
855 pctl->devdata->din_offset;
a6df410d 856
9f940d8e 857 bit = BIT(offset & pctl->devdata->mode_mask);
a6df410d
HY		 858 regmap_read(pctl->regmap1, reg_addr, &read_val);
859 return !!(read_val & bit);
860}
861
d9819eb9
MM		 862static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
863{
11aa679a 864 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
d9819eb9 865 const struct mtk_desc_pin *pin;
e46df235 866 unsigned long eint_n;
d9819eb9
MM		 867
868 pin = pctl->devdata->pins + offset;
869 if (pin->eint.eintnum == NO_EINT_SUPPORT)
870 return -EINVAL;
871
e46df235 872 eint_n = pin->eint.eintnum;
d9819eb9 873
e46df235 874 return mtk_eint_find_irq(pctl->eint, eint_n);
d9819eb9
MM		 875}
876
2956b5d9
MW		 877static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset,
878 unsigned long config)
879{
e46df235
SW		 880 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
881 const struct mtk_desc_pin *pin;
882 unsigned long eint_n;
2956b5d9
MW		 883 u32 debounce;
884
885 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
886 return -ENOTSUPP;
887
e46df235
SW		 888 pin = pctl->devdata->pins + offset;
889 if (pin->eint.eintnum == NO_EINT_SUPPORT)
890 return -EINVAL;
891
2956b5d9 892 debounce = pinconf_to_config_argument(config);
e46df235
SW		 893 eint_n = pin->eint.eintnum;
894
895 return mtk_eint_set_debounce(pctl->eint, eint_n, debounce);
2956b5d9
MW		 896}
897
03e9888f 898static const struct gpio_chip mtk_gpio_chip = {
a6df410d 899 .owner = THIS_MODULE,
98c85d58
JG		 900 .request = gpiochip_generic_request,
901 .free = gpiochip_generic_free,
f97c2309 902 .get_direction = mtk_gpio_get_direction,
a6df410d
HY		 903 .direction_input = mtk_gpio_direction_input,
904 .direction_output = mtk_gpio_direction_output,
905 .get = mtk_gpio_get,
906 .set = mtk_gpio_set,
d9819eb9 907 .to_irq = mtk_gpio_to_irq,
2956b5d9 908 .set_config = mtk_gpio_set_config,
a6df410d
HY		 909};
910
58a5e1b6
MM		 911static int mtk_eint_suspend(struct device *device)
912{
58a5e1b6 913 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
58a5e1b6 914
e46df235 915 return mtk_eint_do_suspend(pctl->eint);
58a5e1b6
MM		 916}
917
918static int mtk_eint_resume(struct device *device)
919{
920 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
58a5e1b6 921
e46df235 922 return mtk_eint_do_resume(pctl->eint);
58a5e1b6
MM		 923}
924
925const struct dev_pm_ops mtk_eint_pm_ops = {
d2fcd62a 926 .suspend_noirq = mtk_eint_suspend,
927 .resume_noirq = mtk_eint_resume,
58a5e1b6
MM		 928};
929
a6df410d
HY		 930static int mtk_pctrl_build_state(struct platform_device *pdev)
931{
932 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
933 int i;
934
935 pctl->ngroups = pctl->devdata->npins;
936
937 /* Allocate groups */
0206caa8
AL		 938 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
939 sizeof(*pctl->groups), GFP_KERNEL);
a6df410d
HY		 940 if (!pctl->groups)
941 return -ENOMEM;
942
943 /* We assume that one pin is one group, use pin name as group name. */
0206caa8
AL		 944 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
945 sizeof(*pctl->grp_names), GFP_KERNEL);
a6df410d
HY		 946 if (!pctl->grp_names)
947 return -ENOMEM;
948
949 for (i = 0; i < pctl->devdata->npins; i++) {
950 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
951 struct mtk_pinctrl_group *group = pctl->groups + i;
952
953 group->name = pin->pin.name;
954 group->pin = pin->pin.number;
955
956 pctl->grp_names[i] = pin->pin.name;
957 }
958
959 return 0;
960}
961
e46df235
SW		 962static int
963mtk_xt_get_gpio_n(void *data, unsigned long eint_n, unsigned int *gpio_n,
964 struct gpio_chip **gpio_chip)
965{
966 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
967 const struct mtk_desc_pin *pin;
968
969 pin = mtk_find_pin_by_eint_num(pctl, eint_n);
970 if (!pin)
971 return -EINVAL;
972
973 *gpio_chip = pctl->chip;
974 *gpio_n = pin->pin.number;
975
976 return 0;
977}
978
979static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
980{
981 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
982 const struct mtk_desc_pin *pin;
983
984 pin = mtk_find_pin_by_eint_num(pctl, eint_n);
985 if (!pin)
986 return -EINVAL;
987
988 return mtk_gpio_get(pctl->chip, pin->pin.number);
989}
990
991static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
992{
993 struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
994 const struct mtk_desc_pin *pin;
995
996 pin = mtk_find_pin_by_eint_num(pctl, eint_n);
997 if (!pin)
998 return -EINVAL;
999
1000 /* set mux to INT mode */
1001 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
1002 /* set gpio direction to input */
1003 mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number,
1004 true);
1005 /* set input-enable */
1006 mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1,
1007 PIN_CONFIG_INPUT_ENABLE);
1008
1009 return 0;
1010}
1011
1012static const struct mtk_eint_xt mtk_eint_xt = {
1013 .get_gpio_n = mtk_xt_get_gpio_n,
1014 .get_gpio_state = mtk_xt_get_gpio_state,
1015 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
1016};
1017
1018static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev)
1019{
1020 struct device_node *np = pdev->dev.of_node;
e46df235
SW		 1021
1022 if (!of_property_read_bool(np, "interrupt-controller"))
1023 return -ENODEV;
1024
1025 pctl->eint = devm_kzalloc(pctl->dev, sizeof(*pctl->eint), GFP_KERNEL);
1026 if (!pctl->eint)
1027 return -ENOMEM;
1028
65713177 1029 pctl->eint->base = devm_platform_ioremap_resource(pdev, 0);
e46df235
SW		 1030 if (IS_ERR(pctl->eint->base))
1031 return PTR_ERR(pctl->eint->base);
1032
1033 pctl->eint->irq = irq_of_parse_and_map(np, 0);
1034 if (!pctl->eint->irq)
1035 return -EINVAL;
1036
1037 pctl->eint->dev = &pdev->dev;
e6612a69
SW		 1038 /*
1039 * If pctl->eint->regs == NULL, it would fall back into using a generic
1040 * register map in mtk_eint_do_init calls.
1041 */
1042 pctl->eint->regs = pctl->devdata->eint_regs;
e46df235
SW		 1043 pctl->eint->hw = &pctl->devdata->eint_hw;
1044 pctl->eint->pctl = pctl;
1045 pctl->eint->gpio_xlate = &mtk_eint_xt;
1046
1047 return mtk_eint_do_init(pctl->eint);
1048}
1049
0dd1628a 1050/* This is used as a common probe function */
a6df410d 1051int mtk_pctrl_init(struct platform_device *pdev,
fc59e66c
HY		 1052 const struct mtk_pinctrl_devdata *data,
1053 struct regmap *regmap)
a6df410d 1054{
0dd1628a 1055 struct device *dev = &pdev->dev;
a6df410d
HY		 1056 struct pinctrl_pin_desc *pins;
1057 struct mtk_pinctrl *pctl;
1058 struct device_node *np = pdev->dev.of_node, *node;
e46df235 1059 int ret, i;
a6df410d
HY		 1060
1061 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1062 if (!pctl)
1063 return -ENOMEM;
1064
1065 platform_set_drvdata(pdev, pctl);
1066
a6df410d
HY		 1067 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1068 if (node) {
1069 pctl->regmap1 = syscon_node_to_regmap(node);
dab4df9c 1070 of_node_put(node);
a6df410d
HY		 1071 if (IS_ERR(pctl->regmap1))
1072 return PTR_ERR(pctl->regmap1);
fc59e66c
HY		 1073 } else if (regmap) {
1074 pctl->regmap1 = regmap;
1075 } else {
0dd1628a 1076 return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n");
a6df410d
HY		 1077 }
1078
1079 /* Only 8135 has two base addr, other SoCs have only one. */
1080 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1081 if (node) {
1082 pctl->regmap2 = syscon_node_to_regmap(node);
dab4df9c 1083 of_node_put(node);
a6df410d
HY		 1084 if (IS_ERR(pctl->regmap2))
1085 return PTR_ERR(pctl->regmap2);
1086 }
1087
1088 pctl->devdata = data;
1089 ret = mtk_pctrl_build_state(pdev);
0dd1628a
ADR		 1090 if (ret)
1091 return dev_err_probe(dev, ret, "build state failed\n");
a6df410d 1092
0206caa8 1093 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
a6df410d
HY		 1094 GFP_KERNEL);
1095 if (!pins)
1096 return -ENOMEM;
1097
1098 for (i = 0; i < pctl->devdata->npins; i++)
1099 pins[i] = pctl->devdata->pins[i].pin;
d48c2c02
HY		 1100
1101 pctl->pctl_desc.name = dev_name(&pdev->dev);
1102 pctl->pctl_desc.owner = THIS_MODULE;
1103 pctl->pctl_desc.pins = pins;
1104 pctl->pctl_desc.npins = pctl->devdata->npins;
1105 pctl->pctl_desc.confops = &mtk_pconf_ops;
1106 pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1107 pctl->pctl_desc.pmxops = &mtk_pmx_ops;
a6df410d 1108 pctl->dev = &pdev->dev;
d48c2c02 1109
03a3a558
LD		 1110 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1111 pctl);
0dd1628a
ADR		 1112 if (IS_ERR(pctl->pctl_dev))
1113 return dev_err_probe(dev, PTR_ERR(pctl->pctl_dev),
1114 "Couldn't register pinctrl driver\n");
a6df410d
HY		 1115
1116 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
03a3a558
LD		 1117 if (!pctl->chip)
1118 return -ENOMEM;
a6df410d 1119
fc63d854 1120 *pctl->chip = mtk_gpio_chip;
a6df410d
HY		 1121 pctl->chip->ngpio = pctl->devdata->npins;
1122 pctl->chip->label = dev_name(&pdev->dev);
58383c78 1123 pctl->chip->parent = &pdev->dev;
fc59e66c 1124 pctl->chip->base = -1;
a6df410d 1125
11aa679a 1126 ret = gpiochip_add_data(pctl->chip, pctl);
03a3a558
LD		 1127 if (ret)
1128 return -EINVAL;
a6df410d
HY		 1129
1130 /* Register the GPIO to pin mappings. */
1131 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1132 0, 0, pctl->devdata->npins);
1133 if (ret) {
1134 ret = -EINVAL;
1135 goto chip_error;
1136 }
1137
e46df235
SW		 1138 ret = mtk_eint_init(pctl, pdev);
1139 if (ret)
61a35576 1140 goto chip_error;
d9819eb9 1141
a6df410d
HY		 1142 return 0;
1143
1144chip_error:
1145 gpiochip_remove(pctl->chip);
a6df410d
HY		 1146 return ret;
1147}
e091feda
ADR		 1148
1149int mtk_pctrl_common_probe(struct platform_device *pdev)
1150{
1151 struct device *dev = &pdev->dev;
1152 const struct mtk_pinctrl_devdata *data = device_get_match_data(dev);
1153
1154 if (!data)
1155 return -ENODEV;
1156
1157 return mtk_pctrl_init(pdev, data, NULL);
1158}
Linux 6.x block layer and io_uring tree(s)