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gpio: pl061: use the generic request/free implementations
[linux-2.6-block.git] / drivers / pinctrl / mediatek / pinctrl-mtk-common.c
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a6df410d
HY		 1/*
2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_device.h>
22#include <linux/of_irq.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/pinctrl/machine.h>
25#include <linux/pinctrl/pinconf.h>
26#include <linux/pinctrl/pinconf-generic.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include <linux/bitops.h>
32#include <linux/regmap.h>
33#include <linux/mfd/syscon.h>
d9819eb9 34#include <linux/delay.h>
30f010f5 35#include <linux/interrupt.h>
58a5e1b6 36#include <linux/pm.h>
a6df410d
HY		 37#include <dt-bindings/pinctrl/mt65xx.h>
38
39#include "../core.h"
40#include "../pinconf.h"
41#include "../pinctrl-utils.h"
42#include "pinctrl-mtk-common.h"
43
44#define MAX_GPIO_MODE_PER_REG 5
45#define GPIO_MODE_BITS 3
46
47static const char * const mtk_gpio_functions[] = {
48 "func0", "func1", "func2", "func3",
49 "func4", "func5", "func6", "func7",
50};
51
52/*
53 * There are two base address for pull related configuration
54 * in mt8135, and different GPIO pins use different base address.
55 * When pin number greater than type1_start and less than type1_end,
56 * should use the second base address.
57 */
58static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
59 unsigned long pin)
60{
61 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
62 return pctl->regmap2;
63 return pctl->regmap1;
64}
65
66static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
67{
68 /* Different SoC has different mask and port shift. */
69 return ((pin >> 4) & pctl->devdata->port_mask)
70 << pctl->devdata->port_shf;
71}
72
73static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
74 struct pinctrl_gpio_range *range, unsigned offset,
75 bool input)
76{
77 unsigned int reg_addr;
78 unsigned int bit;
79 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
80
81 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
82 bit = BIT(offset & 0xf);
83
84 if (input)
85 /* Different SoC has different alignment offset. */
86 reg_addr = CLR_ADDR(reg_addr, pctl);
87 else
88 reg_addr = SET_ADDR(reg_addr, pctl);
89
90 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
91 return 0;
92}
93
94static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
95{
96 unsigned int reg_addr;
97 unsigned int bit;
98 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
99
100 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
101 bit = BIT(offset & 0xf);
102
103 if (value)
104 reg_addr = SET_ADDR(reg_addr, pctl);
105 else
106 reg_addr = CLR_ADDR(reg_addr, pctl);
107
108 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
109}
110
25d76b21
HY		 111static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
112 int value, enum pin_config_param arg)
a6df410d
HY		 113{
114 unsigned int reg_addr, offset;
115 unsigned int bit;
25d76b21
HY		 116
117 /**
118 * Due to some soc are not support ies/smt config, add this special
119 * control to handle it.
120 */
121 if (!pctl->devdata->spec_ies_smt_set &&
122 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
123 arg == PIN_CONFIG_INPUT_ENABLE)
124 return -EINVAL;
125
126 if (!pctl->devdata->spec_ies_smt_set &&
127 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
128 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
129 return -EINVAL;
30f010f5
HY		 130
131 /*
132 * Due to some pins are irregular, their input enable and smt
25d76b21 133 * control register are discontinuous, so we need this special handle.
30f010f5
HY		 134 */
135 if (pctl->devdata->spec_ies_smt_set) {
25d76b21
HY		 136 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
137 pin, pctl->devdata->port_align, value, arg);
30f010f5 138 }
a6df410d
HY		 139
140 bit = BIT(pin & 0xf);
141
25d76b21 142 if (arg == PIN_CONFIG_INPUT_ENABLE)
a6df410d
HY		 143 offset = pctl->devdata->ies_offset;
144 else
145 offset = pctl->devdata->smt_offset;
146
147 if (value)
148 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
149 else
150 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
151
152 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
25d76b21
HY		 153 return 0;
154}
155
156int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
157 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
158 unsigned int pin, unsigned char align, int value)
159{
160 unsigned int i, reg_addr, bit;
161
162 for (i = 0; i < info_num; i++) {
163 if (pin >= ies_smt_infos[i].start &&
164 pin <= ies_smt_infos[i].end) {
165 break;
166 }
167 }
168
169 if (i == info_num)
170 return -EINVAL;
171
172 if (value)
173 reg_addr = ies_smt_infos[i].offset + align;
174 else
175 reg_addr = ies_smt_infos[i].offset + (align << 1);
176
177 bit = BIT(ies_smt_infos[i].bit);
178 regmap_write(regmap, reg_addr, bit);
179 return 0;
a6df410d
HY		 180}
181
182static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
183 struct mtk_pinctrl *pctl, unsigned long pin) {
184 int i;
185
186 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
187 const struct mtk_pin_drv_grp *pin_drv =
188 pctl->devdata->pin_drv_grp + i;
189 if (pin == pin_drv->pin)
190 return pin_drv;
191 }
192
193 return NULL;
194}
195
196static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
197 unsigned int pin, unsigned char driving)
198{
199 const struct mtk_pin_drv_grp *pin_drv;
200 unsigned int val;
201 unsigned int bits, mask, shift;
202 const struct mtk_drv_group_desc *drv_grp;
203
204 if (pin >= pctl->devdata->npins)
205 return -EINVAL;
206
207 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
208 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
209 return -EINVAL;
210
211 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
212 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
213 && !(driving % drv_grp->step)) {
214 val = driving / drv_grp->step - 1;
215 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
216 mask = BIT(bits) - 1;
217 shift = pin_drv->bit + drv_grp->low_bit;
218 mask <<= shift;
219 val <<= shift;
220 return regmap_update_bits(mtk_get_regmap(pctl, pin),
221 pin_drv->offset, mask, val);
222 }
223
224 return -EINVAL;
225}
226
e73fe271
YC		 227int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
228 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
229 unsigned int info_num, unsigned int pin,
230 unsigned char align, bool isup, unsigned int r1r0)
231{
232 unsigned int i;
233 unsigned int reg_pupd, reg_set, reg_rst;
234 unsigned int bit_pupd, bit_r0, bit_r1;
235 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
236 bool find = false;
237
238 for (i = 0; i < info_num; i++) {
239 if (pin == pupd_infos[i].pin) {
240 find = true;
241 break;
242 }
243 }
244
245 if (!find)
246 return -EINVAL;
247
248 spec_pupd_pin = pupd_infos + i;
249 reg_set = spec_pupd_pin->offset + align;
250 reg_rst = spec_pupd_pin->offset + (align << 1);
251
252 if (isup)
253 reg_pupd = reg_rst;
254 else
255 reg_pupd = reg_set;
256
257 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
258 regmap_write(regmap, reg_pupd, bit_pupd);
259
260 bit_r0 = BIT(spec_pupd_pin->r0_bit);
261 bit_r1 = BIT(spec_pupd_pin->r1_bit);
262
263 switch (r1r0) {
264 case MTK_PUPD_SET_R1R0_00:
265 regmap_write(regmap, reg_rst, bit_r0);
266 regmap_write(regmap, reg_rst, bit_r1);
267 break;
268 case MTK_PUPD_SET_R1R0_01:
269 regmap_write(regmap, reg_set, bit_r0);
270 regmap_write(regmap, reg_rst, bit_r1);
271 break;
272 case MTK_PUPD_SET_R1R0_10:
273 regmap_write(regmap, reg_rst, bit_r0);
274 regmap_write(regmap, reg_set, bit_r1);
275 break;
276 case MTK_PUPD_SET_R1R0_11:
277 regmap_write(regmap, reg_set, bit_r0);
278 regmap_write(regmap, reg_set, bit_r1);
279 break;
280 default:
281 return -EINVAL;
282 }
283
284 return 0;
285}
286
a6df410d
HY		 287static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
288 unsigned int pin, bool enable, bool isup, unsigned int arg)
289{
290 unsigned int bit;
291 unsigned int reg_pullen, reg_pullsel;
292 int ret;
293
294 /* Some pins' pull setting are very different,
295 * they have separate pull up/down bit, R0 and R1
296 * resistor bit, so we need this special handle.
297 */
298 if (pctl->devdata->spec_pull_set) {
299 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
300 pin, pctl->devdata->port_align, isup, arg);
301 if (!ret)
302 return 0;
303 }
304
305 /* For generic pull config, default arg value should be 0 or 1. */
306 if (arg != 0 && arg != 1) {
307 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
308 arg, pin);
309 return -EINVAL;
310 }
311
312 bit = BIT(pin & 0xf);
313 if (enable)
314 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
315 pctl->devdata->pullen_offset, pctl);
316 else
317 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
318 pctl->devdata->pullen_offset, pctl);
319
320 if (isup)
321 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
322 pctl->devdata->pullsel_offset, pctl);
323 else
324 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
325 pctl->devdata->pullsel_offset, pctl);
326
327 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
328 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
329 return 0;
330}
331
332static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
333 unsigned int pin, enum pin_config_param param,
334 enum pin_config_param arg)
335{
25d76b21 336 int ret = 0;
a6df410d
HY		 337 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
338
339 switch (param) {
340 case PIN_CONFIG_BIAS_DISABLE:
25d76b21 341 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
a6df410d
HY		 342 break;
343 case PIN_CONFIG_BIAS_PULL_UP:
25d76b21 344 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
a6df410d
HY		 345 break;
346 case PIN_CONFIG_BIAS_PULL_DOWN:
25d76b21 347 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
a6df410d
HY		 348 break;
349 case PIN_CONFIG_INPUT_ENABLE:
25d76b21 350 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 351 break;
352 case PIN_CONFIG_OUTPUT:
353 mtk_gpio_set(pctl->chip, pin, arg);
25d76b21 354 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
a6df410d
HY		 355 break;
356 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
25d76b21 357 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 358 break;
359 case PIN_CONFIG_DRIVE_STRENGTH:
25d76b21 360 ret = mtk_pconf_set_driving(pctl, pin, arg);
a6df410d
HY		 361 break;
362 default:
25d76b21 363 ret = -EINVAL;
a6df410d
HY		 364 }
365
25d76b21 366 return ret;
a6df410d
HY		 367}
368
369static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
370 unsigned group,
371 unsigned long *config)
372{
373 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
374
375 *config = pctl->groups[group].config;
376
377 return 0;
378}
379
380static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
381 unsigned long *configs, unsigned num_configs)
382{
383 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
384 struct mtk_pinctrl_group *g = &pctl->groups[group];
25d76b21 385 int i, ret;
a6df410d
HY		 386
387 for (i = 0; i < num_configs; i++) {
25d76b21 388 ret = mtk_pconf_parse_conf(pctldev, g->pin,
a6df410d
HY		 389 pinconf_to_config_param(configs[i]),
390 pinconf_to_config_argument(configs[i]));
25d76b21
HY		 391 if (ret < 0)
392 return ret;
a6df410d
HY		 393
394 g->config = configs[i];
395 }
396
397 return 0;
398}
399
400static const struct pinconf_ops mtk_pconf_ops = {
401 .pin_config_group_get = mtk_pconf_group_get,
402 .pin_config_group_set = mtk_pconf_group_set,
403};
404
405static struct mtk_pinctrl_group *
406mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
407{
408 int i;
409
410 for (i = 0; i < pctl->ngroups; i++) {
411 struct mtk_pinctrl_group *grp = pctl->groups + i;
412
413 if (grp->pin == pin)
414 return grp;
415 }
416
417 return NULL;
418}
419
420static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
421 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
422{
423 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
424 const struct mtk_desc_function *func = pin->functions;
425
426 while (func && func->name) {
427 if (func->muxval == fnum)
428 return func;
429 func++;
430 }
431
432 return NULL;
433}
434
435static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
436 u32 pin_num, u32 fnum)
437{
438 int i;
439
440 for (i = 0; i < pctl->devdata->npins; i++) {
441 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
442
443 if (pin->pin.number == pin_num) {
444 const struct mtk_desc_function *func =
445 pin->functions;
446
447 while (func && func->name) {
448 if (func->muxval == fnum)
449 return true;
450 func++;
451 }
452
453 break;
454 }
455 }
456
457 return false;
458}
459
460static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
461 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
462 struct pinctrl_map **map, unsigned *reserved_maps,
463 unsigned *num_maps)
464{
465 bool ret;
466
467 if (*num_maps == *reserved_maps)
468 return -ENOSPC;
469
470 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
471 (*map)[*num_maps].data.mux.group = grp->name;
472
473 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
474 if (!ret) {
475 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
476 fnum, pin);
477 return -EINVAL;
478 }
479
480 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
481 (*num_maps)++;
482
483 return 0;
484}
485
486static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
487 struct device_node *node,
488 struct pinctrl_map **map,
489 unsigned *reserved_maps,
490 unsigned *num_maps)
491{
492 struct property *pins;
493 u32 pinfunc, pin, func;
494 int num_pins, num_funcs, maps_per_pin;
495 unsigned long *configs;
496 unsigned int num_configs;
497 bool has_config = 0;
498 int i, err;
499 unsigned reserve = 0;
500 struct mtk_pinctrl_group *grp;
501 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
502
503 pins = of_find_property(node, "pinmux", NULL);
504 if (!pins) {
505 dev_err(pctl->dev, "missing pins property in node %s .\n",
506 node->name);
507 return -EINVAL;
508 }
509
c445cac3
HY		 510 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
511 &num_configs);
a6df410d
HY		 512 if (num_configs)
513 has_config = 1;
514
515 num_pins = pins->length / sizeof(u32);
516 num_funcs = num_pins;
517 maps_per_pin = 0;
518 if (num_funcs)
519 maps_per_pin++;
520 if (has_config && num_pins >= 1)
521 maps_per_pin++;
522
523 if (!num_pins || !maps_per_pin)
524 return -EINVAL;
525
526 reserve = num_pins * maps_per_pin;
527
528 err = pinctrl_utils_reserve_map(pctldev, map,
529 reserved_maps, num_maps, reserve);
530 if (err < 0)
531 goto fail;
532
533 for (i = 0; i < num_pins; i++) {
534 err = of_property_read_u32_index(node, "pinmux",
535 i, &pinfunc);
536 if (err)
537 goto fail;
538
539 pin = MTK_GET_PIN_NO(pinfunc);
540 func = MTK_GET_PIN_FUNC(pinfunc);
541
542 if (pin >= pctl->devdata->npins ||
543 func >= ARRAY_SIZE(mtk_gpio_functions)) {
544 dev_err(pctl->dev, "invalid pins value.\n");
545 err = -EINVAL;
546 goto fail;
547 }
548
549 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
550 if (!grp) {
551 dev_err(pctl->dev, "unable to match pin %d to group\n",
552 pin);
553 return -EINVAL;
554 }
555
556 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
557 reserved_maps, num_maps);
558 if (err < 0)
559 goto fail;
560
561 if (has_config) {
562 err = pinctrl_utils_add_map_configs(pctldev, map,
563 reserved_maps, num_maps, grp->name,
564 configs, num_configs,
565 PIN_MAP_TYPE_CONFIGS_GROUP);
566 if (err < 0)
567 goto fail;
568 }
569 }
570
571 return 0;
572
573fail:
574 return err;
575}
576
577static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
578 struct device_node *np_config,
579 struct pinctrl_map **map, unsigned *num_maps)
580{
581 struct device_node *np;
582 unsigned reserved_maps;
583 int ret;
584
585 *map = NULL;
586 *num_maps = 0;
587 reserved_maps = 0;
588
589 for_each_child_of_node(np_config, np) {
590 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
591 &reserved_maps, num_maps);
592 if (ret < 0) {
593 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
594 return ret;
595 }
596 }
597
598 return 0;
599}
600
601static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
602{
603 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
604
605 return pctl->ngroups;
606}
607
608static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
609 unsigned group)
610{
611 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
612
613 return pctl->groups[group].name;
614}
615
616static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
617 unsigned group,
618 const unsigned **pins,
619 unsigned *num_pins)
620{
621 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
622
623 *pins = (unsigned *)&pctl->groups[group].pin;
624 *num_pins = 1;
625
626 return 0;
627}
628
629static const struct pinctrl_ops mtk_pctrl_ops = {
630 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
631 .dt_free_map = pinctrl_utils_dt_free_map,
632 .get_groups_count = mtk_pctrl_get_groups_count,
633 .get_group_name = mtk_pctrl_get_group_name,
634 .get_group_pins = mtk_pctrl_get_group_pins,
635};
636
637static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
638{
639 return ARRAY_SIZE(mtk_gpio_functions);
640}
641
642static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
643 unsigned selector)
644{
645 return mtk_gpio_functions[selector];
646}
647
648static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
649 unsigned function,
650 const char * const **groups,
651 unsigned * const num_groups)
652{
653 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
654
655 *groups = pctl->grp_names;
656 *num_groups = pctl->ngroups;
657
658 return 0;
659}
660
661static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
662 unsigned long pin, unsigned long mode)
663{
664 unsigned int reg_addr;
665 unsigned char bit;
666 unsigned int val;
667 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
668 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
669
670 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
671 + pctl->devdata->pinmux_offset;
672
673 bit = pin % MAX_GPIO_MODE_PER_REG;
674 mask <<= (GPIO_MODE_BITS * bit);
675 val = (mode << (GPIO_MODE_BITS * bit));
676 return regmap_update_bits(mtk_get_regmap(pctl, pin),
677 reg_addr, mask, val);
678}
679
d9819eb9
MM		 680static const struct mtk_desc_pin *
681mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
682{
683 int i;
684 const struct mtk_desc_pin *pin;
685
686 for (i = 0; i < pctl->devdata->npins; i++) {
687 pin = pctl->devdata->pins + i;
688 if (pin->eint.eintnum == eint_num)
689 return pin;
690 }
691
692 return NULL;
693}
694
a6df410d
HY		 695static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
696 unsigned function,
697 unsigned group)
698{
699 bool ret;
700 const struct mtk_desc_function *desc;
701 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
702 struct mtk_pinctrl_group *g = pctl->groups + group;
703
704 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
705 if (!ret) {
c70336cc 706 dev_err(pctl->dev, "invalid function %d on group %d .\n",
a6df410d
HY		 707 function, group);
708 return -EINVAL;
709 }
710
711 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
712 if (!desc)
713 return -EINVAL;
714 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
715 return 0;
716}
717
718static const struct pinmux_ops mtk_pmx_ops = {
719 .get_functions_count = mtk_pmx_get_funcs_cnt,
720 .get_function_name = mtk_pmx_get_func_name,
721 .get_function_groups = mtk_pmx_get_func_groups,
722 .set_mux = mtk_pmx_set_mux,
723 .gpio_set_direction = mtk_pmx_gpio_set_direction,
724};
725
726static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
727{
728 return pinctrl_request_gpio(chip->base + offset);
729}
730
731static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
732{
733 pinctrl_free_gpio(chip->base + offset);
734}
735
736static int mtk_gpio_direction_input(struct gpio_chip *chip,
737 unsigned offset)
738{
739 return pinctrl_gpio_direction_input(chip->base + offset);
740}
741
742static int mtk_gpio_direction_output(struct gpio_chip *chip,
743 unsigned offset, int value)
744{
745 mtk_gpio_set(chip, offset, value);
746 return pinctrl_gpio_direction_output(chip->base + offset);
747}
748
749static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
750{
751 unsigned int reg_addr;
752 unsigned int bit;
753 unsigned int read_val = 0;
754
755 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
756
757 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
758 bit = BIT(offset & 0xf);
759 regmap_read(pctl->regmap1, reg_addr, &read_val);
760 return !!(read_val & bit);
761}
762
763static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
764{
765 unsigned int reg_addr;
766 unsigned int bit;
767 unsigned int read_val = 0;
768 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
769
770 if (mtk_gpio_get_direction(chip, offset))
771 reg_addr = mtk_get_port(pctl, offset) +
772 pctl->devdata->dout_offset;
773 else
774 reg_addr = mtk_get_port(pctl, offset) +
775 pctl->devdata->din_offset;
776
777 bit = BIT(offset & 0xf);
778 regmap_read(pctl->regmap1, reg_addr, &read_val);
779 return !!(read_val & bit);
780}
781
d9819eb9
MM		 782static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
783{
784 const struct mtk_desc_pin *pin;
785 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
786 int irq;
787
788 pin = pctl->devdata->pins + offset;
789 if (pin->eint.eintnum == NO_EINT_SUPPORT)
790 return -EINVAL;
791
792 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
793 if (!irq)
794 return -EINVAL;
795
796 return irq;
797}
798
799static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
800{
801 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
802 const struct mtk_desc_pin *pin;
803 int ret;
804
805 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
806
807 if (!pin) {
808 dev_err(pctl->dev, "Can not find pin\n");
809 return -EINVAL;
810 }
811
812 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
813 if (ret) {
814 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
815 irqd_to_hwirq(d));
816 return ret;
817 }
818
819 /* set mux to INT mode */
820 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
821
822 return 0;
823}
824
825static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
826{
827 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
828 const struct mtk_desc_pin *pin;
829
830 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
831
832 if (!pin) {
833 dev_err(pctl->dev, "Can not find pin\n");
834 return;
835 }
836
837 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
838}
839
840static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
841 unsigned int eint_num, unsigned int offset)
842{
843 unsigned int eint_base = 0;
844 void __iomem *reg;
845
846 if (eint_num >= pctl->devdata->ap_num)
847 eint_base = pctl->devdata->ap_num;
848
849 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
850
851 return reg;
852}
853
854/*
855 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
856 * @eint_num: the EINT number to setmtk_pinctrl
857 */
858static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
859 unsigned int eint_num)
860{
861 unsigned int sens;
862 unsigned int bit = BIT(eint_num % 32);
863 const struct mtk_eint_offsets *eint_offsets =
864 &pctl->devdata->eint_offsets;
865
866 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
867 eint_offsets->sens);
868
869 if (readl(reg) & bit)
870 sens = MT_LEVEL_SENSITIVE;
871 else
872 sens = MT_EDGE_SENSITIVE;
873
874 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
875 return 1;
876 else
877 return 0;
878}
879
880/*
881 * mtk_eint_get_mask: To get the eint mask
882 * @eint_num: the EINT number to get
883 */
884static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
885 unsigned int eint_num)
886{
887 unsigned int bit = BIT(eint_num % 32);
888 const struct mtk_eint_offsets *eint_offsets =
889 &pctl->devdata->eint_offsets;
890
891 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
892 eint_offsets->mask);
893
894 return !!(readl(reg) & bit);
895}
896
3221f40b
YC		 897static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
898{
899 int start_level, curr_level;
900 unsigned int reg_offset;
901 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
902 u32 mask = 1 << (hwirq & 0x1f);
903 u32 port = (hwirq >> 5) & eint_offsets->port_mask;
904 void __iomem *reg = pctl->eint_reg_base + (port << 2);
905 const struct mtk_desc_pin *pin;
906
907 pin = mtk_find_pin_by_eint_num(pctl, hwirq);
908 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
909 do {
910 start_level = curr_level;
911 if (start_level)
912 reg_offset = eint_offsets->pol_clr;
913 else
914 reg_offset = eint_offsets->pol_set;
915 writel(mask, reg + reg_offset);
916
917 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
918 } while (start_level != curr_level);
919
920 return start_level;
921}
922
d9819eb9
MM		 923static void mtk_eint_mask(struct irq_data *d)
924{
925 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
926 const struct mtk_eint_offsets *eint_offsets =
927 &pctl->devdata->eint_offsets;
928 u32 mask = BIT(d->hwirq & 0x1f);
929 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
930 eint_offsets->mask_set);
931
932 writel(mask, reg);
933}
934
935static void mtk_eint_unmask(struct irq_data *d)
936{
937 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
938 const struct mtk_eint_offsets *eint_offsets =
939 &pctl->devdata->eint_offsets;
940 u32 mask = BIT(d->hwirq & 0x1f);
941 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
942 eint_offsets->mask_clr);
943
944 writel(mask, reg);
3221f40b
YC		 945
946 if (pctl->eint_dual_edges[d->hwirq])
947 mtk_eint_flip_edge(pctl, d->hwirq);
d9819eb9
MM		 948}
949
950static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
951 unsigned debounce)
952{
953 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
954 int eint_num, virq, eint_offset;
955 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
956 static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256};
957 const struct mtk_desc_pin *pin;
958 struct irq_data *d;
959
960 pin = pctl->devdata->pins + offset;
961 if (pin->eint.eintnum == NO_EINT_SUPPORT)
962 return -EINVAL;
963
964 eint_num = pin->eint.eintnum;
965 virq = irq_find_mapping(pctl->domain, eint_num);
966 eint_offset = (eint_num % 4) * 8;
967 d = irq_get_irq_data(virq);
968
969 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
970 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
971 if (!mtk_eint_can_en_debounce(pctl, eint_num))
972 return -ENOSYS;
973
974 dbnc = ARRAY_SIZE(dbnc_arr);
975 for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) {
976 if (debounce <= dbnc_arr[i]) {
977 dbnc = i;
978 break;
979 }
980 }
981
982 if (!mtk_eint_get_mask(pctl, eint_num)) {
983 mtk_eint_mask(d);
984 unmask = 1;
74d77e50
CIK		 985 } else {
986 unmask = 0;
d9819eb9
MM		 987 }
988
989 clr_bit = 0xff << eint_offset;
990 writel(clr_bit, pctl->eint_reg_base + clr_offset);
991
992 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
993 eint_offset;
994 rst = EINT_DBNC_RST_BIT << eint_offset;
995 writel(rst | bit, pctl->eint_reg_base + set_offset);
996
997 /* Delay a while (more than 2T) to wait for hw debounce counter reset
998 work correctly */
999 udelay(1);
1000 if (unmask == 1)
1001 mtk_eint_unmask(d);
1002
1003 return 0;
1004}
1005
a6df410d
HY		 1006static struct gpio_chip mtk_gpio_chip = {
1007 .owner = THIS_MODULE,
1008 .request = mtk_gpio_request,
1009 .free = mtk_gpio_free,
1010 .direction_input = mtk_gpio_direction_input,
1011 .direction_output = mtk_gpio_direction_output,
1012 .get = mtk_gpio_get,
1013 .set = mtk_gpio_set,
d9819eb9
MM		 1014 .to_irq = mtk_gpio_to_irq,
1015 .set_debounce = mtk_gpio_set_debounce,
a6df410d
HY		 1016 .of_gpio_n_cells = 2,
1017};
1018
d9819eb9
MM		 1019static int mtk_eint_set_type(struct irq_data *d,
1020 unsigned int type)
1021{
1022 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1023 const struct mtk_eint_offsets *eint_offsets =
1024 &pctl->devdata->eint_offsets;
1025 u32 mask = BIT(d->hwirq & 0x1f);
1026 void __iomem *reg;
1027
1028 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
d9819eb9
MM		 1029 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
1030 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
1031 d->irq, d->hwirq, type);
1032 return -EINVAL;
1033 }
1034
3221f40b
YC		 1035 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1036 pctl->eint_dual_edges[d->hwirq] = 1;
1037 else
1038 pctl->eint_dual_edges[d->hwirq] = 0;
1039
d9819eb9
MM		 1040 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
1041 reg = mtk_eint_get_offset(pctl, d->hwirq,
1042 eint_offsets->pol_clr);
1043 writel(mask, reg);
1044 } else {
1045 reg = mtk_eint_get_offset(pctl, d->hwirq,
1046 eint_offsets->pol_set);
1047 writel(mask, reg);
1048 }
1049
1050 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1051 reg = mtk_eint_get_offset(pctl, d->hwirq,
1052 eint_offsets->sens_clr);
1053 writel(mask, reg);
1054 } else {
1055 reg = mtk_eint_get_offset(pctl, d->hwirq,
1056 eint_offsets->sens_set);
1057 writel(mask, reg);
1058 }
1059
3221f40b
YC		 1060 if (pctl->eint_dual_edges[d->hwirq])
1061 mtk_eint_flip_edge(pctl, d->hwirq);
1062
d9819eb9
MM		 1063 return 0;
1064}
1065
58a5e1b6
MM		 1066static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
1067{
1068 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1069 int shift = d->hwirq & 0x1f;
1070 int reg = d->hwirq >> 5;
1071
1072 if (on)
1073 pctl->wake_mask[reg] |= BIT(shift);
1074 else
1075 pctl->wake_mask[reg] &= ~BIT(shift);
1076
1077 return 0;
1078}
1079
1080static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip,
1081 void __iomem *eint_reg_base, u32 *buf)
1082{
1083 int port;
1084 void __iomem *reg;
1085
1086 for (port = 0; port < chip->ports; port++) {
1087 reg = eint_reg_base + (port << 2);
1088 writel_relaxed(~buf[port], reg + chip->mask_set);
1089 writel_relaxed(buf[port], reg + chip->mask_clr);
1090 }
1091}
1092
1093static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip,
1094 void __iomem *eint_reg_base, u32 *buf)
1095{
1096 int port;
1097 void __iomem *reg;
1098
1099 for (port = 0; port < chip->ports; port++) {
1100 reg = eint_reg_base + chip->mask + (port << 2);
1101 buf[port] = ~readl_relaxed(reg);
1102 /* Mask is 0 when irq is enabled, and 1 when disabled. */
1103 }
1104}
1105
1106static int mtk_eint_suspend(struct device *device)
1107{
1108 void __iomem *reg;
1109 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1110 const struct mtk_eint_offsets *eint_offsets =
1111 &pctl->devdata->eint_offsets;
1112
1113 reg = pctl->eint_reg_base;
1114 mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask);
1115 mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask);
1116
1117 return 0;
1118}
1119
1120static int mtk_eint_resume(struct device *device)
1121{
1122 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1123 const struct mtk_eint_offsets *eint_offsets =
1124 &pctl->devdata->eint_offsets;
1125
1126 mtk_eint_chip_write_mask(eint_offsets,
1127 pctl->eint_reg_base, pctl->cur_mask);
1128
1129 return 0;
1130}
1131
1132const struct dev_pm_ops mtk_eint_pm_ops = {
1133 .suspend = mtk_eint_suspend,
1134 .resume = mtk_eint_resume,
1135};
1136
d9819eb9
MM		 1137static void mtk_eint_ack(struct irq_data *d)
1138{
1139 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1140 const struct mtk_eint_offsets *eint_offsets =
1141 &pctl->devdata->eint_offsets;
1142 u32 mask = BIT(d->hwirq & 0x1f);
1143 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
1144 eint_offsets->ack);
1145
1146 writel(mask, reg);
1147}
1148
1149static struct irq_chip mtk_pinctrl_irq_chip = {
1150 .name = "mt-eint",
58a5e1b6 1151 .irq_disable = mtk_eint_mask,
d9819eb9
MM		 1152 .irq_mask = mtk_eint_mask,
1153 .irq_unmask = mtk_eint_unmask,
1154 .irq_ack = mtk_eint_ack,
1155 .irq_set_type = mtk_eint_set_type,
58a5e1b6 1156 .irq_set_wake = mtk_eint_irq_set_wake,
d9819eb9
MM		 1157 .irq_request_resources = mtk_pinctrl_irq_request_resources,
1158 .irq_release_resources = mtk_pinctrl_irq_release_resources,
1159};
1160
1161static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
1162{
1163 const struct mtk_eint_offsets *eint_offsets =
1164 &pctl->devdata->eint_offsets;
1165 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
1166 unsigned int i;
1167
1168 for (i = 0; i < pctl->devdata->ap_num; i += 32) {
1169 writel(0xffffffff, reg);
1170 reg += 4;
1171 }
1172 return 0;
1173}
1174
1175static inline void
1176mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
1177{
1178 unsigned int rst, ctrl_offset;
1179 unsigned int bit, dbnc;
1180 const struct mtk_eint_offsets *eint_offsets =
1181 &pctl->devdata->eint_offsets;
1182
1183 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
1184 dbnc = readl(pctl->eint_reg_base + ctrl_offset);
1185 bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
1186 if ((bit & dbnc) > 0) {
1187 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
1188 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
1189 writel(rst, pctl->eint_reg_base + ctrl_offset);
1190 }
1191}
1192
bd0b9ac4 1193static void mtk_eint_irq_handler(struct irq_desc *desc)
d9819eb9 1194{
5663bb27
JL		 1195 struct irq_chip *chip = irq_desc_get_chip(desc);
1196 struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
d9819eb9
MM		 1197 unsigned int status, eint_num;
1198 int offset, index, virq;
1199 const struct mtk_eint_offsets *eint_offsets =
1200 &pctl->devdata->eint_offsets;
1201 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
3221f40b
YC		 1202 int dual_edges, start_level, curr_level;
1203 const struct mtk_desc_pin *pin;
d9819eb9
MM		 1204
1205 chained_irq_enter(chip, desc);
1206 for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) {
1207 status = readl(reg);
1208 reg += 4;
1209 while (status) {
1210 offset = __ffs(status);
1211 index = eint_num + offset;
1212 virq = irq_find_mapping(pctl->domain, index);
1213 status &= ~BIT(offset);
1214
3221f40b
YC		 1215 dual_edges = pctl->eint_dual_edges[index];
1216 if (dual_edges) {
1217 /* Clear soft-irq in case we raised it
1218 last time */
1219 writel(BIT(offset), reg - eint_offsets->stat +
1220 eint_offsets->soft_clr);
1221
1222 pin = mtk_find_pin_by_eint_num(pctl, index);
1223 start_level = mtk_gpio_get(pctl->chip,
1224 pin->pin.number);
1225 }
1226
d9819eb9
MM		 1227 generic_handle_irq(virq);
1228
3221f40b
YC		 1229 if (dual_edges) {
1230 curr_level = mtk_eint_flip_edge(pctl, index);
1231
1232 /* If level changed, we might lost one edge
1233 interrupt, raised it through soft-irq */
1234 if (start_level != curr_level)
1235 writel(BIT(offset), reg -
1236 eint_offsets->stat +
1237 eint_offsets->soft_set);
1238 }
1239
d9819eb9
MM		 1240 if (index < pctl->devdata->db_cnt)
1241 mtk_eint_debounce_process(pctl , index);
1242 }
1243 }
1244 chained_irq_exit(chip, desc);
1245}
1246
a6df410d
HY		 1247static int mtk_pctrl_build_state(struct platform_device *pdev)
1248{
1249 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
1250 int i;
1251
1252 pctl->ngroups = pctl->devdata->npins;
1253
1254 /* Allocate groups */
0206caa8
AL		 1255 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1256 sizeof(*pctl->groups), GFP_KERNEL);
a6df410d
HY		 1257 if (!pctl->groups)
1258 return -ENOMEM;
1259
1260 /* We assume that one pin is one group, use pin name as group name. */
0206caa8
AL		 1261 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1262 sizeof(*pctl->grp_names), GFP_KERNEL);
a6df410d
HY		 1263 if (!pctl->grp_names)
1264 return -ENOMEM;
1265
1266 for (i = 0; i < pctl->devdata->npins; i++) {
1267 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
1268 struct mtk_pinctrl_group *group = pctl->groups + i;
1269
1270 group->name = pin->pin.name;
1271 group->pin = pin->pin.number;
1272
1273 pctl->grp_names[i] = pin->pin.name;
1274 }
1275
1276 return 0;
1277}
1278
a6df410d 1279int mtk_pctrl_init(struct platform_device *pdev,
fc59e66c
HY		 1280 const struct mtk_pinctrl_devdata *data,
1281 struct regmap *regmap)
a6df410d
HY		 1282{
1283 struct pinctrl_pin_desc *pins;
1284 struct mtk_pinctrl *pctl;
1285 struct device_node *np = pdev->dev.of_node, *node;
1286 struct property *prop;
d9819eb9 1287 struct resource *res;
58a5e1b6 1288 int i, ret, irq, ports_buf;
a6df410d
HY		 1289
1290 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1291 if (!pctl)
1292 return -ENOMEM;
1293
1294 platform_set_drvdata(pdev, pctl);
1295
1296 prop = of_find_property(np, "pins-are-numbered", NULL);
1297 if (!prop) {
c445cac3 1298 dev_err(&pdev->dev, "only support pins-are-numbered format\n");
a6df410d
HY		 1299 return -EINVAL;
1300 }
1301
1302 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1303 if (node) {
1304 pctl->regmap1 = syscon_node_to_regmap(node);
1305 if (IS_ERR(pctl->regmap1))
1306 return PTR_ERR(pctl->regmap1);
fc59e66c
HY		 1307 } else if (regmap) {
1308 pctl->regmap1 = regmap;
1309 } else {
1310 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1311 return -EINVAL;
a6df410d
HY		 1312 }
1313
1314 /* Only 8135 has two base addr, other SoCs have only one. */
1315 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1316 if (node) {
1317 pctl->regmap2 = syscon_node_to_regmap(node);
1318 if (IS_ERR(pctl->regmap2))
1319 return PTR_ERR(pctl->regmap2);
1320 }
1321
1322 pctl->devdata = data;
1323 ret = mtk_pctrl_build_state(pdev);
1324 if (ret) {
1325 dev_err(&pdev->dev, "build state failed: %d\n", ret);
1326 return -EINVAL;
1327 }
1328
0206caa8 1329 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
a6df410d
HY		 1330 GFP_KERNEL);
1331 if (!pins)
1332 return -ENOMEM;
1333
1334 for (i = 0; i < pctl->devdata->npins; i++)
1335 pins[i] = pctl->devdata->pins[i].pin;
d48c2c02
HY		 1336
1337 pctl->pctl_desc.name = dev_name(&pdev->dev);
1338 pctl->pctl_desc.owner = THIS_MODULE;
1339 pctl->pctl_desc.pins = pins;
1340 pctl->pctl_desc.npins = pctl->devdata->npins;
1341 pctl->pctl_desc.confops = &mtk_pconf_ops;
1342 pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1343 pctl->pctl_desc.pmxops = &mtk_pmx_ops;
a6df410d 1344 pctl->dev = &pdev->dev;
d48c2c02
HY		 1345
1346 pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl);
323de9ef 1347 if (IS_ERR(pctl->pctl_dev)) {
a6df410d 1348 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
323de9ef 1349 return PTR_ERR(pctl->pctl_dev);
a6df410d
HY		 1350 }
1351
1352 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1353 if (!pctl->chip) {
1354 ret = -ENOMEM;
1355 goto pctrl_error;
1356 }
1357
fc63d854 1358 *pctl->chip = mtk_gpio_chip;
a6df410d
HY		 1359 pctl->chip->ngpio = pctl->devdata->npins;
1360 pctl->chip->label = dev_name(&pdev->dev);
1361 pctl->chip->dev = &pdev->dev;
fc59e66c 1362 pctl->chip->base = -1;
a6df410d
HY		 1363
1364 ret = gpiochip_add(pctl->chip);
1365 if (ret) {
1366 ret = -EINVAL;
1367 goto pctrl_error;
1368 }
1369
1370 /* Register the GPIO to pin mappings. */
1371 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1372 0, 0, pctl->devdata->npins);
1373 if (ret) {
1374 ret = -EINVAL;
1375 goto chip_error;
1376 }
1377
fc63d854 1378 if (!of_property_read_bool(np, "interrupt-controller"))
fc59e66c
HY		 1379 return 0;
1380
d9819eb9
MM		 1381 /* Get EINT register base from dts. */
1382 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1383 if (!res) {
1384 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
1385 ret = -EINVAL;
1386 goto chip_error;
1387 }
1388
1389 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
1390 if (IS_ERR(pctl->eint_reg_base)) {
1391 ret = -EINVAL;
1392 goto chip_error;
1393 }
1394
58a5e1b6
MM		 1395 ports_buf = pctl->devdata->eint_offsets.ports;
1396 pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf,
1397 sizeof(*pctl->wake_mask), GFP_KERNEL);
1398 if (!pctl->wake_mask) {
1399 ret = -ENOMEM;
1400 goto chip_error;
1401 }
1402
1403 pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf,
1404 sizeof(*pctl->cur_mask), GFP_KERNEL);
1405 if (!pctl->cur_mask) {
1406 ret = -ENOMEM;
1407 goto chip_error;
1408 }
1409
0206caa8
AL		 1410 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
1411 sizeof(int), GFP_KERNEL);
3221f40b
YC		 1412 if (!pctl->eint_dual_edges) {
1413 ret = -ENOMEM;
1414 goto chip_error;
1415 }
1416
d9819eb9
MM		 1417 irq = irq_of_parse_and_map(np, 0);
1418 if (!irq) {
1419 dev_err(&pdev->dev, "couldn't parse and map irq\n");
1420 ret = -EINVAL;
61a35576 1421 goto chip_error;
d9819eb9
MM		 1422 }
1423
1424 pctl->domain = irq_domain_add_linear(np,
1425 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
1426 if (!pctl->domain) {
1427 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1428 ret = -ENOMEM;
61a35576 1429 goto chip_error;
d9819eb9
MM		 1430 }
1431
1432 mtk_eint_init(pctl);
1433 for (i = 0; i < pctl->devdata->ap_num; i++) {
1434 int virq = irq_create_mapping(pctl->domain, i);
1435
1436 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1437 handle_level_irq);
1438 irq_set_chip_data(virq, pctl);
d9819eb9
MM		 1439 };
1440
1e105921 1441 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
a6df410d
HY		 1442 return 0;
1443
1444chip_error:
1445 gpiochip_remove(pctl->chip);
1446pctrl_error:
1447 pinctrl_unregister(pctl->pctl_dev);
1448 return ret;
1449}
1450
1451MODULE_LICENSE("GPL");
1452MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
1453MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
Linux 6.x block layer and io_uring tree(s)