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875a92b3 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
7981c001 MW |
2 | /* |
3 | * Core pinctrl/GPIO driver for Intel GPIO controllers | |
4 | * | |
5 | * Copyright (C) 2015, Intel Corporation | |
6 | * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> | |
7 | * Mika Westerberg <mika.westerberg@linux.intel.com> | |
7981c001 MW |
8 | */ |
9 | ||
10 | #ifndef PINCTRL_INTEL_H | |
11 | #define PINCTRL_INTEL_H | |
12 | ||
f29047a0 | 13 | #include <linux/array_size.h> |
04d53068 AS |
14 | #include <linux/bits.h> |
15 | #include <linux/compiler_types.h> | |
66c812d2 AS |
16 | #include <linux/gpio/driver.h> |
17 | #include <linux/irq.h> | |
677506ee | 18 | #include <linux/pm.h> |
04d53068 | 19 | #include <linux/pinctrl/pinctrl.h> |
66c812d2 | 20 | #include <linux/spinlock_types.h> |
677506ee | 21 | |
7981c001 MW |
22 | struct platform_device; |
23 | struct device; | |
24 | ||
25 | /** | |
26 | * struct intel_pingroup - Description about group of pins | |
277b95a9 AS |
27 | * @grp: Generic data of the pin group (name and pins) |
28 | * @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL. | |
1f6b419b | 29 | * @modes: If not %NULL this will hold mode for each pin in @pins |
7981c001 MW |
30 | */ |
31 | struct intel_pingroup { | |
277b95a9 | 32 | struct pingroup grp; |
7981c001 | 33 | unsigned short mode; |
04035f7f | 34 | const unsigned int *modes; |
7981c001 MW |
35 | }; |
36 | ||
37 | /** | |
38 | * struct intel_function - Description about a function | |
999b85bf | 39 | * @func: Generic data of the pin function (name and groups of pins) |
7981c001 MW |
40 | */ |
41 | struct intel_function { | |
999b85bf | 42 | struct pinfunction func; |
7981c001 MW |
43 | }; |
44 | ||
ed153b07 AS |
45 | #define INTEL_PINCTRL_MAX_GPP_SIZE 32 |
46 | ||
919eb475 MW |
47 | /** |
48 | * struct intel_padgroup - Hardware pad group information | |
49 | * @reg_num: GPI_IS register number | |
50 | * @base: Starting pin of this group | |
ed153b07 | 51 | * @size: Size of this group (maximum is %INTEL_PINCTRL_MAX_GPP_SIZE). |
e5a4ab6a | 52 | * @gpio_base: Starting GPIO base of this group |
919eb475 MW |
53 | * @padown_num: PAD_OWN register number (assigned by the core driver) |
54 | * | |
55 | * If pad groups of a community are not the same size, use this structure | |
56 | * to specify them. | |
57 | */ | |
58 | struct intel_padgroup { | |
04035f7f AS |
59 | unsigned int reg_num; |
60 | unsigned int base; | |
61 | unsigned int size; | |
a60eac32 | 62 | int gpio_base; |
04035f7f | 63 | unsigned int padown_num; |
919eb475 MW |
64 | }; |
65 | ||
e5a4ab6a AS |
66 | /** |
67 | * enum - Special treatment for GPIO base in pad group | |
68 | * | |
9bd59157 | 69 | * @INTEL_GPIO_BASE_ZERO: force GPIO base to be 0 |
e5a4ab6a AS |
70 | * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created |
71 | * @INTEL_GPIO_BASE_MATCH: matches with starting pin number | |
72 | */ | |
73 | enum { | |
9bd59157 | 74 | INTEL_GPIO_BASE_ZERO = -2, |
e5a4ab6a AS |
75 | INTEL_GPIO_BASE_NOMAP = -1, |
76 | INTEL_GPIO_BASE_MATCH = 0, | |
77 | }; | |
78 | ||
7981c001 MW |
79 | /** |
80 | * struct intel_community - Intel pin community description | |
81 | * @barno: MMIO BAR number where registers for this community reside | |
82 | * @padown_offset: Register offset of PAD_OWN register from @regs. If %0 | |
83 | * then there is no support for owner. | |
84 | * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then | |
85 | * locking is not supported. | |
86 | * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it | |
87 | * is assumed that the host owns the pin (rather than | |
88 | * ACPI). | |
179e5a61 | 89 | * @is_offset: Register offset of GPI_IS from @regs. |
7981c001 | 90 | * @ie_offset: Register offset of GPI_IE from @regs. |
34e65670 | 91 | * @features: Additional features supported by the hardware |
7981c001 | 92 | * @pin_base: Starting pin of pins in this community |
6d649fca | 93 | * @npins: Number of pins in this community |
618a919b | 94 | * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, |
2ccb9cc3 | 95 | * HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL. |
919eb475 | 96 | * @gpp_num_padown_regs: Number of pad registers each pad group consumes at |
cd025b1c | 97 | * minimum. Used when @gpps is %NULL. |
919eb475 MW |
98 | * @gpps: Pad groups if the controller has variable size pad groups |
99 | * @ngpps: Number of pad groups in this community | |
34e65670 | 100 | * @pad_map: Optional non-linear mapping of the pads |
42fecd55 | 101 | * @nirqs: Optional total number of IRQs this community can generate |
c8f8f65e | 102 | * @acpi_space_id: Optional address space ID for ACPI OpRegion handler |
7981c001 MW |
103 | * @regs: Community specific common registers (reserved for core driver) |
104 | * @pad_regs: Community specific pad registers (reserved for core driver) | |
919eb475 | 105 | * |
cd025b1c | 106 | * In older Intel GPIO host controllers, this driver supports, each pad group |
2ccb9cc3 | 107 | * is of equal size (except the last one). In that case the driver can just |
cd025b1c AS |
108 | * fill in @gpp_size and @gpp_num_padown_regs fields and let the core driver |
109 | * to handle the rest. | |
110 | * | |
111 | * In newer Intel GPIO host controllers each pad group is of variable size, | |
112 | * so the client driver can pass custom @gpps and @ngpps instead. | |
7981c001 MW |
113 | */ |
114 | struct intel_community { | |
04035f7f AS |
115 | unsigned int barno; |
116 | unsigned int padown_offset; | |
117 | unsigned int padcfglock_offset; | |
118 | unsigned int hostown_offset; | |
119 | unsigned int is_offset; | |
120 | unsigned int ie_offset; | |
34e65670 | 121 | unsigned int features; |
04035f7f | 122 | unsigned int pin_base; |
6d649fca | 123 | size_t npins; |
04035f7f AS |
124 | unsigned int gpp_size; |
125 | unsigned int gpp_num_padown_regs; | |
919eb475 MW |
126 | const struct intel_padgroup *gpps; |
127 | size_t ngpps; | |
34e65670 | 128 | const unsigned int *pad_map; |
42fecd55 | 129 | unsigned short nirqs; |
c8f8f65e | 130 | unsigned short acpi_space_id; |
6d649fca | 131 | |
919eb475 | 132 | /* Reserved for the core driver */ |
7981c001 MW |
133 | void __iomem *regs; |
134 | void __iomem *pad_regs; | |
7981c001 MW |
135 | }; |
136 | ||
e57725ea MW |
137 | /* Additional features supported by the hardware */ |
138 | #define PINCTRL_FEATURE_DEBOUNCE BIT(0) | |
04cc058f | 139 | #define PINCTRL_FEATURE_1K_PD BIT(1) |
91d898e5 AS |
140 | #define PINCTRL_FEATURE_GPIO_HW_INFO BIT(2) |
141 | #define PINCTRL_FEATURE_PWM BIT(3) | |
142 | #define PINCTRL_FEATURE_BLINK BIT(4) | |
143 | #define PINCTRL_FEATURE_EXP BIT(5) | |
e57725ea | 144 | |
100b54e4 AS |
145 | #define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc) \ |
146 | { \ | |
147 | .barno = (b), \ | |
148 | .padown_offset = soc ## _PAD_OWN, \ | |
149 | .padcfglock_offset = soc ## _PADCFGLOCK, \ | |
150 | .hostown_offset = soc ## _HOSTSW_OWN, \ | |
151 | .is_offset = soc ## _GPI_IS, \ | |
152 | .ie_offset = soc ## _GPI_IE, \ | |
153 | .gpp_size = (gs), \ | |
154 | .gpp_num_padown_regs = (gn), \ | |
155 | .pin_base = (s), \ | |
156 | .npins = ((e) - (s) + 1), \ | |
157 | .gpps = (g), \ | |
158 | .ngpps = (n), \ | |
159 | } | |
160 | ||
161 | #define INTEL_COMMUNITY_GPPS(b, s, e, g, soc) \ | |
162 | __INTEL_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), 0, 0, soc) | |
163 | ||
164 | #define INTEL_COMMUNITY_SIZE(b, s, e, gs, gn, soc) \ | |
165 | __INTEL_COMMUNITY(b, s, e, NULL, 0, gs, gn, soc) | |
166 | ||
1f6b419b MW |
167 | /** |
168 | * PIN_GROUP - Declare a pin group | |
169 | * @n: Name of the group | |
170 | * @p: An array of pins this group consists | |
171 | * @m: Mode which the pins are put when this group is active. Can be either | |
172 | * a single integer or an array of integers in which case mode is per | |
173 | * pin. | |
174 | */ | |
277b95a9 AS |
175 | #define PIN_GROUP(n, p, m) \ |
176 | { \ | |
277b95a9 AS |
177 | .grp = PINCTRL_PINGROUP((n), (p), ARRAY_SIZE((p))), \ |
178 | .mode = __builtin_choose_expr(__builtin_constant_p((m)), (m), 0), \ | |
179 | .modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \ | |
7981c001 MW |
180 | } |
181 | ||
fed6d9a8 HG |
182 | #define PIN_GROUP_GPIO(n, p, m) \ |
183 | PIN_GROUP(n, p, m), \ | |
184 | PIN_GROUP(n "_gpio", p, 0) | |
185 | ||
999b85bf AS |
186 | #define FUNCTION(n, g) \ |
187 | { \ | |
188 | .func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)), \ | |
7981c001 MW |
189 | } |
190 | ||
191 | /** | |
192 | * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration | |
193 | * @uid: ACPI _UID for the probe driver use if needed | |
194 | * @pins: Array if pins this pinctrl controls | |
195 | * @npins: Number of pins in the array | |
196 | * @groups: Array of pin groups | |
197 | * @ngroups: Number of groups in the array | |
198 | * @functions: Array of functions | |
199 | * @nfunctions: Number of functions in the array | |
200 | * @communities: Array of communities this pinctrl handles | |
201 | * @ncommunities: Number of communities in the array | |
202 | * | |
203 | * The @communities is used as a template by the core driver. It will make | |
204 | * copy of all communities and fill in rest of the information. | |
205 | */ | |
206 | struct intel_pinctrl_soc_data { | |
207 | const char *uid; | |
208 | const struct pinctrl_pin_desc *pins; | |
209 | size_t npins; | |
210 | const struct intel_pingroup *groups; | |
211 | size_t ngroups; | |
212 | const struct intel_function *functions; | |
213 | size_t nfunctions; | |
214 | const struct intel_community *communities; | |
215 | size_t ncommunities; | |
216 | }; | |
217 | ||
ff360d62 AS |
218 | const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev); |
219 | ||
66c812d2 AS |
220 | struct intel_pad_context; |
221 | struct intel_community_context; | |
222 | ||
223 | /** | |
224 | * struct intel_pinctrl_context - context to be saved during suspend-resume | |
225 | * @pads: Opaque context per pad (driver dependent) | |
226 | * @communities: Opaque context per community (driver dependent) | |
227 | */ | |
228 | struct intel_pinctrl_context { | |
229 | struct intel_pad_context *pads; | |
230 | struct intel_community_context *communities; | |
231 | }; | |
232 | ||
233 | /** | |
234 | * struct intel_pinctrl - Intel pinctrl private structure | |
235 | * @dev: Pointer to the device structure | |
236 | * @lock: Lock to serialize register access | |
237 | * @pctldesc: Pin controller description | |
238 | * @pctldev: Pointer to the pin controller device | |
239 | * @chip: GPIO chip in this pin controller | |
66c812d2 AS |
240 | * @soc: SoC/PCH specific pin configuration data |
241 | * @communities: All communities in this pin controller | |
242 | * @ncommunities: Number of communities in this pin controller | |
243 | * @context: Configuration saved over system sleep | |
244 | * @irq: pinctrl/GPIO chip irq number | |
245 | */ | |
246 | struct intel_pinctrl { | |
247 | struct device *dev; | |
248 | raw_spinlock_t lock; | |
249 | struct pinctrl_desc pctldesc; | |
250 | struct pinctrl_dev *pctldev; | |
251 | struct gpio_chip chip; | |
66c812d2 AS |
252 | const struct intel_pinctrl_soc_data *soc; |
253 | struct intel_community *communities; | |
254 | size_t ncommunities; | |
255 | struct intel_pinctrl_context context; | |
256 | int irq; | |
257 | }; | |
258 | ||
4c51ea95 AS |
259 | int intel_pinctrl_probe(struct platform_device *pdev, |
260 | const struct intel_pinctrl_soc_data *soc_data); | |
261 | ||
70c263c4 | 262 | int intel_pinctrl_probe_by_hid(struct platform_device *pdev); |
924cf800 AS |
263 | int intel_pinctrl_probe_by_uid(struct platform_device *pdev); |
264 | ||
b10a74b5 AS |
265 | extern const struct dev_pm_ops intel_pinctrl_pm_ops; |
266 | ||
25018ace RJ |
267 | struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin); |
268 | ||
269 | int intel_get_groups_count(struct pinctrl_dev *pctldev); | |
270 | const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group); | |
271 | int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, | |
272 | const unsigned int **pins, unsigned int *npins); | |
273 | ||
274 | int intel_get_functions_count(struct pinctrl_dev *pctldev); | |
275 | const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function); | |
276 | int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, | |
277 | const char * const **groups, unsigned int * const ngroups); | |
278 | ||
7981c001 | 279 | #endif /* PINCTRL_INTEL_H */ |