Commit | Line | Data |
---|---|---|
875a92b3 | 1 | // SPDX-License-Identifier: GPL-2.0 |
7981c001 MW |
2 | /* |
3 | * Intel pinctrl/GPIO core driver. | |
4 | * | |
5 | * Copyright (C) 2015, Intel Corporation | |
6 | * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> | |
7 | * Mika Westerberg <mika.westerberg@linux.intel.com> | |
7981c001 MW |
8 | */ |
9 | ||
924cf800 | 10 | #include <linux/acpi.h> |
7981c001 | 11 | #include <linux/gpio/driver.h> |
66c812d2 | 12 | #include <linux/interrupt.h> |
e57725ea | 13 | #include <linux/log2.h> |
6a33a1d6 | 14 | #include <linux/module.h> |
7981c001 | 15 | #include <linux/platform_device.h> |
924cf800 | 16 | #include <linux/property.h> |
6a33a1d6 | 17 | #include <linux/time.h> |
924cf800 | 18 | |
7981c001 MW |
19 | #include <linux/pinctrl/pinctrl.h> |
20 | #include <linux/pinctrl/pinmux.h> | |
21 | #include <linux/pinctrl/pinconf.h> | |
22 | #include <linux/pinctrl/pinconf-generic.h> | |
23 | ||
c538b943 | 24 | #include "../core.h" |
7981c001 MW |
25 | #include "pinctrl-intel.h" |
26 | ||
7981c001 | 27 | /* Offset from regs */ |
e57725ea MW |
28 | #define REVID 0x000 |
29 | #define REVID_SHIFT 16 | |
30 | #define REVID_MASK GENMASK(31, 16) | |
31 | ||
91d898e5 AS |
32 | #define CAPLIST 0x004 |
33 | #define CAPLIST_ID_SHIFT 16 | |
34 | #define CAPLIST_ID_MASK GENMASK(23, 16) | |
35 | #define CAPLIST_ID_GPIO_HW_INFO 1 | |
36 | #define CAPLIST_ID_PWM 2 | |
37 | #define CAPLIST_ID_BLINK 3 | |
38 | #define CAPLIST_ID_EXP 4 | |
39 | #define CAPLIST_NEXT_SHIFT 0 | |
40 | #define CAPLIST_NEXT_MASK GENMASK(15, 0) | |
41 | ||
7981c001 | 42 | #define PADBAR 0x00c |
7981c001 MW |
43 | |
44 | #define PADOWN_BITS 4 | |
45 | #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) | |
e58926e7 | 46 | #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) |
99a735b3 | 47 | #define PADOWN_GPP(p) ((p) / 8) |
7981c001 MW |
48 | |
49 | /* Offset from pad_regs */ | |
50 | #define PADCFG0 0x000 | |
51 | #define PADCFG0_RXEVCFG_SHIFT 25 | |
e58926e7 | 52 | #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25) |
7981c001 MW |
53 | #define PADCFG0_RXEVCFG_LEVEL 0 |
54 | #define PADCFG0_RXEVCFG_EDGE 1 | |
55 | #define PADCFG0_RXEVCFG_DISABLED 2 | |
56 | #define PADCFG0_RXEVCFG_EDGE_BOTH 3 | |
e57725ea | 57 | #define PADCFG0_PREGFRXSEL BIT(24) |
7981c001 MW |
58 | #define PADCFG0_RXINV BIT(23) |
59 | #define PADCFG0_GPIROUTIOXAPIC BIT(20) | |
60 | #define PADCFG0_GPIROUTSCI BIT(19) | |
61 | #define PADCFG0_GPIROUTSMI BIT(18) | |
62 | #define PADCFG0_GPIROUTNMI BIT(17) | |
63 | #define PADCFG0_PMODE_SHIFT 10 | |
e58926e7 | 64 | #define PADCFG0_PMODE_MASK GENMASK(13, 10) |
4973ddc8 | 65 | #define PADCFG0_PMODE_GPIO 0 |
7981c001 MW |
66 | #define PADCFG0_GPIORXDIS BIT(9) |
67 | #define PADCFG0_GPIOTXDIS BIT(8) | |
68 | #define PADCFG0_GPIORXSTATE BIT(1) | |
69 | #define PADCFG0_GPIOTXSTATE BIT(0) | |
70 | ||
71 | #define PADCFG1 0x004 | |
72 | #define PADCFG1_TERM_UP BIT(13) | |
73 | #define PADCFG1_TERM_SHIFT 10 | |
e58926e7 | 74 | #define PADCFG1_TERM_MASK GENMASK(12, 10) |
dd26209b AS |
75 | #define PADCFG1_TERM_20K BIT(2) |
76 | #define PADCFG1_TERM_5K BIT(1) | |
77 | #define PADCFG1_TERM_1K BIT(0) | |
78 | #define PADCFG1_TERM_833 (BIT(1) | BIT(0)) | |
7981c001 | 79 | |
e57725ea MW |
80 | #define PADCFG2 0x008 |
81 | #define PADCFG2_DEBEN BIT(0) | |
82 | #define PADCFG2_DEBOUNCE_SHIFT 1 | |
83 | #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) | |
84 | ||
6a33a1d6 | 85 | #define DEBOUNCE_PERIOD_NSEC 31250 |
e57725ea | 86 | |
7981c001 MW |
87 | struct intel_pad_context { |
88 | u32 padcfg0; | |
89 | u32 padcfg1; | |
e57725ea | 90 | u32 padcfg2; |
7981c001 MW |
91 | }; |
92 | ||
93 | struct intel_community_context { | |
94 | u32 *intmask; | |
a0a5f766 | 95 | u32 *hostown; |
7981c001 MW |
96 | }; |
97 | ||
7981c001 | 98 | #define pin_to_padno(c, p) ((p) - (c)->pin_base) |
919eb475 | 99 | #define padgroup_offset(g, p) ((p) - (g)->base) |
7981c001 MW |
100 | |
101 | static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, | |
04035f7f | 102 | unsigned int pin) |
7981c001 MW |
103 | { |
104 | struct intel_community *community; | |
105 | int i; | |
106 | ||
107 | for (i = 0; i < pctrl->ncommunities; i++) { | |
108 | community = &pctrl->communities[i]; | |
109 | if (pin >= community->pin_base && | |
110 | pin < community->pin_base + community->npins) | |
111 | return community; | |
112 | } | |
113 | ||
114 | dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin); | |
115 | return NULL; | |
116 | } | |
117 | ||
919eb475 MW |
118 | static const struct intel_padgroup * |
119 | intel_community_get_padgroup(const struct intel_community *community, | |
04035f7f | 120 | unsigned int pin) |
919eb475 MW |
121 | { |
122 | int i; | |
123 | ||
124 | for (i = 0; i < community->ngpps; i++) { | |
125 | const struct intel_padgroup *padgrp = &community->gpps[i]; | |
126 | ||
127 | if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) | |
128 | return padgrp; | |
129 | } | |
130 | ||
131 | return NULL; | |
132 | } | |
133 | ||
04035f7f AS |
134 | static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, |
135 | unsigned int pin, unsigned int reg) | |
7981c001 MW |
136 | { |
137 | const struct intel_community *community; | |
04035f7f | 138 | unsigned int padno; |
e57725ea | 139 | size_t nregs; |
7981c001 MW |
140 | |
141 | community = intel_get_community(pctrl, pin); | |
142 | if (!community) | |
143 | return NULL; | |
144 | ||
145 | padno = pin_to_padno(community, pin); | |
e57725ea MW |
146 | nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; |
147 | ||
7eb7ecdd | 148 | if (reg >= nregs * 4) |
e57725ea MW |
149 | return NULL; |
150 | ||
151 | return community->pad_regs + reg + padno * nregs * 4; | |
7981c001 MW |
152 | } |
153 | ||
04035f7f | 154 | static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin) |
7981c001 MW |
155 | { |
156 | const struct intel_community *community; | |
919eb475 | 157 | const struct intel_padgroup *padgrp; |
04035f7f | 158 | unsigned int gpp, offset, gpp_offset; |
7981c001 MW |
159 | void __iomem *padown; |
160 | ||
161 | community = intel_get_community(pctrl, pin); | |
162 | if (!community) | |
163 | return false; | |
164 | if (!community->padown_offset) | |
165 | return true; | |
166 | ||
919eb475 MW |
167 | padgrp = intel_community_get_padgroup(community, pin); |
168 | if (!padgrp) | |
169 | return false; | |
170 | ||
171 | gpp_offset = padgroup_offset(padgrp, pin); | |
172 | gpp = PADOWN_GPP(gpp_offset); | |
173 | offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; | |
7981c001 MW |
174 | padown = community->regs + offset; |
175 | ||
919eb475 | 176 | return !(readl(padown) & PADOWN_MASK(gpp_offset)); |
7981c001 MW |
177 | } |
178 | ||
04035f7f | 179 | static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) |
7981c001 MW |
180 | { |
181 | const struct intel_community *community; | |
919eb475 | 182 | const struct intel_padgroup *padgrp; |
04035f7f | 183 | unsigned int offset, gpp_offset; |
7981c001 MW |
184 | void __iomem *hostown; |
185 | ||
186 | community = intel_get_community(pctrl, pin); | |
187 | if (!community) | |
188 | return true; | |
189 | if (!community->hostown_offset) | |
190 | return false; | |
191 | ||
919eb475 MW |
192 | padgrp = intel_community_get_padgroup(community, pin); |
193 | if (!padgrp) | |
194 | return true; | |
195 | ||
196 | gpp_offset = padgroup_offset(padgrp, pin); | |
197 | offset = community->hostown_offset + padgrp->reg_num * 4; | |
7981c001 MW |
198 | hostown = community->regs + offset; |
199 | ||
919eb475 | 200 | return !(readl(hostown) & BIT(gpp_offset)); |
7981c001 MW |
201 | } |
202 | ||
1bd23153 AS |
203 | /** |
204 | * enum - Locking variants of the pad configuration | |
205 | * | |
206 | * @PAD_UNLOCKED: pad is fully controlled by the configuration registers | |
207 | * @PAD_LOCKED: pad configuration registers, except TX state, are locked | |
208 | * @PAD_LOCKED_TX: pad configuration TX state is locked | |
209 | * @PAD_LOCKED_FULL: pad configuration registers are locked completely | |
210 | * | |
211 | * Locking is considered as read-only mode for corresponding registers and | |
212 | * their respective fields. That said, TX state bit is locked separately from | |
213 | * the main locking scheme. | |
214 | */ | |
215 | enum { | |
216 | PAD_UNLOCKED = 0, | |
217 | PAD_LOCKED = 1, | |
218 | PAD_LOCKED_TX = 2, | |
219 | PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, | |
220 | }; | |
221 | ||
222 | static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) | |
7981c001 MW |
223 | { |
224 | struct intel_community *community; | |
919eb475 | 225 | const struct intel_padgroup *padgrp; |
04035f7f | 226 | unsigned int offset, gpp_offset; |
7981c001 | 227 | u32 value; |
1bd23153 | 228 | int ret = PAD_UNLOCKED; |
7981c001 MW |
229 | |
230 | community = intel_get_community(pctrl, pin); | |
231 | if (!community) | |
1bd23153 | 232 | return PAD_LOCKED_FULL; |
7981c001 | 233 | if (!community->padcfglock_offset) |
1bd23153 | 234 | return PAD_UNLOCKED; |
7981c001 | 235 | |
919eb475 MW |
236 | padgrp = intel_community_get_padgroup(community, pin); |
237 | if (!padgrp) | |
1bd23153 | 238 | return PAD_LOCKED_FULL; |
919eb475 MW |
239 | |
240 | gpp_offset = padgroup_offset(padgrp, pin); | |
7981c001 MW |
241 | |
242 | /* | |
243 | * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, | |
244 | * the pad is considered unlocked. Any other case means that it is | |
1bd23153 | 245 | * either fully or partially locked. |
7981c001 | 246 | */ |
1bd23153 | 247 | offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; |
7981c001 | 248 | value = readl(community->regs + offset); |
919eb475 | 249 | if (value & BIT(gpp_offset)) |
1bd23153 | 250 | ret |= PAD_LOCKED; |
7981c001 | 251 | |
919eb475 | 252 | offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; |
7981c001 | 253 | value = readl(community->regs + offset); |
919eb475 | 254 | if (value & BIT(gpp_offset)) |
1bd23153 | 255 | ret |= PAD_LOCKED_TX; |
7981c001 | 256 | |
1bd23153 AS |
257 | return ret; |
258 | } | |
259 | ||
260 | static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin) | |
261 | { | |
262 | return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; | |
7981c001 MW |
263 | } |
264 | ||
04035f7f | 265 | static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) |
7981c001 | 266 | { |
1bd23153 | 267 | return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); |
7981c001 MW |
268 | } |
269 | ||
270 | static int intel_get_groups_count(struct pinctrl_dev *pctldev) | |
271 | { | |
272 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
273 | ||
274 | return pctrl->soc->ngroups; | |
275 | } | |
276 | ||
277 | static const char *intel_get_group_name(struct pinctrl_dev *pctldev, | |
04035f7f | 278 | unsigned int group) |
7981c001 MW |
279 | { |
280 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
281 | ||
282 | return pctrl->soc->groups[group].name; | |
283 | } | |
284 | ||
04035f7f AS |
285 | static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, |
286 | const unsigned int **pins, unsigned int *npins) | |
7981c001 MW |
287 | { |
288 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
289 | ||
290 | *pins = pctrl->soc->groups[group].pins; | |
291 | *npins = pctrl->soc->groups[group].npins; | |
292 | return 0; | |
293 | } | |
294 | ||
295 | static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
04035f7f | 296 | unsigned int pin) |
7981c001 MW |
297 | { |
298 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
e57725ea | 299 | void __iomem *padcfg; |
7981c001 | 300 | u32 cfg0, cfg1, mode; |
1bd23153 AS |
301 | int locked; |
302 | bool acpi; | |
7981c001 MW |
303 | |
304 | if (!intel_pad_owned_by_host(pctrl, pin)) { | |
305 | seq_puts(s, "not available"); | |
306 | return; | |
307 | } | |
308 | ||
309 | cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); | |
310 | cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1)); | |
311 | ||
312 | mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; | |
4973ddc8 | 313 | if (mode == PADCFG0_PMODE_GPIO) |
7981c001 MW |
314 | seq_puts(s, "GPIO "); |
315 | else | |
316 | seq_printf(s, "mode %d ", mode); | |
317 | ||
318 | seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); | |
319 | ||
e57725ea MW |
320 | /* Dump the additional PADCFG registers if available */ |
321 | padcfg = intel_get_padcfg(pctrl, pin, PADCFG2); | |
322 | if (padcfg) | |
323 | seq_printf(s, " 0x%08x", readl(padcfg)); | |
324 | ||
7981c001 | 325 | locked = intel_pad_locked(pctrl, pin); |
4341e8a5 | 326 | acpi = intel_pad_acpi_mode(pctrl, pin); |
7981c001 MW |
327 | |
328 | if (locked || acpi) { | |
329 | seq_puts(s, " ["); | |
1bd23153 | 330 | if (locked) |
7981c001 | 331 | seq_puts(s, "LOCKED"); |
1bd23153 AS |
332 | if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) |
333 | seq_puts(s, " tx"); | |
334 | else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) | |
335 | seq_puts(s, " full"); | |
336 | ||
337 | if (locked && acpi) | |
338 | seq_puts(s, ", "); | |
339 | ||
7981c001 MW |
340 | if (acpi) |
341 | seq_puts(s, "ACPI"); | |
342 | seq_puts(s, "]"); | |
343 | } | |
344 | } | |
345 | ||
346 | static const struct pinctrl_ops intel_pinctrl_ops = { | |
347 | .get_groups_count = intel_get_groups_count, | |
348 | .get_group_name = intel_get_group_name, | |
349 | .get_group_pins = intel_get_group_pins, | |
350 | .pin_dbg_show = intel_pin_dbg_show, | |
351 | }; | |
352 | ||
353 | static int intel_get_functions_count(struct pinctrl_dev *pctldev) | |
354 | { | |
355 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
356 | ||
357 | return pctrl->soc->nfunctions; | |
358 | } | |
359 | ||
360 | static const char *intel_get_function_name(struct pinctrl_dev *pctldev, | |
04035f7f | 361 | unsigned int function) |
7981c001 MW |
362 | { |
363 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
364 | ||
365 | return pctrl->soc->functions[function].name; | |
366 | } | |
367 | ||
368 | static int intel_get_function_groups(struct pinctrl_dev *pctldev, | |
04035f7f | 369 | unsigned int function, |
7981c001 | 370 | const char * const **groups, |
04035f7f | 371 | unsigned int * const ngroups) |
7981c001 MW |
372 | { |
373 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
374 | ||
375 | *groups = pctrl->soc->functions[function].groups; | |
376 | *ngroups = pctrl->soc->functions[function].ngroups; | |
377 | return 0; | |
378 | } | |
379 | ||
04035f7f AS |
380 | static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, |
381 | unsigned int function, unsigned int group) | |
7981c001 MW |
382 | { |
383 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
384 | const struct intel_pingroup *grp = &pctrl->soc->groups[group]; | |
385 | unsigned long flags; | |
386 | int i; | |
387 | ||
27d9098c | 388 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 MW |
389 | |
390 | /* | |
391 | * All pins in the groups needs to be accessible and writable | |
392 | * before we can enable the mux for this group. | |
393 | */ | |
394 | for (i = 0; i < grp->npins; i++) { | |
395 | if (!intel_pad_usable(pctrl, grp->pins[i])) { | |
27d9098c | 396 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
397 | return -EBUSY; |
398 | } | |
399 | } | |
400 | ||
401 | /* Now enable the mux setting for each pin in the group */ | |
402 | for (i = 0; i < grp->npins; i++) { | |
403 | void __iomem *padcfg0; | |
404 | u32 value; | |
405 | ||
406 | padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); | |
407 | value = readl(padcfg0); | |
408 | ||
409 | value &= ~PADCFG0_PMODE_MASK; | |
1f6b419b MW |
410 | |
411 | if (grp->modes) | |
412 | value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; | |
413 | else | |
414 | value |= grp->mode << PADCFG0_PMODE_SHIFT; | |
7981c001 MW |
415 | |
416 | writel(value, padcfg0); | |
417 | } | |
418 | ||
27d9098c | 419 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
420 | |
421 | return 0; | |
422 | } | |
423 | ||
17fab473 AS |
424 | static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input) |
425 | { | |
426 | u32 value; | |
427 | ||
428 | value = readl(padcfg0); | |
429 | if (input) { | |
430 | value &= ~PADCFG0_GPIORXDIS; | |
431 | value |= PADCFG0_GPIOTXDIS; | |
432 | } else { | |
433 | value &= ~PADCFG0_GPIOTXDIS; | |
434 | value |= PADCFG0_GPIORXDIS; | |
435 | } | |
436 | writel(value, padcfg0); | |
437 | } | |
438 | ||
4973ddc8 AS |
439 | static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) |
440 | { | |
441 | return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; | |
442 | } | |
443 | ||
f5a26acf MW |
444 | static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) |
445 | { | |
446 | u32 value; | |
447 | ||
af7e3eeb AS |
448 | value = readl(padcfg0); |
449 | ||
f5a26acf | 450 | /* Put the pad into GPIO mode */ |
af7e3eeb AS |
451 | value &= ~PADCFG0_PMODE_MASK; |
452 | value |= PADCFG0_PMODE_GPIO; | |
453 | ||
e12963c4 AS |
454 | /* Disable TX buffer and enable RX (this will be input) */ |
455 | value &= ~PADCFG0_GPIORXDIS; | |
e8873c0a | 456 | value |= PADCFG0_GPIOTXDIS; |
af7e3eeb | 457 | |
f5a26acf MW |
458 | /* Disable SCI/SMI/NMI generation */ |
459 | value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI); | |
460 | value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI); | |
af7e3eeb | 461 | |
f5a26acf MW |
462 | writel(value, padcfg0); |
463 | } | |
464 | ||
7981c001 MW |
465 | static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, |
466 | struct pinctrl_gpio_range *range, | |
04035f7f | 467 | unsigned int pin) |
7981c001 MW |
468 | { |
469 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
470 | void __iomem *padcfg0; | |
471 | unsigned long flags; | |
7981c001 | 472 | |
f62cdde5 AS |
473 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); |
474 | ||
27d9098c | 475 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 | 476 | |
1bd23153 | 477 | if (!intel_pad_owned_by_host(pctrl, pin)) { |
27d9098c | 478 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
479 | return -EBUSY; |
480 | } | |
481 | ||
1bd23153 AS |
482 | if (!intel_pad_is_unlocked(pctrl, pin)) { |
483 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); | |
484 | return 0; | |
485 | } | |
486 | ||
4973ddc8 AS |
487 | /* |
488 | * If pin is already configured in GPIO mode, we assume that | |
489 | * firmware provides correct settings. In such case we avoid | |
490 | * potential glitches on the pin. Otherwise, for the pin in | |
491 | * alternative mode, consumer has to supply respective flags. | |
492 | */ | |
493 | if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) { | |
494 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); | |
495 | return 0; | |
496 | } | |
497 | ||
f5a26acf | 498 | intel_gpio_set_gpio_mode(padcfg0); |
4973ddc8 | 499 | |
27d9098c | 500 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
501 | |
502 | return 0; | |
503 | } | |
504 | ||
505 | static int intel_gpio_set_direction(struct pinctrl_dev *pctldev, | |
506 | struct pinctrl_gpio_range *range, | |
04035f7f | 507 | unsigned int pin, bool input) |
7981c001 MW |
508 | { |
509 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
510 | void __iomem *padcfg0; | |
511 | unsigned long flags; | |
7981c001 | 512 | |
7981c001 | 513 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); |
7981c001 | 514 | |
f62cdde5 AS |
515 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
516 | __intel_gpio_set_direction(padcfg0, input); | |
27d9098c | 517 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
518 | |
519 | return 0; | |
520 | } | |
521 | ||
522 | static const struct pinmux_ops intel_pinmux_ops = { | |
523 | .get_functions_count = intel_get_functions_count, | |
524 | .get_function_name = intel_get_function_name, | |
525 | .get_function_groups = intel_get_function_groups, | |
526 | .set_mux = intel_pinmux_set_mux, | |
527 | .gpio_request_enable = intel_gpio_request_enable, | |
528 | .gpio_set_direction = intel_gpio_set_direction, | |
529 | }; | |
530 | ||
81ab5542 AS |
531 | static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin, |
532 | enum pin_config_param param, u32 *arg) | |
7981c001 | 533 | { |
04cc058f | 534 | const struct intel_community *community; |
81ab5542 | 535 | void __iomem *padcfg1; |
e64fbfa5 | 536 | unsigned long flags; |
7981c001 | 537 | u32 value, term; |
7981c001 | 538 | |
04cc058f | 539 | community = intel_get_community(pctrl, pin); |
81ab5542 | 540 | padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); |
e64fbfa5 AS |
541 | |
542 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
81ab5542 | 543 | value = readl(padcfg1); |
e64fbfa5 | 544 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
81ab5542 | 545 | |
7981c001 MW |
546 | term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT; |
547 | ||
548 | switch (param) { | |
549 | case PIN_CONFIG_BIAS_DISABLE: | |
550 | if (term) | |
551 | return -EINVAL; | |
552 | break; | |
553 | ||
554 | case PIN_CONFIG_BIAS_PULL_UP: | |
555 | if (!term || !(value & PADCFG1_TERM_UP)) | |
556 | return -EINVAL; | |
557 | ||
558 | switch (term) { | |
dd26209b AS |
559 | case PADCFG1_TERM_833: |
560 | *arg = 833; | |
561 | break; | |
7981c001 | 562 | case PADCFG1_TERM_1K: |
81ab5542 | 563 | *arg = 1000; |
7981c001 | 564 | break; |
7981c001 | 565 | case PADCFG1_TERM_5K: |
81ab5542 | 566 | *arg = 5000; |
7981c001 MW |
567 | break; |
568 | case PADCFG1_TERM_20K: | |
81ab5542 | 569 | *arg = 20000; |
7981c001 MW |
570 | break; |
571 | } | |
572 | ||
573 | break; | |
574 | ||
575 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
576 | if (!term || value & PADCFG1_TERM_UP) | |
577 | return -EINVAL; | |
578 | ||
579 | switch (term) { | |
dd26209b AS |
580 | case PADCFG1_TERM_833: |
581 | if (!(community->features & PINCTRL_FEATURE_1K_PD)) | |
582 | return -EINVAL; | |
583 | *arg = 833; | |
584 | break; | |
04cc058f MW |
585 | case PADCFG1_TERM_1K: |
586 | if (!(community->features & PINCTRL_FEATURE_1K_PD)) | |
587 | return -EINVAL; | |
81ab5542 | 588 | *arg = 1000; |
04cc058f | 589 | break; |
7981c001 | 590 | case PADCFG1_TERM_5K: |
81ab5542 | 591 | *arg = 5000; |
7981c001 MW |
592 | break; |
593 | case PADCFG1_TERM_20K: | |
81ab5542 | 594 | *arg = 20000; |
7981c001 MW |
595 | break; |
596 | } | |
597 | ||
598 | break; | |
599 | ||
81ab5542 AS |
600 | default: |
601 | return -EINVAL; | |
602 | } | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
607 | static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin, | |
608 | enum pin_config_param param, u32 *arg) | |
609 | { | |
610 | void __iomem *padcfg2; | |
e64fbfa5 | 611 | unsigned long flags; |
81ab5542 AS |
612 | unsigned long v; |
613 | u32 value2; | |
e57725ea | 614 | |
81ab5542 AS |
615 | padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); |
616 | if (!padcfg2) | |
617 | return -ENOTSUPP; | |
e57725ea | 618 | |
e64fbfa5 | 619 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
81ab5542 | 620 | value2 = readl(padcfg2); |
e64fbfa5 | 621 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
81ab5542 AS |
622 | if (!(value2 & PADCFG2_DEBEN)) |
623 | return -EINVAL; | |
e57725ea | 624 | |
81ab5542 AS |
625 | v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; |
626 | *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; | |
e57725ea | 627 | |
81ab5542 AS |
628 | return 0; |
629 | } | |
630 | ||
631 | static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
632 | unsigned long *config) | |
633 | { | |
634 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
635 | enum pin_config_param param = pinconf_to_config_param(*config); | |
636 | u32 arg = 0; | |
637 | int ret; | |
638 | ||
639 | if (!intel_pad_owned_by_host(pctrl, pin)) | |
640 | return -ENOTSUPP; | |
641 | ||
642 | switch (param) { | |
643 | case PIN_CONFIG_BIAS_DISABLE: | |
644 | case PIN_CONFIG_BIAS_PULL_UP: | |
645 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
646 | ret = intel_config_get_pull(pctrl, pin, param, &arg); | |
647 | if (ret) | |
648 | return ret; | |
649 | break; | |
650 | ||
651 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
652 | ret = intel_config_get_debounce(pctrl, pin, param, &arg); | |
653 | if (ret) | |
654 | return ret; | |
e57725ea | 655 | break; |
e57725ea | 656 | |
7981c001 MW |
657 | default: |
658 | return -ENOTSUPP; | |
659 | } | |
660 | ||
661 | *config = pinconf_to_config_packed(param, arg); | |
662 | return 0; | |
663 | } | |
664 | ||
04035f7f | 665 | static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, |
7981c001 MW |
666 | unsigned long config) |
667 | { | |
04035f7f AS |
668 | unsigned int param = pinconf_to_config_param(config); |
669 | unsigned int arg = pinconf_to_config_argument(config); | |
04cc058f | 670 | const struct intel_community *community; |
7981c001 MW |
671 | void __iomem *padcfg1; |
672 | unsigned long flags; | |
673 | int ret = 0; | |
674 | u32 value; | |
675 | ||
04cc058f | 676 | community = intel_get_community(pctrl, pin); |
7981c001 | 677 | padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1); |
f62cdde5 AS |
678 | |
679 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
680 | ||
7981c001 MW |
681 | value = readl(padcfg1); |
682 | ||
683 | switch (param) { | |
684 | case PIN_CONFIG_BIAS_DISABLE: | |
685 | value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP); | |
686 | break; | |
687 | ||
688 | case PIN_CONFIG_BIAS_PULL_UP: | |
689 | value &= ~PADCFG1_TERM_MASK; | |
690 | ||
691 | value |= PADCFG1_TERM_UP; | |
692 | ||
f3c75e7a AS |
693 | /* Set default strength value in case none is given */ |
694 | if (arg == 1) | |
695 | arg = 5000; | |
696 | ||
7981c001 MW |
697 | switch (arg) { |
698 | case 20000: | |
699 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; | |
700 | break; | |
701 | case 5000: | |
702 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; | |
703 | break; | |
7981c001 MW |
704 | case 1000: |
705 | value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; | |
706 | break; | |
dd26209b AS |
707 | case 833: |
708 | value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; | |
709 | break; | |
7981c001 MW |
710 | default: |
711 | ret = -EINVAL; | |
712 | } | |
713 | ||
714 | break; | |
715 | ||
716 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
717 | value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK); | |
718 | ||
f3c75e7a AS |
719 | /* Set default strength value in case none is given */ |
720 | if (arg == 1) | |
721 | arg = 5000; | |
722 | ||
7981c001 MW |
723 | switch (arg) { |
724 | case 20000: | |
725 | value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT; | |
726 | break; | |
727 | case 5000: | |
728 | value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT; | |
729 | break; | |
04cc058f | 730 | case 1000: |
aa1dd80f DC |
731 | if (!(community->features & PINCTRL_FEATURE_1K_PD)) { |
732 | ret = -EINVAL; | |
733 | break; | |
734 | } | |
04cc058f MW |
735 | value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT; |
736 | break; | |
dd26209b AS |
737 | case 833: |
738 | if (!(community->features & PINCTRL_FEATURE_1K_PD)) { | |
739 | ret = -EINVAL; | |
740 | break; | |
741 | } | |
742 | value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT; | |
743 | break; | |
7981c001 MW |
744 | default: |
745 | ret = -EINVAL; | |
746 | } | |
747 | ||
748 | break; | |
749 | } | |
750 | ||
751 | if (!ret) | |
752 | writel(value, padcfg1); | |
753 | ||
27d9098c | 754 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
755 | |
756 | return ret; | |
757 | } | |
758 | ||
04035f7f AS |
759 | static int intel_config_set_debounce(struct intel_pinctrl *pctrl, |
760 | unsigned int pin, unsigned int debounce) | |
e57725ea MW |
761 | { |
762 | void __iomem *padcfg0, *padcfg2; | |
763 | unsigned long flags; | |
764 | u32 value0, value2; | |
e57725ea MW |
765 | |
766 | padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2); | |
767 | if (!padcfg2) | |
768 | return -ENOTSUPP; | |
769 | ||
770 | padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); | |
771 | ||
772 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
773 | ||
774 | value0 = readl(padcfg0); | |
775 | value2 = readl(padcfg2); | |
776 | ||
777 | /* Disable glitch filter and debouncer */ | |
778 | value0 &= ~PADCFG0_PREGFRXSEL; | |
779 | value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK); | |
780 | ||
781 | if (debounce) { | |
782 | unsigned long v; | |
783 | ||
6a33a1d6 | 784 | v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); |
e57725ea | 785 | if (v < 3 || v > 15) { |
8fff0427 AS |
786 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
787 | return -EINVAL; | |
e57725ea | 788 | } |
bb2f43d4 AS |
789 | |
790 | /* Enable glitch filter and debouncer */ | |
791 | value0 |= PADCFG0_PREGFRXSEL; | |
792 | value2 |= v << PADCFG2_DEBOUNCE_SHIFT; | |
793 | value2 |= PADCFG2_DEBEN; | |
e57725ea MW |
794 | } |
795 | ||
796 | writel(value0, padcfg0); | |
797 | writel(value2, padcfg2); | |
798 | ||
e57725ea MW |
799 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
800 | ||
8fff0427 | 801 | return 0; |
e57725ea MW |
802 | } |
803 | ||
04035f7f AS |
804 | static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin, |
805 | unsigned long *configs, unsigned int nconfigs) | |
7981c001 MW |
806 | { |
807 | struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
808 | int i, ret; | |
809 | ||
810 | if (!intel_pad_usable(pctrl, pin)) | |
811 | return -ENOTSUPP; | |
812 | ||
813 | for (i = 0; i < nconfigs; i++) { | |
814 | switch (pinconf_to_config_param(configs[i])) { | |
815 | case PIN_CONFIG_BIAS_DISABLE: | |
816 | case PIN_CONFIG_BIAS_PULL_UP: | |
817 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
818 | ret = intel_config_set_pull(pctrl, pin, configs[i]); | |
819 | if (ret) | |
820 | return ret; | |
821 | break; | |
822 | ||
e57725ea MW |
823 | case PIN_CONFIG_INPUT_DEBOUNCE: |
824 | ret = intel_config_set_debounce(pctrl, pin, | |
825 | pinconf_to_config_argument(configs[i])); | |
826 | if (ret) | |
827 | return ret; | |
828 | break; | |
829 | ||
7981c001 MW |
830 | default: |
831 | return -ENOTSUPP; | |
832 | } | |
833 | } | |
834 | ||
835 | return 0; | |
836 | } | |
837 | ||
838 | static const struct pinconf_ops intel_pinconf_ops = { | |
839 | .is_generic = true, | |
840 | .pin_config_get = intel_config_get, | |
841 | .pin_config_set = intel_config_set, | |
842 | }; | |
843 | ||
844 | static const struct pinctrl_desc intel_pinctrl_desc = { | |
845 | .pctlops = &intel_pinctrl_ops, | |
846 | .pmxops = &intel_pinmux_ops, | |
847 | .confops = &intel_pinconf_ops, | |
848 | .owner = THIS_MODULE, | |
849 | }; | |
850 | ||
96147db1 MW |
851 | /** |
852 | * intel_gpio_to_pin() - Translate from GPIO offset to pin number | |
853 | * @pctrl: Pinctrl structure | |
854 | * @offset: GPIO offset from gpiolib | |
946ffefc | 855 | * @community: Community is filled here if not %NULL |
96147db1 MW |
856 | * @padgrp: Pad group is filled here if not %NULL |
857 | * | |
858 | * When coming through gpiolib irqchip, the GPIO offset is not | |
859 | * automatically translated to pinctrl pin number. This function can be | |
860 | * used to find out the corresponding pinctrl pin. | |
861 | */ | |
04035f7f | 862 | static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, |
96147db1 MW |
863 | const struct intel_community **community, |
864 | const struct intel_padgroup **padgrp) | |
865 | { | |
866 | int i; | |
867 | ||
868 | for (i = 0; i < pctrl->ncommunities; i++) { | |
869 | const struct intel_community *comm = &pctrl->communities[i]; | |
870 | int j; | |
871 | ||
872 | for (j = 0; j < comm->ngpps; j++) { | |
873 | const struct intel_padgroup *pgrp = &comm->gpps[j]; | |
874 | ||
e5a4ab6a | 875 | if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) |
96147db1 MW |
876 | continue; |
877 | ||
878 | if (offset >= pgrp->gpio_base && | |
879 | offset < pgrp->gpio_base + pgrp->size) { | |
880 | int pin; | |
881 | ||
882 | pin = pgrp->base + offset - pgrp->gpio_base; | |
883 | if (community) | |
884 | *community = comm; | |
885 | if (padgrp) | |
886 | *padgrp = pgrp; | |
887 | ||
888 | return pin; | |
889 | } | |
890 | } | |
891 | } | |
892 | ||
893 | return -EINVAL; | |
894 | } | |
895 | ||
6cb0880f CC |
896 | /** |
897 | * intel_pin_to_gpio() - Translate from pin number to GPIO offset | |
898 | * @pctrl: Pinctrl structure | |
899 | * @pin: pin number | |
900 | * | |
901 | * Translate the pin number of pinctrl to GPIO offset | |
902 | */ | |
55dac437 | 903 | static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin) |
6cb0880f CC |
904 | { |
905 | const struct intel_community *community; | |
906 | const struct intel_padgroup *padgrp; | |
907 | ||
908 | community = intel_get_community(pctrl, pin); | |
909 | if (!community) | |
910 | return -EINVAL; | |
911 | ||
912 | padgrp = intel_community_get_padgroup(community, pin); | |
913 | if (!padgrp) | |
914 | return -EINVAL; | |
915 | ||
916 | return pin - padgrp->base + padgrp->gpio_base; | |
917 | } | |
918 | ||
04035f7f | 919 | static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) |
7981c001 | 920 | { |
acfd4c63 | 921 | struct intel_pinctrl *pctrl = gpiochip_get_data(chip); |
7981c001 | 922 | void __iomem *reg; |
d68b42e3 | 923 | u32 padcfg0; |
96147db1 | 924 | int pin; |
7981c001 | 925 | |
96147db1 MW |
926 | pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); |
927 | if (pin < 0) | |
928 | return -EINVAL; | |
7981c001 | 929 | |
96147db1 | 930 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); |
7981c001 MW |
931 | if (!reg) |
932 | return -EINVAL; | |
933 | ||
d68b42e3 AS |
934 | padcfg0 = readl(reg); |
935 | if (!(padcfg0 & PADCFG0_GPIOTXDIS)) | |
936 | return !!(padcfg0 & PADCFG0_GPIOTXSTATE); | |
937 | ||
938 | return !!(padcfg0 & PADCFG0_GPIORXSTATE); | |
7981c001 MW |
939 | } |
940 | ||
04035f7f AS |
941 | static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset, |
942 | int value) | |
7981c001 | 943 | { |
acfd4c63 | 944 | struct intel_pinctrl *pctrl = gpiochip_get_data(chip); |
85461377 | 945 | unsigned long flags; |
7981c001 | 946 | void __iomem *reg; |
85461377 | 947 | u32 padcfg0; |
96147db1 | 948 | int pin; |
7981c001 | 949 | |
96147db1 MW |
950 | pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); |
951 | if (pin < 0) | |
952 | return; | |
953 | ||
954 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); | |
85461377 AS |
955 | if (!reg) |
956 | return; | |
957 | ||
958 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
959 | padcfg0 = readl(reg); | |
960 | if (value) | |
961 | padcfg0 |= PADCFG0_GPIOTXSTATE; | |
962 | else | |
963 | padcfg0 &= ~PADCFG0_GPIOTXSTATE; | |
964 | writel(padcfg0, reg); | |
965 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); | |
7981c001 MW |
966 | } |
967 | ||
67e6d3e8 JA |
968 | static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
969 | { | |
970 | struct intel_pinctrl *pctrl = gpiochip_get_data(chip); | |
e64fbfa5 | 971 | unsigned long flags; |
67e6d3e8 JA |
972 | void __iomem *reg; |
973 | u32 padcfg0; | |
96147db1 MW |
974 | int pin; |
975 | ||
976 | pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL); | |
977 | if (pin < 0) | |
978 | return -EINVAL; | |
67e6d3e8 | 979 | |
96147db1 | 980 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); |
67e6d3e8 JA |
981 | if (!reg) |
982 | return -EINVAL; | |
983 | ||
e64fbfa5 | 984 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
67e6d3e8 | 985 | padcfg0 = readl(reg); |
e64fbfa5 | 986 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
67e6d3e8 JA |
987 | if (padcfg0 & PADCFG0_PMODE_MASK) |
988 | return -EINVAL; | |
989 | ||
6a304752 MV |
990 | if (padcfg0 & PADCFG0_GPIOTXDIS) |
991 | return GPIO_LINE_DIRECTION_IN; | |
992 | ||
993 | return GPIO_LINE_DIRECTION_OUT; | |
67e6d3e8 JA |
994 | } |
995 | ||
04035f7f | 996 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) |
7981c001 MW |
997 | { |
998 | return pinctrl_gpio_direction_input(chip->base + offset); | |
999 | } | |
1000 | ||
04035f7f | 1001 | static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, |
7981c001 MW |
1002 | int value) |
1003 | { | |
1004 | intel_gpio_set(chip, offset, value); | |
1005 | return pinctrl_gpio_direction_output(chip->base + offset); | |
1006 | } | |
1007 | ||
1008 | static const struct gpio_chip intel_gpio_chip = { | |
1009 | .owner = THIS_MODULE, | |
98c85d58 JG |
1010 | .request = gpiochip_generic_request, |
1011 | .free = gpiochip_generic_free, | |
67e6d3e8 | 1012 | .get_direction = intel_gpio_get_direction, |
7981c001 MW |
1013 | .direction_input = intel_gpio_direction_input, |
1014 | .direction_output = intel_gpio_direction_output, | |
1015 | .get = intel_gpio_get, | |
1016 | .set = intel_gpio_set, | |
e57725ea | 1017 | .set_config = gpiochip_generic_config, |
7981c001 MW |
1018 | }; |
1019 | ||
1020 | static void intel_gpio_irq_ack(struct irq_data *d) | |
1021 | { | |
1022 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 1023 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 | 1024 | const struct intel_community *community; |
a60eac32 MW |
1025 | const struct intel_padgroup *padgrp; |
1026 | int pin; | |
7981c001 | 1027 | |
a60eac32 MW |
1028 | pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); |
1029 | if (pin >= 0) { | |
04035f7f | 1030 | unsigned int gpp, gpp_offset, is_offset; |
919eb475 | 1031 | |
919eb475 MW |
1032 | gpp = padgrp->reg_num; |
1033 | gpp_offset = padgroup_offset(padgrp, pin); | |
cf769bd8 | 1034 | is_offset = community->is_offset + gpp * 4; |
7981c001 | 1035 | |
919eb475 | 1036 | raw_spin_lock(&pctrl->lock); |
cf769bd8 | 1037 | writel(BIT(gpp_offset), community->regs + is_offset); |
919eb475 | 1038 | raw_spin_unlock(&pctrl->lock); |
7981c001 | 1039 | } |
7981c001 MW |
1040 | } |
1041 | ||
1042 | static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) | |
1043 | { | |
1044 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 1045 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
7981c001 | 1046 | const struct intel_community *community; |
a60eac32 MW |
1047 | const struct intel_padgroup *padgrp; |
1048 | int pin; | |
7981c001 | 1049 | |
a60eac32 MW |
1050 | pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp); |
1051 | if (pin >= 0) { | |
04035f7f | 1052 | unsigned int gpp, gpp_offset; |
919eb475 | 1053 | unsigned long flags; |
670784fb | 1054 | void __iomem *reg, *is; |
7981c001 MW |
1055 | u32 value; |
1056 | ||
919eb475 MW |
1057 | gpp = padgrp->reg_num; |
1058 | gpp_offset = padgroup_offset(padgrp, pin); | |
1059 | ||
7981c001 | 1060 | reg = community->regs + community->ie_offset + gpp * 4; |
670784fb | 1061 | is = community->regs + community->is_offset + gpp * 4; |
919eb475 MW |
1062 | |
1063 | raw_spin_lock_irqsave(&pctrl->lock, flags); | |
670784fb KHF |
1064 | |
1065 | /* Clear interrupt status first to avoid unexpected interrupt */ | |
1066 | writel(BIT(gpp_offset), is); | |
1067 | ||
7981c001 MW |
1068 | value = readl(reg); |
1069 | if (mask) | |
1070 | value &= ~BIT(gpp_offset); | |
1071 | else | |
1072 | value |= BIT(gpp_offset); | |
1073 | writel(value, reg); | |
919eb475 | 1074 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 | 1075 | } |
7981c001 MW |
1076 | } |
1077 | ||
1078 | static void intel_gpio_irq_mask(struct irq_data *d) | |
1079 | { | |
1080 | intel_gpio_irq_mask_unmask(d, true); | |
1081 | } | |
1082 | ||
1083 | static void intel_gpio_irq_unmask(struct irq_data *d) | |
1084 | { | |
1085 | intel_gpio_irq_mask_unmask(d, false); | |
1086 | } | |
1087 | ||
04035f7f | 1088 | static int intel_gpio_irq_type(struct irq_data *d, unsigned int type) |
7981c001 MW |
1089 | { |
1090 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 1091 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
04035f7f | 1092 | unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); |
7981c001 MW |
1093 | unsigned long flags; |
1094 | void __iomem *reg; | |
1095 | u32 value; | |
1096 | ||
1097 | reg = intel_get_padcfg(pctrl, pin, PADCFG0); | |
1098 | if (!reg) | |
1099 | return -EINVAL; | |
1100 | ||
4341e8a5 MW |
1101 | /* |
1102 | * If the pin is in ACPI mode it is still usable as a GPIO but it | |
1103 | * cannot be used as IRQ because GPI_IS status bit will not be | |
1104 | * updated by the host controller hardware. | |
1105 | */ | |
1106 | if (intel_pad_acpi_mode(pctrl, pin)) { | |
1107 | dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin); | |
1108 | return -EPERM; | |
1109 | } | |
1110 | ||
27d9098c | 1111 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
7981c001 | 1112 | |
f5a26acf MW |
1113 | intel_gpio_set_gpio_mode(reg); |
1114 | ||
7981c001 MW |
1115 | value = readl(reg); |
1116 | ||
1117 | value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); | |
1118 | ||
1119 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
1120 | value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT; | |
1121 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
1122 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; | |
1123 | value |= PADCFG0_RXINV; | |
1124 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
1125 | value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT; | |
bf380cfa QZ |
1126 | } else if (type & IRQ_TYPE_LEVEL_MASK) { |
1127 | if (type & IRQ_TYPE_LEVEL_LOW) | |
1128 | value |= PADCFG0_RXINV; | |
7981c001 MW |
1129 | } else { |
1130 | value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT; | |
1131 | } | |
1132 | ||
1133 | writel(value, reg); | |
1134 | ||
1135 | if (type & IRQ_TYPE_EDGE_BOTH) | |
fc756bcd | 1136 | irq_set_handler_locked(d, handle_edge_irq); |
7981c001 | 1137 | else if (type & IRQ_TYPE_LEVEL_MASK) |
fc756bcd | 1138 | irq_set_handler_locked(d, handle_level_irq); |
7981c001 | 1139 | |
27d9098c | 1140 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
7981c001 MW |
1141 | |
1142 | return 0; | |
1143 | } | |
1144 | ||
1145 | static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) | |
1146 | { | |
1147 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
acfd4c63 | 1148 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); |
04035f7f | 1149 | unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); |
9a520fd9 | 1150 | |
7981c001 | 1151 | if (on) |
01dabe91 | 1152 | enable_irq_wake(pctrl->irq); |
7981c001 | 1153 | else |
01dabe91 | 1154 | disable_irq_wake(pctrl->irq); |
9a520fd9 | 1155 | |
7981c001 MW |
1156 | dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); |
1157 | return 0; | |
1158 | } | |
1159 | ||
86851bbc AS |
1160 | static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, |
1161 | const struct intel_community *community) | |
7981c001 | 1162 | { |
193b40c8 | 1163 | struct gpio_chip *gc = &pctrl->chip; |
86851bbc AS |
1164 | unsigned int gpp; |
1165 | int ret = 0; | |
7981c001 MW |
1166 | |
1167 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
919eb475 | 1168 | const struct intel_padgroup *padgrp = &community->gpps[gpp]; |
7981c001 | 1169 | unsigned long pending, enabled, gpp_offset; |
e64fbfa5 | 1170 | |
5b613df3 | 1171 | raw_spin_lock(&pctrl->lock); |
7981c001 | 1172 | |
cf769bd8 MW |
1173 | pending = readl(community->regs + community->is_offset + |
1174 | padgrp->reg_num * 4); | |
7981c001 | 1175 | enabled = readl(community->regs + community->ie_offset + |
919eb475 | 1176 | padgrp->reg_num * 4); |
7981c001 | 1177 | |
5b613df3 | 1178 | raw_spin_unlock(&pctrl->lock); |
e64fbfa5 | 1179 | |
7981c001 MW |
1180 | /* Only interrupts that are enabled */ |
1181 | pending &= enabled; | |
1182 | ||
919eb475 | 1183 | for_each_set_bit(gpp_offset, &pending, padgrp->size) { |
11b389cc | 1184 | unsigned int irq; |
7981c001 | 1185 | |
f0fbe7bc | 1186 | irq = irq_find_mapping(gc->irq.domain, |
a60eac32 | 1187 | padgrp->gpio_base + gpp_offset); |
7981c001 MW |
1188 | generic_handle_irq(irq); |
1189 | } | |
86851bbc AS |
1190 | |
1191 | ret += pending ? 1 : 0; | |
7981c001 | 1192 | } |
193b40c8 MW |
1193 | |
1194 | return ret; | |
7981c001 MW |
1195 | } |
1196 | ||
193b40c8 | 1197 | static irqreturn_t intel_gpio_irq(int irq, void *data) |
7981c001 | 1198 | { |
193b40c8 MW |
1199 | const struct intel_community *community; |
1200 | struct intel_pinctrl *pctrl = data; | |
86851bbc AS |
1201 | unsigned int i; |
1202 | int ret = 0; | |
7981c001 | 1203 | |
7981c001 | 1204 | /* Need to check all communities for pending interrupts */ |
193b40c8 MW |
1205 | for (i = 0; i < pctrl->ncommunities; i++) { |
1206 | community = &pctrl->communities[i]; | |
86851bbc | 1207 | ret += intel_gpio_community_irq_handler(pctrl, community); |
193b40c8 | 1208 | } |
7981c001 | 1209 | |
86851bbc | 1210 | return IRQ_RETVAL(ret); |
7981c001 MW |
1211 | } |
1212 | ||
e986f0e6 ŁB |
1213 | static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) |
1214 | { | |
1215 | int i; | |
1216 | ||
1217 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1218 | const struct intel_community *community; | |
1219 | void __iomem *base; | |
1220 | unsigned int gpp; | |
1221 | ||
1222 | community = &pctrl->communities[i]; | |
1223 | base = community->regs; | |
1224 | ||
1225 | for (gpp = 0; gpp < community->ngpps; gpp++) { | |
1226 | /* Mask and clear all interrupts */ | |
1227 | writel(0, base + community->ie_offset + gpp * 4); | |
1228 | writel(0xffff, base + community->is_offset + gpp * 4); | |
1229 | } | |
1230 | } | |
1231 | } | |
1232 | ||
1233 | static int intel_gpio_irq_init_hw(struct gpio_chip *gc) | |
1234 | { | |
1235 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); | |
1236 | ||
1237 | /* | |
1238 | * Make sure the interrupt lines are in a proper state before | |
1239 | * further configuration. | |
1240 | */ | |
1241 | intel_gpio_irq_init(pctrl); | |
1242 | ||
1243 | return 0; | |
1244 | } | |
1245 | ||
6d416b9b LW |
1246 | static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, |
1247 | const struct intel_community *community) | |
a60eac32 | 1248 | { |
33b6cb58 | 1249 | int ret = 0, i; |
a60eac32 MW |
1250 | |
1251 | for (i = 0; i < community->ngpps; i++) { | |
1252 | const struct intel_padgroup *gpp = &community->gpps[i]; | |
1253 | ||
e5a4ab6a | 1254 | if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) |
a60eac32 MW |
1255 | continue; |
1256 | ||
1257 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), | |
1258 | gpp->gpio_base, gpp->base, | |
1259 | gpp->size); | |
1260 | if (ret) | |
1261 | return ret; | |
1262 | } | |
1263 | ||
1264 | return ret; | |
1265 | } | |
1266 | ||
6d416b9b LW |
1267 | static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) |
1268 | { | |
1269 | struct intel_pinctrl *pctrl = gpiochip_get_data(gc); | |
1270 | int ret, i; | |
1271 | ||
1272 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1273 | struct intel_community *community = &pctrl->communities[i]; | |
1274 | ||
1275 | ret = intel_gpio_add_community_ranges(pctrl, community); | |
1276 | if (ret) { | |
1277 | dev_err(pctrl->dev, "failed to add GPIO pin range\n"); | |
1278 | return ret; | |
1279 | } | |
1280 | } | |
1281 | ||
1282 | return 0; | |
1283 | } | |
1284 | ||
11b389cc | 1285 | static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) |
a60eac32 MW |
1286 | { |
1287 | const struct intel_community *community; | |
04035f7f | 1288 | unsigned int ngpio = 0; |
a60eac32 MW |
1289 | int i, j; |
1290 | ||
1291 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1292 | community = &pctrl->communities[i]; | |
1293 | for (j = 0; j < community->ngpps; j++) { | |
1294 | const struct intel_padgroup *gpp = &community->gpps[j]; | |
1295 | ||
e5a4ab6a | 1296 | if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) |
a60eac32 MW |
1297 | continue; |
1298 | ||
1299 | if (gpp->gpio_base + gpp->size > ngpio) | |
1300 | ngpio = gpp->gpio_base + gpp->size; | |
1301 | } | |
1302 | } | |
1303 | ||
1304 | return ngpio; | |
1305 | } | |
1306 | ||
7981c001 MW |
1307 | static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) |
1308 | { | |
6d416b9b | 1309 | int ret; |
af0c5330 | 1310 | struct gpio_irq_chip *girq; |
7981c001 MW |
1311 | |
1312 | pctrl->chip = intel_gpio_chip; | |
1313 | ||
57ff2df1 | 1314 | /* Setup GPIO chip */ |
a60eac32 | 1315 | pctrl->chip.ngpio = intel_gpio_ngpio(pctrl); |
7981c001 | 1316 | pctrl->chip.label = dev_name(pctrl->dev); |
58383c78 | 1317 | pctrl->chip.parent = pctrl->dev; |
7981c001 | 1318 | pctrl->chip.base = -1; |
6d416b9b | 1319 | pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges; |
01dabe91 | 1320 | pctrl->irq = irq; |
7981c001 | 1321 | |
57ff2df1 AS |
1322 | /* Setup IRQ chip */ |
1323 | pctrl->irqchip.name = dev_name(pctrl->dev); | |
1324 | pctrl->irqchip.irq_ack = intel_gpio_irq_ack; | |
1325 | pctrl->irqchip.irq_mask = intel_gpio_irq_mask; | |
1326 | pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask; | |
1327 | pctrl->irqchip.irq_set_type = intel_gpio_irq_type; | |
1328 | pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake; | |
1329 | pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND; | |
1330 | ||
193b40c8 | 1331 | /* |
af0c5330 LW |
1332 | * On some platforms several GPIO controllers share the same interrupt |
1333 | * line. | |
193b40c8 | 1334 | */ |
1a7d1cb8 MW |
1335 | ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, |
1336 | IRQF_SHARED | IRQF_NO_THREAD, | |
193b40c8 MW |
1337 | dev_name(pctrl->dev), pctrl); |
1338 | if (ret) { | |
1339 | dev_err(pctrl->dev, "failed to request interrupt\n"); | |
f25c3aa9 | 1340 | return ret; |
7981c001 MW |
1341 | } |
1342 | ||
af0c5330 LW |
1343 | girq = &pctrl->chip.irq; |
1344 | girq->chip = &pctrl->irqchip; | |
1345 | /* This will let us handle the IRQ in the driver */ | |
1346 | girq->parent_handler = NULL; | |
1347 | girq->num_parents = 0; | |
1348 | girq->default_type = IRQ_TYPE_NONE; | |
1349 | girq->handler = handle_bad_irq; | |
e986f0e6 | 1350 | girq->init_hw = intel_gpio_irq_init_hw; |
af0c5330 LW |
1351 | |
1352 | ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); | |
7981c001 | 1353 | if (ret) { |
af0c5330 | 1354 | dev_err(pctrl->dev, "failed to register gpiochip\n"); |
f25c3aa9 | 1355 | return ret; |
7981c001 MW |
1356 | } |
1357 | ||
7981c001 MW |
1358 | return 0; |
1359 | } | |
1360 | ||
036e126c AS |
1361 | static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl, |
1362 | struct intel_community *community) | |
919eb475 MW |
1363 | { |
1364 | struct intel_padgroup *gpps; | |
04035f7f | 1365 | unsigned int padown_num = 0; |
036e126c | 1366 | size_t i, ngpps = community->ngpps; |
919eb475 MW |
1367 | |
1368 | gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); | |
1369 | if (!gpps) | |
1370 | return -ENOMEM; | |
1371 | ||
1372 | for (i = 0; i < ngpps; i++) { | |
036e126c | 1373 | gpps[i] = community->gpps[i]; |
919eb475 MW |
1374 | |
1375 | if (gpps[i].size > 32) | |
1376 | return -EINVAL; | |
1377 | ||
e5a4ab6a AS |
1378 | /* Special treatment for GPIO base */ |
1379 | switch (gpps[i].gpio_base) { | |
1380 | case INTEL_GPIO_BASE_MATCH: | |
1381 | gpps[i].gpio_base = gpps[i].base; | |
1382 | break; | |
9bd59157 AS |
1383 | case INTEL_GPIO_BASE_ZERO: |
1384 | gpps[i].gpio_base = 0; | |
1385 | break; | |
e5a4ab6a | 1386 | case INTEL_GPIO_BASE_NOMAP: |
77e14126 | 1387 | break; |
e5a4ab6a AS |
1388 | default: |
1389 | break; | |
1390 | } | |
a60eac32 | 1391 | |
036e126c AS |
1392 | gpps[i].padown_num = padown_num; |
1393 | padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); | |
1394 | } | |
1395 | ||
1396 | community->gpps = gpps; | |
1397 | ||
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl, | |
1402 | struct intel_community *community) | |
1403 | { | |
1404 | struct intel_padgroup *gpps; | |
1405 | unsigned int npins = community->npins; | |
1406 | unsigned int padown_num = 0; | |
1407 | size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size); | |
1408 | ||
1409 | if (community->gpp_size > 32) | |
1410 | return -EINVAL; | |
1411 | ||
1412 | gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); | |
1413 | if (!gpps) | |
1414 | return -ENOMEM; | |
1415 | ||
1416 | for (i = 0; i < ngpps; i++) { | |
1417 | unsigned int gpp_size = community->gpp_size; | |
1418 | ||
1419 | gpps[i].reg_num = i; | |
1420 | gpps[i].base = community->pin_base + i * gpp_size; | |
1421 | gpps[i].size = min(gpp_size, npins); | |
1422 | npins -= gpps[i].size; | |
1423 | ||
77e14126 | 1424 | gpps[i].gpio_base = gpps[i].base; |
919eb475 MW |
1425 | gpps[i].padown_num = padown_num; |
1426 | ||
1427 | /* | |
1428 | * In older hardware the number of padown registers per | |
1429 | * group is fixed regardless of the group size. | |
1430 | */ | |
1431 | if (community->gpp_num_padown_regs) | |
1432 | padown_num += community->gpp_num_padown_regs; | |
1433 | else | |
1434 | padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); | |
1435 | } | |
1436 | ||
1437 | community->ngpps = ngpps; | |
1438 | community->gpps = gpps; | |
1439 | ||
1440 | return 0; | |
1441 | } | |
1442 | ||
7981c001 MW |
1443 | static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) |
1444 | { | |
1445 | #ifdef CONFIG_PM_SLEEP | |
1446 | const struct intel_pinctrl_soc_data *soc = pctrl->soc; | |
1447 | struct intel_community_context *communities; | |
1448 | struct intel_pad_context *pads; | |
1449 | int i; | |
1450 | ||
1451 | pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL); | |
1452 | if (!pads) | |
1453 | return -ENOMEM; | |
1454 | ||
1455 | communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities, | |
1456 | sizeof(*communities), GFP_KERNEL); | |
1457 | if (!communities) | |
1458 | return -ENOMEM; | |
1459 | ||
1460 | ||
1461 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1462 | struct intel_community *community = &pctrl->communities[i]; | |
a0a5f766 | 1463 | u32 *intmask, *hostown; |
7981c001 MW |
1464 | |
1465 | intmask = devm_kcalloc(pctrl->dev, community->ngpps, | |
1466 | sizeof(*intmask), GFP_KERNEL); | |
1467 | if (!intmask) | |
1468 | return -ENOMEM; | |
1469 | ||
1470 | communities[i].intmask = intmask; | |
a0a5f766 CC |
1471 | |
1472 | hostown = devm_kcalloc(pctrl->dev, community->ngpps, | |
1473 | sizeof(*hostown), GFP_KERNEL); | |
1474 | if (!hostown) | |
1475 | return -ENOMEM; | |
1476 | ||
1477 | communities[i].hostown = hostown; | |
7981c001 MW |
1478 | } |
1479 | ||
1480 | pctrl->context.pads = pads; | |
1481 | pctrl->context.communities = communities; | |
1482 | #endif | |
1483 | ||
1484 | return 0; | |
1485 | } | |
1486 | ||
0dd519e3 AS |
1487 | static int intel_pinctrl_probe(struct platform_device *pdev, |
1488 | const struct intel_pinctrl_soc_data *soc_data) | |
7981c001 MW |
1489 | { |
1490 | struct intel_pinctrl *pctrl; | |
1491 | int i, ret, irq; | |
1492 | ||
7981c001 MW |
1493 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); |
1494 | if (!pctrl) | |
1495 | return -ENOMEM; | |
1496 | ||
1497 | pctrl->dev = &pdev->dev; | |
1498 | pctrl->soc = soc_data; | |
27d9098c | 1499 | raw_spin_lock_init(&pctrl->lock); |
7981c001 MW |
1500 | |
1501 | /* | |
1502 | * Make a copy of the communities which we can use to hold pointers | |
1503 | * to the registers. | |
1504 | */ | |
1505 | pctrl->ncommunities = pctrl->soc->ncommunities; | |
1506 | pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, | |
1507 | sizeof(*pctrl->communities), GFP_KERNEL); | |
1508 | if (!pctrl->communities) | |
1509 | return -ENOMEM; | |
1510 | ||
1511 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1512 | struct intel_community *community = &pctrl->communities[i]; | |
7981c001 | 1513 | void __iomem *regs; |
91d898e5 | 1514 | u32 offset; |
998c49e8 | 1515 | u32 value; |
7981c001 MW |
1516 | |
1517 | *community = pctrl->soc->communities[i]; | |
1518 | ||
9d5b6a95 | 1519 | regs = devm_platform_ioremap_resource(pdev, community->barno); |
7981c001 MW |
1520 | if (IS_ERR(regs)) |
1521 | return PTR_ERR(regs); | |
1522 | ||
39c1f1bd RPM |
1523 | /* |
1524 | * Determine community features based on the revision. | |
1525 | * A value of all ones means the device is not present. | |
1526 | */ | |
998c49e8 | 1527 | value = readl(regs + REVID); |
39c1f1bd RPM |
1528 | if (value == ~0u) |
1529 | return -ENODEV; | |
998c49e8 AS |
1530 | if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) { |
1531 | community->features |= PINCTRL_FEATURE_DEBOUNCE; | |
1532 | community->features |= PINCTRL_FEATURE_1K_PD; | |
e57725ea MW |
1533 | } |
1534 | ||
91d898e5 AS |
1535 | /* Determine community features based on the capabilities */ |
1536 | offset = CAPLIST; | |
1537 | do { | |
1538 | value = readl(regs + offset); | |
1539 | switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) { | |
1540 | case CAPLIST_ID_GPIO_HW_INFO: | |
1541 | community->features |= PINCTRL_FEATURE_GPIO_HW_INFO; | |
1542 | break; | |
1543 | case CAPLIST_ID_PWM: | |
1544 | community->features |= PINCTRL_FEATURE_PWM; | |
1545 | break; | |
1546 | case CAPLIST_ID_BLINK: | |
1547 | community->features |= PINCTRL_FEATURE_BLINK; | |
1548 | break; | |
1549 | case CAPLIST_ID_EXP: | |
1550 | community->features |= PINCTRL_FEATURE_EXP; | |
1551 | break; | |
1552 | default: | |
1553 | break; | |
1554 | } | |
1555 | offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT; | |
1556 | } while (offset); | |
1557 | ||
1558 | dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features); | |
1559 | ||
7981c001 | 1560 | /* Read offset of the pad configuration registers */ |
91d898e5 | 1561 | offset = readl(regs + PADBAR); |
7981c001 MW |
1562 | |
1563 | community->regs = regs; | |
91d898e5 | 1564 | community->pad_regs = regs + offset; |
919eb475 | 1565 | |
036e126c AS |
1566 | if (community->gpps) |
1567 | ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community); | |
1568 | else | |
1569 | ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); | |
919eb475 MW |
1570 | if (ret) |
1571 | return ret; | |
7981c001 MW |
1572 | } |
1573 | ||
1574 | irq = platform_get_irq(pdev, 0); | |
4e73d02f | 1575 | if (irq < 0) |
7981c001 | 1576 | return irq; |
7981c001 MW |
1577 | |
1578 | ret = intel_pinctrl_pm_init(pctrl); | |
1579 | if (ret) | |
1580 | return ret; | |
1581 | ||
1582 | pctrl->pctldesc = intel_pinctrl_desc; | |
1583 | pctrl->pctldesc.name = dev_name(&pdev->dev); | |
1584 | pctrl->pctldesc.pins = pctrl->soc->pins; | |
1585 | pctrl->pctldesc.npins = pctrl->soc->npins; | |
1586 | ||
54d46cd7 LD |
1587 | pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, |
1588 | pctrl); | |
323de9ef | 1589 | if (IS_ERR(pctrl->pctldev)) { |
7981c001 | 1590 | dev_err(&pdev->dev, "failed to register pinctrl driver\n"); |
323de9ef | 1591 | return PTR_ERR(pctrl->pctldev); |
7981c001 MW |
1592 | } |
1593 | ||
1594 | ret = intel_gpio_probe(pctrl, irq); | |
54d46cd7 | 1595 | if (ret) |
7981c001 | 1596 | return ret; |
7981c001 MW |
1597 | |
1598 | platform_set_drvdata(pdev, pctrl); | |
1599 | ||
1600 | return 0; | |
1601 | } | |
7981c001 | 1602 | |
70c263c4 AS |
1603 | int intel_pinctrl_probe_by_hid(struct platform_device *pdev) |
1604 | { | |
1605 | const struct intel_pinctrl_soc_data *data; | |
1606 | ||
1607 | data = device_get_match_data(&pdev->dev); | |
ff360d62 AS |
1608 | if (!data) |
1609 | return -ENODATA; | |
1610 | ||
70c263c4 AS |
1611 | return intel_pinctrl_probe(pdev, data); |
1612 | } | |
1613 | EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); | |
1614 | ||
924cf800 | 1615 | int intel_pinctrl_probe_by_uid(struct platform_device *pdev) |
ff360d62 AS |
1616 | { |
1617 | const struct intel_pinctrl_soc_data *data; | |
1618 | ||
1619 | data = intel_pinctrl_get_soc_data(pdev); | |
1620 | if (IS_ERR(data)) | |
1621 | return PTR_ERR(data); | |
1622 | ||
1623 | return intel_pinctrl_probe(pdev, data); | |
1624 | } | |
1625 | EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); | |
1626 | ||
1627 | const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) | |
924cf800 AS |
1628 | { |
1629 | const struct intel_pinctrl_soc_data *data = NULL; | |
1630 | const struct intel_pinctrl_soc_data **table; | |
1631 | struct acpi_device *adev; | |
1632 | unsigned int i; | |
1633 | ||
1634 | adev = ACPI_COMPANION(&pdev->dev); | |
1635 | if (adev) { | |
1636 | const void *match = device_get_match_data(&pdev->dev); | |
1637 | ||
1638 | table = (const struct intel_pinctrl_soc_data **)match; | |
1639 | for (i = 0; table[i]; i++) { | |
1640 | if (!strcmp(adev->pnp.unique_id, table[i]->uid)) { | |
1641 | data = table[i]; | |
1642 | break; | |
1643 | } | |
1644 | } | |
1645 | } else { | |
1646 | const struct platform_device_id *id; | |
1647 | ||
1648 | id = platform_get_device_id(pdev); | |
1649 | if (!id) | |
ff360d62 | 1650 | return ERR_PTR(-ENODEV); |
924cf800 AS |
1651 | |
1652 | table = (const struct intel_pinctrl_soc_data **)id->driver_data; | |
1653 | data = table[pdev->id]; | |
1654 | } | |
924cf800 | 1655 | |
ff360d62 | 1656 | return data ?: ERR_PTR(-ENODATA); |
924cf800 | 1657 | } |
ff360d62 | 1658 | EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); |
924cf800 | 1659 | |
7981c001 | 1660 | #ifdef CONFIG_PM_SLEEP |
04035f7f | 1661 | static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) |
c538b943 MW |
1662 | { |
1663 | const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); | |
1664 | ||
1665 | if (!pd || !intel_pad_usable(pctrl, pin)) | |
1666 | return false; | |
1667 | ||
1668 | /* | |
1669 | * Only restore the pin if it is actually in use by the kernel (or | |
1670 | * by userspace). It is possible that some pins are used by the | |
1671 | * BIOS during resume and those are not always locked down so leave | |
1672 | * them alone. | |
1673 | */ | |
1674 | if (pd->mux_owner || pd->gpio_owner || | |
6cb0880f | 1675 | gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) |
c538b943 MW |
1676 | return true; |
1677 | ||
1678 | return false; | |
1679 | } | |
1680 | ||
2fef3276 | 1681 | int intel_pinctrl_suspend_noirq(struct device *dev) |
7981c001 | 1682 | { |
cb035d74 | 1683 | struct intel_pinctrl *pctrl = dev_get_drvdata(dev); |
7981c001 MW |
1684 | struct intel_community_context *communities; |
1685 | struct intel_pad_context *pads; | |
1686 | int i; | |
1687 | ||
1688 | pads = pctrl->context.pads; | |
1689 | for (i = 0; i < pctrl->soc->npins; i++) { | |
1690 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; | |
e57725ea | 1691 | void __iomem *padcfg; |
7981c001 MW |
1692 | u32 val; |
1693 | ||
c538b943 | 1694 | if (!intel_pinctrl_should_save(pctrl, desc->number)) |
7981c001 MW |
1695 | continue; |
1696 | ||
1697 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0)); | |
1698 | pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; | |
1699 | val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1)); | |
1700 | pads[i].padcfg1 = val; | |
e57725ea MW |
1701 | |
1702 | padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2); | |
1703 | if (padcfg) | |
1704 | pads[i].padcfg2 = readl(padcfg); | |
7981c001 MW |
1705 | } |
1706 | ||
1707 | communities = pctrl->context.communities; | |
1708 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1709 | struct intel_community *community = &pctrl->communities[i]; | |
1710 | void __iomem *base; | |
04035f7f | 1711 | unsigned int gpp; |
7981c001 MW |
1712 | |
1713 | base = community->regs + community->ie_offset; | |
1714 | for (gpp = 0; gpp < community->ngpps; gpp++) | |
1715 | communities[i].intmask[gpp] = readl(base + gpp * 4); | |
a0a5f766 CC |
1716 | |
1717 | base = community->regs + community->hostown_offset; | |
1718 | for (gpp = 0; gpp < community->ngpps; gpp++) | |
1719 | communities[i].hostown[gpp] = readl(base + gpp * 4); | |
7981c001 MW |
1720 | } |
1721 | ||
1722 | return 0; | |
1723 | } | |
2fef3276 | 1724 | EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq); |
7981c001 | 1725 | |
942c5ea4 | 1726 | static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value) |
a0a5f766 | 1727 | { |
5f61d951 | 1728 | u32 curr, updated; |
a0a5f766 | 1729 | |
942c5ea4 AS |
1730 | curr = readl(reg); |
1731 | ||
5f61d951 | 1732 | updated = (curr & ~mask) | (value & mask); |
942c5ea4 AS |
1733 | if (curr == updated) |
1734 | return false; | |
5f61d951 | 1735 | |
942c5ea4 AS |
1736 | writel(updated, reg); |
1737 | return true; | |
a0a5f766 CC |
1738 | } |
1739 | ||
7101e022 AS |
1740 | static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, |
1741 | void __iomem *base, unsigned int gpp, u32 saved) | |
1742 | { | |
1743 | const struct intel_community *community = &pctrl->communities[c]; | |
1744 | const struct intel_padgroup *padgrp = &community->gpps[gpp]; | |
1745 | struct device *dev = pctrl->dev; | |
d1bfd022 AS |
1746 | const char *dummy; |
1747 | u32 requested = 0; | |
1748 | unsigned int i; | |
7101e022 | 1749 | |
e5a4ab6a | 1750 | if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) |
7101e022 AS |
1751 | return; |
1752 | ||
d1bfd022 AS |
1753 | for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy) |
1754 | requested |= BIT(i); | |
1755 | ||
942c5ea4 | 1756 | if (!intel_gpio_update_reg(base + gpp * 4, requested, saved)) |
7101e022 AS |
1757 | return; |
1758 | ||
764cfe33 | 1759 | dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); |
7101e022 AS |
1760 | } |
1761 | ||
471dd9a9 AS |
1762 | static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c, |
1763 | void __iomem *base, unsigned int gpp, u32 saved) | |
1764 | { | |
1765 | struct device *dev = pctrl->dev; | |
1766 | ||
942c5ea4 AS |
1767 | if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved)) |
1768 | return; | |
1769 | ||
471dd9a9 AS |
1770 | dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4)); |
1771 | } | |
1772 | ||
f78f152a AS |
1773 | static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin, |
1774 | unsigned int reg, u32 saved) | |
1775 | { | |
1776 | u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0; | |
1777 | unsigned int n = reg / sizeof(u32); | |
1778 | struct device *dev = pctrl->dev; | |
1779 | void __iomem *padcfg; | |
f78f152a AS |
1780 | |
1781 | padcfg = intel_get_padcfg(pctrl, pin, reg); | |
1782 | if (!padcfg) | |
1783 | return; | |
1784 | ||
942c5ea4 | 1785 | if (!intel_gpio_update_reg(padcfg, ~mask, saved)) |
f78f152a AS |
1786 | return; |
1787 | ||
f78f152a AS |
1788 | dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg)); |
1789 | } | |
1790 | ||
2fef3276 | 1791 | int intel_pinctrl_resume_noirq(struct device *dev) |
7981c001 | 1792 | { |
cb035d74 | 1793 | struct intel_pinctrl *pctrl = dev_get_drvdata(dev); |
7981c001 MW |
1794 | const struct intel_community_context *communities; |
1795 | const struct intel_pad_context *pads; | |
1796 | int i; | |
1797 | ||
1798 | /* Mask all interrupts */ | |
1799 | intel_gpio_irq_init(pctrl); | |
1800 | ||
1801 | pads = pctrl->context.pads; | |
1802 | for (i = 0; i < pctrl->soc->npins; i++) { | |
1803 | const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; | |
7981c001 | 1804 | |
c538b943 | 1805 | if (!intel_pinctrl_should_save(pctrl, desc->number)) |
7981c001 MW |
1806 | continue; |
1807 | ||
f78f152a AS |
1808 | intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); |
1809 | intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1); | |
1810 | intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2); | |
7981c001 MW |
1811 | } |
1812 | ||
1813 | communities = pctrl->context.communities; | |
1814 | for (i = 0; i < pctrl->ncommunities; i++) { | |
1815 | struct intel_community *community = &pctrl->communities[i]; | |
1816 | void __iomem *base; | |
04035f7f | 1817 | unsigned int gpp; |
7981c001 MW |
1818 | |
1819 | base = community->regs + community->ie_offset; | |
471dd9a9 AS |
1820 | for (gpp = 0; gpp < community->ngpps; gpp++) |
1821 | intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]); | |
a0a5f766 CC |
1822 | |
1823 | base = community->regs + community->hostown_offset; | |
7101e022 AS |
1824 | for (gpp = 0; gpp < community->ngpps; gpp++) |
1825 | intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]); | |
7981c001 MW |
1826 | } |
1827 | ||
1828 | return 0; | |
1829 | } | |
2fef3276 | 1830 | EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq); |
7981c001 MW |
1831 | #endif |
1832 | ||
1833 | MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>"); | |
1834 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); | |
1835 | MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver"); | |
1836 | MODULE_LICENSE("GPL v2"); |