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Merge tag 'x86_kdump_for_v5.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / drivers / pinctrl / intel / pinctrl-alderlake.c
CommitLineData
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AS		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Alder Lake PCH pinctrl/GPIO driver
4 *
114b610b 5 * Copyright (C) 2020, 2022 Intel Corporation
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AS		 6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 */
8
9#include <linux/mod_devicetable.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12
13#include <linux/pinctrl/pinctrl.h>
14
15#include "pinctrl-intel.h"
16
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AS		 17#define ADL_N_PAD_OWN 0x020
18#define ADL_N_PADCFGLOCK 0x080
19#define ADL_N_HOSTSW_OWN 0x0b0
20#define ADL_N_GPI_IS 0x100
21#define ADL_N_GPI_IE 0x120
22
23#define ADL_S_PAD_OWN 0x0a0
24#define ADL_S_PADCFGLOCK 0x110
25#define ADL_S_HOSTSW_OWN 0x150
26#define ADL_S_GPI_IS 0x200
27#define ADL_S_GPI_IE 0x220
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AS		 28
29#define ADL_GPP(r, s, e, g) \
30 { \
31 .reg_num = (r), \
32 .base = (s), \
33 .size = ((e) - (s) + 1), \
34 .gpio_base = (g), \
35 }
36
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AS		 37#define ADL_N_COMMUNITY(b, s, e, g) \
38 { \
39 .barno = (b), \
40 .padown_offset = ADL_N_PAD_OWN, \
41 .padcfglock_offset = ADL_N_PADCFGLOCK, \
42 .hostown_offset = ADL_N_HOSTSW_OWN, \
43 .is_offset = ADL_N_GPI_IS, \
44 .ie_offset = ADL_N_GPI_IE, \
45 .pin_base = (s), \
46 .npins = ((e) - (s) + 1), \
47 .gpps = (g), \
48 .ngpps = ARRAY_SIZE(g), \
49 }
50
51#define ADL_S_COMMUNITY(b, s, e, g) \
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AS		 52 { \
53 .barno = (b), \
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AS		 54 .padown_offset = ADL_S_PAD_OWN, \
55 .padcfglock_offset = ADL_S_PADCFGLOCK, \
56 .hostown_offset = ADL_S_HOSTSW_OWN, \
57 .is_offset = ADL_S_GPI_IS, \
58 .ie_offset = ADL_S_GPI_IE, \
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AS		 59 .pin_base = (s), \
60 .npins = ((e) - (s) + 1), \
61 .gpps = (g), \
62 .ngpps = ARRAY_SIZE(g), \
63 }
64
114b610b
AS		 65/* Alder Lake-N */
66static const struct pinctrl_pin_desc adln_pins[] = {
67 /* GPP_B */
68 PINCTRL_PIN(0, "CORE_VID_0"),
69 PINCTRL_PIN(1, "CORE_VID_1"),
70 PINCTRL_PIN(2, "GPPC_B_2"),
71 PINCTRL_PIN(3, "GPPC_B_3"),
72 PINCTRL_PIN(4, "GPPC_B_4"),
73 PINCTRL_PIN(5, "GPPC_B_5"),
74 PINCTRL_PIN(6, "GPPC_B_6"),
75 PINCTRL_PIN(7, "GPPC_B_7"),
76 PINCTRL_PIN(8, "GPPC_B_8"),
77 PINCTRL_PIN(9, "GPPC_B_9"),
78 PINCTRL_PIN(10, "GPPC_B_10"),
79 PINCTRL_PIN(11, "GPPC_B_11"),
80 PINCTRL_PIN(12, "SLP_S0B"),
81 PINCTRL_PIN(13, "PLTRSTB"),
82 PINCTRL_PIN(14, "GPPC_B_14"),
83 PINCTRL_PIN(15, "GPPC_B_15"),
84 PINCTRL_PIN(16, "GPPC_B_16"),
85 PINCTRL_PIN(17, "GPPC_B_17"),
86 PINCTRL_PIN(18, "GPPC_B_18"),
87 PINCTRL_PIN(19, "GPPC_B_19"),
88 PINCTRL_PIN(20, "GPPC_B_20"),
89 PINCTRL_PIN(21, "GPPC_B_21"),
90 PINCTRL_PIN(22, "GPPC_B_22"),
91 PINCTRL_PIN(23, "GPPC_B_23"),
92 PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
93 PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
94 /* GPP_T */
95 PINCTRL_PIN(26, "GPPC_T_0"),
96 PINCTRL_PIN(27, "GPPC_T_1"),
97 PINCTRL_PIN(28, "FUSA_DIAGTEST_EN"),
98 PINCTRL_PIN(29, "FUSA_DIAGTEST_MODE"),
99 PINCTRL_PIN(30, "GPPC_T_4"),
100 PINCTRL_PIN(31, "GPPC_T_5"),
101 PINCTRL_PIN(32, "GPPC_T_6"),
102 PINCTRL_PIN(33, "GPPC_T_7"),
103 PINCTRL_PIN(34, "GPPC_T_8"),
104 PINCTRL_PIN(35, "GPPC_T_9"),
105 PINCTRL_PIN(36, "GPPC_T_10"),
106 PINCTRL_PIN(37, "GPPC_T_11"),
107 PINCTRL_PIN(38, "GPPC_T_12"),
108 PINCTRL_PIN(39, "GPPC_T_13"),
109 PINCTRL_PIN(40, "GPPC_T_14"),
110 PINCTRL_PIN(41, "GPPC_T_15"),
111 /* GPP_A */
112 PINCTRL_PIN(42, "ESPI_IO_0"),
113 PINCTRL_PIN(43, "ESPI_IO_1"),
114 PINCTRL_PIN(44, "ESPI_IO_2"),
115 PINCTRL_PIN(45, "ESPI_IO_3"),
116 PINCTRL_PIN(46, "ESPI_CS0B"),
117 PINCTRL_PIN(47, "ESPI_ALERT0B"),
118 PINCTRL_PIN(48, "ESPI_ALERT1B"),
119 PINCTRL_PIN(49, "GPPC_A_7"),
120 PINCTRL_PIN(50, "GPPC_A_8"),
121 PINCTRL_PIN(51, "ESPI_CLK"),
122 PINCTRL_PIN(52, "ESPI_RESETB"),
123 PINCTRL_PIN(53, "GPPC_A_11"),
124 PINCTRL_PIN(54, "GPPC_A_12"),
125 PINCTRL_PIN(55, "GPPC_A_13"),
126 PINCTRL_PIN(56, "GPPC_A_14"),
127 PINCTRL_PIN(57, "GPPC_A_15"),
128 PINCTRL_PIN(58, "GPPC_A_16"),
129 PINCTRL_PIN(59, "GPPC_A_17"),
130 PINCTRL_PIN(60, "GPPC_A_18"),
131 PINCTRL_PIN(61, "GPPC_A_19"),
132 PINCTRL_PIN(62, "GPPC_A_20"),
133 PINCTRL_PIN(63, "GPPC_A_21"),
134 PINCTRL_PIN(64, "GPPC_A_22"),
135 PINCTRL_PIN(65, "ESPI_CS1B"),
136 PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
137 /* GPP_S */
138 PINCTRL_PIN(67, "GPP_S_0"),
139 PINCTRL_PIN(68, "GPP_S_1"),
140 PINCTRL_PIN(69, "GPP_S_2"),
141 PINCTRL_PIN(70, "GPP_S_3"),
142 PINCTRL_PIN(71, "GPP_S_4"),
143 PINCTRL_PIN(72, "GPP_S_5"),
144 PINCTRL_PIN(73, "GPP_S_6"),
145 PINCTRL_PIN(74, "GPP_S_7"),
146 /* GPP_I */
147 PINCTRL_PIN(75, "GPP_F_0_CNV_BRI_DT_UART0_RTSB"),
148 PINCTRL_PIN(76, "GPP_F_1_CNV_BRI_RSP_UART0_RXD"),
149 PINCTRL_PIN(77, "GPP_F_2_CNV_RGI_DT_UART0_TXD"),
150 PINCTRL_PIN(78, "GPP_F_3_CNV_RGI_RSP_UART0_CTSB"),
151 PINCTRL_PIN(79, "GPP_F_4_CNV_RF_RESET_B"),
152 PINCTRL_PIN(80, "GPP_F_5_MODEM_CLKREQ"),
153 PINCTRL_PIN(81, "GPP_F_6_CNV_PA_BLANKING"),
154 PINCTRL_PIN(82, "GPP_F_7_EMMC_CMD"),
155 PINCTRL_PIN(83, "GPP_F_8_EMMC_DATA0"),
156 PINCTRL_PIN(84, "GPP_F_9_EMMC_DATA1"),
157 PINCTRL_PIN(85, "GPP_F_10_EMMC_DATA2"),
158 PINCTRL_PIN(86, "GPP_F_11_EMMC_DATA3"),
159 PINCTRL_PIN(87, "GPP_F_12_EMMC_DATA4"),
160 PINCTRL_PIN(88, "GPP_F_13_EMMC_DATA5"),
161 PINCTRL_PIN(89, "GPP_F_14_EMMC_DATA6"),
162 PINCTRL_PIN(90, "GPP_F_15_EMMC_DATA7"),
163 PINCTRL_PIN(91, "GPP_F_16_EMMC_RCLK"),
164 PINCTRL_PIN(92, "GPP_F_17_EMMC_CLK"),
165 PINCTRL_PIN(93, "GPP_F_18_EMMC_RESETB"),
166 PINCTRL_PIN(94, "GPP_F_19_A4WP_PRESENT"),
167 /* GPP_H */
168 PINCTRL_PIN(95, "GPPC_H_0"),
169 PINCTRL_PIN(96, "GPPC_H_1"),
170 PINCTRL_PIN(97, "GPPC_H_2"),
171 PINCTRL_PIN(98, "GPPC_H_3"),
172 PINCTRL_PIN(99, "GPPC_H_4"),
173 PINCTRL_PIN(100, "GPPC_H_5"),
174 PINCTRL_PIN(101, "GPPC_H_6"),
175 PINCTRL_PIN(102, "GPPC_H_7"),
176 PINCTRL_PIN(103, "GPPC_H_8"),
177 PINCTRL_PIN(104, "GPPC_H_9"),
178 PINCTRL_PIN(105, "GPPC_H_10"),
179 PINCTRL_PIN(106, "GPPC_H_11"),
180 PINCTRL_PIN(107, "I2C7_SDA"),
181 PINCTRL_PIN(108, "I2C7_SCL"),
182 PINCTRL_PIN(109, "GPPC_H_14"),
183 PINCTRL_PIN(110, "GPPC_H_15"),
184 PINCTRL_PIN(111, "GPPC_H_16"),
185 PINCTRL_PIN(112, "GPPC_H_17"),
186 PINCTRL_PIN(113, "CPU_C10_GATEB"),
187 PINCTRL_PIN(114, "GPPC_H_19"),
188 PINCTRL_PIN(115, "GPPC_H_20"),
189 PINCTRL_PIN(116, "GPPC_H_21"),
190 PINCTRL_PIN(117, "GPPC_H_22"),
191 PINCTRL_PIN(118, "GPPC_H_23"),
192 /* GPP_D */
193 PINCTRL_PIN(119, "GPPC_D_0"),
194 PINCTRL_PIN(120, "GPPC_D_1"),
195 PINCTRL_PIN(121, "GPPC_D_2"),
196 PINCTRL_PIN(122, "GPPC_D_3"),
197 PINCTRL_PIN(123, "GPPC_D_4"),
198 PINCTRL_PIN(124, "GPPC_D_5"),
199 PINCTRL_PIN(125, "GPPC_D_6"),
200 PINCTRL_PIN(126, "GPPC_D_7"),
201 PINCTRL_PIN(127, "GPPC_D_8"),
202 PINCTRL_PIN(128, "BSSB_LS2_RX"),
203 PINCTRL_PIN(129, "BSSB_LS2_TX"),
204 PINCTRL_PIN(130, "BSSB_LS3_RX"),
205 PINCTRL_PIN(131, "BSSB_LS3_TX"),
206 PINCTRL_PIN(132, "GPPC_D_13"),
207 PINCTRL_PIN(133, "GPPC_D_14"),
208 PINCTRL_PIN(134, "GPPC_D_15"),
209 PINCTRL_PIN(135, "GPPC_D_16"),
210 PINCTRL_PIN(136, "GPPC_D_17"),
211 PINCTRL_PIN(137, "GPPC_D_18"),
212 PINCTRL_PIN(138, "GPPC_D_19"),
213 PINCTRL_PIN(139, "GSPI2_CLK_LOOPBK"),
214 /* vGPIO */
215 PINCTRL_PIN(140, "CNV_BTEN"),
216 PINCTRL_PIN(141, "CNV_BT_HOST_WAKEB"),
217 PINCTRL_PIN(142, "CNV_BT_IF_SELECT"),
218 PINCTRL_PIN(143, "vCNV_BT_UART_TXD"),
219 PINCTRL_PIN(144, "vCNV_BT_UART_RXD"),
220 PINCTRL_PIN(145, "vCNV_BT_UART_CTS_B"),
221 PINCTRL_PIN(146, "vCNV_BT_UART_RTS_B"),
222 PINCTRL_PIN(147, "vCNV_MFUART1_TXD"),
223 PINCTRL_PIN(148, "vCNV_MFUART1_RXD"),
224 PINCTRL_PIN(149, "vCNV_MFUART1_CTS_B"),
225 PINCTRL_PIN(150, "vCNV_MFUART1_RTS_B"),
226 PINCTRL_PIN(151, "vUART0_TXD"),
227 PINCTRL_PIN(152, "vUART0_RXD"),
228 PINCTRL_PIN(153, "vUART0_CTS_B"),
229 PINCTRL_PIN(154, "vUART0_RTS_B"),
230 PINCTRL_PIN(155, "vISH_UART0_TXD"),
231 PINCTRL_PIN(156, "vISH_UART0_RXD"),
232 PINCTRL_PIN(157, "vISH_UART0_CTS_B"),
233 PINCTRL_PIN(158, "vISH_UART0_RTS_B"),
234 PINCTRL_PIN(159, "vCNV_BT_I2S_BCLK"),
235 PINCTRL_PIN(160, "vCNV_BT_I2S_WS_SYNC"),
236 PINCTRL_PIN(161, "vCNV_BT_I2S_SDO"),
237 PINCTRL_PIN(162, "vCNV_BT_I2S_SDI"),
238 PINCTRL_PIN(163, "vI2S2_SCLK"),
239 PINCTRL_PIN(164, "vI2S2_SFRM"),
240 PINCTRL_PIN(165, "vI2S2_TXD"),
241 PINCTRL_PIN(166, "vI2S2_RXD"),
242 PINCTRL_PIN(167, "THC0_WOT_INT"),
243 PINCTRL_PIN(168, "THC1_WOT_INT"),
244 /* GPP_C */
245 PINCTRL_PIN(169, "SMBCLK"),
246 PINCTRL_PIN(170, "SMBDATA"),
247 PINCTRL_PIN(171, "SMBALERTB"),
248 PINCTRL_PIN(172, "SML0CLK"),
249 PINCTRL_PIN(173, "SML0DATA"),
250 PINCTRL_PIN(174, "GPPC_C_5"),
251 PINCTRL_PIN(175, "GPPC_C_6"),
252 PINCTRL_PIN(176, "GPPC_C_7"),
253 PINCTRL_PIN(177, "GPPC_C_8"),
254 PINCTRL_PIN(178, "GPPC_C_9"),
255 PINCTRL_PIN(179, "GPPC_C_10"),
256 PINCTRL_PIN(180, "GPPC_C_11"),
257 PINCTRL_PIN(181, "GPPC_C_12"),
258 PINCTRL_PIN(182, "GPPC_C_13"),
259 PINCTRL_PIN(183, "GPPC_C_14"),
260 PINCTRL_PIN(184, "GPPC_C_15"),
261 PINCTRL_PIN(185, "GPPC_C_16"),
262 PINCTRL_PIN(186, "GPPC_C_17"),
263 PINCTRL_PIN(187, "GPPC_C_18"),
264 PINCTRL_PIN(188, "GPPC_C_19"),
265 PINCTRL_PIN(189, "GPPC_C_20"),
266 PINCTRL_PIN(190, "GPPC_C_21"),
267 PINCTRL_PIN(191, "GPPC_C_22"),
268 PINCTRL_PIN(192, "GPPC_C_23"),
269 /* GPP_F */
270 PINCTRL_PIN(193, "CNV_BRI_DT"),
271 PINCTRL_PIN(194, "CNV_BRI_RSP"),
272 PINCTRL_PIN(195, "CNV_RGI_DT"),
273 PINCTRL_PIN(196, "CNV_RGI_RSP"),
274 PINCTRL_PIN(197, "CNV_RF_RESET_B"),
275 PINCTRL_PIN(198, "MODEM_CLKREQ"),
276 PINCTRL_PIN(199, "GPPC_F_6"),
277 PINCTRL_PIN(200, "GPPC_F_7"),
278 PINCTRL_PIN(201, "GPPC_F_8"),
279 PINCTRL_PIN(202, "BOOTMPC"),
280 PINCTRL_PIN(203, "GPPC_F_10"),
281 PINCTRL_PIN(204, "GPPC_F_11"),
282 PINCTRL_PIN(205, "GPPC_F_12"),
283 PINCTRL_PIN(206, "GPPC_F_13"),
284 PINCTRL_PIN(207, "GPPC_F_14"),
285 PINCTRL_PIN(208, "GPPC_F_15"),
286 PINCTRL_PIN(209, "GPPC_F_16"),
287 PINCTRL_PIN(210, "GPPC_F_17"),
288 PINCTRL_PIN(211, "GPPC_F_18"),
289 PINCTRL_PIN(212, "GPPC_F_19"),
290 PINCTRL_PIN(213, "EXT_PWR_GATEB"),
291 PINCTRL_PIN(214, "EXT_PWR_GATE2B"),
292 PINCTRL_PIN(215, "GPPC_F_22"),
293 PINCTRL_PIN(216, "GPPC_F_23"),
294 PINCTRL_PIN(217, "GPPF_CLK_LOOPBACK"),
295 /* HVCMOS */
296 PINCTRL_PIN(218, "L_BKLTEN"),
297 PINCTRL_PIN(219, "L_BKLTCTL"),
298 PINCTRL_PIN(220, "L_VDDEN"),
299 PINCTRL_PIN(221, "SYS_PWROK"),
300 PINCTRL_PIN(222, "SYS_RESETB"),
301 PINCTRL_PIN(223, "MLK_RSTB"),
302 /* GPP_E */
303 PINCTRL_PIN(224, "GPPC_E_0"),
304 PINCTRL_PIN(225, "GPPC_E_1"),
305 PINCTRL_PIN(226, "GPPC_E_2"),
306 PINCTRL_PIN(227, "GPPC_E_3"),
307 PINCTRL_PIN(228, "GPPC_E_4"),
308 PINCTRL_PIN(229, "GPPC_E_5"),
309 PINCTRL_PIN(230, "GPPC_E_6"),
310 PINCTRL_PIN(231, "GPPC_E_7"),
311 PINCTRL_PIN(232, "GPPC_E_8"),
312 PINCTRL_PIN(233, "GPPC_E_9"),
313 PINCTRL_PIN(234, "GPPC_E_10"),
314 PINCTRL_PIN(235, "GPPC_E_11"),
315 PINCTRL_PIN(236, "GPPC_E_12"),
316 PINCTRL_PIN(237, "GPPC_E_13"),
317 PINCTRL_PIN(238, "GPPC_E_14"),
318 PINCTRL_PIN(239, "FIVR_DIGPB_0"),
319 PINCTRL_PIN(240, "FIVR_DIGPB_1"),
320 PINCTRL_PIN(241, "GPPC_E_17"),
321 PINCTRL_PIN(242, "BSSB_LS0_RX"),
322 PINCTRL_PIN(243, "BSSB_LS0_TX"),
323 PINCTRL_PIN(244, "BSSB_LS1_RX"),
324 PINCTRL_PIN(245, "BSSB_LS1_TX"),
325 PINCTRL_PIN(246, "DNX_FORCE_RELOAD"),
326 PINCTRL_PIN(247, "GPPC_E_23"),
327 PINCTRL_PIN(248, "GPPE_CLK_LOOPBACK"),
328 /* GPP_R */
329 PINCTRL_PIN(249, "HDA_BCLK"),
330 PINCTRL_PIN(250, "HDA_SYNC"),
331 PINCTRL_PIN(251, "HDA_SDO"),
332 PINCTRL_PIN(252, "HDA_SDI_0"),
333 PINCTRL_PIN(253, "HDA_RSTB"),
334 PINCTRL_PIN(254, "GPP_R_5"),
335 PINCTRL_PIN(255, "GPP_R_6"),
336 PINCTRL_PIN(256, "GPP_R_7"),
337};
338
339static const struct intel_padgroup adln_community0_gpps[] = {
340 ADL_GPP(0, 0, 25, 0), /* GPP_B */
341 ADL_GPP(1, 26, 41, 32), /* GPP_T */
342 ADL_GPP(2, 42, 66, 64), /* GPP_A */
343};
344
345static const struct intel_padgroup adln_community1_gpps[] = {
346 ADL_GPP(0, 67, 74, 96), /* GPP_S */
347 ADL_GPP(1, 75, 94, 128), /* GPP_I */
348 ADL_GPP(2, 95, 118, 160), /* GPP_H */
349 ADL_GPP(3, 119, 139, 192), /* GPP_D */
350 ADL_GPP(4, 140, 168, 224), /* vGPIO */
351};
352
353static const struct intel_padgroup adln_community4_gpps[] = {
354 ADL_GPP(0, 169, 192, 256), /* GPP_C */
355 ADL_GPP(1, 193, 217, 288), /* GPP_F */
356 ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
357 ADL_GPP(3, 224, 248, 320), /* GPP_E */
358};
359
360static const struct intel_padgroup adln_community5_gpps[] = {
361 ADL_GPP(0, 249, 256, 352), /* GPP_R */
362};
363
364static const struct intel_community adln_communities[] = {
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AS		 365 ADL_N_COMMUNITY(0, 0, 66, adln_community0_gpps),
366 ADL_N_COMMUNITY(1, 67, 168, adln_community1_gpps),
367 ADL_N_COMMUNITY(2, 169, 248, adln_community4_gpps),
368 ADL_N_COMMUNITY(3, 249, 256, adln_community5_gpps),
114b610b
AS		 369};
370
371static const struct intel_pinctrl_soc_data adln_soc_data = {
372 .pins = adln_pins,
373 .npins = ARRAY_SIZE(adln_pins),
374 .communities = adln_communities,
375 .ncommunities = ARRAY_SIZE(adln_communities),
376};
377
e789e61f
AS		 378/* Alder Lake-S */
379static const struct pinctrl_pin_desc adls_pins[] = {
380 /* GPP_I */
381 PINCTRL_PIN(0, "EXT_PWR_GATEB"),
382 PINCTRL_PIN(1, "DDSP_HPD_1"),
383 PINCTRL_PIN(2, "DDSP_HPD_2"),
384 PINCTRL_PIN(3, "DDSP_HPD_3"),
385 PINCTRL_PIN(4, "DDSP_HPD_4"),
386 PINCTRL_PIN(5, "DDPB_CTRLCLK"),
387 PINCTRL_PIN(6, "DDPB_CTRLDATA"),
388 PINCTRL_PIN(7, "DDPC_CTRLCLK"),
389 PINCTRL_PIN(8, "DDPC_CTRLDATA"),
390 PINCTRL_PIN(9, "GSPI0_CS1B"),
391 PINCTRL_PIN(10, "GSPI1_CS1B"),
392 PINCTRL_PIN(11, "USB2_OCB_4"),
393 PINCTRL_PIN(12, "USB2_OCB_5"),
394 PINCTRL_PIN(13, "USB2_OCB_6"),
395 PINCTRL_PIN(14, "USB2_OCB_7"),
396 PINCTRL_PIN(15, "GSPI0_CS0B"),
397 PINCTRL_PIN(16, "GSPI0_CLK"),
398 PINCTRL_PIN(17, "GSPI0_MISO"),
399 PINCTRL_PIN(18, "GSPI0_MOSI"),
400 PINCTRL_PIN(19, "GSPI1_CS0B"),
401 PINCTRL_PIN(20, "GSPI1_CLK"),
402 PINCTRL_PIN(21, "GSPI1_MISO"),
403 PINCTRL_PIN(22, "GSPI1_MOSI"),
404 PINCTRL_PIN(23, "GSPI0_CLK_LOOPBK"),
405 PINCTRL_PIN(24, "GSPI1_CLK_LOOPBK"),
406 /* GPP_R */
407 PINCTRL_PIN(25, "HDA_BCLK"),
408 PINCTRL_PIN(26, "HDA_SYNC"),
409 PINCTRL_PIN(27, "HDA_SDO"),
410 PINCTRL_PIN(28, "HDA_SDI_0"),
411 PINCTRL_PIN(29, "HDA_RSTB"),
412 PINCTRL_PIN(30, "HDA_SDI_1"),
413 PINCTRL_PIN(31, "GPP_R_6"),
414 PINCTRL_PIN(32, "GPP_R_7"),
415 PINCTRL_PIN(33, "GPP_R_8"),
416 PINCTRL_PIN(34, "DDSP_HPD_A"),
417 PINCTRL_PIN(35, "DDSP_HPD_B"),
418 PINCTRL_PIN(36, "DDSP_HPD_C"),
419 PINCTRL_PIN(37, "ISH_SPI_CSB"),
420 PINCTRL_PIN(38, "ISH_SPI_CLK"),
421 PINCTRL_PIN(39, "ISH_SPI_MISO"),
422 PINCTRL_PIN(40, "ISH_SPI_MOSI"),
423 PINCTRL_PIN(41, "DDP1_CTRLCLK"),
424 PINCTRL_PIN(42, "DDP1_CTRLDATA"),
425 PINCTRL_PIN(43, "DDP2_CTRLCLK"),
426 PINCTRL_PIN(44, "DDP2_CTRLDATA"),
427 PINCTRL_PIN(45, "DDPA_CTRLCLK"),
428 PINCTRL_PIN(46, "DDPA_CTRLDATA"),
429 PINCTRL_PIN(47, "GSPI2_CLK_LOOPBK"),
430 /* GPP_J */
431 PINCTRL_PIN(48, "CNV_PA_BLANKING"),
432 PINCTRL_PIN(49, "CPU_C10_GATEB"),
433 PINCTRL_PIN(50, "CNV_BRI_DT"),
434 PINCTRL_PIN(51, "CNV_BRI_RSP"),
435 PINCTRL_PIN(52, "CNV_RGI_DT"),
436 PINCTRL_PIN(53, "CNV_RGI_RSP"),
437 PINCTRL_PIN(54, "CNV_MFUART2_RXD"),
438 PINCTRL_PIN(55, "CNV_MFUART2_TXD"),
439 PINCTRL_PIN(56, "SRCCLKREQB_16"),
440 PINCTRL_PIN(57, "SRCCLKREQB_17"),
441 PINCTRL_PIN(58, "BSSB_LS_RX"),
442 PINCTRL_PIN(59, "BSSB_LS_TX"),
443 /* vGPIO */
444 PINCTRL_PIN(60, "CNV_BTEN"),
445 PINCTRL_PIN(61, "CNV_BT_HOST_WAKEB"),
446 PINCTRL_PIN(62, "CNV_BT_IF_SELECT"),
447 PINCTRL_PIN(63, "vCNV_BT_UART_TXD"),
448 PINCTRL_PIN(64, "vCNV_BT_UART_RXD"),
449 PINCTRL_PIN(65, "vCNV_BT_UART_CTS_B"),
450 PINCTRL_PIN(66, "vCNV_BT_UART_RTS_B"),
451 PINCTRL_PIN(67, "vCNV_MFUART1_TXD"),
452 PINCTRL_PIN(68, "vCNV_MFUART1_RXD"),
453 PINCTRL_PIN(69, "vCNV_MFUART1_CTS_B"),
454 PINCTRL_PIN(70, "vCNV_MFUART1_RTS_B"),
455 PINCTRL_PIN(71, "vUART0_TXD"),
456 PINCTRL_PIN(72, "vUART0_RXD"),
457 PINCTRL_PIN(73, "vUART0_CTS_B"),
458 PINCTRL_PIN(74, "vUART0_RTS_B"),
459 PINCTRL_PIN(75, "vISH_UART0_TXD"),
460 PINCTRL_PIN(76, "vISH_UART0_RXD"),
461 PINCTRL_PIN(77, "vISH_UART0_CTS_B"),
462 PINCTRL_PIN(78, "vISH_UART0_RTS_B"),
463 PINCTRL_PIN(79, "vCNV_BT_I2S_BCLK"),
464 PINCTRL_PIN(80, "vCNV_BT_I2S_WS_SYNC"),
465 PINCTRL_PIN(81, "vCNV_BT_I2S_SDO"),
466 PINCTRL_PIN(82, "vCNV_BT_I2S_SDI"),
467 PINCTRL_PIN(83, "vI2S2_SCLK"),
468 PINCTRL_PIN(84, "vI2S2_SFRM"),
469 PINCTRL_PIN(85, "vI2S2_TXD"),
470 PINCTRL_PIN(86, "vI2S2_RXD"),
471 /* vGPIO_0 */
472 PINCTRL_PIN(87, "ESPI_USB_OCB_0"),
473 PINCTRL_PIN(88, "ESPI_USB_OCB_1"),
474 PINCTRL_PIN(89, "ESPI_USB_OCB_2"),
475 PINCTRL_PIN(90, "ESPI_USB_OCB_3"),
476 PINCTRL_PIN(91, "USB_CPU_OCB_0"),
477 PINCTRL_PIN(92, "USB_CPU_OCB_1"),
478 PINCTRL_PIN(93, "USB_CPU_OCB_2"),
479 PINCTRL_PIN(94, "USB_CPU_OCB_3"),
480 /* GPP_B */
481 PINCTRL_PIN(95, "PCIE_LNK_DOWN"),
482 PINCTRL_PIN(96, "ISH_UART0_RTSB"),
483 PINCTRL_PIN(97, "VRALERTB"),
484 PINCTRL_PIN(98, "CPU_GP_2"),
485 PINCTRL_PIN(99, "CPU_GP_3"),
486 PINCTRL_PIN(100, "SX_EXIT_HOLDOFFB"),
487 PINCTRL_PIN(101, "CLKOUT_48"),
488 PINCTRL_PIN(102, "ISH_GP_7"),
489 PINCTRL_PIN(103, "ISH_GP_0"),
490 PINCTRL_PIN(104, "ISH_GP_1"),
491 PINCTRL_PIN(105, "ISH_GP_2"),
492 PINCTRL_PIN(106, "I2S_MCLK"),
493 PINCTRL_PIN(107, "SLP_S0B"),
494 PINCTRL_PIN(108, "PLTRSTB"),
495 PINCTRL_PIN(109, "SPKR"),
496 PINCTRL_PIN(110, "ISH_GP_3"),
497 PINCTRL_PIN(111, "ISH_GP_4"),
498 PINCTRL_PIN(112, "ISH_GP_5"),
499 PINCTRL_PIN(113, "PMCALERTB"),
500 PINCTRL_PIN(114, "FUSA_DIAGTEST_EN"),
501 PINCTRL_PIN(115, "FUSA_DIAGTEST_MODE"),
502 PINCTRL_PIN(116, "GPP_B_21"),
503 PINCTRL_PIN(117, "GPP_B_22"),
504 PINCTRL_PIN(118, "SML1ALERTB"),
505 /* GPP_G */
506 PINCTRL_PIN(119, "GPP_G_0"),
507 PINCTRL_PIN(120, "GPP_G_1"),
508 PINCTRL_PIN(121, "DNX_FORCE_RELOAD"),
509 PINCTRL_PIN(122, "GMII_MDC_0"),
510 PINCTRL_PIN(123, "GMII_MDIO_0"),
511 PINCTRL_PIN(124, "SLP_DRAMB"),
512 PINCTRL_PIN(125, "GPP_G_6"),
513 PINCTRL_PIN(126, "GPP_G_7"),
514 /* GPP_H */
515 PINCTRL_PIN(127, "SRCCLKREQB_18"),
516 PINCTRL_PIN(128, "GPP_H_1"),
517 PINCTRL_PIN(129, "SRCCLKREQB_8"),
518 PINCTRL_PIN(130, "SRCCLKREQB_9"),
519 PINCTRL_PIN(131, "SRCCLKREQB_10"),
520 PINCTRL_PIN(132, "SRCCLKREQB_11"),
521 PINCTRL_PIN(133, "SRCCLKREQB_12"),
522 PINCTRL_PIN(134, "SRCCLKREQB_13"),
523 PINCTRL_PIN(135, "SRCCLKREQB_14"),
524 PINCTRL_PIN(136, "SRCCLKREQB_15"),
525 PINCTRL_PIN(137, "SML2CLK"),
526 PINCTRL_PIN(138, "SML2DATA"),
527 PINCTRL_PIN(139, "SML2ALERTB"),
528 PINCTRL_PIN(140, "SML3CLK"),
529 PINCTRL_PIN(141, "SML3DATA"),
530 PINCTRL_PIN(142, "SML3ALERTB"),
531 PINCTRL_PIN(143, "SML4CLK"),
532 PINCTRL_PIN(144, "SML4DATA"),
533 PINCTRL_PIN(145, "SML4ALERTB"),
534 PINCTRL_PIN(146, "ISH_I2C0_SDA"),
535 PINCTRL_PIN(147, "ISH_I2C0_SCL"),
536 PINCTRL_PIN(148, "ISH_I2C1_SDA"),
537 PINCTRL_PIN(149, "ISH_I2C1_SCL"),
538 PINCTRL_PIN(150, "TIME_SYNC_0"),
539 /* SPI0 */
540 PINCTRL_PIN(151, "SPI0_IO_2"),
541 PINCTRL_PIN(152, "SPI0_IO_3"),
542 PINCTRL_PIN(153, "SPI0_MOSI_IO_0"),
543 PINCTRL_PIN(154, "SPI0_MISO_IO_1"),
544 PINCTRL_PIN(155, "SPI0_TPM_CSB"),
545 PINCTRL_PIN(156, "SPI0_FLASH_0_CSB"),
546 PINCTRL_PIN(157, "SPI0_FLASH_1_CSB"),
547 PINCTRL_PIN(158, "SPI0_CLK"),
548 PINCTRL_PIN(159, "SPI0_CLK_LOOPBK"),
549 /* GPP_A */
550 PINCTRL_PIN(160, "ESPI_IO_0"),
551 PINCTRL_PIN(161, "ESPI_IO_1"),
552 PINCTRL_PIN(162, "ESPI_IO_2"),
553 PINCTRL_PIN(163, "ESPI_IO_3"),
554 PINCTRL_PIN(164, "ESPI_CS0B"),
555 PINCTRL_PIN(165, "ESPI_CLK"),
556 PINCTRL_PIN(166, "ESPI_RESETB"),
557 PINCTRL_PIN(167, "ESPI_CS1B"),
558 PINCTRL_PIN(168, "ESPI_CS2B"),
559 PINCTRL_PIN(169, "ESPI_CS3B"),
560 PINCTRL_PIN(170, "ESPI_ALERT0B"),
561 PINCTRL_PIN(171, "ESPI_ALERT1B"),
562 PINCTRL_PIN(172, "ESPI_ALERT2B"),
563 PINCTRL_PIN(173, "ESPI_ALERT3B"),
564 PINCTRL_PIN(174, "GPP_A_14"),
565 PINCTRL_PIN(175, "ESPI_CLK_LOOPBK"),
566 /* GPP_C */
567 PINCTRL_PIN(176, "SMBCLK"),
568 PINCTRL_PIN(177, "SMBDATA"),
569 PINCTRL_PIN(178, "SMBALERTB"),
570 PINCTRL_PIN(179, "ISH_UART0_RXD"),
571 PINCTRL_PIN(180, "ISH_UART0_TXD"),
572 PINCTRL_PIN(181, "SML0ALERTB"),
573 PINCTRL_PIN(182, "ISH_I2C2_SDA"),
574 PINCTRL_PIN(183, "ISH_I2C2_SCL"),
575 PINCTRL_PIN(184, "UART0_RXD"),
576 PINCTRL_PIN(185, "UART0_TXD"),
577 PINCTRL_PIN(186, "UART0_RTSB"),
578 PINCTRL_PIN(187, "UART0_CTSB"),
579 PINCTRL_PIN(188, "UART1_RXD"),
580 PINCTRL_PIN(189, "UART1_TXD"),
581 PINCTRL_PIN(190, "UART1_RTSB"),
582 PINCTRL_PIN(191, "UART1_CTSB"),
583 PINCTRL_PIN(192, "I2C0_SDA"),
584 PINCTRL_PIN(193, "I2C0_SCL"),
585 PINCTRL_PIN(194, "I2C1_SDA"),
586 PINCTRL_PIN(195, "I2C1_SCL"),
587 PINCTRL_PIN(196, "UART2_RXD"),
588 PINCTRL_PIN(197, "UART2_TXD"),
589 PINCTRL_PIN(198, "UART2_RTSB"),
590 PINCTRL_PIN(199, "UART2_CTSB"),
591 /* GPP_S */
592 PINCTRL_PIN(200, "SNDW1_CLK"),
593 PINCTRL_PIN(201, "SNDW1_DATA"),
594 PINCTRL_PIN(202, "SNDW2_CLK"),
595 PINCTRL_PIN(203, "SNDW2_DATA"),
596 PINCTRL_PIN(204, "SNDW3_CLK"),
597 PINCTRL_PIN(205, "SNDW3_DATA"),
598 PINCTRL_PIN(206, "SNDW4_CLK"),
599 PINCTRL_PIN(207, "SNDW4_DATA"),
600 /* GPP_E */
601 PINCTRL_PIN(208, "SATAXPCIE_0"),
602 PINCTRL_PIN(209, "SATAXPCIE_1"),
603 PINCTRL_PIN(210, "SATAXPCIE_2"),
604 PINCTRL_PIN(211, "CPU_GP_0"),
605 PINCTRL_PIN(212, "SATA_DEVSLP_0"),
606 PINCTRL_PIN(213, "SATA_DEVSLP_1"),
607 PINCTRL_PIN(214, "SATA_DEVSLP_2"),
608 PINCTRL_PIN(215, "CPU_GP_1"),
609 PINCTRL_PIN(216, "SATA_LEDB"),
610 PINCTRL_PIN(217, "USB2_OCB_0"),
611 PINCTRL_PIN(218, "USB2_OCB_1"),
612 PINCTRL_PIN(219, "USB2_OCB_2"),
613 PINCTRL_PIN(220, "USB2_OCB_3"),
614 PINCTRL_PIN(221, "SPI1_CSB"),
615 PINCTRL_PIN(222, "SPI1_CLK"),
616 PINCTRL_PIN(223, "SPI1_MISO_IO_1"),
617 PINCTRL_PIN(224, "SPI1_MOSI_IO_0"),
618 PINCTRL_PIN(225, "SPI1_IO_2"),
619 PINCTRL_PIN(226, "SPI1_IO_3"),
620 PINCTRL_PIN(227, "GPP_E_19"),
621 PINCTRL_PIN(228, "GPP_E_20"),
622 PINCTRL_PIN(229, "ISH_UART0_CTSB"),
623 PINCTRL_PIN(230, "SPI1_CLK_LOOPBK"),
624 /* GPP_K */
625 PINCTRL_PIN(231, "GSXDOUT"),
626 PINCTRL_PIN(232, "GSXSLOAD"),
627 PINCTRL_PIN(233, "GSXDIN"),
628 PINCTRL_PIN(234, "GSXSRESETB"),
629 PINCTRL_PIN(235, "GSXCLK"),
630 PINCTRL_PIN(236, "ADR_COMPLETE"),
631 PINCTRL_PIN(237, "GPP_K_6"),
632 PINCTRL_PIN(238, "GPP_K_7"),
633 PINCTRL_PIN(239, "CORE_VID_0"),
634 PINCTRL_PIN(240, "CORE_VID_1"),
635 PINCTRL_PIN(241, "GPP_K_10"),
636 PINCTRL_PIN(242, "GPP_K_11"),
637 PINCTRL_PIN(243, "SYS_PWROK"),
638 PINCTRL_PIN(244, "SYS_RESETB"),
639 PINCTRL_PIN(245, "MLK_RSTB"),
640 /* GPP_F */
641 PINCTRL_PIN(246, "SATAXPCIE_3"),
642 PINCTRL_PIN(247, "SATAXPCIE_4"),
643 PINCTRL_PIN(248, "SATAXPCIE_5"),
644 PINCTRL_PIN(249, "SATAXPCIE_6"),
645 PINCTRL_PIN(250, "SATAXPCIE_7"),
646 PINCTRL_PIN(251, "SATA_DEVSLP_3"),
647 PINCTRL_PIN(252, "SATA_DEVSLP_4"),
648 PINCTRL_PIN(253, "SATA_DEVSLP_5"),
649 PINCTRL_PIN(254, "SATA_DEVSLP_6"),
650 PINCTRL_PIN(255, "SATA_DEVSLP_7"),
651 PINCTRL_PIN(256, "SATA_SCLOCK"),
652 PINCTRL_PIN(257, "SATA_SLOAD"),
653 PINCTRL_PIN(258, "SATA_SDATAOUT1"),
654 PINCTRL_PIN(259, "SATA_SDATAOUT0"),
655 PINCTRL_PIN(260, "PS_ONB"),
656 PINCTRL_PIN(261, "M2_SKT2_CFG_0"),
657 PINCTRL_PIN(262, "M2_SKT2_CFG_1"),
658 PINCTRL_PIN(263, "M2_SKT2_CFG_2"),
659 PINCTRL_PIN(264, "M2_SKT2_CFG_3"),
660 PINCTRL_PIN(265, "L_VDDEN"),
661 PINCTRL_PIN(266, "L_BKLTEN"),
662 PINCTRL_PIN(267, "L_BKLTCTL"),
663 PINCTRL_PIN(268, "VNN_CTRL"),
664 PINCTRL_PIN(269, "GPP_F_23"),
665 /* GPP_D */
666 PINCTRL_PIN(270, "SRCCLKREQB_0"),
667 PINCTRL_PIN(271, "SRCCLKREQB_1"),
668 PINCTRL_PIN(272, "SRCCLKREQB_2"),
669 PINCTRL_PIN(273, "SRCCLKREQB_3"),
670 PINCTRL_PIN(274, "SML1CLK"),
671 PINCTRL_PIN(275, "I2S2_SFRM"),
672 PINCTRL_PIN(276, "I2S2_TXD"),
673 PINCTRL_PIN(277, "I2S2_RXD"),
674 PINCTRL_PIN(278, "I2S2_SCLK"),
675 PINCTRL_PIN(279, "SML0CLK"),
676 PINCTRL_PIN(280, "SML0DATA"),
677 PINCTRL_PIN(281, "SRCCLKREQB_4"),
678 PINCTRL_PIN(282, "SRCCLKREQB_5"),
679 PINCTRL_PIN(283, "SRCCLKREQB_6"),
680 PINCTRL_PIN(284, "SRCCLKREQB_7"),
681 PINCTRL_PIN(285, "SML1DATA"),
682 PINCTRL_PIN(286, "GSPI3_CS0B"),
683 PINCTRL_PIN(287, "GSPI3_CLK"),
684 PINCTRL_PIN(288, "GSPI3_MISO"),
685 PINCTRL_PIN(289, "GSPI3_MOSI"),
686 PINCTRL_PIN(290, "UART3_RXD"),
687 PINCTRL_PIN(291, "UART3_TXD"),
688 PINCTRL_PIN(292, "UART3_RTSB"),
689 PINCTRL_PIN(293, "UART3_CTSB"),
690 PINCTRL_PIN(294, "GSPI3_CLK_LOOPBK"),
691 /* JTAG */
692 PINCTRL_PIN(295, "JTAG_TDO"),
693 PINCTRL_PIN(296, "JTAGX"),
694 PINCTRL_PIN(297, "PRDYB"),
695 PINCTRL_PIN(298, "PREQB"),
696 PINCTRL_PIN(299, "JTAG_TDI"),
697 PINCTRL_PIN(300, "JTAG_TMS"),
698 PINCTRL_PIN(301, "JTAG_TCK"),
699 PINCTRL_PIN(302, "DBG_PMODE"),
700 PINCTRL_PIN(303, "CPU_TRSTB"),
701};
702
703static const struct intel_padgroup adls_community0_gpps[] = {
704 ADL_GPP(0, 0, 24, 0), /* GPP_I */
705 ADL_GPP(1, 25, 47, 32), /* GPP_R */
706 ADL_GPP(2, 48, 59, 64), /* GPP_J */
707 ADL_GPP(3, 60, 86, 96), /* vGPIO */
708 ADL_GPP(4, 87, 94, 128), /* vGPIO_0 */
709};
710
711static const struct intel_padgroup adls_community1_gpps[] = {
712 ADL_GPP(0, 95, 118, 160), /* GPP_B */
713 ADL_GPP(1, 119, 126, 192), /* GPP_G */
714 ADL_GPP(2, 127, 150, 224), /* GPP_H */
715};
716
717static const struct intel_padgroup adls_community3_gpps[] = {
718 ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */
719 ADL_GPP(1, 160, 175, 256), /* GPP_A */
720 ADL_GPP(2, 176, 199, 288), /* GPP_C */
721};
722
723static const struct intel_padgroup adls_community4_gpps[] = {
724 ADL_GPP(0, 200, 207, 320), /* GPP_S */
725 ADL_GPP(1, 208, 230, 352), /* GPP_E */
726 ADL_GPP(2, 231, 245, 384), /* GPP_K */
727 ADL_GPP(3, 246, 269, 416), /* GPP_F */
728};
729
730static const struct intel_padgroup adls_community5_gpps[] = {
731 ADL_GPP(0, 270, 294, 448), /* GPP_D */
732 ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */
733};
734
735static const struct intel_community adls_communities[] = {
0be0b70d
AS		 736 ADL_S_COMMUNITY(0, 0, 94, adls_community0_gpps),
737 ADL_S_COMMUNITY(1, 95, 150, adls_community1_gpps),
738 ADL_S_COMMUNITY(2, 151, 199, adls_community3_gpps),
739 ADL_S_COMMUNITY(3, 200, 269, adls_community4_gpps),
740 ADL_S_COMMUNITY(4, 270, 303, adls_community5_gpps),
e789e61f
AS		 741};
742
743static const struct intel_pinctrl_soc_data adls_soc_data = {
744 .pins = adls_pins,
745 .npins = ARRAY_SIZE(adls_pins),
746 .communities = adls_communities,
747 .ncommunities = ARRAY_SIZE(adls_communities),
748};
749
750static const struct acpi_device_id adl_pinctrl_acpi_match[] = {
751 { "INTC1056", (kernel_ulong_t)&adls_soc_data },
114b610b 752 { "INTC1057", (kernel_ulong_t)&adln_soc_data },
ddfdd130 753 { "INTC1085", (kernel_ulong_t)&adls_soc_data },
e789e61f
AS		 754 { }
755};
756MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match);
757
758static INTEL_PINCTRL_PM_OPS(adl_pinctrl_pm_ops);
759
760static struct platform_driver adl_pinctrl_driver = {
761 .probe = intel_pinctrl_probe_by_hid,
762 .driver = {
763 .name = "alderlake-pinctrl",
764 .acpi_match_table = adl_pinctrl_acpi_match,
765 .pm = &adl_pinctrl_pm_ops,
766 },
767};
768module_platform_driver(adl_pinctrl_driver);
769
770MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
771MODULE_DESCRIPTION("Intel Alder Lake PCH pinctrl/GPIO driver");
772MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)