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c2b39dec FE |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
3 | // Freescale imx6ul pinctrl driver | |
4 | // | |
5 | // Author: Anson Huang <Anson.Huang@freescale.com> | |
6 | // Copyright (C) 2015 Freescale Semiconductor, Inc. | |
9612327c FL |
7 | |
8 | #include <linux/err.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/io.h> | |
9612327c FL |
11 | #include <linux/of.h> |
12 | #include <linux/of_device.h> | |
13 | #include <linux/pinctrl/pinctrl.h> | |
14 | ||
15 | #include "pinctrl-imx.h" | |
16 | ||
17 | enum imx6ul_pads { | |
18 | MX6UL_PAD_RESERVE0 = 0, | |
19 | MX6UL_PAD_RESERVE1 = 1, | |
20 | MX6UL_PAD_RESERVE2 = 2, | |
21 | MX6UL_PAD_RESERVE3 = 3, | |
22 | MX6UL_PAD_RESERVE4 = 4, | |
23 | MX6UL_PAD_RESERVE5 = 5, | |
24 | MX6UL_PAD_RESERVE6 = 6, | |
25 | MX6UL_PAD_RESERVE7 = 7, | |
26 | MX6UL_PAD_RESERVE8 = 8, | |
27 | MX6UL_PAD_RESERVE9 = 9, | |
28 | MX6UL_PAD_RESERVE10 = 10, | |
29 | MX6UL_PAD_SNVS_TAMPER4 = 11, | |
30 | MX6UL_PAD_RESERVE12 = 12, | |
31 | MX6UL_PAD_RESERVE13 = 13, | |
32 | MX6UL_PAD_RESERVE14 = 14, | |
33 | MX6UL_PAD_RESERVE15 = 15, | |
34 | MX6UL_PAD_RESERVE16 = 16, | |
35 | MX6UL_PAD_JTAG_MOD = 17, | |
36 | MX6UL_PAD_JTAG_TMS = 18, | |
37 | MX6UL_PAD_JTAG_TDO = 19, | |
38 | MX6UL_PAD_JTAG_TDI = 20, | |
39 | MX6UL_PAD_JTAG_TCK = 21, | |
40 | MX6UL_PAD_JTAG_TRST_B = 22, | |
41 | MX6UL_PAD_GPIO1_IO00 = 23, | |
42 | MX6UL_PAD_GPIO1_IO01 = 24, | |
43 | MX6UL_PAD_GPIO1_IO02 = 25, | |
44 | MX6UL_PAD_GPIO1_IO03 = 26, | |
45 | MX6UL_PAD_GPIO1_IO04 = 27, | |
46 | MX6UL_PAD_GPIO1_IO05 = 28, | |
47 | MX6UL_PAD_GPIO1_IO06 = 29, | |
48 | MX6UL_PAD_GPIO1_IO07 = 30, | |
49 | MX6UL_PAD_GPIO1_IO08 = 31, | |
50 | MX6UL_PAD_GPIO1_IO09 = 32, | |
51 | MX6UL_PAD_UART1_TX_DATA = 33, | |
52 | MX6UL_PAD_UART1_RX_DATA = 34, | |
53 | MX6UL_PAD_UART1_CTS_B = 35, | |
54 | MX6UL_PAD_UART1_RTS_B = 36, | |
55 | MX6UL_PAD_UART2_TX_DATA = 37, | |
56 | MX6UL_PAD_UART2_RX_DATA = 38, | |
57 | MX6UL_PAD_UART2_CTS_B = 39, | |
58 | MX6UL_PAD_UART2_RTS_B = 40, | |
59 | MX6UL_PAD_UART3_TX_DATA = 41, | |
60 | MX6UL_PAD_UART3_RX_DATA = 42, | |
61 | MX6UL_PAD_UART3_CTS_B = 43, | |
62 | MX6UL_PAD_UART3_RTS_B = 44, | |
63 | MX6UL_PAD_UART4_TX_DATA = 45, | |
64 | MX6UL_PAD_UART4_RX_DATA = 46, | |
65 | MX6UL_PAD_UART5_TX_DATA = 47, | |
66 | MX6UL_PAD_UART5_RX_DATA = 48, | |
67 | MX6UL_PAD_ENET1_RX_DATA0 = 49, | |
68 | MX6UL_PAD_ENET1_RX_DATA1 = 50, | |
69 | MX6UL_PAD_ENET1_RX_EN = 51, | |
70 | MX6UL_PAD_ENET1_TX_DATA0 = 52, | |
71 | MX6UL_PAD_ENET1_TX_DATA1 = 53, | |
72 | MX6UL_PAD_ENET1_TX_EN = 54, | |
73 | MX6UL_PAD_ENET1_TX_CLK = 55, | |
74 | MX6UL_PAD_ENET1_RX_ER = 56, | |
75 | MX6UL_PAD_ENET2_RX_DATA0 = 57, | |
76 | MX6UL_PAD_ENET2_RX_DATA1 = 58, | |
77 | MX6UL_PAD_ENET2_RX_EN = 59, | |
78 | MX6UL_PAD_ENET2_TX_DATA0 = 60, | |
79 | MX6UL_PAD_ENET2_TX_DATA1 = 61, | |
80 | MX6UL_PAD_ENET2_TX_EN = 62, | |
81 | MX6UL_PAD_ENET2_TX_CLK = 63, | |
82 | MX6UL_PAD_ENET2_RX_ER = 64, | |
83 | MX6UL_PAD_LCD_CLK = 65, | |
84 | MX6UL_PAD_LCD_ENABLE = 66, | |
85 | MX6UL_PAD_LCD_HSYNC = 67, | |
86 | MX6UL_PAD_LCD_VSYNC = 68, | |
87 | MX6UL_PAD_LCD_RESET = 69, | |
88 | MX6UL_PAD_LCD_DATA00 = 70, | |
89 | MX6UL_PAD_LCD_DATA01 = 71, | |
90 | MX6UL_PAD_LCD_DATA02 = 72, | |
91 | MX6UL_PAD_LCD_DATA03 = 73, | |
92 | MX6UL_PAD_LCD_DATA04 = 74, | |
93 | MX6UL_PAD_LCD_DATA05 = 75, | |
94 | MX6UL_PAD_LCD_DATA06 = 76, | |
95 | MX6UL_PAD_LCD_DATA07 = 77, | |
96 | MX6UL_PAD_LCD_DATA08 = 78, | |
97 | MX6UL_PAD_LCD_DATA09 = 79, | |
98 | MX6UL_PAD_LCD_DATA10 = 80, | |
99 | MX6UL_PAD_LCD_DATA11 = 81, | |
100 | MX6UL_PAD_LCD_DATA12 = 82, | |
101 | MX6UL_PAD_LCD_DATA13 = 83, | |
102 | MX6UL_PAD_LCD_DATA14 = 84, | |
103 | MX6UL_PAD_LCD_DATA15 = 85, | |
104 | MX6UL_PAD_LCD_DATA16 = 86, | |
105 | MX6UL_PAD_LCD_DATA17 = 87, | |
106 | MX6UL_PAD_LCD_DATA18 = 88, | |
107 | MX6UL_PAD_LCD_DATA19 = 89, | |
108 | MX6UL_PAD_LCD_DATA20 = 90, | |
109 | MX6UL_PAD_LCD_DATA21 = 91, | |
110 | MX6UL_PAD_LCD_DATA22 = 92, | |
111 | MX6UL_PAD_LCD_DATA23 = 93, | |
112 | MX6UL_PAD_NAND_RE_B = 94, | |
113 | MX6UL_PAD_NAND_WE_B = 95, | |
114 | MX6UL_PAD_NAND_DATA00 = 96, | |
115 | MX6UL_PAD_NAND_DATA01 = 97, | |
116 | MX6UL_PAD_NAND_DATA02 = 98, | |
117 | MX6UL_PAD_NAND_DATA03 = 99, | |
118 | MX6UL_PAD_NAND_DATA04 = 100, | |
119 | MX6UL_PAD_NAND_DATA05 = 101, | |
120 | MX6UL_PAD_NAND_DATA06 = 102, | |
121 | MX6UL_PAD_NAND_DATA07 = 103, | |
122 | MX6UL_PAD_NAND_ALE = 104, | |
123 | MX6UL_PAD_NAND_WP_B = 105, | |
124 | MX6UL_PAD_NAND_READY_B = 106, | |
125 | MX6UL_PAD_NAND_CE0_B = 107, | |
126 | MX6UL_PAD_NAND_CE1_B = 108, | |
127 | MX6UL_PAD_NAND_CLE = 109, | |
128 | MX6UL_PAD_NAND_DQS = 110, | |
129 | MX6UL_PAD_SD1_CMD = 111, | |
130 | MX6UL_PAD_SD1_CLK = 112, | |
131 | MX6UL_PAD_SD1_DATA0 = 113, | |
132 | MX6UL_PAD_SD1_DATA1 = 114, | |
133 | MX6UL_PAD_SD1_DATA2 = 115, | |
134 | MX6UL_PAD_SD1_DATA3 = 116, | |
135 | MX6UL_PAD_CSI_MCLK = 117, | |
136 | MX6UL_PAD_CSI_PIXCLK = 118, | |
137 | MX6UL_PAD_CSI_VSYNC = 119, | |
138 | MX6UL_PAD_CSI_HSYNC = 120, | |
139 | MX6UL_PAD_CSI_DATA00 = 121, | |
140 | MX6UL_PAD_CSI_DATA01 = 122, | |
141 | MX6UL_PAD_CSI_DATA02 = 123, | |
142 | MX6UL_PAD_CSI_DATA03 = 124, | |
143 | MX6UL_PAD_CSI_DATA04 = 125, | |
144 | MX6UL_PAD_CSI_DATA05 = 126, | |
145 | MX6UL_PAD_CSI_DATA06 = 127, | |
146 | MX6UL_PAD_CSI_DATA07 = 128, | |
147 | }; | |
148 | ||
ba33f4f4 BP |
149 | enum imx6ull_lpsr_pads { |
150 | MX6ULL_PAD_BOOT_MODE0 = 0, | |
151 | MX6ULL_PAD_BOOT_MODE1 = 1, | |
152 | MX6ULL_PAD_SNVS_TAMPER0 = 2, | |
153 | MX6ULL_PAD_SNVS_TAMPER1 = 3, | |
154 | MX6ULL_PAD_SNVS_TAMPER2 = 4, | |
155 | MX6ULL_PAD_SNVS_TAMPER3 = 5, | |
156 | MX6ULL_PAD_SNVS_TAMPER4 = 6, | |
157 | MX6ULL_PAD_SNVS_TAMPER5 = 7, | |
158 | MX6ULL_PAD_SNVS_TAMPER6 = 8, | |
159 | MX6ULL_PAD_SNVS_TAMPER7 = 9, | |
160 | MX6ULL_PAD_SNVS_TAMPER8 = 10, | |
161 | MX6ULL_PAD_SNVS_TAMPER9 = 11, | |
162 | }; | |
163 | ||
9612327c FL |
164 | /* Pad names for the pinmux subsystem */ |
165 | static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = { | |
166 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0), | |
167 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1), | |
168 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2), | |
169 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3), | |
170 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4), | |
171 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5), | |
172 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6), | |
173 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7), | |
174 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8), | |
175 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9), | |
176 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10), | |
177 | IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4), | |
178 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12), | |
179 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13), | |
180 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14), | |
181 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15), | |
182 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE16), | |
183 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_MOD), | |
184 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TMS), | |
185 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDO), | |
186 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDI), | |
187 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TCK), | |
188 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TRST_B), | |
189 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO00), | |
190 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO01), | |
191 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO02), | |
192 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO03), | |
193 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO04), | |
194 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO05), | |
195 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO06), | |
196 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO07), | |
197 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO08), | |
198 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO09), | |
199 | IMX_PINCTRL_PIN(MX6UL_PAD_UART1_TX_DATA), | |
200 | IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RX_DATA), | |
201 | IMX_PINCTRL_PIN(MX6UL_PAD_UART1_CTS_B), | |
202 | IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RTS_B), | |
203 | IMX_PINCTRL_PIN(MX6UL_PAD_UART2_TX_DATA), | |
204 | IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RX_DATA), | |
205 | IMX_PINCTRL_PIN(MX6UL_PAD_UART2_CTS_B), | |
206 | IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RTS_B), | |
207 | IMX_PINCTRL_PIN(MX6UL_PAD_UART3_TX_DATA), | |
208 | IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RX_DATA), | |
209 | IMX_PINCTRL_PIN(MX6UL_PAD_UART3_CTS_B), | |
210 | IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RTS_B), | |
211 | IMX_PINCTRL_PIN(MX6UL_PAD_UART4_TX_DATA), | |
212 | IMX_PINCTRL_PIN(MX6UL_PAD_UART4_RX_DATA), | |
213 | IMX_PINCTRL_PIN(MX6UL_PAD_UART5_TX_DATA), | |
214 | IMX_PINCTRL_PIN(MX6UL_PAD_UART5_RX_DATA), | |
215 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA0), | |
216 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA1), | |
217 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_EN), | |
218 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA0), | |
219 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA1), | |
220 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_EN), | |
221 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_CLK), | |
222 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_ER), | |
223 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA0), | |
224 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA1), | |
225 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_EN), | |
226 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA0), | |
227 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA1), | |
228 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_EN), | |
229 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_CLK), | |
230 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_ER), | |
231 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_CLK), | |
232 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_ENABLE), | |
233 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_HSYNC), | |
234 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_VSYNC), | |
235 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_RESET), | |
236 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA00), | |
237 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA01), | |
238 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA02), | |
239 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA03), | |
240 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA04), | |
241 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA05), | |
242 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA06), | |
243 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA07), | |
244 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA08), | |
245 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA09), | |
246 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA10), | |
247 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA11), | |
248 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA12), | |
249 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA13), | |
250 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA14), | |
251 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA15), | |
252 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA16), | |
253 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA17), | |
254 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA18), | |
255 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA19), | |
256 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA20), | |
257 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA21), | |
258 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA22), | |
259 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA23), | |
260 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_RE_B), | |
261 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WE_B), | |
262 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA00), | |
263 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA01), | |
264 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA02), | |
265 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA03), | |
266 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA04), | |
267 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA05), | |
268 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA06), | |
269 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA07), | |
270 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_ALE), | |
271 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WP_B), | |
272 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_READY_B), | |
273 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE0_B), | |
274 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE1_B), | |
275 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CLE), | |
276 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DQS), | |
277 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CMD), | |
278 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CLK), | |
279 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA0), | |
280 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA1), | |
281 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA2), | |
282 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA3), | |
283 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_MCLK), | |
284 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_PIXCLK), | |
285 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_VSYNC), | |
286 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_HSYNC), | |
287 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA00), | |
288 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA01), | |
289 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA02), | |
290 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA03), | |
291 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA04), | |
292 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA05), | |
293 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA06), | |
294 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07), | |
295 | }; | |
296 | ||
ba33f4f4 BP |
297 | /* pad for i.MX6ULL lpsr pinmux */ |
298 | static const struct pinctrl_pin_desc imx6ull_snvs_pinctrl_pads[] = { | |
299 | IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE0), | |
300 | IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE1), | |
301 | IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER0), | |
302 | IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER1), | |
303 | IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER2), | |
304 | IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER3), | |
305 | IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER4), | |
306 | IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER5), | |
307 | IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER6), | |
308 | IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER7), | |
309 | IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER8), | |
310 | IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER9), | |
311 | }; | |
312 | ||
313 | static const struct imx_pinctrl_soc_info imx6ul_pinctrl_info = { | |
9612327c FL |
314 | .pins = imx6ul_pinctrl_pads, |
315 | .npins = ARRAY_SIZE(imx6ul_pinctrl_pads), | |
8626ada8 | 316 | .gpr_compatible = "fsl,imx6ul-iomuxc-gpr", |
9612327c FL |
317 | }; |
318 | ||
ba33f4f4 BP |
319 | static const struct imx_pinctrl_soc_info imx6ull_snvs_pinctrl_info = { |
320 | .pins = imx6ull_snvs_pinctrl_pads, | |
321 | .npins = ARRAY_SIZE(imx6ull_snvs_pinctrl_pads), | |
322 | .flags = ZERO_OFFSET_VALID, | |
323 | }; | |
324 | ||
325 | static const struct of_device_id imx6ul_pinctrl_of_match[] = { | |
326 | { .compatible = "fsl,imx6ul-iomuxc", .data = &imx6ul_pinctrl_info, }, | |
327 | { .compatible = "fsl,imx6ull-iomuxc-snvs", .data = &imx6ull_snvs_pinctrl_info, }, | |
9612327c FL |
328 | { /* sentinel */ } |
329 | }; | |
330 | ||
331 | static int imx6ul_pinctrl_probe(struct platform_device *pdev) | |
332 | { | |
ba33f4f4 BP |
333 | const struct imx_pinctrl_soc_info *pinctrl_info; |
334 | ||
335 | pinctrl_info = of_device_get_match_data(&pdev->dev); | |
336 | if (!pinctrl_info) | |
337 | return -ENODEV; | |
338 | ||
339 | return imx_pinctrl_probe(pdev, pinctrl_info); | |
9612327c FL |
340 | } |
341 | ||
342 | static struct platform_driver imx6ul_pinctrl_driver = { | |
343 | .driver = { | |
344 | .name = "imx6ul-pinctrl", | |
9612327c FL |
345 | .of_match_table = of_match_ptr(imx6ul_pinctrl_of_match), |
346 | }, | |
347 | .probe = imx6ul_pinctrl_probe, | |
9612327c FL |
348 | }; |
349 | ||
350 | static int __init imx6ul_pinctrl_init(void) | |
351 | { | |
352 | return platform_driver_register(&imx6ul_pinctrl_driver); | |
353 | } | |
354 | arch_initcall(imx6ul_pinctrl_init); |