Commit | Line | Data |
---|---|---|
c2b39dec FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // Core driver for the imx pin controller | |
4 | // | |
5 | // Copyright (C) 2012 Freescale Semiconductor, Inc. | |
6 | // Copyright (C) 2012 Linaro Ltd. | |
7 | // | |
8 | // Author: Dong Aisheng <dong.aisheng@linaro.org> | |
ae75ff81 DA |
9 | |
10 | #include <linux/err.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/io.h> | |
8626ada8 | 13 | #include <linux/mfd/syscon.h> |
7233f7cf | 14 | #include <linux/module.h> |
ae75ff81 | 15 | #include <linux/of.h> |
26d8cde5 | 16 | #include <linux/of_address.h> |
060f03e9 | 17 | #include <linux/platform_device.h> |
6e8bc379 AS |
18 | #include <linux/regmap.h> |
19 | #include <linux/seq_file.h> | |
20 | #include <linux/slab.h> | |
21 | ||
ae75ff81 DA |
22 | #include <linux/pinctrl/machine.h> |
23 | #include <linux/pinctrl/pinconf.h> | |
24 | #include <linux/pinctrl/pinctrl.h> | |
25 | #include <linux/pinctrl/pinmux.h> | |
ae75ff81 | 26 | |
edad3b2a | 27 | #include "../core.h" |
a5cadbbb | 28 | #include "../pinconf.h" |
3fd6d6ad | 29 | #include "../pinmux.h" |
ae75ff81 DA |
30 | #include "pinctrl-imx.h" |
31 | ||
ae75ff81 DA |
32 | /* The bits in CONFIG cell defined in binding doc*/ |
33 | #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ | |
34 | #define IMX_PAD_SION 0x40000000 /* set SION */ | |
35 | ||
e566fc11 GB |
36 | static inline const struct group_desc *imx_pinctrl_find_group_by_name( |
37 | struct pinctrl_dev *pctldev, | |
ae75ff81 DA |
38 | const char *name) |
39 | { | |
e566fc11 | 40 | const struct group_desc *grp = NULL; |
ae75ff81 DA |
41 | int i; |
42 | ||
e566fc11 GB |
43 | for (i = 0; i < pctldev->num_groups; i++) { |
44 | grp = pinctrl_generic_get_group(pctldev, i); | |
390270f2 | 45 | if (grp && !strcmp(grp->grp.name, name)) |
ae75ff81 | 46 | break; |
ae75ff81 DA |
47 | } |
48 | ||
49 | return grp; | |
50 | } | |
51 | ||
ae75ff81 DA |
52 | static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
53 | unsigned offset) | |
54 | { | |
55 | seq_printf(s, "%s", dev_name(pctldev->dev)); | |
56 | } | |
57 | ||
58 | static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, | |
59 | struct device_node *np, | |
60 | struct pinctrl_map **map, unsigned *num_maps) | |
61 | { | |
62 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
b96eea71 | 63 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
e566fc11 | 64 | const struct group_desc *grp; |
ae75ff81 DA |
65 | struct pinctrl_map *new_map; |
66 | struct device_node *parent; | |
b96eea71 | 67 | struct imx_pin *pin; |
ae75ff81 | 68 | int map_num = 1; |
18071610 | 69 | int i, j; |
ae75ff81 DA |
70 | |
71 | /* | |
72 | * first find the group of this node and check if we need create | |
73 | * config maps for pins | |
74 | */ | |
e566fc11 | 75 | grp = imx_pinctrl_find_group_by_name(pctldev, np->name); |
ae75ff81 | 76 | if (!grp) { |
94f4e54c | 77 | dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np); |
ae75ff81 DA |
78 | return -EINVAL; |
79 | } | |
80 | ||
b96eea71 | 81 | if (info->flags & IMX_USE_SCU) { |
390270f2 | 82 | map_num += grp->grp.npins; |
b96eea71 | 83 | } else { |
390270f2 | 84 | for (i = 0; i < grp->grp.npins; i++) { |
b96eea71 D |
85 | pin = &((struct imx_pin *)(grp->data))[i]; |
86 | if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) | |
87 | map_num++; | |
88 | } | |
ae75ff81 DA |
89 | } |
90 | ||
6da2ec56 KC |
91 | new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map), |
92 | GFP_KERNEL); | |
ae75ff81 DA |
93 | if (!new_map) |
94 | return -ENOMEM; | |
95 | ||
96 | *map = new_map; | |
97 | *num_maps = map_num; | |
98 | ||
99 | /* create mux map */ | |
100 | parent = of_get_parent(np); | |
c71157c5 DN |
101 | if (!parent) { |
102 | kfree(new_map); | |
ae75ff81 | 103 | return -EINVAL; |
c71157c5 | 104 | } |
ae75ff81 DA |
105 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; |
106 | new_map[0].data.mux.function = parent->name; | |
107 | new_map[0].data.mux.group = np->name; | |
108 | of_node_put(parent); | |
109 | ||
110 | /* create config map */ | |
111 | new_map++; | |
390270f2 | 112 | for (i = j = 0; i < grp->grp.npins; i++) { |
b96eea71 | 113 | pin = &((struct imx_pin *)(grp->data))[i]; |
57161067 D |
114 | |
115 | /* | |
116 | * We only create config maps for SCU pads or MMIO pads that | |
117 | * are not using the default config(a.k.a IMX_NO_PAD_CTL) | |
118 | */ | |
119 | if (!(info->flags & IMX_USE_SCU) && | |
120 | (pin->conf.mmio.config & IMX_NO_PAD_CTL)) | |
121 | continue; | |
122 | ||
b96eea71 D |
123 | new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; |
124 | new_map[j].data.configs.group_or_pin = | |
e566fc11 | 125 | pin_get_name(pctldev, pin->pin); |
b96eea71 D |
126 | |
127 | if (info->flags & IMX_USE_SCU) { | |
128 | /* | |
129 | * For SCU case, we set mux and conf together | |
130 | * in one IPC call | |
131 | */ | |
132 | new_map[j].data.configs.configs = | |
133 | (unsigned long *)&pin->conf.scu; | |
134 | new_map[j].data.configs.num_configs = 2; | |
57161067 | 135 | } else { |
b96eea71 D |
136 | new_map[j].data.configs.configs = |
137 | &pin->conf.mmio.config; | |
18071610 | 138 | new_map[j].data.configs.num_configs = 1; |
ae75ff81 | 139 | } |
b96eea71 D |
140 | |
141 | j++; | |
ae75ff81 DA |
142 | } |
143 | ||
144 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
67695f2e | 145 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); |
ae75ff81 DA |
146 | |
147 | return 0; | |
148 | } | |
149 | ||
150 | static void imx_dt_free_map(struct pinctrl_dev *pctldev, | |
151 | struct pinctrl_map *map, unsigned num_maps) | |
152 | { | |
3a86a5f8 | 153 | kfree(map); |
ae75ff81 DA |
154 | } |
155 | ||
022ab148 | 156 | static const struct pinctrl_ops imx_pctrl_ops = { |
e566fc11 GB |
157 | .get_groups_count = pinctrl_generic_get_group_count, |
158 | .get_group_name = pinctrl_generic_get_group_name, | |
159 | .get_group_pins = pinctrl_generic_get_group_pins, | |
ae75ff81 DA |
160 | .pin_dbg_show = imx_pin_dbg_show, |
161 | .dt_node_to_map = imx_dt_node_to_map, | |
162 | .dt_free_map = imx_dt_free_map, | |
ae75ff81 DA |
163 | }; |
164 | ||
b96eea71 D |
165 | static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl, |
166 | struct imx_pin *pin) | |
167 | { | |
168 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
169 | struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; | |
170 | const struct imx_pin_reg *pin_reg; | |
171 | unsigned int pin_id; | |
172 | ||
173 | pin_id = pin->pin; | |
174 | pin_reg = &ipctl->pin_regs[pin_id]; | |
175 | ||
176 | if (pin_reg->mux_reg == -1) { | |
177 | dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", | |
178 | info->pins[pin_id].name); | |
179 | return 0; | |
180 | } | |
181 | ||
182 | if (info->flags & SHARE_MUX_CONF_REG) { | |
183 | u32 reg; | |
184 | ||
185 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
186 | reg &= ~info->mux_mask; | |
187 | reg |= (pin_mmio->mux_mode << info->mux_shift); | |
188 | writel(reg, ipctl->base + pin_reg->mux_reg); | |
189 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", | |
190 | pin_reg->mux_reg, reg); | |
191 | } else { | |
192 | writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); | |
193 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", | |
194 | pin_reg->mux_reg, pin_mmio->mux_mode); | |
195 | } | |
196 | ||
197 | /* | |
198 | * If the select input value begins with 0xff, it's a quirky | |
199 | * select input and the value should be interpreted as below. | |
200 | * 31 23 15 7 0 | |
201 | * | 0xff | shift | width | select | | |
202 | * It's used to work around the problem that the select | |
203 | * input for some pin is not implemented in the select | |
204 | * input register but in some general purpose register. | |
205 | * We encode the select input value, width and shift of | |
206 | * the bit field into input_val cell of pin function ID | |
207 | * in device tree, and then decode them here for setting | |
208 | * up the select input bits in general purpose register. | |
209 | */ | |
210 | if (pin_mmio->input_val >> 24 == 0xff) { | |
211 | u32 val = pin_mmio->input_val; | |
212 | u8 select = val & 0xff; | |
213 | u8 width = (val >> 8) & 0xff; | |
214 | u8 shift = (val >> 16) & 0xff; | |
215 | u32 mask = ((1 << width) - 1) << shift; | |
216 | /* | |
217 | * The input_reg[i] here is actually some IOMUXC general | |
218 | * purpose register, not regular select input register. | |
219 | */ | |
220 | val = readl(ipctl->base + pin_mmio->input_reg); | |
221 | val &= ~mask; | |
222 | val |= select << shift; | |
223 | writel(val, ipctl->base + pin_mmio->input_reg); | |
224 | } else if (pin_mmio->input_reg) { | |
225 | /* | |
226 | * Regular select input register can never be at offset | |
227 | * 0, and we only print register value for regular case. | |
228 | */ | |
229 | if (ipctl->input_sel_base) | |
230 | writel(pin_mmio->input_val, ipctl->input_sel_base + | |
231 | pin_mmio->input_reg); | |
232 | else | |
233 | writel(pin_mmio->input_val, ipctl->base + | |
234 | pin_mmio->input_reg); | |
235 | dev_dbg(ipctl->dev, | |
236 | "==>select_input: offset 0x%x val 0x%x\n", | |
237 | pin_mmio->input_reg, pin_mmio->input_val); | |
238 | } | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
03e9f0ca LW |
243 | static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, |
244 | unsigned group) | |
ae75ff81 DA |
245 | { |
246 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
f5843492 | 247 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
b96eea71 D |
248 | struct function_desc *func; |
249 | struct group_desc *grp; | |
250 | struct imx_pin *pin; | |
251 | unsigned int npins; | |
252 | int i, err; | |
ae75ff81 DA |
253 | |
254 | /* | |
255 | * Configure the mux mode for each pin in the group for a specific | |
256 | * function. | |
257 | */ | |
e566fc11 | 258 | grp = pinctrl_generic_get_group(pctldev, group); |
a51c158b GB |
259 | if (!grp) |
260 | return -EINVAL; | |
261 | ||
3fd6d6ad | 262 | func = pinmux_generic_get_function(pctldev, selector); |
a51c158b GB |
263 | if (!func) |
264 | return -EINVAL; | |
265 | ||
390270f2 | 266 | npins = grp->grp.npins; |
ae75ff81 DA |
267 | |
268 | dev_dbg(ipctl->dev, "enable function %s group %s\n", | |
f3e0473a | 269 | func->func.name, grp->grp.name); |
ae75ff81 DA |
270 | |
271 | for (i = 0; i < npins; i++) { | |
94176faf | 272 | /* |
b96eea71 D |
273 | * For IMX_USE_SCU case, we postpone the mux setting |
274 | * until config is set as we can set them together | |
275 | * in one IPC call | |
94176faf | 276 | */ |
b96eea71 D |
277 | pin = &((struct imx_pin *)(grp->data))[i]; |
278 | if (!(info->flags & IMX_USE_SCU)) { | |
279 | err = imx_pmx_set_one_pin_mmio(ipctl, pin); | |
280 | if (err) | |
281 | return err; | |
ae75ff81 DA |
282 | } |
283 | } | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
3be6f651 | 288 | struct pinmux_ops imx_pmx_ops = { |
3fd6d6ad GB |
289 | .get_functions_count = pinmux_generic_get_function_count, |
290 | .get_function_name = pinmux_generic_get_function_name, | |
291 | .get_function_groups = pinmux_generic_get_function_groups, | |
03e9f0ca | 292 | .set_mux = imx_pmx_set, |
ae75ff81 DA |
293 | }; |
294 | ||
b96eea71 D |
295 | static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id, |
296 | unsigned long *config) | |
ae75ff81 DA |
297 | { |
298 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
f5843492 SA |
299 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
300 | const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; | |
ae75ff81 | 301 | |
3dac1918 | 302 | if (pin_reg->conf_reg == -1) { |
f5843492 | 303 | dev_err(ipctl->dev, "Pin(%s) does not support config function\n", |
ae75ff81 DA |
304 | info->pins[pin_id].name); |
305 | return -EINVAL; | |
306 | } | |
307 | ||
308 | *config = readl(ipctl->base + pin_reg->conf_reg); | |
309 | ||
bf5a5309 | 310 | if (info->flags & SHARE_MUX_CONF_REG) |
5586ee41 | 311 | *config &= ~info->mux_mask; |
bf5a5309 | 312 | |
ae75ff81 DA |
313 | return 0; |
314 | } | |
315 | ||
b96eea71 D |
316 | static int imx_pinconf_get(struct pinctrl_dev *pctldev, |
317 | unsigned pin_id, unsigned long *config) | |
318 | { | |
319 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
320 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
321 | ||
322 | if (info->flags & IMX_USE_SCU) | |
07ae3f07 | 323 | return info->imx_pinconf_get(pctldev, pin_id, config); |
b96eea71 D |
324 | else |
325 | return imx_pinconf_get_mmio(pctldev, pin_id, config); | |
326 | } | |
327 | ||
328 | static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, | |
329 | unsigned pin_id, unsigned long *configs, | |
330 | unsigned num_configs) | |
ae75ff81 DA |
331 | { |
332 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
f5843492 SA |
333 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
334 | const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; | |
03b054e9 | 335 | int i; |
ae75ff81 | 336 | |
3dac1918 | 337 | if (pin_reg->conf_reg == -1) { |
f5843492 | 338 | dev_err(ipctl->dev, "Pin(%s) does not support config function\n", |
ae75ff81 DA |
339 | info->pins[pin_id].name); |
340 | return -EINVAL; | |
341 | } | |
342 | ||
343 | dev_dbg(ipctl->dev, "pinconf set pin %s\n", | |
344 | info->pins[pin_id].name); | |
345 | ||
03b054e9 SY |
346 | for (i = 0; i < num_configs; i++) { |
347 | if (info->flags & SHARE_MUX_CONF_REG) { | |
348 | u32 reg; | |
349 | reg = readl(ipctl->base + pin_reg->conf_reg); | |
5586ee41 | 350 | reg &= info->mux_mask; |
03b054e9 SY |
351 | reg |= configs[i]; |
352 | writel(reg, ipctl->base + pin_reg->conf_reg); | |
66b54e3a DA |
353 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", |
354 | pin_reg->conf_reg, reg); | |
03b054e9 SY |
355 | } else { |
356 | writel(configs[i], ipctl->base + pin_reg->conf_reg); | |
66b54e3a DA |
357 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", |
358 | pin_reg->conf_reg, configs[i]); | |
03b054e9 | 359 | } |
03b054e9 | 360 | } /* for each config */ |
ae75ff81 DA |
361 | |
362 | return 0; | |
363 | } | |
364 | ||
b96eea71 D |
365 | static int imx_pinconf_set(struct pinctrl_dev *pctldev, |
366 | unsigned pin_id, unsigned long *configs, | |
367 | unsigned num_configs) | |
368 | { | |
369 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
370 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
371 | ||
372 | if (info->flags & IMX_USE_SCU) | |
07ae3f07 | 373 | return info->imx_pinconf_set(pctldev, pin_id, |
b96eea71 D |
374 | configs, num_configs); |
375 | else | |
376 | return imx_pinconf_set_mmio(pctldev, pin_id, | |
377 | configs, num_configs); | |
378 | } | |
379 | ||
ae75ff81 DA |
380 | static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, |
381 | struct seq_file *s, unsigned pin_id) | |
382 | { | |
383 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
b96eea71 D |
384 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
385 | const struct imx_pin_reg *pin_reg; | |
ae75ff81 | 386 | unsigned long config; |
b96eea71 | 387 | int ret; |
ae75ff81 | 388 | |
b96eea71 | 389 | if (info->flags & IMX_USE_SCU) { |
07ae3f07 | 390 | ret = info->imx_pinconf_get(pctldev, pin_id, &config); |
b96eea71 D |
391 | if (ret) { |
392 | dev_err(ipctl->dev, "failed to get %s pinconf\n", | |
393 | pin_get_name(pctldev, pin_id)); | |
394 | seq_puts(s, "N/A"); | |
395 | return; | |
396 | } | |
397 | } else { | |
398 | pin_reg = &ipctl->pin_regs[pin_id]; | |
c7df94c6 | 399 | if (pin_reg->conf_reg == -1) { |
b96eea71 D |
400 | seq_puts(s, "N/A"); |
401 | return; | |
402 | } | |
403 | ||
404 | config = readl(ipctl->base + pin_reg->conf_reg); | |
ae75ff81 DA |
405 | } |
406 | ||
ae75ff81 DA |
407 | seq_printf(s, "0x%lx", config); |
408 | } | |
409 | ||
410 | static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
411 | struct seq_file *s, unsigned group) | |
412 | { | |
e566fc11 | 413 | struct group_desc *grp; |
ae75ff81 DA |
414 | unsigned long config; |
415 | const char *name; | |
416 | int i, ret; | |
417 | ||
b4859f3e | 418 | if (group >= pctldev->num_groups) |
ae75ff81 DA |
419 | return; |
420 | ||
7d6989ad | 421 | seq_puts(s, "\n"); |
e566fc11 | 422 | grp = pinctrl_generic_get_group(pctldev, group); |
a51c158b GB |
423 | if (!grp) |
424 | return; | |
425 | ||
390270f2 | 426 | for (i = 0; i < grp->grp.npins; i++) { |
e566fc11 GB |
427 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; |
428 | ||
8f903f8a SH |
429 | name = pin_get_name(pctldev, pin->pin); |
430 | ret = imx_pinconf_get(pctldev, pin->pin, &config); | |
ae75ff81 DA |
431 | if (ret) |
432 | return; | |
a2d16a21 | 433 | seq_printf(s, " %s: 0x%lx\n", name, config); |
ae75ff81 DA |
434 | } |
435 | } | |
436 | ||
022ab148 | 437 | static const struct pinconf_ops imx_pinconf_ops = { |
ae75ff81 DA |
438 | .pin_config_get = imx_pinconf_get, |
439 | .pin_config_set = imx_pinconf_set, | |
440 | .pin_config_dbg_show = imx_pinconf_dbg_show, | |
441 | .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, | |
442 | }; | |
443 | ||
e1641531 | 444 | /* |
37c1628f DA |
445 | * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID |
446 | * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin. | |
37c1628f DA |
447 | * |
448 | * PIN_FUNC_ID format: | |
449 | * Default: | |
450 | * <mux_reg conf_reg input_reg mux_mode input_val> | |
451 | * SHARE_MUX_CONF_REG: | |
452 | * <mux_conf_reg input_reg mux_mode input_val> | |
b96eea71 D |
453 | * IMX_USE_SCU: |
454 | * <pin_id mux_mode> | |
e1641531 SG |
455 | */ |
456 | #define FSL_PIN_SIZE 24 | |
37c1628f | 457 | #define FSL_PIN_SHARE_SIZE 20 |
b96eea71 D |
458 | #define FSL_SCU_PIN_SIZE 12 |
459 | ||
460 | static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl, | |
461 | unsigned int *pin_id, struct imx_pin *pin, | |
462 | const __be32 **list_p, | |
463 | struct device_node *np) | |
464 | { | |
465 | const struct imx_pinctrl_soc_info *info = ipctl->info; | |
466 | struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; | |
467 | struct imx_pin_reg *pin_reg; | |
468 | const __be32 *list = *list_p; | |
469 | u32 mux_reg, conf_reg; | |
470 | u32 config; | |
471 | ||
472 | mux_reg = be32_to_cpu(*list++); | |
473 | ||
474 | if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) | |
475 | mux_reg = -1; | |
476 | ||
477 | if (info->flags & SHARE_MUX_CONF_REG) { | |
478 | conf_reg = mux_reg; | |
479 | } else { | |
480 | conf_reg = be32_to_cpu(*list++); | |
481 | if (!conf_reg) | |
482 | conf_reg = -1; | |
483 | } | |
484 | ||
485 | *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; | |
486 | pin_reg = &ipctl->pin_regs[*pin_id]; | |
487 | pin->pin = *pin_id; | |
488 | pin_reg->mux_reg = mux_reg; | |
489 | pin_reg->conf_reg = conf_reg; | |
490 | pin_mmio->input_reg = be32_to_cpu(*list++); | |
491 | pin_mmio->mux_mode = be32_to_cpu(*list++); | |
492 | pin_mmio->input_val = be32_to_cpu(*list++); | |
493 | ||
6cf103bc | 494 | config = be32_to_cpu(*list++); |
b96eea71 | 495 | |
6cf103bc RV |
496 | /* SION bit is in mux register */ |
497 | if (config & IMX_PAD_SION) | |
498 | pin_mmio->mux_mode |= IOMUXC_CONFIG_SION; | |
499 | pin_mmio->config = config & ~IMX_PAD_SION; | |
b96eea71 | 500 | |
57161067 D |
501 | *list_p = list; |
502 | ||
b96eea71 D |
503 | dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name, |
504 | pin_mmio->mux_mode, pin_mmio->config); | |
505 | } | |
ae75ff81 | 506 | |
150632b0 | 507 | static int imx_pinctrl_parse_groups(struct device_node *np, |
e566fc11 | 508 | struct group_desc *grp, |
a5cadbbb | 509 | struct imx_pinctrl *ipctl, |
150632b0 | 510 | u32 index) |
ae75ff81 | 511 | { |
f5843492 | 512 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
b96eea71 | 513 | struct imx_pin *pin; |
26ea8229 | 514 | unsigned int *pins; |
bf5a5309 | 515 | int size, pin_size; |
a695145b | 516 | const __be32 *list; |
e1641531 | 517 | int i; |
ae75ff81 | 518 | |
94f4e54c | 519 | dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np); |
ae75ff81 | 520 | |
b96eea71 D |
521 | if (info->flags & IMX_USE_SCU) |
522 | pin_size = FSL_SCU_PIN_SIZE; | |
523 | else if (info->flags & SHARE_MUX_CONF_REG) | |
37c1628f | 524 | pin_size = FSL_PIN_SHARE_SIZE; |
bf5a5309 JL |
525 | else |
526 | pin_size = FSL_PIN_SIZE; | |
a5cadbbb | 527 | |
ae75ff81 | 528 | /* Initialise group */ |
390270f2 | 529 | grp->grp.name = np->name; |
ae75ff81 DA |
530 | |
531 | /* | |
532 | * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, | |
533 | * do sanity check and calculate pins number | |
a5cadbbb DA |
534 | * |
535 | * First try legacy 'fsl,pins' property, then fall back to the | |
fc4f351a | 536 | * generic 'pinmux'. |
a5cadbbb | 537 | * |
fc4f351a | 538 | * Note: for generic 'pinmux' case, there's no CONFIG part in |
a5cadbbb | 539 | * the binding format. |
ae75ff81 DA |
540 | */ |
541 | list = of_get_property(np, "fsl,pins", &size); | |
1bf1fea9 | 542 | if (!list) { |
fc4f351a | 543 | list = of_get_property(np, "pinmux", &size); |
a5cadbbb | 544 | if (!list) { |
f5843492 | 545 | dev_err(ipctl->dev, |
f5292d06 | 546 | "no fsl,pins and pins property in node %pOF\n", np); |
a5cadbbb DA |
547 | return -EINVAL; |
548 | } | |
1bf1fea9 SH |
549 | } |
550 | ||
ae75ff81 | 551 | /* we do not check return since it's safe node passed down */ |
bf5a5309 | 552 | if (!size || size % pin_size) { |
f5843492 | 553 | dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np); |
ae75ff81 DA |
554 | return -EINVAL; |
555 | } | |
556 | ||
390270f2 AS |
557 | grp->grp.npins = size / pin_size; |
558 | grp->data = devm_kcalloc(ipctl->dev, grp->grp.npins, sizeof(*pin), GFP_KERNEL); | |
26ea8229 AS |
559 | if (!grp->data) |
560 | return -ENOMEM; | |
561 | ||
390270f2 | 562 | pins = devm_kcalloc(ipctl->dev, grp->grp.npins, sizeof(*pins), GFP_KERNEL); |
26ea8229 | 563 | if (!pins) |
8f903f8a | 564 | return -ENOMEM; |
390270f2 | 565 | grp->grp.pins = pins; |
8f903f8a | 566 | |
390270f2 | 567 | for (i = 0; i < grp->grp.npins; i++) { |
b96eea71 D |
568 | pin = &((struct imx_pin *)(grp->data))[i]; |
569 | if (info->flags & IMX_USE_SCU) | |
26ea8229 | 570 | info->imx_pinctrl_parse_pin(ipctl, &pins[i], pin, &list); |
b96eea71 | 571 | else |
26ea8229 | 572 | imx_pinctrl_parse_pin_mmio(ipctl, &pins[i], pin, &list, np); |
40604469 | 573 | } |
3a86a5f8 | 574 | |
ae75ff81 DA |
575 | return 0; |
576 | } | |
577 | ||
150632b0 | 578 | static int imx_pinctrl_parse_functions(struct device_node *np, |
e566fc11 | 579 | struct imx_pinctrl *ipctl, |
150632b0 | 580 | u32 index) |
ae75ff81 | 581 | { |
e566fc11 | 582 | struct pinctrl_dev *pctl = ipctl->pctl; |
3fd6d6ad | 583 | struct function_desc *func; |
e566fc11 | 584 | struct group_desc *grp; |
02f11713 | 585 | const char **group_names; |
74429366 | 586 | u32 i; |
ae75ff81 | 587 | |
94f4e54c | 588 | dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np); |
ae75ff81 | 589 | |
3fd6d6ad | 590 | func = pinmux_generic_get_function(pctl, index); |
a51c158b GB |
591 | if (!func) |
592 | return -EINVAL; | |
ae75ff81 DA |
593 | |
594 | /* Initialise function */ | |
f3e0473a AS |
595 | func->func.name = np->name; |
596 | func->func.ngroups = of_get_child_count(np); | |
597 | if (func->func.ngroups == 0) { | |
f5141ae4 | 598 | dev_info(ipctl->dev, "no groups defined in %pOF\n", np); |
ae75ff81 DA |
599 | return -EINVAL; |
600 | } | |
02f11713 | 601 | |
f3e0473a AS |
602 | group_names = devm_kcalloc(ipctl->dev, func->func.ngroups, |
603 | sizeof(*func->func.groups), GFP_KERNEL); | |
aa63e656 | 604 | if (!group_names) |
49af64e6 | 605 | return -ENOMEM; |
74429366 | 606 | i = 0; |
cb3cb99a | 607 | for_each_child_of_node_scoped(np, child) |
74429366 | 608 | group_names[i++] = child->name; |
f3e0473a | 609 | func->func.groups = group_names; |
ae75ff81 | 610 | |
74429366 | 611 | i = 0; |
cb3cb99a | 612 | for_each_child_of_node_scoped(np, child) { |
390270f2 | 613 | grp = devm_kzalloc(ipctl->dev, sizeof(*grp), GFP_KERNEL); |
cb3cb99a | 614 | if (!grp) |
a51c158b GB |
615 | return -ENOMEM; |
616 | ||
f5843492 | 617 | mutex_lock(&ipctl->mutex); |
e566fc11 | 618 | radix_tree_insert(&pctl->pin_group_tree, |
f5843492 SA |
619 | ipctl->group_index++, grp); |
620 | mutex_unlock(&ipctl->mutex); | |
a51c158b | 621 | |
a5cadbbb | 622 | imx_pinctrl_parse_groups(child, grp, ipctl, i++); |
ae75ff81 DA |
623 | } |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
5fcdf6a7 MP |
628 | /* |
629 | * Check if the DT contains pins in the direct child nodes. This indicates the | |
630 | * newer DT format to store pins. This function returns true if the first found | |
631 | * fsl,pins property is in a child of np. Otherwise false is returned. | |
632 | */ | |
633 | static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) | |
634 | { | |
cb3cb99a PF |
635 | for_each_child_of_node_scoped(np, function_np) { |
636 | if (of_property_read_bool(function_np, "fsl,pins")) | |
5fcdf6a7 MP |
637 | return true; |
638 | ||
cb3cb99a PF |
639 | for_each_child_of_node_scoped(function_np, pinctrl_np) { |
640 | if (of_property_read_bool(pinctrl_np, "fsl,pins")) | |
5fcdf6a7 MP |
641 | return false; |
642 | } | |
643 | } | |
644 | ||
645 | return true; | |
646 | } | |
647 | ||
150632b0 | 648 | static int imx_pinctrl_probe_dt(struct platform_device *pdev, |
e566fc11 | 649 | struct imx_pinctrl *ipctl) |
ae75ff81 DA |
650 | { |
651 | struct device_node *np = pdev->dev.of_node; | |
652 | struct device_node *child; | |
e566fc11 | 653 | struct pinctrl_dev *pctl = ipctl->pctl; |
ae75ff81 DA |
654 | u32 nfuncs = 0; |
655 | u32 i = 0; | |
5fcdf6a7 | 656 | bool flat_funcs; |
ae75ff81 DA |
657 | |
658 | if (!np) | |
659 | return -ENODEV; | |
660 | ||
5fcdf6a7 MP |
661 | flat_funcs = imx_pinctrl_dt_is_flat_functions(np); |
662 | if (flat_funcs) { | |
663 | nfuncs = 1; | |
664 | } else { | |
665 | nfuncs = of_get_child_count(np); | |
562088ee | 666 | if (nfuncs == 0) { |
5fcdf6a7 MP |
667 | dev_err(&pdev->dev, "no functions defined\n"); |
668 | return -EINVAL; | |
669 | } | |
ae75ff81 DA |
670 | } |
671 | ||
a51c158b | 672 | for (i = 0; i < nfuncs; i++) { |
3fd6d6ad | 673 | struct function_desc *function; |
a51c158b GB |
674 | |
675 | function = devm_kzalloc(&pdev->dev, sizeof(*function), | |
ae75ff81 | 676 | GFP_KERNEL); |
a51c158b GB |
677 | if (!function) |
678 | return -ENOMEM; | |
679 | ||
f5843492 | 680 | mutex_lock(&ipctl->mutex); |
3fd6d6ad | 681 | radix_tree_insert(&pctl->pin_function_tree, i, function); |
f5843492 | 682 | mutex_unlock(&ipctl->mutex); |
a51c158b | 683 | } |
3fd6d6ad | 684 | pctl->num_functions = nfuncs; |
ae75ff81 | 685 | |
f5843492 | 686 | ipctl->group_index = 0; |
5fcdf6a7 | 687 | if (flat_funcs) { |
e566fc11 | 688 | pctl->num_groups = of_get_child_count(np); |
5fcdf6a7 | 689 | } else { |
e566fc11 | 690 | pctl->num_groups = 0; |
5fcdf6a7 | 691 | for_each_child_of_node(np, child) |
e566fc11 | 692 | pctl->num_groups += of_get_child_count(child); |
5fcdf6a7 | 693 | } |
ae75ff81 | 694 | |
5fcdf6a7 | 695 | if (flat_funcs) { |
e566fc11 | 696 | imx_pinctrl_parse_functions(np, ipctl, 0); |
5fcdf6a7 | 697 | } else { |
a51c158b | 698 | i = 0; |
5fcdf6a7 | 699 | for_each_child_of_node(np, child) |
e566fc11 | 700 | imx_pinctrl_parse_functions(child, ipctl, i++); |
5fcdf6a7 | 701 | } |
ae75ff81 DA |
702 | |
703 | return 0; | |
704 | } | |
705 | ||
150632b0 | 706 | int imx_pinctrl_probe(struct platform_device *pdev, |
f5843492 | 707 | const struct imx_pinctrl_soc_info *info) |
ae75ff81 | 708 | { |
8626ada8 | 709 | struct regmap_config config = { .name = "gpr" }; |
26d8cde5 | 710 | struct device_node *dev_np = pdev->dev.of_node; |
6e408ed8 | 711 | struct pinctrl_desc *imx_pinctrl_desc; |
26d8cde5 | 712 | struct device_node *np; |
ae75ff81 | 713 | struct imx_pinctrl *ipctl; |
8626ada8 | 714 | struct regmap *gpr; |
4691dd01 | 715 | int ret, i; |
ae75ff81 | 716 | |
e1641531 | 717 | if (!info || !info->pins || !info->npins) { |
ae75ff81 DA |
718 | dev_err(&pdev->dev, "wrong pinctrl info\n"); |
719 | return -EINVAL; | |
720 | } | |
ae75ff81 | 721 | |
8626ada8 PZ |
722 | if (info->gpr_compatible) { |
723 | gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); | |
724 | if (!IS_ERR(gpr)) | |
725 | regmap_attach_dev(&pdev->dev, gpr, &config); | |
726 | } | |
727 | ||
ae75ff81 DA |
728 | /* Create state holders etc for this driver */ |
729 | ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); | |
730 | if (!ipctl) | |
731 | return -ENOMEM; | |
732 | ||
b96eea71 D |
733 | if (!(info->flags & IMX_USE_SCU)) { |
734 | ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins, | |
735 | sizeof(*ipctl->pin_regs), | |
736 | GFP_KERNEL); | |
737 | if (!ipctl->pin_regs) | |
738 | return -ENOMEM; | |
4691dd01 | 739 | |
b96eea71 D |
740 | for (i = 0; i < info->npins; i++) { |
741 | ipctl->pin_regs[i].mux_reg = -1; | |
742 | ipctl->pin_regs[i].conf_reg = -1; | |
743 | } | |
e1641531 | 744 | |
e05487d4 | 745 | ipctl->base = devm_platform_ioremap_resource(pdev, 0); |
b96eea71 D |
746 | if (IS_ERR(ipctl->base)) |
747 | return PTR_ERR(ipctl->base); | |
ae75ff81 | 748 | |
b96eea71 D |
749 | if (of_property_read_bool(dev_np, "fsl,input-sel")) { |
750 | np = of_parse_phandle(dev_np, "fsl,input-sel", 0); | |
751 | if (!np) { | |
752 | dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); | |
753 | return -EINVAL; | |
754 | } | |
9a4f4245 | 755 | |
13f2d25b | 756 | ipctl->input_sel_base = of_iomap(np, 0); |
b96eea71 | 757 | of_node_put(np); |
13f2d25b | 758 | if (!ipctl->input_sel_base) { |
b96eea71 D |
759 | dev_err(&pdev->dev, |
760 | "iomuxc input select base address not found\n"); | |
13f2d25b | 761 | return -ENOMEM; |
b96eea71 | 762 | } |
9a4f4245 | 763 | } |
26d8cde5 AA |
764 | } |
765 | ||
6e408ed8 PF |
766 | imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), |
767 | GFP_KERNEL); | |
768 | if (!imx_pinctrl_desc) | |
769 | return -ENOMEM; | |
770 | ||
771 | imx_pinctrl_desc->name = dev_name(&pdev->dev); | |
772 | imx_pinctrl_desc->pins = info->pins; | |
773 | imx_pinctrl_desc->npins = info->npins; | |
8f5983ad GB |
774 | imx_pinctrl_desc->pctlops = &imx_pctrl_ops; |
775 | imx_pinctrl_desc->pmxops = &imx_pmx_ops; | |
776 | imx_pinctrl_desc->confops = &imx_pinconf_ops; | |
777 | imx_pinctrl_desc->owner = THIS_MODULE; | |
ae75ff81 | 778 | |
3be6f651 DA |
779 | /* platform specific callback */ |
780 | imx_pmx_ops.gpio_set_direction = info->gpio_set_direction; | |
781 | ||
f5843492 | 782 | mutex_init(&ipctl->mutex); |
a51c158b | 783 | |
ae75ff81 | 784 | ipctl->info = info; |
f5843492 | 785 | ipctl->dev = &pdev->dev; |
ae75ff81 | 786 | platform_set_drvdata(pdev, ipctl); |
950b0d91 TL |
787 | ret = devm_pinctrl_register_and_init(&pdev->dev, |
788 | imx_pinctrl_desc, ipctl, | |
789 | &ipctl->pctl); | |
790 | if (ret) { | |
ae75ff81 | 791 | dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); |
11d8da5c | 792 | return ret; |
ae75ff81 DA |
793 | } |
794 | ||
e566fc11 GB |
795 | ret = imx_pinctrl_probe_dt(pdev, ipctl); |
796 | if (ret) { | |
797 | dev_err(&pdev->dev, "fail to probe dt properties\n"); | |
11d8da5c | 798 | return ret; |
e566fc11 GB |
799 | } |
800 | ||
ae75ff81 DA |
801 | dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); |
802 | ||
61187142 | 803 | return pinctrl_enable(ipctl->pctl); |
ae75ff81 | 804 | } |
b4554dee | 805 | EXPORT_SYMBOL_GPL(imx_pinctrl_probe); |
855811ea AV |
806 | |
807 | static int __maybe_unused imx_pinctrl_suspend(struct device *dev) | |
808 | { | |
809 | struct imx_pinctrl *ipctl = dev_get_drvdata(dev); | |
810 | ||
811 | return pinctrl_force_sleep(ipctl->pctl); | |
812 | } | |
813 | ||
814 | static int __maybe_unused imx_pinctrl_resume(struct device *dev) | |
815 | { | |
816 | struct imx_pinctrl *ipctl = dev_get_drvdata(dev); | |
817 | ||
818 | return pinctrl_force_default(ipctl->pctl); | |
819 | } | |
820 | ||
821 | const struct dev_pm_ops imx_pinctrl_pm_ops = { | |
822 | SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend, | |
823 | imx_pinctrl_resume) | |
824 | }; | |
b4554dee | 825 | EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops); |
7233f7cf AH |
826 | |
827 | MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>"); | |
828 | MODULE_DESCRIPTION("NXP i.MX common pinctrl driver"); | |
829 | MODULE_LICENSE("GPL v2"); |