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c2b39dec FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // Core driver for the imx pin controller | |
4 | // | |
5 | // Copyright (C) 2012 Freescale Semiconductor, Inc. | |
6 | // Copyright (C) 2012 Linaro Ltd. | |
7 | // | |
8 | // Author: Dong Aisheng <dong.aisheng@linaro.org> | |
ae75ff81 DA |
9 | |
10 | #include <linux/err.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/io.h> | |
8626ada8 | 13 | #include <linux/mfd/syscon.h> |
ae75ff81 DA |
14 | #include <linux/of.h> |
15 | #include <linux/of_device.h> | |
26d8cde5 | 16 | #include <linux/of_address.h> |
ae75ff81 DA |
17 | #include <linux/pinctrl/machine.h> |
18 | #include <linux/pinctrl/pinconf.h> | |
19 | #include <linux/pinctrl/pinctrl.h> | |
20 | #include <linux/pinctrl/pinmux.h> | |
21 | #include <linux/slab.h> | |
8626ada8 | 22 | #include <linux/regmap.h> |
ae75ff81 | 23 | |
edad3b2a | 24 | #include "../core.h" |
a5cadbbb | 25 | #include "../pinconf.h" |
3fd6d6ad | 26 | #include "../pinmux.h" |
ae75ff81 DA |
27 | #include "pinctrl-imx.h" |
28 | ||
ae75ff81 DA |
29 | /* The bits in CONFIG cell defined in binding doc*/ |
30 | #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ | |
31 | #define IMX_PAD_SION 0x40000000 /* set SION */ | |
32 | ||
e566fc11 GB |
33 | static inline const struct group_desc *imx_pinctrl_find_group_by_name( |
34 | struct pinctrl_dev *pctldev, | |
ae75ff81 DA |
35 | const char *name) |
36 | { | |
e566fc11 | 37 | const struct group_desc *grp = NULL; |
ae75ff81 DA |
38 | int i; |
39 | ||
e566fc11 GB |
40 | for (i = 0; i < pctldev->num_groups; i++) { |
41 | grp = pinctrl_generic_get_group(pctldev, i); | |
a51c158b | 42 | if (grp && !strcmp(grp->name, name)) |
ae75ff81 | 43 | break; |
ae75ff81 DA |
44 | } |
45 | ||
46 | return grp; | |
47 | } | |
48 | ||
ae75ff81 DA |
49 | static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
50 | unsigned offset) | |
51 | { | |
52 | seq_printf(s, "%s", dev_name(pctldev->dev)); | |
53 | } | |
54 | ||
55 | static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, | |
56 | struct device_node *np, | |
57 | struct pinctrl_map **map, unsigned *num_maps) | |
58 | { | |
59 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
e566fc11 | 60 | const struct group_desc *grp; |
ae75ff81 DA |
61 | struct pinctrl_map *new_map; |
62 | struct device_node *parent; | |
63 | int map_num = 1; | |
18071610 | 64 | int i, j; |
ae75ff81 DA |
65 | |
66 | /* | |
67 | * first find the group of this node and check if we need create | |
68 | * config maps for pins | |
69 | */ | |
e566fc11 | 70 | grp = imx_pinctrl_find_group_by_name(pctldev, np->name); |
ae75ff81 | 71 | if (!grp) { |
f5843492 | 72 | dev_err(ipctl->dev, "unable to find group for node %s\n", |
ae75ff81 DA |
73 | np->name); |
74 | return -EINVAL; | |
75 | } | |
76 | ||
e566fc11 GB |
77 | for (i = 0; i < grp->num_pins; i++) { |
78 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; | |
79 | ||
80 | if (!(pin->config & IMX_NO_PAD_CTL)) | |
ae75ff81 DA |
81 | map_num++; |
82 | } | |
83 | ||
6da2ec56 KC |
84 | new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map), |
85 | GFP_KERNEL); | |
ae75ff81 DA |
86 | if (!new_map) |
87 | return -ENOMEM; | |
88 | ||
89 | *map = new_map; | |
90 | *num_maps = map_num; | |
91 | ||
92 | /* create mux map */ | |
93 | parent = of_get_parent(np); | |
c71157c5 DN |
94 | if (!parent) { |
95 | kfree(new_map); | |
ae75ff81 | 96 | return -EINVAL; |
c71157c5 | 97 | } |
ae75ff81 DA |
98 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; |
99 | new_map[0].data.mux.function = parent->name; | |
100 | new_map[0].data.mux.group = np->name; | |
101 | of_node_put(parent); | |
102 | ||
103 | /* create config map */ | |
104 | new_map++; | |
e566fc11 GB |
105 | for (i = j = 0; i < grp->num_pins; i++) { |
106 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; | |
107 | ||
108 | if (!(pin->config & IMX_NO_PAD_CTL)) { | |
18071610 HW |
109 | new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; |
110 | new_map[j].data.configs.group_or_pin = | |
e566fc11 GB |
111 | pin_get_name(pctldev, pin->pin); |
112 | new_map[j].data.configs.configs = &pin->config; | |
18071610 HW |
113 | new_map[j].data.configs.num_configs = 1; |
114 | j++; | |
ae75ff81 DA |
115 | } |
116 | } | |
117 | ||
118 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
67695f2e | 119 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); |
ae75ff81 DA |
120 | |
121 | return 0; | |
122 | } | |
123 | ||
124 | static void imx_dt_free_map(struct pinctrl_dev *pctldev, | |
125 | struct pinctrl_map *map, unsigned num_maps) | |
126 | { | |
3a86a5f8 | 127 | kfree(map); |
ae75ff81 DA |
128 | } |
129 | ||
022ab148 | 130 | static const struct pinctrl_ops imx_pctrl_ops = { |
e566fc11 GB |
131 | .get_groups_count = pinctrl_generic_get_group_count, |
132 | .get_group_name = pinctrl_generic_get_group_name, | |
133 | .get_group_pins = pinctrl_generic_get_group_pins, | |
ae75ff81 DA |
134 | .pin_dbg_show = imx_pin_dbg_show, |
135 | .dt_node_to_map = imx_dt_node_to_map, | |
136 | .dt_free_map = imx_dt_free_map, | |
137 | ||
138 | }; | |
139 | ||
03e9f0ca LW |
140 | static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, |
141 | unsigned group) | |
ae75ff81 DA |
142 | { |
143 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
f5843492 | 144 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
ae75ff81 | 145 | const struct imx_pin_reg *pin_reg; |
ae75ff81 DA |
146 | unsigned int npins, pin_id; |
147 | int i; | |
e566fc11 | 148 | struct group_desc *grp = NULL; |
3fd6d6ad | 149 | struct function_desc *func = NULL; |
ae75ff81 DA |
150 | |
151 | /* | |
152 | * Configure the mux mode for each pin in the group for a specific | |
153 | * function. | |
154 | */ | |
e566fc11 | 155 | grp = pinctrl_generic_get_group(pctldev, group); |
a51c158b GB |
156 | if (!grp) |
157 | return -EINVAL; | |
158 | ||
3fd6d6ad | 159 | func = pinmux_generic_get_function(pctldev, selector); |
a51c158b GB |
160 | if (!func) |
161 | return -EINVAL; | |
162 | ||
e566fc11 | 163 | npins = grp->num_pins; |
ae75ff81 DA |
164 | |
165 | dev_dbg(ipctl->dev, "enable function %s group %s\n", | |
a51c158b | 166 | func->name, grp->name); |
ae75ff81 DA |
167 | |
168 | for (i = 0; i < npins; i++) { | |
e566fc11 GB |
169 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; |
170 | ||
8f903f8a | 171 | pin_id = pin->pin; |
f5843492 | 172 | pin_reg = &ipctl->pin_regs[pin_id]; |
ae75ff81 | 173 | |
3dac1918 | 174 | if (pin_reg->mux_reg == -1) { |
ba562d5e | 175 | dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", |
ae75ff81 | 176 | info->pins[pin_id].name); |
ba562d5e | 177 | continue; |
ae75ff81 DA |
178 | } |
179 | ||
bf5a5309 JL |
180 | if (info->flags & SHARE_MUX_CONF_REG) { |
181 | u32 reg; | |
182 | reg = readl(ipctl->base + pin_reg->mux_reg); | |
5586ee41 DA |
183 | reg &= ~info->mux_mask; |
184 | reg |= (pin->mux_mode << info->mux_shift); | |
bf5a5309 | 185 | writel(reg, ipctl->base + pin_reg->mux_reg); |
66b54e3a DA |
186 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", |
187 | pin_reg->mux_reg, reg); | |
bf5a5309 | 188 | } else { |
8f903f8a | 189 | writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); |
66b54e3a DA |
190 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", |
191 | pin_reg->mux_reg, pin->mux_mode); | |
bf5a5309 | 192 | } |
ae75ff81 | 193 | |
94176faf SG |
194 | /* |
195 | * If the select input value begins with 0xff, it's a quirky | |
196 | * select input and the value should be interpreted as below. | |
197 | * 31 23 15 7 0 | |
198 | * | 0xff | shift | width | select | | |
199 | * It's used to work around the problem that the select | |
200 | * input for some pin is not implemented in the select | |
201 | * input register but in some general purpose register. | |
202 | * We encode the select input value, width and shift of | |
203 | * the bit field into input_val cell of pin function ID | |
204 | * in device tree, and then decode them here for setting | |
205 | * up the select input bits in general purpose register. | |
206 | */ | |
8f903f8a SH |
207 | if (pin->input_val >> 24 == 0xff) { |
208 | u32 val = pin->input_val; | |
94176faf SG |
209 | u8 select = val & 0xff; |
210 | u8 width = (val >> 8) & 0xff; | |
211 | u8 shift = (val >> 16) & 0xff; | |
212 | u32 mask = ((1 << width) - 1) << shift; | |
213 | /* | |
214 | * The input_reg[i] here is actually some IOMUXC general | |
215 | * purpose register, not regular select input register. | |
216 | */ | |
a3183c60 | 217 | val = readl(ipctl->base + pin->input_reg); |
94176faf SG |
218 | val &= ~mask; |
219 | val |= select << shift; | |
a3183c60 PC |
220 | writel(val, ipctl->base + pin->input_reg); |
221 | } else if (pin->input_reg) { | |
94176faf SG |
222 | /* |
223 | * Regular select input register can never be at offset | |
224 | * 0, and we only print register value for regular case. | |
225 | */ | |
26d8cde5 AA |
226 | if (ipctl->input_sel_base) |
227 | writel(pin->input_val, ipctl->input_sel_base + | |
228 | pin->input_reg); | |
229 | else | |
230 | writel(pin->input_val, ipctl->base + | |
231 | pin->input_reg); | |
ae75ff81 DA |
232 | dev_dbg(ipctl->dev, |
233 | "==>select_input: offset 0x%x val 0x%x\n", | |
8f903f8a | 234 | pin->input_reg, pin->input_val); |
ae75ff81 DA |
235 | } |
236 | } | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
3be6f651 | 241 | struct pinmux_ops imx_pmx_ops = { |
3fd6d6ad GB |
242 | .get_functions_count = pinmux_generic_get_function_count, |
243 | .get_function_name = pinmux_generic_get_function_name, | |
244 | .get_function_groups = pinmux_generic_get_function_groups, | |
03e9f0ca | 245 | .set_mux = imx_pmx_set, |
ae75ff81 DA |
246 | }; |
247 | ||
a5cadbbb DA |
248 | /* decode generic config into raw register values */ |
249 | static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl, | |
250 | unsigned long *configs, | |
251 | unsigned int num_configs) | |
252 | { | |
f5843492 | 253 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
d6093367 | 254 | const struct imx_cfg_params_decode *decode; |
a5cadbbb DA |
255 | enum pin_config_param param; |
256 | u32 raw_config = 0; | |
257 | u32 param_val; | |
258 | int i, j; | |
259 | ||
260 | WARN_ON(num_configs > info->num_decodes); | |
261 | ||
262 | for (i = 0; i < num_configs; i++) { | |
263 | param = pinconf_to_config_param(configs[i]); | |
264 | param_val = pinconf_to_config_argument(configs[i]); | |
265 | decode = info->decodes; | |
266 | for (j = 0; j < info->num_decodes; j++) { | |
267 | if (param == decode->param) { | |
268 | if (decode->invert) | |
269 | param_val = !param_val; | |
270 | raw_config |= (param_val << decode->shift) | |
271 | & decode->mask; | |
272 | break; | |
273 | } | |
274 | decode++; | |
275 | } | |
276 | } | |
277 | ||
278 | if (info->fixup) | |
279 | info->fixup(configs, num_configs, &raw_config); | |
280 | ||
281 | return raw_config; | |
282 | } | |
283 | ||
284 | static u32 imx_pinconf_parse_generic_config(struct device_node *np, | |
285 | struct imx_pinctrl *ipctl) | |
286 | { | |
f5843492 | 287 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
a5cadbbb DA |
288 | struct pinctrl_dev *pctl = ipctl->pctl; |
289 | unsigned int num_configs; | |
290 | unsigned long *configs; | |
291 | int ret; | |
292 | ||
293 | if (!info->generic_pinconf) | |
294 | return 0; | |
295 | ||
296 | ret = pinconf_generic_parse_dt_config(np, pctl, &configs, | |
297 | &num_configs); | |
298 | if (ret) | |
299 | return 0; | |
300 | ||
301 | return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); | |
302 | } | |
303 | ||
ae75ff81 DA |
304 | static int imx_pinconf_get(struct pinctrl_dev *pctldev, |
305 | unsigned pin_id, unsigned long *config) | |
306 | { | |
307 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
f5843492 SA |
308 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
309 | const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; | |
ae75ff81 | 310 | |
3dac1918 | 311 | if (pin_reg->conf_reg == -1) { |
f5843492 | 312 | dev_err(ipctl->dev, "Pin(%s) does not support config function\n", |
ae75ff81 DA |
313 | info->pins[pin_id].name); |
314 | return -EINVAL; | |
315 | } | |
316 | ||
317 | *config = readl(ipctl->base + pin_reg->conf_reg); | |
318 | ||
bf5a5309 | 319 | if (info->flags & SHARE_MUX_CONF_REG) |
5586ee41 | 320 | *config &= ~info->mux_mask; |
bf5a5309 | 321 | |
ae75ff81 DA |
322 | return 0; |
323 | } | |
324 | ||
325 | static int imx_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
326 | unsigned pin_id, unsigned long *configs, |
327 | unsigned num_configs) | |
ae75ff81 DA |
328 | { |
329 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
f5843492 SA |
330 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
331 | const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; | |
03b054e9 | 332 | int i; |
ae75ff81 | 333 | |
3dac1918 | 334 | if (pin_reg->conf_reg == -1) { |
f5843492 | 335 | dev_err(ipctl->dev, "Pin(%s) does not support config function\n", |
ae75ff81 DA |
336 | info->pins[pin_id].name); |
337 | return -EINVAL; | |
338 | } | |
339 | ||
340 | dev_dbg(ipctl->dev, "pinconf set pin %s\n", | |
341 | info->pins[pin_id].name); | |
342 | ||
03b054e9 SY |
343 | for (i = 0; i < num_configs; i++) { |
344 | if (info->flags & SHARE_MUX_CONF_REG) { | |
345 | u32 reg; | |
346 | reg = readl(ipctl->base + pin_reg->conf_reg); | |
5586ee41 | 347 | reg &= info->mux_mask; |
03b054e9 SY |
348 | reg |= configs[i]; |
349 | writel(reg, ipctl->base + pin_reg->conf_reg); | |
66b54e3a DA |
350 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", |
351 | pin_reg->conf_reg, reg); | |
03b054e9 SY |
352 | } else { |
353 | writel(configs[i], ipctl->base + pin_reg->conf_reg); | |
66b54e3a DA |
354 | dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", |
355 | pin_reg->conf_reg, configs[i]); | |
03b054e9 | 356 | } |
03b054e9 | 357 | } /* for each config */ |
ae75ff81 DA |
358 | |
359 | return 0; | |
360 | } | |
361 | ||
362 | static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
363 | struct seq_file *s, unsigned pin_id) | |
364 | { | |
365 | struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); | |
f5843492 | 366 | const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; |
ae75ff81 DA |
367 | unsigned long config; |
368 | ||
4ff0f034 | 369 | if (!pin_reg || pin_reg->conf_reg == -1) { |
7d6989ad | 370 | seq_puts(s, "N/A"); |
ae75ff81 DA |
371 | return; |
372 | } | |
373 | ||
374 | config = readl(ipctl->base + pin_reg->conf_reg); | |
375 | seq_printf(s, "0x%lx", config); | |
376 | } | |
377 | ||
378 | static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
379 | struct seq_file *s, unsigned group) | |
380 | { | |
e566fc11 | 381 | struct group_desc *grp; |
ae75ff81 DA |
382 | unsigned long config; |
383 | const char *name; | |
384 | int i, ret; | |
385 | ||
e566fc11 | 386 | if (group > pctldev->num_groups) |
ae75ff81 DA |
387 | return; |
388 | ||
7d6989ad | 389 | seq_puts(s, "\n"); |
e566fc11 | 390 | grp = pinctrl_generic_get_group(pctldev, group); |
a51c158b GB |
391 | if (!grp) |
392 | return; | |
393 | ||
e566fc11 GB |
394 | for (i = 0; i < grp->num_pins; i++) { |
395 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; | |
396 | ||
8f903f8a SH |
397 | name = pin_get_name(pctldev, pin->pin); |
398 | ret = imx_pinconf_get(pctldev, pin->pin, &config); | |
ae75ff81 DA |
399 | if (ret) |
400 | return; | |
a2d16a21 | 401 | seq_printf(s, " %s: 0x%lx\n", name, config); |
ae75ff81 DA |
402 | } |
403 | } | |
404 | ||
022ab148 | 405 | static const struct pinconf_ops imx_pinconf_ops = { |
ae75ff81 DA |
406 | .pin_config_get = imx_pinconf_get, |
407 | .pin_config_set = imx_pinconf_set, | |
408 | .pin_config_dbg_show = imx_pinconf_dbg_show, | |
409 | .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, | |
410 | }; | |
411 | ||
e1641531 | 412 | /* |
37c1628f DA |
413 | * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID |
414 | * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin. | |
415 | * For generic_pinconf case, there's no extra u32 CONFIG. | |
416 | * | |
417 | * PIN_FUNC_ID format: | |
418 | * Default: | |
419 | * <mux_reg conf_reg input_reg mux_mode input_val> | |
420 | * SHARE_MUX_CONF_REG: | |
421 | * <mux_conf_reg input_reg mux_mode input_val> | |
e1641531 SG |
422 | */ |
423 | #define FSL_PIN_SIZE 24 | |
37c1628f | 424 | #define FSL_PIN_SHARE_SIZE 20 |
ae75ff81 | 425 | |
150632b0 | 426 | static int imx_pinctrl_parse_groups(struct device_node *np, |
e566fc11 | 427 | struct group_desc *grp, |
a5cadbbb | 428 | struct imx_pinctrl *ipctl, |
150632b0 | 429 | u32 index) |
ae75ff81 | 430 | { |
f5843492 | 431 | const struct imx_pinctrl_soc_info *info = ipctl->info; |
bf5a5309 | 432 | int size, pin_size; |
a695145b | 433 | const __be32 *list; |
e1641531 | 434 | int i; |
ae75ff81 DA |
435 | u32 config; |
436 | ||
f5843492 | 437 | dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name); |
ae75ff81 | 438 | |
bf5a5309 | 439 | if (info->flags & SHARE_MUX_CONF_REG) |
37c1628f | 440 | pin_size = FSL_PIN_SHARE_SIZE; |
bf5a5309 JL |
441 | else |
442 | pin_size = FSL_PIN_SIZE; | |
a5cadbbb DA |
443 | |
444 | if (info->generic_pinconf) | |
445 | pin_size -= 4; | |
446 | ||
ae75ff81 DA |
447 | /* Initialise group */ |
448 | grp->name = np->name; | |
449 | ||
450 | /* | |
451 | * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, | |
452 | * do sanity check and calculate pins number | |
a5cadbbb DA |
453 | * |
454 | * First try legacy 'fsl,pins' property, then fall back to the | |
fc4f351a | 455 | * generic 'pinmux'. |
a5cadbbb | 456 | * |
fc4f351a | 457 | * Note: for generic 'pinmux' case, there's no CONFIG part in |
a5cadbbb | 458 | * the binding format. |
ae75ff81 DA |
459 | */ |
460 | list = of_get_property(np, "fsl,pins", &size); | |
1bf1fea9 | 461 | if (!list) { |
fc4f351a | 462 | list = of_get_property(np, "pinmux", &size); |
a5cadbbb | 463 | if (!list) { |
f5843492 | 464 | dev_err(ipctl->dev, |
f5292d06 | 465 | "no fsl,pins and pins property in node %pOF\n", np); |
a5cadbbb DA |
466 | return -EINVAL; |
467 | } | |
1bf1fea9 SH |
468 | } |
469 | ||
ae75ff81 | 470 | /* we do not check return since it's safe node passed down */ |
bf5a5309 | 471 | if (!size || size % pin_size) { |
f5843492 | 472 | dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np); |
ae75ff81 DA |
473 | return -EINVAL; |
474 | } | |
475 | ||
a5cadbbb DA |
476 | /* first try to parse the generic pin config */ |
477 | config = imx_pinconf_parse_generic_config(np, ipctl); | |
478 | ||
e566fc11 | 479 | grp->num_pins = size / pin_size; |
f5843492 | 480 | grp->data = devm_kzalloc(ipctl->dev, grp->num_pins * |
e566fc11 | 481 | sizeof(struct imx_pin), GFP_KERNEL); |
f5843492 | 482 | grp->pins = devm_kzalloc(ipctl->dev, grp->num_pins * |
e566fc11 GB |
483 | sizeof(unsigned int), GFP_KERNEL); |
484 | if (!grp->pins || !grp->data) | |
8f903f8a SH |
485 | return -ENOMEM; |
486 | ||
e566fc11 | 487 | for (i = 0; i < grp->num_pins; i++) { |
e1641531 | 488 | u32 mux_reg = be32_to_cpu(*list++); |
bf5a5309 JL |
489 | u32 conf_reg; |
490 | unsigned int pin_id; | |
491 | struct imx_pin_reg *pin_reg; | |
e566fc11 | 492 | struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; |
e1641531 | 493 | |
e7b37a52 AA |
494 | if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) |
495 | mux_reg = -1; | |
496 | ||
16837f95 | 497 | if (info->flags & SHARE_MUX_CONF_REG) { |
bf5a5309 | 498 | conf_reg = mux_reg; |
16837f95 | 499 | } else { |
bf5a5309 | 500 | conf_reg = be32_to_cpu(*list++); |
16837f95 MP |
501 | if (!conf_reg) |
502 | conf_reg = -1; | |
503 | } | |
bf5a5309 | 504 | |
e7b37a52 | 505 | pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; |
f5843492 | 506 | pin_reg = &ipctl->pin_regs[pin_id]; |
8f903f8a | 507 | pin->pin = pin_id; |
e566fc11 | 508 | grp->pins[i] = pin_id; |
e1641531 SG |
509 | pin_reg->mux_reg = mux_reg; |
510 | pin_reg->conf_reg = conf_reg; | |
8f903f8a SH |
511 | pin->input_reg = be32_to_cpu(*list++); |
512 | pin->mux_mode = be32_to_cpu(*list++); | |
513 | pin->input_val = be32_to_cpu(*list++); | |
e1641531 | 514 | |
a5cadbbb DA |
515 | if (info->generic_pinconf) { |
516 | /* generic pin config decoded */ | |
517 | pin->config = config; | |
518 | } else { | |
519 | /* legacy pin config read from devicetree */ | |
520 | config = be32_to_cpu(*list++); | |
521 | ||
522 | /* SION bit is in mux register */ | |
523 | if (config & IMX_PAD_SION) | |
524 | pin->mux_mode |= IOMUXC_CONFIG_SION; | |
525 | pin->config = config & ~IMX_PAD_SION; | |
526 | } | |
ae75ff81 | 527 | |
f5843492 | 528 | dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, |
40604469 SH |
529 | pin->mux_mode, pin->config); |
530 | } | |
3a86a5f8 | 531 | |
ae75ff81 DA |
532 | return 0; |
533 | } | |
534 | ||
150632b0 | 535 | static int imx_pinctrl_parse_functions(struct device_node *np, |
e566fc11 | 536 | struct imx_pinctrl *ipctl, |
150632b0 | 537 | u32 index) |
ae75ff81 | 538 | { |
e566fc11 | 539 | struct pinctrl_dev *pctl = ipctl->pctl; |
ae75ff81 | 540 | struct device_node *child; |
3fd6d6ad | 541 | struct function_desc *func; |
e566fc11 | 542 | struct group_desc *grp; |
ae75ff81 DA |
543 | u32 i = 0; |
544 | ||
f5843492 | 545 | dev_dbg(pctl->dev, "parse function(%d): %s\n", index, np->name); |
ae75ff81 | 546 | |
3fd6d6ad | 547 | func = pinmux_generic_get_function(pctl, index); |
a51c158b GB |
548 | if (!func) |
549 | return -EINVAL; | |
ae75ff81 DA |
550 | |
551 | /* Initialise function */ | |
552 | func->name = np->name; | |
3fd6d6ad GB |
553 | func->num_group_names = of_get_child_count(np); |
554 | if (func->num_group_names == 0) { | |
f5843492 | 555 | dev_err(ipctl->dev, "no groups defined in %pOF\n", np); |
ae75ff81 DA |
556 | return -EINVAL; |
557 | } | |
f5843492 | 558 | func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names, |
3fd6d6ad | 559 | sizeof(char *), GFP_KERNEL); |
49af64e6 CJ |
560 | if (!func->group_names) |
561 | return -ENOMEM; | |
ae75ff81 DA |
562 | |
563 | for_each_child_of_node(np, child) { | |
3fd6d6ad | 564 | func->group_names[i] = child->name; |
a51c158b | 565 | |
f5843492 | 566 | grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc), |
a51c158b GB |
567 | GFP_KERNEL); |
568 | if (!grp) | |
569 | return -ENOMEM; | |
570 | ||
f5843492 | 571 | mutex_lock(&ipctl->mutex); |
e566fc11 | 572 | radix_tree_insert(&pctl->pin_group_tree, |
f5843492 SA |
573 | ipctl->group_index++, grp); |
574 | mutex_unlock(&ipctl->mutex); | |
a51c158b | 575 | |
a5cadbbb | 576 | imx_pinctrl_parse_groups(child, grp, ipctl, i++); |
ae75ff81 DA |
577 | } |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
5fcdf6a7 MP |
582 | /* |
583 | * Check if the DT contains pins in the direct child nodes. This indicates the | |
584 | * newer DT format to store pins. This function returns true if the first found | |
585 | * fsl,pins property is in a child of np. Otherwise false is returned. | |
586 | */ | |
587 | static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) | |
588 | { | |
589 | struct device_node *function_np; | |
590 | struct device_node *pinctrl_np; | |
591 | ||
592 | for_each_child_of_node(np, function_np) { | |
593 | if (of_property_read_bool(function_np, "fsl,pins")) | |
594 | return true; | |
595 | ||
596 | for_each_child_of_node(function_np, pinctrl_np) { | |
597 | if (of_property_read_bool(pinctrl_np, "fsl,pins")) | |
598 | return false; | |
599 | } | |
600 | } | |
601 | ||
602 | return true; | |
603 | } | |
604 | ||
150632b0 | 605 | static int imx_pinctrl_probe_dt(struct platform_device *pdev, |
e566fc11 | 606 | struct imx_pinctrl *ipctl) |
ae75ff81 DA |
607 | { |
608 | struct device_node *np = pdev->dev.of_node; | |
609 | struct device_node *child; | |
e566fc11 | 610 | struct pinctrl_dev *pctl = ipctl->pctl; |
ae75ff81 DA |
611 | u32 nfuncs = 0; |
612 | u32 i = 0; | |
5fcdf6a7 | 613 | bool flat_funcs; |
ae75ff81 DA |
614 | |
615 | if (!np) | |
616 | return -ENODEV; | |
617 | ||
5fcdf6a7 MP |
618 | flat_funcs = imx_pinctrl_dt_is_flat_functions(np); |
619 | if (flat_funcs) { | |
620 | nfuncs = 1; | |
621 | } else { | |
622 | nfuncs = of_get_child_count(np); | |
562088ee | 623 | if (nfuncs == 0) { |
5fcdf6a7 MP |
624 | dev_err(&pdev->dev, "no functions defined\n"); |
625 | return -EINVAL; | |
626 | } | |
ae75ff81 DA |
627 | } |
628 | ||
a51c158b | 629 | for (i = 0; i < nfuncs; i++) { |
3fd6d6ad | 630 | struct function_desc *function; |
a51c158b GB |
631 | |
632 | function = devm_kzalloc(&pdev->dev, sizeof(*function), | |
ae75ff81 | 633 | GFP_KERNEL); |
a51c158b GB |
634 | if (!function) |
635 | return -ENOMEM; | |
636 | ||
f5843492 | 637 | mutex_lock(&ipctl->mutex); |
3fd6d6ad | 638 | radix_tree_insert(&pctl->pin_function_tree, i, function); |
f5843492 | 639 | mutex_unlock(&ipctl->mutex); |
a51c158b | 640 | } |
3fd6d6ad | 641 | pctl->num_functions = nfuncs; |
ae75ff81 | 642 | |
f5843492 | 643 | ipctl->group_index = 0; |
5fcdf6a7 | 644 | if (flat_funcs) { |
e566fc11 | 645 | pctl->num_groups = of_get_child_count(np); |
5fcdf6a7 | 646 | } else { |
e566fc11 | 647 | pctl->num_groups = 0; |
5fcdf6a7 | 648 | for_each_child_of_node(np, child) |
e566fc11 | 649 | pctl->num_groups += of_get_child_count(child); |
5fcdf6a7 | 650 | } |
ae75ff81 | 651 | |
5fcdf6a7 | 652 | if (flat_funcs) { |
e566fc11 | 653 | imx_pinctrl_parse_functions(np, ipctl, 0); |
5fcdf6a7 | 654 | } else { |
a51c158b | 655 | i = 0; |
5fcdf6a7 | 656 | for_each_child_of_node(np, child) |
e566fc11 | 657 | imx_pinctrl_parse_functions(child, ipctl, i++); |
5fcdf6a7 | 658 | } |
ae75ff81 DA |
659 | |
660 | return 0; | |
661 | } | |
662 | ||
a51c158b GB |
663 | /* |
664 | * imx_free_resources() - free memory used by this driver | |
665 | * @info: info driver instance | |
666 | */ | |
667 | static void imx_free_resources(struct imx_pinctrl *ipctl) | |
668 | { | |
669 | if (ipctl->pctl) | |
670 | pinctrl_unregister(ipctl->pctl); | |
a51c158b GB |
671 | } |
672 | ||
150632b0 | 673 | int imx_pinctrl_probe(struct platform_device *pdev, |
f5843492 | 674 | const struct imx_pinctrl_soc_info *info) |
ae75ff81 | 675 | { |
8626ada8 | 676 | struct regmap_config config = { .name = "gpr" }; |
26d8cde5 | 677 | struct device_node *dev_np = pdev->dev.of_node; |
6e408ed8 | 678 | struct pinctrl_desc *imx_pinctrl_desc; |
26d8cde5 | 679 | struct device_node *np; |
ae75ff81 DA |
680 | struct imx_pinctrl *ipctl; |
681 | struct resource *res; | |
8626ada8 | 682 | struct regmap *gpr; |
4691dd01 | 683 | int ret, i; |
ae75ff81 | 684 | |
e1641531 | 685 | if (!info || !info->pins || !info->npins) { |
ae75ff81 DA |
686 | dev_err(&pdev->dev, "wrong pinctrl info\n"); |
687 | return -EINVAL; | |
688 | } | |
ae75ff81 | 689 | |
8626ada8 PZ |
690 | if (info->gpr_compatible) { |
691 | gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible); | |
692 | if (!IS_ERR(gpr)) | |
693 | regmap_attach_dev(&pdev->dev, gpr, &config); | |
694 | } | |
695 | ||
ae75ff81 DA |
696 | /* Create state holders etc for this driver */ |
697 | ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); | |
698 | if (!ipctl) | |
699 | return -ENOMEM; | |
700 | ||
f5843492 | 701 | ipctl->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*ipctl->pin_regs) * |
e1641531 | 702 | info->npins, GFP_KERNEL); |
f5843492 | 703 | if (!ipctl->pin_regs) |
e1641531 | 704 | return -ENOMEM; |
4691dd01 SA |
705 | |
706 | for (i = 0; i < info->npins; i++) { | |
f5843492 SA |
707 | ipctl->pin_regs[i].mux_reg = -1; |
708 | ipctl->pin_regs[i].conf_reg = -1; | |
4691dd01 | 709 | } |
e1641531 | 710 | |
ae75ff81 | 711 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
9e0c1fb2 TR |
712 | ipctl->base = devm_ioremap_resource(&pdev->dev, res); |
713 | if (IS_ERR(ipctl->base)) | |
714 | return PTR_ERR(ipctl->base); | |
ae75ff81 | 715 | |
26d8cde5 AA |
716 | if (of_property_read_bool(dev_np, "fsl,input-sel")) { |
717 | np = of_parse_phandle(dev_np, "fsl,input-sel", 0); | |
9a4f4245 | 718 | if (!np) { |
26d8cde5 AA |
719 | dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); |
720 | return -EINVAL; | |
721 | } | |
9a4f4245 VZ |
722 | |
723 | ipctl->input_sel_base = of_iomap(np, 0); | |
26d8cde5 | 724 | of_node_put(np); |
9a4f4245 VZ |
725 | if (!ipctl->input_sel_base) { |
726 | dev_err(&pdev->dev, | |
727 | "iomuxc input select base address not found\n"); | |
728 | return -ENOMEM; | |
729 | } | |
26d8cde5 AA |
730 | } |
731 | ||
6e408ed8 PF |
732 | imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc), |
733 | GFP_KERNEL); | |
734 | if (!imx_pinctrl_desc) | |
735 | return -ENOMEM; | |
736 | ||
737 | imx_pinctrl_desc->name = dev_name(&pdev->dev); | |
738 | imx_pinctrl_desc->pins = info->pins; | |
739 | imx_pinctrl_desc->npins = info->npins; | |
8f5983ad GB |
740 | imx_pinctrl_desc->pctlops = &imx_pctrl_ops; |
741 | imx_pinctrl_desc->pmxops = &imx_pmx_ops; | |
742 | imx_pinctrl_desc->confops = &imx_pinconf_ops; | |
743 | imx_pinctrl_desc->owner = THIS_MODULE; | |
ae75ff81 | 744 | |
a5cadbbb DA |
745 | /* for generic pinconf */ |
746 | imx_pinctrl_desc->custom_params = info->custom_params; | |
747 | imx_pinctrl_desc->num_custom_params = info->num_custom_params; | |
748 | ||
3be6f651 DA |
749 | /* platform specific callback */ |
750 | imx_pmx_ops.gpio_set_direction = info->gpio_set_direction; | |
751 | ||
f5843492 | 752 | mutex_init(&ipctl->mutex); |
a51c158b | 753 | |
ae75ff81 | 754 | ipctl->info = info; |
f5843492 | 755 | ipctl->dev = &pdev->dev; |
ae75ff81 | 756 | platform_set_drvdata(pdev, ipctl); |
950b0d91 TL |
757 | ret = devm_pinctrl_register_and_init(&pdev->dev, |
758 | imx_pinctrl_desc, ipctl, | |
759 | &ipctl->pctl); | |
760 | if (ret) { | |
ae75ff81 | 761 | dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); |
a51c158b | 762 | goto free; |
ae75ff81 DA |
763 | } |
764 | ||
e566fc11 GB |
765 | ret = imx_pinctrl_probe_dt(pdev, ipctl); |
766 | if (ret) { | |
767 | dev_err(&pdev->dev, "fail to probe dt properties\n"); | |
768 | goto free; | |
769 | } | |
770 | ||
ae75ff81 DA |
771 | dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); |
772 | ||
61187142 | 773 | return pinctrl_enable(ipctl->pctl); |
a51c158b GB |
774 | |
775 | free: | |
776 | imx_free_resources(ipctl); | |
777 | ||
778 | return ret; | |
ae75ff81 | 779 | } |