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Merge tag 'pstore-v5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees...
[linux-block.git] / drivers / pinctrl / bcm / pinctrl-cygnus-mux.c
CommitLineData
34f46848 1/*
18f75c0a 2 * Copyright (C) 2014-2017 Broadcom
cbd159ed
RJ		 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
18f75c0a
SB		 12 */
13
14/*
15 * Broadcom Cygnus IOMUX driver
cbd159ed
RJ		 16 *
17 * This file contains the Cygnus IOMUX driver that supports group based PINMUX
18 * configuration. Although PINMUX configuration is mainly group based, the
19 * Cygnus IOMUX controller allows certain pins to be individually muxed to GPIO
20 * function, and therefore be controlled by the Cygnus ASIU GPIO controller
21 */
22
23#include <linux/err.h>
24#include <linux/io.h>
cbd159ed
RJ		 25#include <linux/of.h>
26#include <linux/slab.h>
27#include <linux/platform_device.h>
28#include <linux/pinctrl/pinctrl.h>
29#include <linux/pinctrl/pinmux.h>
30#include <linux/pinctrl/pinconf.h>
31#include <linux/pinctrl/pinconf-generic.h>
32#include "../core.h"
33#include "../pinctrl-utils.h"
34
35#define CYGNUS_NUM_IOMUX_REGS 8
36#define CYGNUS_NUM_MUX_PER_REG 8
37#define CYGNUS_NUM_IOMUX (CYGNUS_NUM_IOMUX_REGS * \
38 CYGNUS_NUM_MUX_PER_REG)
39
40/*
41 * Cygnus IOMUX register description
42 *
43 * @offset: register offset for mux configuration of a group
44 * @shift: bit shift for mux configuration of a group
45 * @alt: alternate function to set to
46 */
47struct cygnus_mux {
48 unsigned int offset;
49 unsigned int shift;
50 unsigned int alt;
51};
52
53/*
54 * Keep track of Cygnus IOMUX configuration and prevent double configuration
55 *
56 * @cygnus_mux: Cygnus IOMUX register description
57 * @is_configured: flag to indicate whether a mux setting has already been
58 * configured
59 */
60struct cygnus_mux_log {
61 struct cygnus_mux mux;
62 bool is_configured;
63};
64
65/*
66 * Group based IOMUX configuration
67 *
68 * @name: name of the group
69 * @pins: array of pins used by this group
70 * @num_pins: total number of pins used by this group
71 * @mux: Cygnus group based IOMUX configuration
72 */
73struct cygnus_pin_group {
74 const char *name;
75 const unsigned *pins;
76 unsigned num_pins;
77 struct cygnus_mux mux;
78};
79
80/*
81 * Cygnus mux function and supported pin groups
82 *
83 * @name: name of the function
84 * @groups: array of groups that can be supported by this function
85 * @num_groups: total number of groups that can be supported by this function
86 */
87struct cygnus_pin_function {
88 const char *name;
89 const char * const *groups;
90 unsigned num_groups;
91};
92
93/*
94 * Cygnus IOMUX pinctrl core
95 *
96 * @pctl: pointer to pinctrl_dev
97 * @dev: pointer to device
98 * @base0: first I/O register base of the Cygnus IOMUX controller
99 * @base1: second I/O register base
100 * @groups: pointer to array of groups
101 * @num_groups: total number of groups
102 * @functions: pointer to array of functions
103 * @num_functions: total number of functions
104 * @mux_log: pointer to the array of mux logs
105 * @lock: lock to protect register access
106 */
107struct cygnus_pinctrl {
108 struct pinctrl_dev *pctl;
109 struct device *dev;
110 void __iomem *base0;
111 void __iomem *base1;
112
113 const struct cygnus_pin_group *groups;
114 unsigned num_groups;
115
116 const struct cygnus_pin_function *functions;
117 unsigned num_functions;
118
119 struct cygnus_mux_log *mux_log;
120
121 spinlock_t lock;
122};
123
124/*
125 * Certain pins can be individually muxed to GPIO function
126 *
127 * @is_supported: flag to indicate GPIO mux is supported for this pin
128 * @offset: register offset for GPIO mux override of a pin
129 * @shift: bit shift for GPIO mux override of a pin
130 */
131struct cygnus_gpio_mux {
132 int is_supported;
133 unsigned int offset;
134 unsigned int shift;
135};
136
137/*
138 * Description of a pin in Cygnus
139 *
140 * @pin: pin number
141 * @name: pin name
142 * @gpio_mux: GPIO override related information
143 */
144struct cygnus_pin {
145 unsigned pin;
146 char *name;
147 struct cygnus_gpio_mux gpio_mux;
148};
149
150#define CYGNUS_PIN_DESC(p, n, i, o, s) \
151{ \
152 .pin = p, \
153 .name = n, \
154 .gpio_mux = { \
155 .is_supported = i, \
156 .offset = o, \
157 .shift = s, \
158 }, \
159}
160
161/*
162 * List of pins in Cygnus
163 */
164static struct cygnus_pin cygnus_pins[] = {
165 CYGNUS_PIN_DESC(0, "ext_device_reset_n", 0, 0, 0),
166 CYGNUS_PIN_DESC(1, "chip_mode0", 0, 0, 0),
167 CYGNUS_PIN_DESC(2, "chip_mode1", 0, 0, 0),
168 CYGNUS_PIN_DESC(3, "chip_mode2", 0, 0, 0),
169 CYGNUS_PIN_DESC(4, "chip_mode3", 0, 0, 0),
170 CYGNUS_PIN_DESC(5, "chip_mode4", 0, 0, 0),
171 CYGNUS_PIN_DESC(6, "bsc0_scl", 0, 0, 0),
172 CYGNUS_PIN_DESC(7, "bsc0_sda", 0, 0, 0),
173 CYGNUS_PIN_DESC(8, "bsc1_scl", 0, 0, 0),
174 CYGNUS_PIN_DESC(9, "bsc1_sda", 0, 0, 0),
175 CYGNUS_PIN_DESC(10, "d1w_dq", 1, 0x28, 0),
176 CYGNUS_PIN_DESC(11, "d1wowstz_l", 1, 0x4, 28),
177 CYGNUS_PIN_DESC(12, "gpio0", 0, 0, 0),
178 CYGNUS_PIN_DESC(13, "gpio1", 0, 0, 0),
179 CYGNUS_PIN_DESC(14, "gpio2", 0, 0, 0),
180 CYGNUS_PIN_DESC(15, "gpio3", 0, 0, 0),
181 CYGNUS_PIN_DESC(16, "gpio4", 0, 0, 0),
182 CYGNUS_PIN_DESC(17, "gpio5", 0, 0, 0),
183 CYGNUS_PIN_DESC(18, "gpio6", 0, 0, 0),
184 CYGNUS_PIN_DESC(19, "gpio7", 0, 0, 0),
185 CYGNUS_PIN_DESC(20, "gpio8", 0, 0, 0),
186 CYGNUS_PIN_DESC(21, "gpio9", 0, 0, 0),
187 CYGNUS_PIN_DESC(22, "gpio10", 0, 0, 0),
188 CYGNUS_PIN_DESC(23, "gpio11", 0, 0, 0),
189 CYGNUS_PIN_DESC(24, "gpio12", 0, 0, 0),
190 CYGNUS_PIN_DESC(25, "gpio13", 0, 0, 0),
191 CYGNUS_PIN_DESC(26, "gpio14", 0, 0, 0),
192 CYGNUS_PIN_DESC(27, "gpio15", 0, 0, 0),
193 CYGNUS_PIN_DESC(28, "gpio16", 0, 0, 0),
194 CYGNUS_PIN_DESC(29, "gpio17", 0, 0, 0),
195 CYGNUS_PIN_DESC(30, "gpio18", 0, 0, 0),
196 CYGNUS_PIN_DESC(31, "gpio19", 0, 0, 0),
197 CYGNUS_PIN_DESC(32, "gpio20", 0, 0, 0),
198 CYGNUS_PIN_DESC(33, "gpio21", 0, 0, 0),
199 CYGNUS_PIN_DESC(34, "gpio22", 0, 0, 0),
200 CYGNUS_PIN_DESC(35, "gpio23", 0, 0, 0),
201 CYGNUS_PIN_DESC(36, "mdc", 0, 0, 0),
202 CYGNUS_PIN_DESC(37, "mdio", 0, 0, 0),
203 CYGNUS_PIN_DESC(38, "pwm0", 1, 0x10, 30),
204 CYGNUS_PIN_DESC(39, "pwm1", 1, 0x10, 28),
205 CYGNUS_PIN_DESC(40, "pwm2", 1, 0x10, 26),
206 CYGNUS_PIN_DESC(41, "pwm3", 1, 0x10, 24),
207 CYGNUS_PIN_DESC(42, "sc0_clk", 1, 0x10, 22),
208 CYGNUS_PIN_DESC(43, "sc0_cmdvcc_l", 1, 0x10, 20),
209 CYGNUS_PIN_DESC(44, "sc0_detect", 1, 0x10, 18),
210 CYGNUS_PIN_DESC(45, "sc0_fcb", 1, 0x10, 16),
211 CYGNUS_PIN_DESC(46, "sc0_io", 1, 0x10, 14),
212 CYGNUS_PIN_DESC(47, "sc0_rst_l", 1, 0x10, 12),
213 CYGNUS_PIN_DESC(48, "sc1_clk", 1, 0x10, 10),
214 CYGNUS_PIN_DESC(49, "sc1_cmdvcc_l", 1, 0x10, 8),
215 CYGNUS_PIN_DESC(50, "sc1_detect", 1, 0x10, 6),
216 CYGNUS_PIN_DESC(51, "sc1_fcb", 1, 0x10, 4),
217 CYGNUS_PIN_DESC(52, "sc1_io", 1, 0x10, 2),
218 CYGNUS_PIN_DESC(53, "sc1_rst_l", 1, 0x10, 0),
219 CYGNUS_PIN_DESC(54, "spi0_clk", 1, 0x18, 10),
220 CYGNUS_PIN_DESC(55, "spi0_mosi", 1, 0x18, 6),
221 CYGNUS_PIN_DESC(56, "spi0_miso", 1, 0x18, 8),
222 CYGNUS_PIN_DESC(57, "spi0_ss", 1, 0x18, 4),
223 CYGNUS_PIN_DESC(58, "spi1_clk", 1, 0x18, 2),
224 CYGNUS_PIN_DESC(59, "spi1_mosi", 1, 0x1c, 30),
225 CYGNUS_PIN_DESC(60, "spi1_miso", 1, 0x18, 0),
226 CYGNUS_PIN_DESC(61, "spi1_ss", 1, 0x1c, 28),
227 CYGNUS_PIN_DESC(62, "spi2_clk", 1, 0x1c, 26),
228 CYGNUS_PIN_DESC(63, "spi2_mosi", 1, 0x1c, 22),
229 CYGNUS_PIN_DESC(64, "spi2_miso", 1, 0x1c, 24),
230 CYGNUS_PIN_DESC(65, "spi2_ss", 1, 0x1c, 20),
231 CYGNUS_PIN_DESC(66, "spi3_clk", 1, 0x1c, 18),
232 CYGNUS_PIN_DESC(67, "spi3_mosi", 1, 0x1c, 14),
233 CYGNUS_PIN_DESC(68, "spi3_miso", 1, 0x1c, 16),
234 CYGNUS_PIN_DESC(69, "spi3_ss", 1, 0x1c, 12),
235 CYGNUS_PIN_DESC(70, "uart0_cts", 1, 0x1c, 10),
236 CYGNUS_PIN_DESC(71, "uart0_rts", 1, 0x1c, 8),
237 CYGNUS_PIN_DESC(72, "uart0_rx", 1, 0x1c, 6),
238 CYGNUS_PIN_DESC(73, "uart0_tx", 1, 0x1c, 4),
239 CYGNUS_PIN_DESC(74, "uart1_cts", 1, 0x1c, 2),
240 CYGNUS_PIN_DESC(75, "uart1_dcd", 1, 0x1c, 0),
241 CYGNUS_PIN_DESC(76, "uart1_dsr", 1, 0x20, 14),
242 CYGNUS_PIN_DESC(77, "uart1_dtr", 1, 0x20, 12),
243 CYGNUS_PIN_DESC(78, "uart1_ri", 1, 0x20, 10),
244 CYGNUS_PIN_DESC(79, "uart1_rts", 1, 0x20, 8),
245 CYGNUS_PIN_DESC(80, "uart1_rx", 1, 0x20, 6),
246 CYGNUS_PIN_DESC(81, "uart1_tx", 1, 0x20, 4),
247 CYGNUS_PIN_DESC(82, "uart3_rx", 1, 0x20, 2),
248 CYGNUS_PIN_DESC(83, "uart3_tx", 1, 0x20, 0),
249 CYGNUS_PIN_DESC(84, "sdio1_clk_sdcard", 1, 0x14, 6),
250 CYGNUS_PIN_DESC(85, "sdio1_cmd", 1, 0x14, 4),
251 CYGNUS_PIN_DESC(86, "sdio1_data0", 1, 0x14, 2),
252 CYGNUS_PIN_DESC(87, "sdio1_data1", 1, 0x14, 0),
253 CYGNUS_PIN_DESC(88, "sdio1_data2", 1, 0x18, 30),
254 CYGNUS_PIN_DESC(89, "sdio1_data3", 1, 0x18, 28),
255 CYGNUS_PIN_DESC(90, "sdio1_wp_n", 1, 0x18, 24),
256 CYGNUS_PIN_DESC(91, "sdio1_card_rst", 1, 0x14, 10),
257 CYGNUS_PIN_DESC(92, "sdio1_led_on", 1, 0x18, 26),
258 CYGNUS_PIN_DESC(93, "sdio1_cd", 1, 0x14, 8),
259 CYGNUS_PIN_DESC(94, "sdio0_clk_sdcard", 1, 0x14, 26),
260 CYGNUS_PIN_DESC(95, "sdio0_cmd", 1, 0x14, 24),
261 CYGNUS_PIN_DESC(96, "sdio0_data0", 1, 0x14, 22),
262 CYGNUS_PIN_DESC(97, "sdio0_data1", 1, 0x14, 20),
263 CYGNUS_PIN_DESC(98, "sdio0_data2", 1, 0x14, 18),
264 CYGNUS_PIN_DESC(99, "sdio0_data3", 1, 0x14, 16),
265 CYGNUS_PIN_DESC(100, "sdio0_wp_n", 1, 0x14, 12),
266 CYGNUS_PIN_DESC(101, "sdio0_card_rst", 1, 0x14, 30),
267 CYGNUS_PIN_DESC(102, "sdio0_led_on", 1, 0x14, 14),
268 CYGNUS_PIN_DESC(103, "sdio0_cd", 1, 0x14, 28),
269 CYGNUS_PIN_DESC(104, "sflash_clk", 1, 0x18, 22),
270 CYGNUS_PIN_DESC(105, "sflash_cs_l", 1, 0x18, 20),
271 CYGNUS_PIN_DESC(106, "sflash_mosi", 1, 0x18, 14),
272 CYGNUS_PIN_DESC(107, "sflash_miso", 1, 0x18, 16),
273 CYGNUS_PIN_DESC(108, "sflash_wp_n", 1, 0x18, 12),
274 CYGNUS_PIN_DESC(109, "sflash_hold_n", 1, 0x18, 18),
275 CYGNUS_PIN_DESC(110, "nand_ale", 1, 0xc, 30),
276 CYGNUS_PIN_DESC(111, "nand_ce0_l", 1, 0xc, 28),
277 CYGNUS_PIN_DESC(112, "nand_ce1_l", 1, 0xc, 26),
278 CYGNUS_PIN_DESC(113, "nand_cle", 1, 0xc, 24),
279 CYGNUS_PIN_DESC(114, "nand_dq0", 1, 0xc, 22),
280 CYGNUS_PIN_DESC(115, "nand_dq1", 1, 0xc, 20),
281 CYGNUS_PIN_DESC(116, "nand_dq2", 1, 0xc, 18),
282 CYGNUS_PIN_DESC(117, "nand_dq3", 1, 0xc, 16),
283 CYGNUS_PIN_DESC(118, "nand_dq4", 1, 0xc, 14),
284 CYGNUS_PIN_DESC(119, "nand_dq5", 1, 0xc, 12),
285 CYGNUS_PIN_DESC(120, "nand_dq6", 1, 0xc, 10),
286 CYGNUS_PIN_DESC(121, "nand_dq7", 1, 0xc, 8),
287 CYGNUS_PIN_DESC(122, "nand_rb_l", 1, 0xc, 6),
288 CYGNUS_PIN_DESC(123, "nand_re_l", 1, 0xc, 4),
289 CYGNUS_PIN_DESC(124, "nand_we_l", 1, 0xc, 2),
290 CYGNUS_PIN_DESC(125, "nand_wp_l", 1, 0xc, 0),
291 CYGNUS_PIN_DESC(126, "lcd_clac", 1, 0x4, 26),
292 CYGNUS_PIN_DESC(127, "lcd_clcp", 1, 0x4, 24),
293 CYGNUS_PIN_DESC(128, "lcd_cld0", 1, 0x4, 22),
294 CYGNUS_PIN_DESC(129, "lcd_cld1", 1, 0x4, 0),
295 CYGNUS_PIN_DESC(130, "lcd_cld10", 1, 0x4, 20),
296 CYGNUS_PIN_DESC(131, "lcd_cld11", 1, 0x4, 18),
297 CYGNUS_PIN_DESC(132, "lcd_cld12", 1, 0x4, 16),
298 CYGNUS_PIN_DESC(133, "lcd_cld13", 1, 0x4, 14),
299 CYGNUS_PIN_DESC(134, "lcd_cld14", 1, 0x4, 12),
300 CYGNUS_PIN_DESC(135, "lcd_cld15", 1, 0x4, 10),
301 CYGNUS_PIN_DESC(136, "lcd_cld16", 1, 0x4, 8),
302 CYGNUS_PIN_DESC(137, "lcd_cld17", 1, 0x4, 6),
303 CYGNUS_PIN_DESC(138, "lcd_cld18", 1, 0x4, 4),
304 CYGNUS_PIN_DESC(139, "lcd_cld19", 1, 0x4, 2),
305 CYGNUS_PIN_DESC(140, "lcd_cld2", 1, 0x8, 22),
306 CYGNUS_PIN_DESC(141, "lcd_cld20", 1, 0x8, 30),
307 CYGNUS_PIN_DESC(142, "lcd_cld21", 1, 0x8, 28),
308 CYGNUS_PIN_DESC(143, "lcd_cld22", 1, 0x8, 26),
309 CYGNUS_PIN_DESC(144, "lcd_cld23", 1, 0x8, 24),
310 CYGNUS_PIN_DESC(145, "lcd_cld3", 1, 0x8, 20),
311 CYGNUS_PIN_DESC(146, "lcd_cld4", 1, 0x8, 18),
312 CYGNUS_PIN_DESC(147, "lcd_cld5", 1, 0x8, 16),
313 CYGNUS_PIN_DESC(148, "lcd_cld6", 1, 0x8, 14),
314 CYGNUS_PIN_DESC(149, "lcd_cld7", 1, 0x8, 12),
315 CYGNUS_PIN_DESC(150, "lcd_cld8", 1, 0x8, 10),
316 CYGNUS_PIN_DESC(151, "lcd_cld9", 1, 0x8, 8),
317 CYGNUS_PIN_DESC(152, "lcd_clfp", 1, 0x8, 6),
318 CYGNUS_PIN_DESC(153, "lcd_clle", 1, 0x8, 4),
319 CYGNUS_PIN_DESC(154, "lcd_cllp", 1, 0x8, 2),
320 CYGNUS_PIN_DESC(155, "lcd_clpower", 1, 0x8, 0),
321 CYGNUS_PIN_DESC(156, "camera_vsync", 1, 0x4, 30),
322 CYGNUS_PIN_DESC(157, "camera_trigger", 1, 0x0, 0),
323 CYGNUS_PIN_DESC(158, "camera_strobe", 1, 0x0, 2),
324 CYGNUS_PIN_DESC(159, "camera_standby", 1, 0x0, 4),
325 CYGNUS_PIN_DESC(160, "camera_reset_n", 1, 0x0, 6),
326 CYGNUS_PIN_DESC(161, "camera_pixdata9", 1, 0x0, 8),
327 CYGNUS_PIN_DESC(162, "camera_pixdata8", 1, 0x0, 10),
328 CYGNUS_PIN_DESC(163, "camera_pixdata7", 1, 0x0, 12),
329 CYGNUS_PIN_DESC(164, "camera_pixdata6", 1, 0x0, 14),
330 CYGNUS_PIN_DESC(165, "camera_pixdata5", 1, 0x0, 16),
331 CYGNUS_PIN_DESC(166, "camera_pixdata4", 1, 0x0, 18),
332 CYGNUS_PIN_DESC(167, "camera_pixdata3", 1, 0x0, 20),
333 CYGNUS_PIN_DESC(168, "camera_pixdata2", 1, 0x0, 22),
334 CYGNUS_PIN_DESC(169, "camera_pixdata1", 1, 0x0, 24),
335 CYGNUS_PIN_DESC(170, "camera_pixdata0", 1, 0x0, 26),
336 CYGNUS_PIN_DESC(171, "camera_pixclk", 1, 0x0, 28),
337 CYGNUS_PIN_DESC(172, "camera_hsync", 1, 0x0, 30),
338 CYGNUS_PIN_DESC(173, "camera_pll_ref_clk", 0, 0, 0),
339 CYGNUS_PIN_DESC(174, "usb_id_indication", 0, 0, 0),
340 CYGNUS_PIN_DESC(175, "usb_vbus_indication", 0, 0, 0),
341 CYGNUS_PIN_DESC(176, "gpio0_3p3", 0, 0, 0),
342 CYGNUS_PIN_DESC(177, "gpio1_3p3", 0, 0, 0),
343 CYGNUS_PIN_DESC(178, "gpio2_3p3", 0, 0, 0),
344 CYGNUS_PIN_DESC(179, "gpio3_3p3", 0, 0, 0),
345};
346
347/*
348 * List of groups of pins
349 */
350static const unsigned bsc1_pins[] = { 8, 9 };
351static const unsigned pcie_clkreq_pins[] = { 8, 9 };
352
353static const unsigned i2s2_0_pins[] = { 12 };
354static const unsigned i2s2_1_pins[] = { 13 };
355static const unsigned i2s2_2_pins[] = { 14 };
356static const unsigned i2s2_3_pins[] = { 15 };
357static const unsigned i2s2_4_pins[] = { 16 };
358
359static const unsigned pwm4_pins[] = { 17 };
360static const unsigned pwm5_pins[] = { 18 };
361
362static const unsigned key0_pins[] = { 20 };
363static const unsigned key1_pins[] = { 21 };
364static const unsigned key2_pins[] = { 22 };
365static const unsigned key3_pins[] = { 23 };
366static const unsigned key4_pins[] = { 24 };
367static const unsigned key5_pins[] = { 25 };
368
369static const unsigned key6_pins[] = { 26 };
370static const unsigned audio_dte0_pins[] = { 26 };
371
372static const unsigned key7_pins[] = { 27 };
373static const unsigned audio_dte1_pins[] = { 27 };
374
375static const unsigned key8_pins[] = { 28 };
376static const unsigned key9_pins[] = { 29 };
377static const unsigned key10_pins[] = { 30 };
378static const unsigned key11_pins[] = { 31 };
379static const unsigned key12_pins[] = { 32 };
380static const unsigned key13_pins[] = { 33 };
381
382static const unsigned key14_pins[] = { 34 };
383static const unsigned audio_dte2_pins[] = { 34 };
384
385static const unsigned key15_pins[] = { 35 };
386static const unsigned audio_dte3_pins[] = { 35 };
387
388static const unsigned pwm0_pins[] = { 38 };
389static const unsigned pwm1_pins[] = { 39 };
390static const unsigned pwm2_pins[] = { 40 };
391static const unsigned pwm3_pins[] = { 41 };
392
393static const unsigned sdio0_pins[] = { 94, 95, 96, 97, 98, 99 };
394
395static const unsigned smart_card0_pins[] = { 42, 43, 44, 46, 47 };
396static const unsigned i2s0_0_pins[] = { 42, 43, 44, 46 };
397static const unsigned spdif_pins[] = { 47 };
398
399static const unsigned smart_card1_pins[] = { 48, 49, 50, 52, 53 };
400static const unsigned i2s1_0_pins[] = { 48, 49, 50, 52 };
401
402static const unsigned spi0_pins[] = { 54, 55, 56, 57 };
403
404static const unsigned spi1_pins[] = { 58, 59, 60, 61 };
405
406static const unsigned spi2_pins[] = { 62, 63, 64, 65 };
407
408static const unsigned spi3_pins[] = { 66, 67, 68, 69 };
409static const unsigned sw_led0_0_pins[] = { 66, 67, 68, 69 };
410
411static const unsigned d1w_pins[] = { 10, 11 };
412static const unsigned uart4_pins[] = { 10, 11 };
413static const unsigned sw_led2_0_pins[] = { 10, 11 };
414
415static const unsigned lcd_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,
416 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
417 148, 149, 150, 151, 152, 153, 154, 155 };
418static const unsigned sram_0_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,
419 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
420 148, 149, 150, 151, 152, 153, 154, 155 };
421static const unsigned spi5_pins[] = { 141, 142, 143, 144 };
422
423static const unsigned uart0_pins[] = { 70, 71, 72, 73 };
424static const unsigned sw_led0_1_pins[] = { 70, 71, 72, 73 };
425
426static const unsigned uart1_dte_pins[] = { 75, 76, 77, 78 };
427static const unsigned uart2_pins[] = { 75, 76, 77, 78 };
428
429static const unsigned uart1_pins[] = { 74, 79, 80, 81 };
430
431static const unsigned uart3_pins[] = { 82, 83 };
432
433static const unsigned qspi_0_pins[] = { 104, 105, 106, 107 };
434
435static const unsigned nand_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117,
436 118, 119, 120, 121, 122, 123, 124, 125 };
437
438static const unsigned sdio0_cd_pins[] = { 103 };
439
440static const unsigned sdio0_mmc_pins[] = { 100, 101, 102 };
441
442static const unsigned sdio1_data_0_pins[] = { 86, 87 };
443static const unsigned can0_pins[] = { 86, 87 };
444static const unsigned spi4_0_pins[] = { 86, 87 };
445
446static const unsigned sdio1_data_1_pins[] = { 88, 89 };
447static const unsigned can1_pins[] = { 88, 89 };
448static const unsigned spi4_1_pins[] = { 88, 89 };
449
450static const unsigned sdio1_cd_pins[] = { 93 };
451
452static const unsigned sdio1_led_pins[] = { 84, 85 };
453static const unsigned sw_led2_1_pins[] = { 84, 85 };
454
455static const unsigned sdio1_mmc_pins[] = { 90, 91, 92 };
456
457static const unsigned cam_led_pins[] = { 156, 157, 158, 159, 160 };
458static const unsigned sw_led1_pins[] = { 156, 157, 158, 159 };
459
460static const unsigned cam_0_pins[] = { 169, 170, 171, 169, 170 };
461
462static const unsigned cam_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,
463 168 };
464static const unsigned sram_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,
465 168 };
466
467static const unsigned qspi_1_pins[] = { 108, 109 };
468
469static const unsigned smart_card0_fcb_pins[] = { 45 };
470static const unsigned i2s0_1_pins[] = { 45 };
471
472static const unsigned smart_card1_fcb_pins[] = { 51 };
473static const unsigned i2s1_1_pins[] = { 51 };
474
475static const unsigned gpio0_3p3_pins[] = { 176 };
476static const unsigned usb0_oc_pins[] = { 176 };
477
478static const unsigned gpio1_3p3_pins[] = { 177 };
479static const unsigned usb1_oc_pins[] = { 177 };
480
481static const unsigned gpio2_3p3_pins[] = { 178 };
482static const unsigned usb2_oc_pins[] = { 178 };
483
484#define CYGNUS_PIN_GROUP(group_name, off, sh, al) \
485{ \
486 .name = __stringify(group_name) "_grp", \
487 .pins = group_name ## _pins, \
488 .num_pins = ARRAY_SIZE(group_name ## _pins), \
489 .mux = { \
490 .offset = off, \
491 .shift = sh, \
492 .alt = al, \
493 } \
494}
495
496/*
497 * List of Cygnus pin groups
498 */
499static const struct cygnus_pin_group cygnus_pin_groups[] = {
500 CYGNUS_PIN_GROUP(i2s2_0, 0x0, 0, 2),
501 CYGNUS_PIN_GROUP(i2s2_1, 0x0, 4, 2),
502 CYGNUS_PIN_GROUP(i2s2_2, 0x0, 8, 2),
503 CYGNUS_PIN_GROUP(i2s2_3, 0x0, 12, 2),
504 CYGNUS_PIN_GROUP(i2s2_4, 0x0, 16, 2),
505 CYGNUS_PIN_GROUP(pwm4, 0x0, 20, 0),
506 CYGNUS_PIN_GROUP(pwm5, 0x0, 24, 2),
507 CYGNUS_PIN_GROUP(key0, 0x4, 0, 1),
508 CYGNUS_PIN_GROUP(key1, 0x4, 4, 1),
509 CYGNUS_PIN_GROUP(key2, 0x4, 8, 1),
510 CYGNUS_PIN_GROUP(key3, 0x4, 12, 1),
511 CYGNUS_PIN_GROUP(key4, 0x4, 16, 1),
512 CYGNUS_PIN_GROUP(key5, 0x4, 20, 1),
513 CYGNUS_PIN_GROUP(key6, 0x4, 24, 1),
514 CYGNUS_PIN_GROUP(audio_dte0, 0x4, 24, 2),
515 CYGNUS_PIN_GROUP(key7, 0x4, 28, 1),
516 CYGNUS_PIN_GROUP(audio_dte1, 0x4, 28, 2),
517 CYGNUS_PIN_GROUP(key8, 0x8, 0, 1),
518 CYGNUS_PIN_GROUP(key9, 0x8, 4, 1),
519 CYGNUS_PIN_GROUP(key10, 0x8, 8, 1),
520 CYGNUS_PIN_GROUP(key11, 0x8, 12, 1),
521 CYGNUS_PIN_GROUP(key12, 0x8, 16, 1),
522 CYGNUS_PIN_GROUP(key13, 0x8, 20, 1),
523 CYGNUS_PIN_GROUP(key14, 0x8, 24, 1),
524 CYGNUS_PIN_GROUP(audio_dte2, 0x8, 24, 2),
525 CYGNUS_PIN_GROUP(key15, 0x8, 28, 1),
526 CYGNUS_PIN_GROUP(audio_dte3, 0x8, 28, 2),
527 CYGNUS_PIN_GROUP(pwm0, 0xc, 0, 0),
528 CYGNUS_PIN_GROUP(pwm1, 0xc, 4, 0),
529 CYGNUS_PIN_GROUP(pwm2, 0xc, 8, 0),
530 CYGNUS_PIN_GROUP(pwm3, 0xc, 12, 0),
531 CYGNUS_PIN_GROUP(sdio0, 0xc, 16, 0),
532 CYGNUS_PIN_GROUP(smart_card0, 0xc, 20, 0),
533 CYGNUS_PIN_GROUP(i2s0_0, 0xc, 20, 1),
534 CYGNUS_PIN_GROUP(spdif, 0xc, 20, 1),
535 CYGNUS_PIN_GROUP(smart_card1, 0xc, 24, 0),
536 CYGNUS_PIN_GROUP(i2s1_0, 0xc, 24, 1),
537 CYGNUS_PIN_GROUP(spi0, 0x10, 0, 0),
538 CYGNUS_PIN_GROUP(spi1, 0x10, 4, 0),
539 CYGNUS_PIN_GROUP(spi2, 0x10, 8, 0),
540 CYGNUS_PIN_GROUP(spi3, 0x10, 12, 0),
541 CYGNUS_PIN_GROUP(sw_led0_0, 0x10, 12, 2),
542 CYGNUS_PIN_GROUP(d1w, 0x10, 16, 0),
543 CYGNUS_PIN_GROUP(uart4, 0x10, 16, 1),
544 CYGNUS_PIN_GROUP(sw_led2_0, 0x10, 16, 2),
545 CYGNUS_PIN_GROUP(lcd, 0x10, 20, 0),
546 CYGNUS_PIN_GROUP(sram_0, 0x10, 20, 1),
547 CYGNUS_PIN_GROUP(spi5, 0x10, 20, 2),
548 CYGNUS_PIN_GROUP(uart0, 0x14, 0, 0),
549 CYGNUS_PIN_GROUP(sw_led0_1, 0x14, 0, 2),
550 CYGNUS_PIN_GROUP(uart1_dte, 0x14, 4, 0),
551 CYGNUS_PIN_GROUP(uart2, 0x14, 4, 1),
552 CYGNUS_PIN_GROUP(uart1, 0x14, 8, 0),
553 CYGNUS_PIN_GROUP(uart3, 0x14, 12, 0),
554 CYGNUS_PIN_GROUP(qspi_0, 0x14, 16, 0),
555 CYGNUS_PIN_GROUP(nand, 0x14, 20, 0),
556 CYGNUS_PIN_GROUP(sdio0_cd, 0x18, 0, 0),
557 CYGNUS_PIN_GROUP(sdio0_mmc, 0x18, 4, 0),
558 CYGNUS_PIN_GROUP(sdio1_data_0, 0x18, 8, 0),
559 CYGNUS_PIN_GROUP(can0, 0x18, 8, 1),
560 CYGNUS_PIN_GROUP(spi4_0, 0x18, 8, 2),
561 CYGNUS_PIN_GROUP(sdio1_data_1, 0x18, 12, 0),
562 CYGNUS_PIN_GROUP(can1, 0x18, 12, 1),
563 CYGNUS_PIN_GROUP(spi4_1, 0x18, 12, 2),
564 CYGNUS_PIN_GROUP(sdio1_cd, 0x18, 16, 0),
565 CYGNUS_PIN_GROUP(sdio1_led, 0x18, 20, 0),
566 CYGNUS_PIN_GROUP(sw_led2_1, 0x18, 20, 2),
567 CYGNUS_PIN_GROUP(sdio1_mmc, 0x18, 24, 0),
568 CYGNUS_PIN_GROUP(cam_led, 0x1c, 0, 0),
569 CYGNUS_PIN_GROUP(sw_led1, 0x1c, 0, 1),
570 CYGNUS_PIN_GROUP(cam_0, 0x1c, 4, 0),
571 CYGNUS_PIN_GROUP(cam_1, 0x1c, 8, 0),
572 CYGNUS_PIN_GROUP(sram_1, 0x1c, 8, 1),
573 CYGNUS_PIN_GROUP(qspi_1, 0x1c, 12, 0),
574 CYGNUS_PIN_GROUP(bsc1, 0x1c, 16, 0),
575 CYGNUS_PIN_GROUP(pcie_clkreq, 0x1c, 16, 1),
576 CYGNUS_PIN_GROUP(smart_card0_fcb, 0x20, 0, 0),
577 CYGNUS_PIN_GROUP(i2s0_1, 0x20, 0, 1),
578 CYGNUS_PIN_GROUP(smart_card1_fcb, 0x20, 4, 0),
579 CYGNUS_PIN_GROUP(i2s1_1, 0x20, 4, 1),
580 CYGNUS_PIN_GROUP(gpio0_3p3, 0x28, 0, 0),
581 CYGNUS_PIN_GROUP(usb0_oc, 0x28, 0, 1),
582 CYGNUS_PIN_GROUP(gpio1_3p3, 0x28, 4, 0),
583 CYGNUS_PIN_GROUP(usb1_oc, 0x28, 4, 1),
584 CYGNUS_PIN_GROUP(gpio2_3p3, 0x28, 8, 0),
585 CYGNUS_PIN_GROUP(usb2_oc, 0x28, 8, 1),
586};
587
588/*
589 * List of groups supported by functions
590 */
591static const char * const i2s0_grps[] = { "i2s0_0_grp", "i2s0_1_grp" };
592static const char * const i2s1_grps[] = { "i2s1_0_grp", "i2s1_1_grp" };
593static const char * const i2s2_grps[] = { "i2s2_0_grp", "i2s2_1_grp",
594 "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" };
595static const char * const spdif_grps[] = { "spdif_grp" };
596static const char * const pwm0_grps[] = { "pwm0_grp" };
597static const char * const pwm1_grps[] = { "pwm1_grp" };
598static const char * const pwm2_grps[] = { "pwm2_grp" };
599static const char * const pwm3_grps[] = { "pwm3_grp" };
600static const char * const pwm4_grps[] = { "pwm4_grp" };
601static const char * const pwm5_grps[] = { "pwm5_grp" };
602static const char * const key_grps[] = { "key0_grp", "key1_grp", "key2_grp",
603 "key3_grp", "key4_grp", "key5_grp", "key6_grp", "key7_grp", "key8_grp",
604 "key9_grp", "key10_grp", "key11_grp", "key12_grp", "key13_grp",
605 "key14_grp", "key15_grp" };
606static const char * const audio_dte_grps[] = { "audio_dte0_grp",
607 "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" };
608static const char * const smart_card0_grps[] = { "smart_card0_grp",
609 "smart_card0_fcb_grp" };
610static const char * const smart_card1_grps[] = { "smart_card1_grp",
611 "smart_card1_fcb_grp" };
612static const char * const spi0_grps[] = { "spi0_grp" };
613static const char * const spi1_grps[] = { "spi1_grp" };
614static const char * const spi2_grps[] = { "spi2_grp" };
615static const char * const spi3_grps[] = { "spi3_grp" };
616static const char * const spi4_grps[] = { "spi4_0_grp", "spi4_1_grp" };
617static const char * const spi5_grps[] = { "spi5_grp" };
618
619static const char * const sw_led0_grps[] = { "sw_led0_0_grp",
620 "sw_led0_1_grp" };
621static const char * const sw_led1_grps[] = { "sw_led1_grp" };
622static const char * const sw_led2_grps[] = { "sw_led2_0_grp",
623 "sw_led2_1_grp" };
624static const char * const d1w_grps[] = { "d1w_grp" };
625static const char * const lcd_grps[] = { "lcd_grp" };
626static const char * const sram_grps[] = { "sram_0_grp", "sram_1_grp" };
627
628static const char * const uart0_grps[] = { "uart0_grp" };
629static const char * const uart1_grps[] = { "uart1_grp", "uart1_dte_grp" };
630static const char * const uart2_grps[] = { "uart2_grp" };
631static const char * const uart3_grps[] = { "uart3_grp" };
632static const char * const uart4_grps[] = { "uart4_grp" };
633static const char * const qspi_grps[] = { "qspi_0_grp", "qspi_1_grp" };
634static const char * const nand_grps[] = { "nand_grp" };
635static const char * const sdio0_grps[] = { "sdio0_grp", "sdio0_cd_grp",
636 "sdio0_mmc_grp" };
637static const char * const sdio1_grps[] = { "sdio1_data_0_grp",
638 "sdio1_data_1_grp", "sdio1_cd_grp", "sdio1_led_grp", "sdio1_mmc_grp" };
639static const char * const can0_grps[] = { "can0_grp" };
640static const char * const can1_grps[] = { "can1_grp" };
641static const char * const cam_grps[] = { "cam_led_grp", "cam_0_grp",
642 "cam_1_grp" };
643static const char * const bsc1_grps[] = { "bsc1_grp" };
644static const char * const pcie_clkreq_grps[] = { "pcie_clkreq_grp" };
645static const char * const usb0_oc_grps[] = { "usb0_oc_grp" };
646static const char * const usb1_oc_grps[] = { "usb1_oc_grp" };
647static const char * const usb2_oc_grps[] = { "usb2_oc_grp" };
648
649#define CYGNUS_PIN_FUNCTION(func) \
650{ \
651 .name = #func, \
652 .groups = func ## _grps, \
653 .num_groups = ARRAY_SIZE(func ## _grps), \
654}
655
656/*
657 * List of supported functions in Cygnus
658 */
659static const struct cygnus_pin_function cygnus_pin_functions[] = {
660 CYGNUS_PIN_FUNCTION(i2s0),
661 CYGNUS_PIN_FUNCTION(i2s1),
662 CYGNUS_PIN_FUNCTION(i2s2),
663 CYGNUS_PIN_FUNCTION(spdif),
664 CYGNUS_PIN_FUNCTION(pwm0),
665 CYGNUS_PIN_FUNCTION(pwm1),
666 CYGNUS_PIN_FUNCTION(pwm2),
667 CYGNUS_PIN_FUNCTION(pwm3),
668 CYGNUS_PIN_FUNCTION(pwm4),
669 CYGNUS_PIN_FUNCTION(pwm5),
670 CYGNUS_PIN_FUNCTION(key),
671 CYGNUS_PIN_FUNCTION(audio_dte),
672 CYGNUS_PIN_FUNCTION(smart_card0),
673 CYGNUS_PIN_FUNCTION(smart_card1),
674 CYGNUS_PIN_FUNCTION(spi0),
675 CYGNUS_PIN_FUNCTION(spi1),
676 CYGNUS_PIN_FUNCTION(spi2),
677 CYGNUS_PIN_FUNCTION(spi3),
678 CYGNUS_PIN_FUNCTION(spi4),
679 CYGNUS_PIN_FUNCTION(spi5),
680 CYGNUS_PIN_FUNCTION(sw_led0),
681 CYGNUS_PIN_FUNCTION(sw_led1),
682 CYGNUS_PIN_FUNCTION(sw_led2),
683 CYGNUS_PIN_FUNCTION(d1w),
684 CYGNUS_PIN_FUNCTION(lcd),
685 CYGNUS_PIN_FUNCTION(sram),
686 CYGNUS_PIN_FUNCTION(uart0),
687 CYGNUS_PIN_FUNCTION(uart1),
688 CYGNUS_PIN_FUNCTION(uart2),
689 CYGNUS_PIN_FUNCTION(uart3),
690 CYGNUS_PIN_FUNCTION(uart4),
691 CYGNUS_PIN_FUNCTION(qspi),
692 CYGNUS_PIN_FUNCTION(nand),
693 CYGNUS_PIN_FUNCTION(sdio0),
694 CYGNUS_PIN_FUNCTION(sdio1),
695 CYGNUS_PIN_FUNCTION(can0),
696 CYGNUS_PIN_FUNCTION(can1),
697 CYGNUS_PIN_FUNCTION(cam),
698 CYGNUS_PIN_FUNCTION(bsc1),
699 CYGNUS_PIN_FUNCTION(pcie_clkreq),
700 CYGNUS_PIN_FUNCTION(usb0_oc),
701 CYGNUS_PIN_FUNCTION(usb1_oc),
702 CYGNUS_PIN_FUNCTION(usb2_oc),
703};
704
705static int cygnus_get_groups_count(struct pinctrl_dev *pctrl_dev)
706{
707 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
708
709 return pinctrl->num_groups;
710}
711
712static const char *cygnus_get_group_name(struct pinctrl_dev *pctrl_dev,
713 unsigned selector)
714{
715 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
716
717 return pinctrl->groups[selector].name;
718}
719
720static int cygnus_get_group_pins(struct pinctrl_dev *pctrl_dev,
721 unsigned selector, const unsigned **pins,
722 unsigned *num_pins)
723{
724 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
725
726 *pins = pinctrl->groups[selector].pins;
727 *num_pins = pinctrl->groups[selector].num_pins;
728
729 return 0;
730}
731
732static void cygnus_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
733 struct seq_file *s, unsigned offset)
734{
735 seq_printf(s, " %s", dev_name(pctrl_dev->dev));
736}
737
738static const struct pinctrl_ops cygnus_pinctrl_ops = {
739 .get_groups_count = cygnus_get_groups_count,
740 .get_group_name = cygnus_get_group_name,
741 .get_group_pins = cygnus_get_group_pins,
742 .pin_dbg_show = cygnus_pin_dbg_show,
743 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
d32f7fd3 744 .dt_free_map = pinctrl_utils_free_map,
cbd159ed
RJ		 745};
746
747static int cygnus_get_functions_count(struct pinctrl_dev *pctrl_dev)
748{
749 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
750
751 return pinctrl->num_functions;
752}
753
754static const char *cygnus_get_function_name(struct pinctrl_dev *pctrl_dev,
755 unsigned selector)
756{
757 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
758
759 return pinctrl->functions[selector].name;
760}
761
762static int cygnus_get_function_groups(struct pinctrl_dev *pctrl_dev,
763 unsigned selector,
764 const char * const **groups,
765 unsigned * const num_groups)
766{
767 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
768
769 *groups = pinctrl->functions[selector].groups;
770 *num_groups = pinctrl->functions[selector].num_groups;
771
772 return 0;
773}
774
775static int cygnus_pinmux_set(struct cygnus_pinctrl *pinctrl,
776 const struct cygnus_pin_function *func,
777 const struct cygnus_pin_group *grp,
778 struct cygnus_mux_log *mux_log)
779{
780 const struct cygnus_mux *mux = &grp->mux;
781 int i;
782 u32 val, mask = 0x7;
783 unsigned long flags;
784
785 for (i = 0; i < CYGNUS_NUM_IOMUX; i++) {
786 if (mux->offset != mux_log[i].mux.offset ||
787 mux->shift != mux_log[i].mux.shift)
788 continue;
789
790 /* match found if we reach here */
791
792 /* if this is a new configuration, just do it! */
793 if (!mux_log[i].is_configured)
794 break;
795
796 /*
797 * IOMUX has been configured previously and one is trying to
798 * configure it to a different function
799 */
800 if (mux_log[i].mux.alt != mux->alt) {
801 dev_err(pinctrl->dev,
802 "double configuration error detected!\n");
803 dev_err(pinctrl->dev, "func:%s grp:%s\n",
804 func->name, grp->name);
805 return -EINVAL;
806 } else {
807 /*
808 * One tries to configure it to the same function.
809 * Just quit and don't bother
810 */
811 return 0;
812 }
813 }
814
815 mux_log[i].mux.alt = mux->alt;
816 mux_log[i].is_configured = true;
817
818 spin_lock_irqsave(&pinctrl->lock, flags);
819
820 val = readl(pinctrl->base0 + grp->mux.offset);
821 val &= ~(mask << grp->mux.shift);
822 val |= grp->mux.alt << grp->mux.shift;
823 writel(val, pinctrl->base0 + grp->mux.offset);
824
825 spin_unlock_irqrestore(&pinctrl->lock, flags);
826
827 return 0;
828}
829
830static int cygnus_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,
831 unsigned func_select, unsigned grp_select)
832{
833 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
834 const struct cygnus_pin_function *func =
835 &pinctrl->functions[func_select];
836 const struct cygnus_pin_group *grp = &pinctrl->groups[grp_select];
837
838 dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
839 func_select, func->name, grp_select, grp->name);
840
841 dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",
842 grp->mux.offset, grp->mux.shift, grp->mux.alt);
843
844 return cygnus_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
845}
846
847static int cygnus_gpio_request_enable(struct pinctrl_dev *pctrl_dev,
848 struct pinctrl_gpio_range *range,
849 unsigned pin)
850{
851 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
852 const struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;
853 u32 val;
854 unsigned long flags;
855
856 /* not all pins support GPIO pinmux override */
857 if (!mux->is_supported)
858 return -ENOTSUPP;
859
860 spin_lock_irqsave(&pinctrl->lock, flags);
861
862 val = readl(pinctrl->base1 + mux->offset);
863 val |= 0x3 << mux->shift;
864 writel(val, pinctrl->base1 + mux->offset);
865
866 spin_unlock_irqrestore(&pinctrl->lock, flags);
867
868 dev_dbg(pctrl_dev->dev,
869 "gpio request enable pin=%u offset=0x%x shift=%u\n",
870 pin, mux->offset, mux->shift);
871
872 return 0;
873}
874
875static void cygnus_gpio_disable_free(struct pinctrl_dev *pctrl_dev,
876 struct pinctrl_gpio_range *range,
877 unsigned pin)
878{
879 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
880 struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;
881 u32 val;
882 unsigned long flags;
883
884 if (!mux->is_supported)
885 return;
886
887 spin_lock_irqsave(&pinctrl->lock, flags);
888
889 val = readl(pinctrl->base1 + mux->offset);
890 val &= ~(0x3 << mux->shift);
891 writel(val, pinctrl->base1 + mux->offset);
892
893 spin_unlock_irqrestore(&pinctrl->lock, flags);
894
895 dev_err(pctrl_dev->dev,
896 "gpio disable free pin=%u offset=0x%x shift=%u\n",
897 pin, mux->offset, mux->shift);
898}
899
900static const struct pinmux_ops cygnus_pinmux_ops = {
901 .get_functions_count = cygnus_get_functions_count,
902 .get_function_name = cygnus_get_function_name,
903 .get_function_groups = cygnus_get_function_groups,
904 .set_mux = cygnus_pinmux_set_mux,
905 .gpio_request_enable = cygnus_gpio_request_enable,
906 .gpio_disable_free = cygnus_gpio_disable_free,
907};
908
909static struct pinctrl_desc cygnus_pinctrl_desc = {
910 .name = "cygnus-pinmux",
911 .pctlops = &cygnus_pinctrl_ops,
912 .pmxops = &cygnus_pinmux_ops,
913};
914
915static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)
916{
917 struct cygnus_mux_log *log;
918 unsigned int i, j;
919
920 pinctrl->mux_log = devm_kcalloc(pinctrl->dev, CYGNUS_NUM_IOMUX,
921 sizeof(struct cygnus_mux_log),
922 GFP_KERNEL);
923 if (!pinctrl->mux_log)
924 return -ENOMEM;
925
cbd159ed
RJ		 926 for (i = 0; i < CYGNUS_NUM_IOMUX_REGS; i++) {
927 for (j = 0; j < CYGNUS_NUM_MUX_PER_REG; j++) {
928 log = &pinctrl->mux_log[i * CYGNUS_NUM_MUX_PER_REG
929 + j];
930 log->mux.offset = i * 4;
931 log->mux.shift = j * 4;
932 log->mux.alt = 0;
933 log->is_configured = false;
934 }
935 }
936
937 return 0;
938}
939
940static int cygnus_pinmux_probe(struct platform_device *pdev)
941{
942 struct cygnus_pinctrl *pinctrl;
cbd159ed
RJ		 943 int i, ret;
944 struct pinctrl_pin_desc *pins;
945 unsigned num_pins = ARRAY_SIZE(cygnus_pins);
946
947 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
948 if (!pinctrl)
949 return -ENOMEM;
950
951 pinctrl->dev = &pdev->dev;
952 platform_set_drvdata(pdev, pinctrl);
953 spin_lock_init(&pinctrl->lock);
954
4b024225 955 pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
cbd159ed
RJ		 956 if (IS_ERR(pinctrl->base0)) {
957 dev_err(&pdev->dev, "unable to map I/O space\n");
958 return PTR_ERR(pinctrl->base0);
959 }
960
4b024225 961 pinctrl->base1 = devm_platform_ioremap_resource(pdev, 1);
cbd159ed
RJ		 962 if (IS_ERR(pinctrl->base1)) {
963 dev_err(&pdev->dev, "unable to map I/O space\n");
964 return PTR_ERR(pinctrl->base1);
965 }
966
967 ret = cygnus_mux_log_init(pinctrl);
968 if (ret) {
969 dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
970 return ret;
971 }
972
973 pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
974 if (!pins)
975 return -ENOMEM;
976
977 for (i = 0; i < num_pins; i++) {
978 pins[i].number = cygnus_pins[i].pin;
979 pins[i].name = cygnus_pins[i].name;
980 pins[i].drv_data = &cygnus_pins[i].gpio_mux;
981 }
982
983 pinctrl->groups = cygnus_pin_groups;
984 pinctrl->num_groups = ARRAY_SIZE(cygnus_pin_groups);
985 pinctrl->functions = cygnus_pin_functions;
986 pinctrl->num_functions = ARRAY_SIZE(cygnus_pin_functions);
987 cygnus_pinctrl_desc.pins = pins;
988 cygnus_pinctrl_desc.npins = num_pins;
989
ead044ee 990 pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &cygnus_pinctrl_desc,
cbd159ed 991 pinctrl);
323de9ef 992 if (IS_ERR(pinctrl->pctl)) {
cbd159ed 993 dev_err(&pdev->dev, "unable to register Cygnus IOMUX pinctrl\n");
323de9ef 994 return PTR_ERR(pinctrl->pctl);
cbd159ed
RJ		 995 }
996
997 return 0;
998}
999
1000static const struct of_device_id cygnus_pinmux_of_match[] = {
1001 { .compatible = "brcm,cygnus-pinmux" },
1002 { }
1003};
1004
1005static struct platform_driver cygnus_pinmux_driver = {
1006 .driver = {
1007 .name = "cygnus-pinmux",
1008 .of_match_table = cygnus_pinmux_of_match,
1009 .suppress_bind_attrs = true,
1010 },
1011 .probe = cygnus_pinmux_probe,
1012};
1013
1014static int __init cygnus_pinmux_init(void)
1015{
1016 return platform_driver_register(&cygnus_pinmux_driver);
1017}
1018arch_initcall(cygnus_pinmux_init);
Linux 6.x block layer and io_uring tree(s)