Commit | Line | Data |
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a62c3677 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
e1b2dc70 SA |
2 | /* |
3 | * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) | |
4 | * | |
5 | * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren | |
6 | * | |
7 | * This driver is inspired by: | |
8 | * pinctrl-nomadik.c, please see original file for copyright information | |
9 | * pinctrl-tegra.c, please see original file for copyright information | |
e1b2dc70 SA |
10 | */ |
11 | ||
12 | #include <linux/bitmap.h> | |
13 | #include <linux/bug.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/err.h> | |
e19a5f79 | 17 | #include <linux/gpio/driver.h> |
e1b2dc70 SA |
18 | #include <linux/io.h> |
19 | #include <linux/irq.h> | |
20 | #include <linux/irqdesc.h> | |
34f46848 | 21 | #include <linux/init.h> |
e1b2dc70 SA |
22 | #include <linux/of_address.h> |
23 | #include <linux/of.h> | |
24 | #include <linux/of_irq.h> | |
25 | #include <linux/pinctrl/consumer.h> | |
26 | #include <linux/pinctrl/machine.h> | |
27 | #include <linux/pinctrl/pinconf.h> | |
28 | #include <linux/pinctrl/pinctrl.h> | |
29 | #include <linux/pinctrl/pinmux.h> | |
0de70495 | 30 | #include <linux/pinctrl/pinconf-generic.h> |
e1b2dc70 SA |
31 | #include <linux/platform_device.h> |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/spinlock.h> | |
35 | #include <linux/types.h> | |
0de70495 | 36 | #include <dt-bindings/pinctrl/bcm2835.h> |
e1b2dc70 SA |
37 | |
38 | #define MODULE_NAME "pinctrl-bcm2835" | |
39 | #define BCM2835_NUM_GPIOS 54 | |
b1d84a3d | 40 | #define BCM2711_NUM_GPIOS 58 |
e1b2dc70 | 41 | #define BCM2835_NUM_BANKS 2 |
00445b5d | 42 | #define BCM2835_NUM_IRQS 3 |
e1b2dc70 | 43 | |
e1b2dc70 SA |
44 | /* GPIO register offsets */ |
45 | #define GPFSEL0 0x0 /* Function Select */ | |
46 | #define GPSET0 0x1c /* Pin Output Set */ | |
47 | #define GPCLR0 0x28 /* Pin Output Clear */ | |
48 | #define GPLEV0 0x34 /* Pin Level */ | |
49 | #define GPEDS0 0x40 /* Pin Event Detect Status */ | |
50 | #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */ | |
51 | #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */ | |
52 | #define GPHEN0 0x64 /* Pin High Detect Enable */ | |
53 | #define GPLEN0 0x70 /* Pin Low Detect Enable */ | |
54 | #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */ | |
55 | #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */ | |
56 | #define GPPUD 0x94 /* Pin Pull-up/down Enable */ | |
57 | #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */ | |
e38a9a43 | 58 | #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */ |
e1b2dc70 SA |
59 | |
60 | #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4)) | |
61 | #define FSEL_SHIFT(p) (((p) % 10) * 3) | |
62 | #define GPIO_REG_OFFSET(p) ((p) / 32) | |
63 | #define GPIO_REG_SHIFT(p) ((p) % 32) | |
64 | ||
e38a9a43 SW |
65 | #define PUD_2711_MASK 0x3 |
66 | #define PUD_2711_REG_OFFSET(p) ((p) / 16) | |
67 | #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2) | |
68 | ||
b40ac08f NC |
69 | /* argument: bcm2835_pinconf_pull */ |
70 | #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1) | |
e1b2dc70 | 71 | |
e38a9a43 SW |
72 | #define BCM2711_PULL_NONE 0x0 |
73 | #define BCM2711_PULL_UP 0x1 | |
74 | #define BCM2711_PULL_DOWN 0x2 | |
75 | ||
e1b2dc70 SA |
76 | struct bcm2835_pinctrl { |
77 | struct device *dev; | |
78 | void __iomem *base; | |
e1b2dc70 SA |
79 | |
80 | /* note: locking assumes each bank will have its own unsigned long */ | |
81 | unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; | |
b1d84a3d | 82 | unsigned int irq_type[BCM2711_NUM_GPIOS]; |
e1b2dc70 SA |
83 | |
84 | struct pinctrl_dev *pctl_dev; | |
e1b2dc70 | 85 | struct gpio_chip gpio_chip; |
90bfaf02 | 86 | struct pinctrl_desc pctl_desc; |
e1b2dc70 SA |
87 | struct pinctrl_gpio_range gpio_range; |
88 | ||
3c7b30f7 | 89 | raw_spinlock_t irq_lock[BCM2835_NUM_BANKS]; |
e1b2dc70 SA |
90 | }; |
91 | ||
e1b2dc70 SA |
92 | /* pins are just named GPIO0..GPIO53 */ |
93 | #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) | |
e8ed912e | 94 | static struct pinctrl_pin_desc bcm2835_gpio_pins[] = { |
e1b2dc70 SA |
95 | BCM2835_GPIO_PIN(0), |
96 | BCM2835_GPIO_PIN(1), | |
97 | BCM2835_GPIO_PIN(2), | |
98 | BCM2835_GPIO_PIN(3), | |
99 | BCM2835_GPIO_PIN(4), | |
100 | BCM2835_GPIO_PIN(5), | |
101 | BCM2835_GPIO_PIN(6), | |
102 | BCM2835_GPIO_PIN(7), | |
103 | BCM2835_GPIO_PIN(8), | |
104 | BCM2835_GPIO_PIN(9), | |
105 | BCM2835_GPIO_PIN(10), | |
106 | BCM2835_GPIO_PIN(11), | |
107 | BCM2835_GPIO_PIN(12), | |
108 | BCM2835_GPIO_PIN(13), | |
109 | BCM2835_GPIO_PIN(14), | |
110 | BCM2835_GPIO_PIN(15), | |
111 | BCM2835_GPIO_PIN(16), | |
112 | BCM2835_GPIO_PIN(17), | |
113 | BCM2835_GPIO_PIN(18), | |
114 | BCM2835_GPIO_PIN(19), | |
115 | BCM2835_GPIO_PIN(20), | |
116 | BCM2835_GPIO_PIN(21), | |
117 | BCM2835_GPIO_PIN(22), | |
118 | BCM2835_GPIO_PIN(23), | |
119 | BCM2835_GPIO_PIN(24), | |
120 | BCM2835_GPIO_PIN(25), | |
121 | BCM2835_GPIO_PIN(26), | |
122 | BCM2835_GPIO_PIN(27), | |
123 | BCM2835_GPIO_PIN(28), | |
124 | BCM2835_GPIO_PIN(29), | |
125 | BCM2835_GPIO_PIN(30), | |
126 | BCM2835_GPIO_PIN(31), | |
127 | BCM2835_GPIO_PIN(32), | |
128 | BCM2835_GPIO_PIN(33), | |
129 | BCM2835_GPIO_PIN(34), | |
130 | BCM2835_GPIO_PIN(35), | |
131 | BCM2835_GPIO_PIN(36), | |
132 | BCM2835_GPIO_PIN(37), | |
133 | BCM2835_GPIO_PIN(38), | |
134 | BCM2835_GPIO_PIN(39), | |
135 | BCM2835_GPIO_PIN(40), | |
136 | BCM2835_GPIO_PIN(41), | |
137 | BCM2835_GPIO_PIN(42), | |
138 | BCM2835_GPIO_PIN(43), | |
139 | BCM2835_GPIO_PIN(44), | |
140 | BCM2835_GPIO_PIN(45), | |
141 | BCM2835_GPIO_PIN(46), | |
142 | BCM2835_GPIO_PIN(47), | |
143 | BCM2835_GPIO_PIN(48), | |
144 | BCM2835_GPIO_PIN(49), | |
145 | BCM2835_GPIO_PIN(50), | |
146 | BCM2835_GPIO_PIN(51), | |
147 | BCM2835_GPIO_PIN(52), | |
148 | BCM2835_GPIO_PIN(53), | |
b1d84a3d SW |
149 | BCM2835_GPIO_PIN(54), |
150 | BCM2835_GPIO_PIN(55), | |
151 | BCM2835_GPIO_PIN(56), | |
152 | BCM2835_GPIO_PIN(57), | |
e1b2dc70 SA |
153 | }; |
154 | ||
155 | /* one pin per group */ | |
156 | static const char * const bcm2835_gpio_groups[] = { | |
157 | "gpio0", | |
158 | "gpio1", | |
159 | "gpio2", | |
160 | "gpio3", | |
161 | "gpio4", | |
162 | "gpio5", | |
163 | "gpio6", | |
164 | "gpio7", | |
165 | "gpio8", | |
166 | "gpio9", | |
167 | "gpio10", | |
168 | "gpio11", | |
169 | "gpio12", | |
170 | "gpio13", | |
171 | "gpio14", | |
172 | "gpio15", | |
173 | "gpio16", | |
174 | "gpio17", | |
175 | "gpio18", | |
176 | "gpio19", | |
177 | "gpio20", | |
178 | "gpio21", | |
179 | "gpio22", | |
180 | "gpio23", | |
181 | "gpio24", | |
182 | "gpio25", | |
183 | "gpio26", | |
184 | "gpio27", | |
185 | "gpio28", | |
186 | "gpio29", | |
187 | "gpio30", | |
188 | "gpio31", | |
189 | "gpio32", | |
190 | "gpio33", | |
191 | "gpio34", | |
192 | "gpio35", | |
193 | "gpio36", | |
194 | "gpio37", | |
195 | "gpio38", | |
196 | "gpio39", | |
197 | "gpio40", | |
198 | "gpio41", | |
199 | "gpio42", | |
200 | "gpio43", | |
201 | "gpio44", | |
202 | "gpio45", | |
203 | "gpio46", | |
204 | "gpio47", | |
205 | "gpio48", | |
206 | "gpio49", | |
207 | "gpio50", | |
208 | "gpio51", | |
209 | "gpio52", | |
210 | "gpio53", | |
b1d84a3d SW |
211 | "gpio54", |
212 | "gpio55", | |
213 | "gpio56", | |
214 | "gpio57", | |
e1b2dc70 SA |
215 | }; |
216 | ||
217 | enum bcm2835_fsel { | |
e1b2dc70 SA |
218 | BCM2835_FSEL_COUNT = 8, |
219 | BCM2835_FSEL_MASK = 0x7, | |
220 | }; | |
221 | ||
222 | static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = { | |
223 | [BCM2835_FSEL_GPIO_IN] = "gpio_in", | |
224 | [BCM2835_FSEL_GPIO_OUT] = "gpio_out", | |
225 | [BCM2835_FSEL_ALT0] = "alt0", | |
226 | [BCM2835_FSEL_ALT1] = "alt1", | |
227 | [BCM2835_FSEL_ALT2] = "alt2", | |
228 | [BCM2835_FSEL_ALT3] = "alt3", | |
229 | [BCM2835_FSEL_ALT4] = "alt4", | |
230 | [BCM2835_FSEL_ALT5] = "alt5", | |
231 | }; | |
232 | ||
233 | static const char * const irq_type_names[] = { | |
234 | [IRQ_TYPE_NONE] = "none", | |
235 | [IRQ_TYPE_EDGE_RISING] = "edge-rising", | |
236 | [IRQ_TYPE_EDGE_FALLING] = "edge-falling", | |
237 | [IRQ_TYPE_EDGE_BOTH] = "edge-both", | |
238 | [IRQ_TYPE_LEVEL_HIGH] = "level-high", | |
239 | [IRQ_TYPE_LEVEL_LOW] = "level-low", | |
240 | }; | |
241 | ||
242 | static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) | |
243 | { | |
244 | return readl(pc->base + reg); | |
245 | } | |
246 | ||
247 | static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg, | |
248 | u32 val) | |
249 | { | |
250 | writel(val, pc->base + reg); | |
251 | } | |
252 | ||
253 | static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg, | |
254 | unsigned bit) | |
255 | { | |
256 | reg += GPIO_REG_OFFSET(bit) * 4; | |
257 | return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1; | |
258 | } | |
259 | ||
260 | /* note NOT a read/modify/write cycle */ | |
261 | static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc, | |
262 | unsigned reg, unsigned bit) | |
263 | { | |
264 | reg += GPIO_REG_OFFSET(bit) * 4; | |
265 | bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit))); | |
266 | } | |
267 | ||
268 | static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get( | |
269 | struct bcm2835_pinctrl *pc, unsigned pin) | |
270 | { | |
271 | u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); | |
272 | enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; | |
273 | ||
274 | dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin, | |
275 | bcm2835_functions[status]); | |
276 | ||
277 | return status; | |
278 | } | |
279 | ||
280 | static inline void bcm2835_pinctrl_fsel_set( | |
281 | struct bcm2835_pinctrl *pc, unsigned pin, | |
282 | enum bcm2835_fsel fsel) | |
283 | { | |
284 | u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); | |
285 | enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; | |
286 | ||
287 | dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin, | |
288 | bcm2835_functions[cur]); | |
289 | ||
290 | if (cur == fsel) | |
291 | return; | |
292 | ||
293 | if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) { | |
294 | /* always transition through GPIO_IN */ | |
295 | val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); | |
296 | val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin); | |
297 | ||
298 | dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin, | |
299 | bcm2835_functions[BCM2835_FSEL_GPIO_IN]); | |
300 | bcm2835_gpio_wr(pc, FSEL_REG(pin), val); | |
301 | } | |
302 | ||
303 | val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); | |
304 | val |= fsel << FSEL_SHIFT(pin); | |
305 | ||
306 | dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin, | |
307 | bcm2835_functions[fsel]); | |
308 | bcm2835_gpio_wr(pc, FSEL_REG(pin), val); | |
309 | } | |
310 | ||
e1b2dc70 SA |
311 | static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
312 | { | |
313 | return pinctrl_gpio_direction_input(chip->base + offset); | |
314 | } | |
315 | ||
316 | static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) | |
317 | { | |
e19a5f79 | 318 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); |
e1b2dc70 SA |
319 | |
320 | return bcm2835_gpio_get_bit(pc, GPLEV0, offset); | |
321 | } | |
322 | ||
20b3d2a7 SW |
323 | static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
324 | { | |
325 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
326 | enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); | |
327 | ||
328 | /* Alternative function doesn't clearly provide a direction */ | |
329 | if (fsel > BCM2835_FSEL_GPIO_OUT) | |
330 | return -EINVAL; | |
331 | ||
3c827873 MV |
332 | if (fsel == BCM2835_FSEL_GPIO_IN) |
333 | return GPIO_LINE_DIRECTION_IN; | |
334 | ||
335 | return GPIO_LINE_DIRECTION_OUT; | |
20b3d2a7 SW |
336 | } |
337 | ||
e1b2dc70 SA |
338 | static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
339 | { | |
e19a5f79 | 340 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); |
e1b2dc70 SA |
341 | |
342 | bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); | |
343 | } | |
344 | ||
4c02cba1 SW |
345 | static int bcm2835_gpio_direction_output(struct gpio_chip *chip, |
346 | unsigned offset, int value) | |
347 | { | |
348 | bcm2835_gpio_set(chip, offset, value); | |
349 | return pinctrl_gpio_direction_output(chip->base + offset); | |
350 | } | |
351 | ||
531bcf73 | 352 | static const struct gpio_chip bcm2835_gpio_chip = { |
e1b2dc70 SA |
353 | .label = MODULE_NAME, |
354 | .owner = THIS_MODULE, | |
98c85d58 JG |
355 | .request = gpiochip_generic_request, |
356 | .free = gpiochip_generic_free, | |
e1b2dc70 SA |
357 | .direction_input = bcm2835_gpio_direction_input, |
358 | .direction_output = bcm2835_gpio_direction_output, | |
20b3d2a7 | 359 | .get_direction = bcm2835_gpio_get_direction, |
e1b2dc70 SA |
360 | .get = bcm2835_gpio_get, |
361 | .set = bcm2835_gpio_set, | |
b6e5531c | 362 | .set_config = gpiochip_generic_config, |
e1b2dc70 SA |
363 | .base = -1, |
364 | .ngpio = BCM2835_NUM_GPIOS, | |
9fb1f39e | 365 | .can_sleep = false, |
e1b2dc70 SA |
366 | }; |
367 | ||
b1d84a3d SW |
368 | static const struct gpio_chip bcm2711_gpio_chip = { |
369 | .label = "pinctrl-bcm2711", | |
370 | .owner = THIS_MODULE, | |
371 | .request = gpiochip_generic_request, | |
372 | .free = gpiochip_generic_free, | |
373 | .direction_input = bcm2835_gpio_direction_input, | |
374 | .direction_output = bcm2835_gpio_direction_output, | |
375 | .get_direction = bcm2835_gpio_get_direction, | |
376 | .get = bcm2835_gpio_get, | |
377 | .set = bcm2835_gpio_set, | |
378 | .set_config = gpiochip_generic_config, | |
379 | .base = -1, | |
380 | .ngpio = BCM2711_NUM_GPIOS, | |
381 | .can_sleep = false, | |
382 | }; | |
383 | ||
85ae9e51 LW |
384 | static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, |
385 | unsigned int bank, u32 mask) | |
e1b2dc70 | 386 | { |
e1b2dc70 SA |
387 | unsigned long events; |
388 | unsigned offset; | |
389 | unsigned gpio; | |
e1b2dc70 SA |
390 | |
391 | events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); | |
00445b5d | 392 | events &= mask; |
e1b2dc70 SA |
393 | events &= pc->enabled_irq_map[bank]; |
394 | for_each_set_bit(offset, &events, 32) { | |
395 | gpio = (32 * bank) + offset; | |
9e9355bb | 396 | generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain, |
85ae9e51 | 397 | gpio)); |
e1b2dc70 | 398 | } |
00445b5d PE |
399 | } |
400 | ||
85ae9e51 | 401 | static void bcm2835_gpio_irq_handler(struct irq_desc *desc) |
00445b5d | 402 | { |
85ae9e51 LW |
403 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
404 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
405 | struct irq_chip *host_chip = irq_desc_get_chip(desc); | |
406 | int irq = irq_desc_get_irq(desc); | |
407 | int group; | |
408 | int i; | |
409 | ||
73345a18 LW |
410 | for (i = 0; i < BCM2835_NUM_IRQS; i++) { |
411 | if (chip->irq.parents[i] == irq) { | |
0d885e9d | 412 | group = i; |
85ae9e51 LW |
413 | break; |
414 | } | |
415 | } | |
416 | /* This should not happen, every IRQ has a bank */ | |
73345a18 | 417 | if (i == BCM2835_NUM_IRQS) |
85ae9e51 | 418 | BUG(); |
00445b5d | 419 | |
85ae9e51 LW |
420 | chained_irq_enter(host_chip, desc); |
421 | ||
422 | switch (group) { | |
00445b5d | 423 | case 0: /* IRQ0 covers GPIOs 0-27 */ |
85ae9e51 | 424 | bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff); |
00445b5d PE |
425 | break; |
426 | case 1: /* IRQ1 covers GPIOs 28-45 */ | |
85ae9e51 LW |
427 | bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000); |
428 | bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff); | |
00445b5d | 429 | break; |
b1d84a3d | 430 | case 2: /* IRQ2 covers GPIOs 46-57 */ |
85ae9e51 | 431 | bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000); |
00445b5d PE |
432 | break; |
433 | } | |
434 | ||
85ae9e51 | 435 | chained_irq_exit(host_chip, desc); |
e1b2dc70 SA |
436 | } |
437 | ||
438 | static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, | |
439 | unsigned reg, unsigned offset, bool enable) | |
440 | { | |
441 | u32 value; | |
442 | reg += GPIO_REG_OFFSET(offset) * 4; | |
443 | value = bcm2835_gpio_rd(pc, reg); | |
444 | if (enable) | |
445 | value |= BIT(GPIO_REG_SHIFT(offset)); | |
446 | else | |
447 | value &= ~(BIT(GPIO_REG_SHIFT(offset))); | |
448 | bcm2835_gpio_wr(pc, reg, value); | |
449 | } | |
450 | ||
451 | /* fast path for IRQ handler */ | |
452 | static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, | |
453 | unsigned offset, bool enable) | |
454 | { | |
455 | switch (pc->irq_type[offset]) { | |
456 | case IRQ_TYPE_EDGE_RISING: | |
457 | __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); | |
458 | break; | |
459 | ||
460 | case IRQ_TYPE_EDGE_FALLING: | |
461 | __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); | |
462 | break; | |
463 | ||
464 | case IRQ_TYPE_EDGE_BOTH: | |
465 | __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); | |
466 | __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); | |
467 | break; | |
468 | ||
469 | case IRQ_TYPE_LEVEL_HIGH: | |
470 | __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable); | |
471 | break; | |
472 | ||
473 | case IRQ_TYPE_LEVEL_LOW: | |
474 | __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable); | |
475 | break; | |
476 | } | |
477 | } | |
478 | ||
479 | static void bcm2835_gpio_irq_enable(struct irq_data *data) | |
480 | { | |
85ae9e51 LW |
481 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); |
482 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
e1b2dc70 SA |
483 | unsigned gpio = irqd_to_hwirq(data); |
484 | unsigned offset = GPIO_REG_SHIFT(gpio); | |
485 | unsigned bank = GPIO_REG_OFFSET(gpio); | |
486 | unsigned long flags; | |
487 | ||
3c7b30f7 | 488 | raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); |
e1b2dc70 SA |
489 | set_bit(offset, &pc->enabled_irq_map[bank]); |
490 | bcm2835_gpio_irq_config(pc, gpio, true); | |
3c7b30f7 | 491 | raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); |
e1b2dc70 SA |
492 | } |
493 | ||
494 | static void bcm2835_gpio_irq_disable(struct irq_data *data) | |
495 | { | |
85ae9e51 LW |
496 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); |
497 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
e1b2dc70 SA |
498 | unsigned gpio = irqd_to_hwirq(data); |
499 | unsigned offset = GPIO_REG_SHIFT(gpio); | |
500 | unsigned bank = GPIO_REG_OFFSET(gpio); | |
501 | unsigned long flags; | |
502 | ||
3c7b30f7 | 503 | raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); |
e1b2dc70 | 504 | bcm2835_gpio_irq_config(pc, gpio, false); |
714b1dd8 JB |
505 | /* Clear events that were latched prior to clearing event sources */ |
506 | bcm2835_gpio_set_bit(pc, GPEDS0, gpio); | |
e1b2dc70 | 507 | clear_bit(offset, &pc->enabled_irq_map[bank]); |
3c7b30f7 | 508 | raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); |
e1b2dc70 SA |
509 | } |
510 | ||
511 | static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc, | |
512 | unsigned offset, unsigned int type) | |
513 | { | |
514 | switch (type) { | |
515 | case IRQ_TYPE_NONE: | |
516 | case IRQ_TYPE_EDGE_RISING: | |
517 | case IRQ_TYPE_EDGE_FALLING: | |
518 | case IRQ_TYPE_EDGE_BOTH: | |
519 | case IRQ_TYPE_LEVEL_HIGH: | |
520 | case IRQ_TYPE_LEVEL_LOW: | |
521 | pc->irq_type[offset] = type; | |
522 | break; | |
523 | ||
524 | default: | |
525 | return -EINVAL; | |
526 | } | |
527 | return 0; | |
528 | } | |
529 | ||
530 | /* slower path for reconfiguring IRQ type */ | |
531 | static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc, | |
532 | unsigned offset, unsigned int type) | |
533 | { | |
534 | switch (type) { | |
535 | case IRQ_TYPE_NONE: | |
536 | if (pc->irq_type[offset] != type) { | |
537 | bcm2835_gpio_irq_config(pc, offset, false); | |
538 | pc->irq_type[offset] = type; | |
539 | } | |
540 | break; | |
541 | ||
542 | case IRQ_TYPE_EDGE_RISING: | |
543 | if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { | |
544 | /* RISING already enabled, disable FALLING */ | |
545 | pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; | |
546 | bcm2835_gpio_irq_config(pc, offset, false); | |
547 | pc->irq_type[offset] = type; | |
548 | } else if (pc->irq_type[offset] != type) { | |
549 | bcm2835_gpio_irq_config(pc, offset, false); | |
550 | pc->irq_type[offset] = type; | |
551 | bcm2835_gpio_irq_config(pc, offset, true); | |
552 | } | |
553 | break; | |
554 | ||
555 | case IRQ_TYPE_EDGE_FALLING: | |
556 | if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { | |
557 | /* FALLING already enabled, disable RISING */ | |
558 | pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; | |
559 | bcm2835_gpio_irq_config(pc, offset, false); | |
560 | pc->irq_type[offset] = type; | |
561 | } else if (pc->irq_type[offset] != type) { | |
562 | bcm2835_gpio_irq_config(pc, offset, false); | |
563 | pc->irq_type[offset] = type; | |
564 | bcm2835_gpio_irq_config(pc, offset, true); | |
565 | } | |
566 | break; | |
567 | ||
568 | case IRQ_TYPE_EDGE_BOTH: | |
569 | if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) { | |
570 | /* RISING already enabled, enable FALLING too */ | |
571 | pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; | |
572 | bcm2835_gpio_irq_config(pc, offset, true); | |
573 | pc->irq_type[offset] = type; | |
574 | } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) { | |
575 | /* FALLING already enabled, enable RISING too */ | |
576 | pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; | |
577 | bcm2835_gpio_irq_config(pc, offset, true); | |
578 | pc->irq_type[offset] = type; | |
579 | } else if (pc->irq_type[offset] != type) { | |
580 | bcm2835_gpio_irq_config(pc, offset, false); | |
581 | pc->irq_type[offset] = type; | |
582 | bcm2835_gpio_irq_config(pc, offset, true); | |
583 | } | |
584 | break; | |
585 | ||
586 | case IRQ_TYPE_LEVEL_HIGH: | |
587 | case IRQ_TYPE_LEVEL_LOW: | |
588 | if (pc->irq_type[offset] != type) { | |
589 | bcm2835_gpio_irq_config(pc, offset, false); | |
590 | pc->irq_type[offset] = type; | |
591 | bcm2835_gpio_irq_config(pc, offset, true); | |
592 | } | |
593 | break; | |
594 | ||
595 | default: | |
596 | return -EINVAL; | |
597 | } | |
598 | return 0; | |
599 | } | |
600 | ||
601 | static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) | |
602 | { | |
85ae9e51 LW |
603 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); |
604 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
e1b2dc70 SA |
605 | unsigned gpio = irqd_to_hwirq(data); |
606 | unsigned offset = GPIO_REG_SHIFT(gpio); | |
607 | unsigned bank = GPIO_REG_OFFSET(gpio); | |
608 | unsigned long flags; | |
609 | int ret; | |
610 | ||
3c7b30f7 | 611 | raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); |
e1b2dc70 SA |
612 | |
613 | if (test_bit(offset, &pc->enabled_irq_map[bank])) | |
614 | ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type); | |
615 | else | |
616 | ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); | |
617 | ||
b8a19382 | 618 | if (type & IRQ_TYPE_EDGE_BOTH) |
1aa74fd0 | 619 | irq_set_handler_locked(data, handle_edge_irq); |
b8a19382 | 620 | else |
1aa74fd0 | 621 | irq_set_handler_locked(data, handle_level_irq); |
b8a19382 | 622 | |
3c7b30f7 | 623 | raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); |
e1b2dc70 SA |
624 | |
625 | return ret; | |
626 | } | |
627 | ||
b8a19382 CK |
628 | static void bcm2835_gpio_irq_ack(struct irq_data *data) |
629 | { | |
85ae9e51 LW |
630 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); |
631 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
b8a19382 CK |
632 | unsigned gpio = irqd_to_hwirq(data); |
633 | ||
634 | bcm2835_gpio_set_bit(pc, GPEDS0, gpio); | |
635 | } | |
636 | ||
e1b2dc70 SA |
637 | static struct irq_chip bcm2835_gpio_irq_chip = { |
638 | .name = MODULE_NAME, | |
639 | .irq_enable = bcm2835_gpio_irq_enable, | |
640 | .irq_disable = bcm2835_gpio_irq_disable, | |
641 | .irq_set_type = bcm2835_gpio_irq_set_type, | |
b8a19382 CK |
642 | .irq_ack = bcm2835_gpio_irq_ack, |
643 | .irq_mask = bcm2835_gpio_irq_disable, | |
644 | .irq_unmask = bcm2835_gpio_irq_enable, | |
e1b2dc70 SA |
645 | }; |
646 | ||
647 | static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) | |
648 | { | |
b1d84a3d | 649 | return BCM2835_NUM_GPIOS; |
e1b2dc70 SA |
650 | } |
651 | ||
652 | static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev, | |
653 | unsigned selector) | |
654 | { | |
655 | return bcm2835_gpio_groups[selector]; | |
656 | } | |
657 | ||
658 | static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev, | |
659 | unsigned selector, | |
660 | const unsigned **pins, | |
661 | unsigned *num_pins) | |
662 | { | |
663 | *pins = &bcm2835_gpio_pins[selector].number; | |
664 | *num_pins = 1; | |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
669 | static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, | |
670 | struct seq_file *s, | |
671 | unsigned offset) | |
672 | { | |
673 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
85ae9e51 | 674 | struct gpio_chip *chip = &pc->gpio_chip; |
e1b2dc70 SA |
675 | enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); |
676 | const char *fname = bcm2835_functions[fsel]; | |
677 | int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset); | |
f0fbe7bc | 678 | int irq = irq_find_mapping(chip->irq.domain, offset); |
e1b2dc70 SA |
679 | |
680 | seq_printf(s, "function %s in %s; irq %d (%s)", | |
681 | fname, value ? "hi" : "lo", | |
682 | irq, irq_type_names[pc->irq_type[offset]]); | |
683 | } | |
684 | ||
685 | static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev, | |
686 | struct pinctrl_map *maps, unsigned num_maps) | |
687 | { | |
688 | int i; | |
689 | ||
690 | for (i = 0; i < num_maps; i++) | |
691 | if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN) | |
692 | kfree(maps[i].data.configs.configs); | |
693 | ||
694 | kfree(maps); | |
695 | } | |
696 | ||
697 | static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc, | |
698 | struct device_node *np, u32 pin, u32 fnum, | |
699 | struct pinctrl_map **maps) | |
700 | { | |
701 | struct pinctrl_map *map = *maps; | |
702 | ||
703 | if (fnum >= ARRAY_SIZE(bcm2835_functions)) { | |
f5292d06 | 704 | dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum); |
e1b2dc70 SA |
705 | return -EINVAL; |
706 | } | |
707 | ||
708 | map->type = PIN_MAP_TYPE_MUX_GROUP; | |
709 | map->data.mux.group = bcm2835_gpio_groups[pin]; | |
710 | map->data.mux.function = bcm2835_functions[fnum]; | |
711 | (*maps)++; | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
716 | static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, | |
717 | struct device_node *np, u32 pin, u32 pull, | |
718 | struct pinctrl_map **maps) | |
719 | { | |
720 | struct pinctrl_map *map = *maps; | |
721 | unsigned long *configs; | |
722 | ||
723 | if (pull > 2) { | |
f5292d06 | 724 | dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull); |
e1b2dc70 SA |
725 | return -EINVAL; |
726 | } | |
727 | ||
728 | configs = kzalloc(sizeof(*configs), GFP_KERNEL); | |
729 | if (!configs) | |
730 | return -ENOMEM; | |
0de70495 | 731 | configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull); |
e1b2dc70 SA |
732 | |
733 | map->type = PIN_MAP_TYPE_CONFIGS_PIN; | |
734 | map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name; | |
735 | map->data.configs.configs = configs; | |
736 | map->data.configs.num_configs = 1; | |
737 | (*maps)++; | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
e1b2dc70 SA |
742 | static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, |
743 | struct device_node *np, | |
0de70495 | 744 | struct pinctrl_map **map, unsigned int *num_maps) |
e1b2dc70 SA |
745 | { |
746 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
747 | struct property *pins, *funcs, *pulls; | |
748 | int num_pins, num_funcs, num_pulls, maps_per_pin; | |
749 | struct pinctrl_map *maps, *cur_map; | |
750 | int i, err; | |
751 | u32 pin, func, pull; | |
752 | ||
0de70495 MC |
753 | /* Check for generic binding in this node */ |
754 | err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps); | |
755 | if (err || *num_maps) | |
756 | return err; | |
757 | ||
758 | /* Generic binding did not find anything continue with legacy parse */ | |
e1b2dc70 SA |
759 | pins = of_find_property(np, "brcm,pins", NULL); |
760 | if (!pins) { | |
f5292d06 | 761 | dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np); |
e1b2dc70 SA |
762 | return -EINVAL; |
763 | } | |
764 | ||
765 | funcs = of_find_property(np, "brcm,function", NULL); | |
766 | pulls = of_find_property(np, "brcm,pull", NULL); | |
767 | ||
768 | if (!funcs && !pulls) { | |
769 | dev_err(pc->dev, | |
f5292d06 RH |
770 | "%pOF: neither brcm,function nor brcm,pull specified\n", |
771 | np); | |
e1b2dc70 SA |
772 | return -EINVAL; |
773 | } | |
774 | ||
775 | num_pins = pins->length / 4; | |
776 | num_funcs = funcs ? (funcs->length / 4) : 0; | |
777 | num_pulls = pulls ? (pulls->length / 4) : 0; | |
778 | ||
779 | if (num_funcs > 1 && num_funcs != num_pins) { | |
780 | dev_err(pc->dev, | |
f5292d06 RH |
781 | "%pOF: brcm,function must have 1 or %d entries\n", |
782 | np, num_pins); | |
e1b2dc70 SA |
783 | return -EINVAL; |
784 | } | |
785 | ||
786 | if (num_pulls > 1 && num_pulls != num_pins) { | |
787 | dev_err(pc->dev, | |
f5292d06 RH |
788 | "%pOF: brcm,pull must have 1 or %d entries\n", |
789 | np, num_pins); | |
e1b2dc70 SA |
790 | return -EINVAL; |
791 | } | |
792 | ||
793 | maps_per_pin = 0; | |
794 | if (num_funcs) | |
795 | maps_per_pin++; | |
796 | if (num_pulls) | |
797 | maps_per_pin++; | |
6396bb22 KC |
798 | cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps), |
799 | GFP_KERNEL); | |
e1b2dc70 SA |
800 | if (!maps) |
801 | return -ENOMEM; | |
802 | ||
803 | for (i = 0; i < num_pins; i++) { | |
ce63d6d4 SW |
804 | err = of_property_read_u32_index(np, "brcm,pins", i, &pin); |
805 | if (err) | |
806 | goto out; | |
b1d84a3d | 807 | if (pin >= pc->pctl_desc.npins) { |
f5292d06 RH |
808 | dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n", |
809 | np, pin); | |
e1b2dc70 SA |
810 | err = -EINVAL; |
811 | goto out; | |
812 | } | |
813 | ||
814 | if (num_funcs) { | |
ce63d6d4 SW |
815 | err = of_property_read_u32_index(np, "brcm,function", |
816 | (num_funcs > 1) ? i : 0, &func); | |
817 | if (err) | |
818 | goto out; | |
e1b2dc70 SA |
819 | err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin, |
820 | func, &cur_map); | |
821 | if (err) | |
822 | goto out; | |
823 | } | |
824 | if (num_pulls) { | |
ce63d6d4 | 825 | err = of_property_read_u32_index(np, "brcm,pull", |
2c7e3306 | 826 | (num_pulls > 1) ? i : 0, &pull); |
ce63d6d4 SW |
827 | if (err) |
828 | goto out; | |
e1b2dc70 SA |
829 | err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin, |
830 | pull, &cur_map); | |
831 | if (err) | |
832 | goto out; | |
833 | } | |
834 | } | |
835 | ||
836 | *map = maps; | |
837 | *num_maps = num_pins * maps_per_pin; | |
838 | ||
839 | return 0; | |
840 | ||
841 | out: | |
53653c6b | 842 | bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin); |
e1b2dc70 SA |
843 | return err; |
844 | } | |
845 | ||
022ab148 | 846 | static const struct pinctrl_ops bcm2835_pctl_ops = { |
e1b2dc70 SA |
847 | .get_groups_count = bcm2835_pctl_get_groups_count, |
848 | .get_group_name = bcm2835_pctl_get_group_name, | |
849 | .get_group_pins = bcm2835_pctl_get_group_pins, | |
850 | .pin_dbg_show = bcm2835_pctl_pin_dbg_show, | |
851 | .dt_node_to_map = bcm2835_pctl_dt_node_to_map, | |
852 | .dt_free_map = bcm2835_pctl_dt_free_map, | |
853 | }; | |
854 | ||
ccca1ad5 PE |
855 | static int bcm2835_pmx_free(struct pinctrl_dev *pctldev, |
856 | unsigned offset) | |
857 | { | |
858 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
859 | ||
860 | /* disable by setting to GPIO_IN */ | |
861 | bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); | |
862 | return 0; | |
863 | } | |
864 | ||
e1b2dc70 SA |
865 | static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev) |
866 | { | |
867 | return BCM2835_FSEL_COUNT; | |
868 | } | |
869 | ||
870 | static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev, | |
871 | unsigned selector) | |
872 | { | |
873 | return bcm2835_functions[selector]; | |
874 | } | |
875 | ||
876 | static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev, | |
877 | unsigned selector, | |
878 | const char * const **groups, | |
879 | unsigned * const num_groups) | |
880 | { | |
881 | /* every pin can do every function */ | |
882 | *groups = bcm2835_gpio_groups; | |
b1d84a3d | 883 | *num_groups = BCM2835_NUM_GPIOS; |
e1b2dc70 SA |
884 | |
885 | return 0; | |
886 | } | |
887 | ||
03e9f0ca | 888 | static int bcm2835_pmx_set(struct pinctrl_dev *pctldev, |
e1b2dc70 SA |
889 | unsigned func_selector, |
890 | unsigned group_selector) | |
891 | { | |
892 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
893 | ||
894 | bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector); | |
895 | ||
896 | return 0; | |
897 | } | |
898 | ||
e1b2dc70 SA |
899 | static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, |
900 | struct pinctrl_gpio_range *range, | |
901 | unsigned offset) | |
902 | { | |
903 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
904 | ||
905 | /* disable by setting to GPIO_IN */ | |
906 | bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); | |
907 | } | |
908 | ||
909 | static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
910 | struct pinctrl_gpio_range *range, | |
911 | unsigned offset, | |
912 | bool input) | |
913 | { | |
914 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
915 | enum bcm2835_fsel fsel = input ? | |
916 | BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT; | |
917 | ||
918 | bcm2835_pinctrl_fsel_set(pc, offset, fsel); | |
919 | ||
920 | return 0; | |
921 | } | |
922 | ||
022ab148 | 923 | static const struct pinmux_ops bcm2835_pmx_ops = { |
ccca1ad5 | 924 | .free = bcm2835_pmx_free, |
e1b2dc70 SA |
925 | .get_functions_count = bcm2835_pmx_get_functions_count, |
926 | .get_function_name = bcm2835_pmx_get_function_name, | |
927 | .get_function_groups = bcm2835_pmx_get_function_groups, | |
03e9f0ca | 928 | .set_mux = bcm2835_pmx_set, |
e1b2dc70 SA |
929 | .gpio_disable_free = bcm2835_pmx_gpio_disable_free, |
930 | .gpio_set_direction = bcm2835_pmx_gpio_set_direction, | |
931 | }; | |
932 | ||
933 | static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, | |
934 | unsigned pin, unsigned long *config) | |
935 | { | |
936 | /* No way to read back config in HW */ | |
937 | return -ENOTSUPP; | |
938 | } | |
939 | ||
0de70495 MC |
940 | static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc, |
941 | unsigned int pin, unsigned int arg) | |
942 | { | |
943 | u32 off, bit; | |
944 | ||
945 | off = GPIO_REG_OFFSET(pin); | |
946 | bit = GPIO_REG_SHIFT(pin); | |
947 | ||
948 | bcm2835_gpio_wr(pc, GPPUD, arg & 3); | |
949 | /* | |
950 | * BCM2835 datasheet say to wait 150 cycles, but not of what. | |
951 | * But the VideoCore firmware delay for this operation | |
952 | * based nearly on the same amount of VPU cycles and this clock | |
953 | * runs at 250 MHz. | |
954 | */ | |
955 | udelay(1); | |
956 | bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); | |
957 | udelay(1); | |
958 | bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); | |
959 | } | |
960 | ||
e1b2dc70 | 961 | static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, |
0de70495 MC |
962 | unsigned int pin, unsigned long *configs, |
963 | unsigned int num_configs) | |
e1b2dc70 SA |
964 | { |
965 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
0de70495 | 966 | u32 param, arg; |
03b054e9 | 967 | int i; |
e1b2dc70 | 968 | |
03b054e9 | 969 | for (i = 0; i < num_configs; i++) { |
0de70495 MC |
970 | param = pinconf_to_config_param(configs[i]); |
971 | arg = pinconf_to_config_argument(configs[i]); | |
972 | ||
973 | switch (param) { | |
974 | /* Set legacy brcm,pull */ | |
975 | case BCM2835_PINCONF_PARAM_PULL: | |
976 | bcm2835_pull_config_set(pc, pin, arg); | |
977 | break; | |
978 | ||
979 | /* Set pull generic bindings */ | |
980 | case PIN_CONFIG_BIAS_DISABLE: | |
981 | bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF); | |
982 | break; | |
983 | ||
984 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
985 | bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN); | |
986 | break; | |
987 | ||
988 | case PIN_CONFIG_BIAS_PULL_UP: | |
989 | bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP); | |
990 | break; | |
03b054e9 | 991 | |
90b60552 MC |
992 | /* Set output-high or output-low */ |
993 | case PIN_CONFIG_OUTPUT: | |
994 | bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); | |
995 | break; | |
996 | ||
0de70495 | 997 | default: |
b6e5531c | 998 | return -ENOTSUPP; |
03b054e9 | 999 | |
0de70495 | 1000 | } /* switch param type */ |
03b054e9 | 1001 | } /* for each config */ |
e1b2dc70 SA |
1002 | |
1003 | return 0; | |
1004 | } | |
1005 | ||
022ab148 | 1006 | static const struct pinconf_ops bcm2835_pinconf_ops = { |
1cb66f08 | 1007 | .is_generic = true, |
e1b2dc70 SA |
1008 | .pin_config_get = bcm2835_pinconf_get, |
1009 | .pin_config_set = bcm2835_pinconf_set, | |
1010 | }; | |
1011 | ||
e38a9a43 SW |
1012 | static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc, |
1013 | unsigned int pin, unsigned int arg) | |
1014 | { | |
1015 | u32 shifter; | |
1016 | u32 value; | |
1017 | u32 off; | |
1018 | ||
1019 | off = PUD_2711_REG_OFFSET(pin); | |
1020 | shifter = PUD_2711_REG_SHIFT(pin); | |
1021 | ||
1022 | value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4)); | |
1023 | value &= ~(PUD_2711_MASK << shifter); | |
1024 | value |= (arg << shifter); | |
1025 | bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value); | |
1026 | } | |
1027 | ||
1028 | static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev, | |
1029 | unsigned int pin, unsigned long *configs, | |
1030 | unsigned int num_configs) | |
1031 | { | |
1032 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
1033 | u32 param, arg; | |
1034 | int i; | |
1035 | ||
1036 | for (i = 0; i < num_configs; i++) { | |
1037 | param = pinconf_to_config_param(configs[i]); | |
1038 | arg = pinconf_to_config_argument(configs[i]); | |
1039 | ||
1040 | switch (param) { | |
1041 | /* convert legacy brcm,pull */ | |
1042 | case BCM2835_PINCONF_PARAM_PULL: | |
1043 | if (arg == BCM2835_PUD_UP) | |
1044 | arg = BCM2711_PULL_UP; | |
1045 | else if (arg == BCM2835_PUD_DOWN) | |
1046 | arg = BCM2711_PULL_DOWN; | |
1047 | else | |
1048 | arg = BCM2711_PULL_NONE; | |
1049 | ||
1050 | bcm2711_pull_config_set(pc, pin, arg); | |
1051 | break; | |
1052 | ||
1053 | /* Set pull generic bindings */ | |
1054 | case PIN_CONFIG_BIAS_DISABLE: | |
1055 | bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE); | |
1056 | break; | |
1057 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
1058 | bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN); | |
1059 | break; | |
1060 | case PIN_CONFIG_BIAS_PULL_UP: | |
1061 | bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP); | |
1062 | break; | |
1063 | ||
1064 | /* Set output-high or output-low */ | |
1065 | case PIN_CONFIG_OUTPUT: | |
1066 | bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); | |
1067 | break; | |
1068 | ||
1069 | default: | |
1070 | return -ENOTSUPP; | |
1071 | } | |
1072 | } /* for each config */ | |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
1077 | static const struct pinconf_ops bcm2711_pinconf_ops = { | |
1078 | .is_generic = true, | |
1079 | .pin_config_get = bcm2835_pinconf_get, | |
1080 | .pin_config_set = bcm2711_pinconf_set, | |
1081 | }; | |
1082 | ||
90bfaf02 | 1083 | static const struct pinctrl_desc bcm2835_pinctrl_desc = { |
e1b2dc70 SA |
1084 | .name = MODULE_NAME, |
1085 | .pins = bcm2835_gpio_pins, | |
b1d84a3d | 1086 | .npins = BCM2835_NUM_GPIOS, |
e1b2dc70 SA |
1087 | .pctlops = &bcm2835_pctl_ops, |
1088 | .pmxops = &bcm2835_pmx_ops, | |
1089 | .confops = &bcm2835_pinconf_ops, | |
1090 | .owner = THIS_MODULE, | |
1091 | }; | |
1092 | ||
90bfaf02 | 1093 | static const struct pinctrl_desc bcm2711_pinctrl_desc = { |
b1d84a3d | 1094 | .name = "pinctrl-bcm2711", |
90bfaf02 | 1095 | .pins = bcm2835_gpio_pins, |
b1d84a3d | 1096 | .npins = BCM2711_NUM_GPIOS, |
90bfaf02 SW |
1097 | .pctlops = &bcm2835_pctl_ops, |
1098 | .pmxops = &bcm2835_pmx_ops, | |
1099 | .confops = &bcm2711_pinconf_ops, | |
1100 | .owner = THIS_MODULE, | |
1101 | }; | |
1102 | ||
1103 | static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = { | |
e1b2dc70 SA |
1104 | .name = MODULE_NAME, |
1105 | .npins = BCM2835_NUM_GPIOS, | |
1106 | }; | |
1107 | ||
b1d84a3d SW |
1108 | static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = { |
1109 | .name = "pinctrl-bcm2711", | |
1110 | .npins = BCM2711_NUM_GPIOS, | |
1111 | }; | |
1112 | ||
90bfaf02 SW |
1113 | struct bcm_plat_data { |
1114 | const struct gpio_chip *gpio_chip; | |
1115 | const struct pinctrl_desc *pctl_desc; | |
1116 | const struct pinctrl_gpio_range *gpio_range; | |
1117 | }; | |
1118 | ||
1119 | static const struct bcm_plat_data bcm2835_plat_data = { | |
1120 | .gpio_chip = &bcm2835_gpio_chip, | |
1121 | .pctl_desc = &bcm2835_pinctrl_desc, | |
1122 | .gpio_range = &bcm2835_pinctrl_gpio_range, | |
1123 | }; | |
1124 | ||
1125 | static const struct bcm_plat_data bcm2711_plat_data = { | |
b1d84a3d | 1126 | .gpio_chip = &bcm2711_gpio_chip, |
90bfaf02 | 1127 | .pctl_desc = &bcm2711_pinctrl_desc, |
b1d84a3d | 1128 | .gpio_range = &bcm2711_pinctrl_gpio_range, |
90bfaf02 SW |
1129 | }; |
1130 | ||
e38a9a43 SW |
1131 | static const struct of_device_id bcm2835_pinctrl_match[] = { |
1132 | { | |
1133 | .compatible = "brcm,bcm2835-gpio", | |
90bfaf02 | 1134 | .data = &bcm2835_plat_data, |
e38a9a43 SW |
1135 | }, |
1136 | { | |
1137 | .compatible = "brcm,bcm2711-gpio", | |
90bfaf02 | 1138 | .data = &bcm2711_plat_data, |
e38a9a43 | 1139 | }, |
562c856f FF |
1140 | { |
1141 | .compatible = "brcm,bcm7211-gpio", | |
1142 | .data = &bcm2711_plat_data, | |
1143 | }, | |
e38a9a43 SW |
1144 | {} |
1145 | }; | |
1146 | ||
150632b0 | 1147 | static int bcm2835_pinctrl_probe(struct platform_device *pdev) |
e1b2dc70 SA |
1148 | { |
1149 | struct device *dev = &pdev->dev; | |
1150 | struct device_node *np = dev->of_node; | |
90bfaf02 | 1151 | const struct bcm_plat_data *pdata; |
e1b2dc70 | 1152 | struct bcm2835_pinctrl *pc; |
73345a18 | 1153 | struct gpio_irq_chip *girq; |
e1b2dc70 SA |
1154 | struct resource iomem; |
1155 | int err, i; | |
e38a9a43 SW |
1156 | const struct of_device_id *match; |
1157 | ||
b1d84a3d SW |
1158 | BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS); |
1159 | BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS); | |
e1b2dc70 SA |
1160 | |
1161 | pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); | |
1162 | if (!pc) | |
1163 | return -ENOMEM; | |
1164 | ||
1165 | platform_set_drvdata(pdev, pc); | |
1166 | pc->dev = dev; | |
1167 | ||
1168 | err = of_address_to_resource(np, 0, &iomem); | |
1169 | if (err) { | |
1170 | dev_err(dev, "could not get IO memory\n"); | |
1171 | return err; | |
1172 | } | |
1173 | ||
9e0c1fb2 TR |
1174 | pc->base = devm_ioremap_resource(dev, &iomem); |
1175 | if (IS_ERR(pc->base)) | |
1176 | return PTR_ERR(pc->base); | |
e1b2dc70 | 1177 | |
90bfaf02 SW |
1178 | match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node); |
1179 | if (!match) | |
1180 | return -EINVAL; | |
1181 | ||
1182 | pdata = match->data; | |
1183 | ||
1184 | pc->gpio_chip = *pdata->gpio_chip; | |
58383c78 | 1185 | pc->gpio_chip.parent = dev; |
e1b2dc70 SA |
1186 | pc->gpio_chip.of_node = np; |
1187 | ||
e1b2dc70 SA |
1188 | for (i = 0; i < BCM2835_NUM_BANKS; i++) { |
1189 | unsigned long events; | |
1190 | unsigned offset; | |
e1b2dc70 SA |
1191 | |
1192 | /* clear event detection flags */ | |
1193 | bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); | |
1194 | bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0); | |
1195 | bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0); | |
1196 | bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0); | |
1197 | bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0); | |
1198 | bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0); | |
1199 | ||
1200 | /* clear all the events */ | |
1201 | events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4); | |
1202 | for_each_set_bit(offset, &events, 32) | |
1203 | bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); | |
1204 | ||
3c7b30f7 | 1205 | raw_spin_lock_init(&pc->irq_lock[i]); |
00445b5d PE |
1206 | } |
1207 | ||
73345a18 LW |
1208 | girq = &pc->gpio_chip.irq; |
1209 | girq->chip = &bcm2835_gpio_irq_chip; | |
1210 | girq->parent_handler = bcm2835_gpio_irq_handler; | |
1211 | girq->num_parents = BCM2835_NUM_IRQS; | |
1212 | girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS, | |
1213 | sizeof(*girq->parents), | |
1214 | GFP_KERNEL); | |
1215 | if (!girq->parents) | |
1216 | return -ENOMEM; | |
1217 | /* | |
1218 | * Use the same handler for all groups: this is necessary | |
1219 | * since we use one gpiochip to cover all lines - the | |
1220 | * irq handler then needs to figure out which group and | |
1221 | * bank that was firing the IRQ and look up the per-group | |
1222 | * and bank data. | |
1223 | */ | |
1224 | for (i = 0; i < BCM2835_NUM_IRQS; i++) | |
1225 | girq->parents[i] = irq_of_parse_and_map(np, i); | |
1226 | girq->default_type = IRQ_TYPE_NONE; | |
1227 | girq->handler = handle_level_irq; | |
1228 | ||
e19a5f79 | 1229 | err = gpiochip_add_data(&pc->gpio_chip, pc); |
e1b2dc70 SA |
1230 | if (err) { |
1231 | dev_err(dev, "could not add GPIO chip\n"); | |
1232 | return err; | |
1233 | } | |
1234 | ||
90bfaf02 SW |
1235 | pc->pctl_desc = *pdata->pctl_desc; |
1236 | pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc); | |
323de9ef | 1237 | if (IS_ERR(pc->pctl_dev)) { |
e1b2dc70 | 1238 | gpiochip_remove(&pc->gpio_chip); |
323de9ef | 1239 | return PTR_ERR(pc->pctl_dev); |
e1b2dc70 SA |
1240 | } |
1241 | ||
90bfaf02 | 1242 | pc->gpio_range = *pdata->gpio_range; |
e1b2dc70 SA |
1243 | pc->gpio_range.base = pc->gpio_chip.base; |
1244 | pc->gpio_range.gc = &pc->gpio_chip; | |
1245 | pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range); | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
e1b2dc70 SA |
1250 | static struct platform_driver bcm2835_pinctrl_driver = { |
1251 | .probe = bcm2835_pinctrl_probe, | |
e1b2dc70 SA |
1252 | .driver = { |
1253 | .name = MODULE_NAME, | |
e1b2dc70 | 1254 | .of_match_table = bcm2835_pinctrl_match, |
34f46848 | 1255 | .suppress_bind_attrs = true, |
e1b2dc70 SA |
1256 | }, |
1257 | }; | |
34f46848 | 1258 | builtin_platform_driver(bcm2835_pinctrl_driver); |