Commit | Line | Data |
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a62c3677 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
e1b2dc70 SA |
2 | /* |
3 | * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) | |
4 | * | |
5 | * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren | |
6 | * | |
7 | * This driver is inspired by: | |
8 | * pinctrl-nomadik.c, please see original file for copyright information | |
9 | * pinctrl-tegra.c, please see original file for copyright information | |
e1b2dc70 SA |
10 | */ |
11 | ||
12 | #include <linux/bitmap.h> | |
13 | #include <linux/bug.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/err.h> | |
e19a5f79 | 17 | #include <linux/gpio/driver.h> |
e1b2dc70 SA |
18 | #include <linux/io.h> |
19 | #include <linux/irq.h> | |
20 | #include <linux/irqdesc.h> | |
34f46848 | 21 | #include <linux/init.h> |
920fecc1 | 22 | #include <linux/interrupt.h> |
e1b2dc70 SA |
23 | #include <linux/of_address.h> |
24 | #include <linux/of.h> | |
25 | #include <linux/of_irq.h> | |
26 | #include <linux/pinctrl/consumer.h> | |
27 | #include <linux/pinctrl/machine.h> | |
28 | #include <linux/pinctrl/pinconf.h> | |
29 | #include <linux/pinctrl/pinctrl.h> | |
30 | #include <linux/pinctrl/pinmux.h> | |
0de70495 | 31 | #include <linux/pinctrl/pinconf-generic.h> |
e1b2dc70 SA |
32 | #include <linux/platform_device.h> |
33 | #include <linux/seq_file.h> | |
34 | #include <linux/slab.h> | |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/types.h> | |
0de70495 | 37 | #include <dt-bindings/pinctrl/bcm2835.h> |
e1b2dc70 SA |
38 | |
39 | #define MODULE_NAME "pinctrl-bcm2835" | |
40 | #define BCM2835_NUM_GPIOS 54 | |
b1d84a3d | 41 | #define BCM2711_NUM_GPIOS 58 |
e1b2dc70 | 42 | #define BCM2835_NUM_BANKS 2 |
00445b5d | 43 | #define BCM2835_NUM_IRQS 3 |
e1b2dc70 | 44 | |
e1b2dc70 SA |
45 | /* GPIO register offsets */ |
46 | #define GPFSEL0 0x0 /* Function Select */ | |
47 | #define GPSET0 0x1c /* Pin Output Set */ | |
48 | #define GPCLR0 0x28 /* Pin Output Clear */ | |
49 | #define GPLEV0 0x34 /* Pin Level */ | |
50 | #define GPEDS0 0x40 /* Pin Event Detect Status */ | |
51 | #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */ | |
52 | #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */ | |
53 | #define GPHEN0 0x64 /* Pin High Detect Enable */ | |
54 | #define GPLEN0 0x70 /* Pin Low Detect Enable */ | |
55 | #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */ | |
56 | #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */ | |
57 | #define GPPUD 0x94 /* Pin Pull-up/down Enable */ | |
58 | #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */ | |
e38a9a43 | 59 | #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */ |
e1b2dc70 SA |
60 | |
61 | #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4)) | |
62 | #define FSEL_SHIFT(p) (((p) % 10) * 3) | |
63 | #define GPIO_REG_OFFSET(p) ((p) / 32) | |
64 | #define GPIO_REG_SHIFT(p) ((p) % 32) | |
65 | ||
e38a9a43 SW |
66 | #define PUD_2711_MASK 0x3 |
67 | #define PUD_2711_REG_OFFSET(p) ((p) / 16) | |
68 | #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2) | |
69 | ||
b40ac08f NC |
70 | /* argument: bcm2835_pinconf_pull */ |
71 | #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1) | |
e1b2dc70 | 72 | |
e38a9a43 SW |
73 | #define BCM2711_PULL_NONE 0x0 |
74 | #define BCM2711_PULL_UP 0x1 | |
75 | #define BCM2711_PULL_DOWN 0x2 | |
76 | ||
e1b2dc70 SA |
77 | struct bcm2835_pinctrl { |
78 | struct device *dev; | |
79 | void __iomem *base; | |
920fecc1 | 80 | int *wake_irq; |
e1b2dc70 SA |
81 | |
82 | /* note: locking assumes each bank will have its own unsigned long */ | |
83 | unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; | |
b1d84a3d | 84 | unsigned int irq_type[BCM2711_NUM_GPIOS]; |
e1b2dc70 SA |
85 | |
86 | struct pinctrl_dev *pctl_dev; | |
e1b2dc70 | 87 | struct gpio_chip gpio_chip; |
90bfaf02 | 88 | struct pinctrl_desc pctl_desc; |
e1b2dc70 SA |
89 | struct pinctrl_gpio_range gpio_range; |
90 | ||
3c7b30f7 | 91 | raw_spinlock_t irq_lock[BCM2835_NUM_BANKS]; |
e1b2dc70 SA |
92 | }; |
93 | ||
e1b2dc70 SA |
94 | /* pins are just named GPIO0..GPIO53 */ |
95 | #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) | |
e8ed912e | 96 | static struct pinctrl_pin_desc bcm2835_gpio_pins[] = { |
e1b2dc70 SA |
97 | BCM2835_GPIO_PIN(0), |
98 | BCM2835_GPIO_PIN(1), | |
99 | BCM2835_GPIO_PIN(2), | |
100 | BCM2835_GPIO_PIN(3), | |
101 | BCM2835_GPIO_PIN(4), | |
102 | BCM2835_GPIO_PIN(5), | |
103 | BCM2835_GPIO_PIN(6), | |
104 | BCM2835_GPIO_PIN(7), | |
105 | BCM2835_GPIO_PIN(8), | |
106 | BCM2835_GPIO_PIN(9), | |
107 | BCM2835_GPIO_PIN(10), | |
108 | BCM2835_GPIO_PIN(11), | |
109 | BCM2835_GPIO_PIN(12), | |
110 | BCM2835_GPIO_PIN(13), | |
111 | BCM2835_GPIO_PIN(14), | |
112 | BCM2835_GPIO_PIN(15), | |
113 | BCM2835_GPIO_PIN(16), | |
114 | BCM2835_GPIO_PIN(17), | |
115 | BCM2835_GPIO_PIN(18), | |
116 | BCM2835_GPIO_PIN(19), | |
117 | BCM2835_GPIO_PIN(20), | |
118 | BCM2835_GPIO_PIN(21), | |
119 | BCM2835_GPIO_PIN(22), | |
120 | BCM2835_GPIO_PIN(23), | |
121 | BCM2835_GPIO_PIN(24), | |
122 | BCM2835_GPIO_PIN(25), | |
123 | BCM2835_GPIO_PIN(26), | |
124 | BCM2835_GPIO_PIN(27), | |
125 | BCM2835_GPIO_PIN(28), | |
126 | BCM2835_GPIO_PIN(29), | |
127 | BCM2835_GPIO_PIN(30), | |
128 | BCM2835_GPIO_PIN(31), | |
129 | BCM2835_GPIO_PIN(32), | |
130 | BCM2835_GPIO_PIN(33), | |
131 | BCM2835_GPIO_PIN(34), | |
132 | BCM2835_GPIO_PIN(35), | |
133 | BCM2835_GPIO_PIN(36), | |
134 | BCM2835_GPIO_PIN(37), | |
135 | BCM2835_GPIO_PIN(38), | |
136 | BCM2835_GPIO_PIN(39), | |
137 | BCM2835_GPIO_PIN(40), | |
138 | BCM2835_GPIO_PIN(41), | |
139 | BCM2835_GPIO_PIN(42), | |
140 | BCM2835_GPIO_PIN(43), | |
141 | BCM2835_GPIO_PIN(44), | |
142 | BCM2835_GPIO_PIN(45), | |
143 | BCM2835_GPIO_PIN(46), | |
144 | BCM2835_GPIO_PIN(47), | |
145 | BCM2835_GPIO_PIN(48), | |
146 | BCM2835_GPIO_PIN(49), | |
147 | BCM2835_GPIO_PIN(50), | |
148 | BCM2835_GPIO_PIN(51), | |
149 | BCM2835_GPIO_PIN(52), | |
150 | BCM2835_GPIO_PIN(53), | |
b1d84a3d SW |
151 | BCM2835_GPIO_PIN(54), |
152 | BCM2835_GPIO_PIN(55), | |
153 | BCM2835_GPIO_PIN(56), | |
154 | BCM2835_GPIO_PIN(57), | |
e1b2dc70 SA |
155 | }; |
156 | ||
157 | /* one pin per group */ | |
158 | static const char * const bcm2835_gpio_groups[] = { | |
159 | "gpio0", | |
160 | "gpio1", | |
161 | "gpio2", | |
162 | "gpio3", | |
163 | "gpio4", | |
164 | "gpio5", | |
165 | "gpio6", | |
166 | "gpio7", | |
167 | "gpio8", | |
168 | "gpio9", | |
169 | "gpio10", | |
170 | "gpio11", | |
171 | "gpio12", | |
172 | "gpio13", | |
173 | "gpio14", | |
174 | "gpio15", | |
175 | "gpio16", | |
176 | "gpio17", | |
177 | "gpio18", | |
178 | "gpio19", | |
179 | "gpio20", | |
180 | "gpio21", | |
181 | "gpio22", | |
182 | "gpio23", | |
183 | "gpio24", | |
184 | "gpio25", | |
185 | "gpio26", | |
186 | "gpio27", | |
187 | "gpio28", | |
188 | "gpio29", | |
189 | "gpio30", | |
190 | "gpio31", | |
191 | "gpio32", | |
192 | "gpio33", | |
193 | "gpio34", | |
194 | "gpio35", | |
195 | "gpio36", | |
196 | "gpio37", | |
197 | "gpio38", | |
198 | "gpio39", | |
199 | "gpio40", | |
200 | "gpio41", | |
201 | "gpio42", | |
202 | "gpio43", | |
203 | "gpio44", | |
204 | "gpio45", | |
205 | "gpio46", | |
206 | "gpio47", | |
207 | "gpio48", | |
208 | "gpio49", | |
209 | "gpio50", | |
210 | "gpio51", | |
211 | "gpio52", | |
212 | "gpio53", | |
b1d84a3d SW |
213 | "gpio54", |
214 | "gpio55", | |
215 | "gpio56", | |
216 | "gpio57", | |
e1b2dc70 SA |
217 | }; |
218 | ||
219 | enum bcm2835_fsel { | |
e1b2dc70 SA |
220 | BCM2835_FSEL_COUNT = 8, |
221 | BCM2835_FSEL_MASK = 0x7, | |
222 | }; | |
223 | ||
224 | static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = { | |
225 | [BCM2835_FSEL_GPIO_IN] = "gpio_in", | |
226 | [BCM2835_FSEL_GPIO_OUT] = "gpio_out", | |
227 | [BCM2835_FSEL_ALT0] = "alt0", | |
228 | [BCM2835_FSEL_ALT1] = "alt1", | |
229 | [BCM2835_FSEL_ALT2] = "alt2", | |
230 | [BCM2835_FSEL_ALT3] = "alt3", | |
231 | [BCM2835_FSEL_ALT4] = "alt4", | |
232 | [BCM2835_FSEL_ALT5] = "alt5", | |
233 | }; | |
234 | ||
235 | static const char * const irq_type_names[] = { | |
236 | [IRQ_TYPE_NONE] = "none", | |
237 | [IRQ_TYPE_EDGE_RISING] = "edge-rising", | |
238 | [IRQ_TYPE_EDGE_FALLING] = "edge-falling", | |
239 | [IRQ_TYPE_EDGE_BOTH] = "edge-both", | |
240 | [IRQ_TYPE_LEVEL_HIGH] = "level-high", | |
241 | [IRQ_TYPE_LEVEL_LOW] = "level-low", | |
242 | }; | |
243 | ||
244 | static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) | |
245 | { | |
246 | return readl(pc->base + reg); | |
247 | } | |
248 | ||
249 | static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg, | |
250 | u32 val) | |
251 | { | |
252 | writel(val, pc->base + reg); | |
253 | } | |
254 | ||
255 | static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg, | |
256 | unsigned bit) | |
257 | { | |
258 | reg += GPIO_REG_OFFSET(bit) * 4; | |
259 | return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1; | |
260 | } | |
261 | ||
262 | /* note NOT a read/modify/write cycle */ | |
263 | static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc, | |
264 | unsigned reg, unsigned bit) | |
265 | { | |
266 | reg += GPIO_REG_OFFSET(bit) * 4; | |
267 | bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit))); | |
268 | } | |
269 | ||
270 | static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get( | |
271 | struct bcm2835_pinctrl *pc, unsigned pin) | |
272 | { | |
273 | u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); | |
274 | enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; | |
275 | ||
276 | dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin, | |
277 | bcm2835_functions[status]); | |
278 | ||
279 | return status; | |
280 | } | |
281 | ||
282 | static inline void bcm2835_pinctrl_fsel_set( | |
283 | struct bcm2835_pinctrl *pc, unsigned pin, | |
284 | enum bcm2835_fsel fsel) | |
285 | { | |
286 | u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin)); | |
287 | enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK; | |
288 | ||
289 | dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin, | |
290 | bcm2835_functions[cur]); | |
291 | ||
292 | if (cur == fsel) | |
293 | return; | |
294 | ||
295 | if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) { | |
296 | /* always transition through GPIO_IN */ | |
297 | val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); | |
298 | val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin); | |
299 | ||
300 | dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin, | |
301 | bcm2835_functions[BCM2835_FSEL_GPIO_IN]); | |
302 | bcm2835_gpio_wr(pc, FSEL_REG(pin), val); | |
303 | } | |
304 | ||
305 | val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin)); | |
306 | val |= fsel << FSEL_SHIFT(pin); | |
307 | ||
308 | dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin, | |
309 | bcm2835_functions[fsel]); | |
310 | bcm2835_gpio_wr(pc, FSEL_REG(pin), val); | |
311 | } | |
312 | ||
e1b2dc70 SA |
313 | static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
314 | { | |
315 | return pinctrl_gpio_direction_input(chip->base + offset); | |
316 | } | |
317 | ||
318 | static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset) | |
319 | { | |
e19a5f79 | 320 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); |
e1b2dc70 SA |
321 | |
322 | return bcm2835_gpio_get_bit(pc, GPLEV0, offset); | |
323 | } | |
324 | ||
20b3d2a7 SW |
325 | static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
326 | { | |
327 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
328 | enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); | |
329 | ||
330 | /* Alternative function doesn't clearly provide a direction */ | |
331 | if (fsel > BCM2835_FSEL_GPIO_OUT) | |
332 | return -EINVAL; | |
333 | ||
3c827873 MV |
334 | if (fsel == BCM2835_FSEL_GPIO_IN) |
335 | return GPIO_LINE_DIRECTION_IN; | |
336 | ||
337 | return GPIO_LINE_DIRECTION_OUT; | |
20b3d2a7 SW |
338 | } |
339 | ||
e1b2dc70 SA |
340 | static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
341 | { | |
e19a5f79 | 342 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); |
e1b2dc70 SA |
343 | |
344 | bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); | |
345 | } | |
346 | ||
4c02cba1 SW |
347 | static int bcm2835_gpio_direction_output(struct gpio_chip *chip, |
348 | unsigned offset, int value) | |
349 | { | |
350 | bcm2835_gpio_set(chip, offset, value); | |
351 | return pinctrl_gpio_direction_output(chip->base + offset); | |
352 | } | |
353 | ||
531bcf73 | 354 | static const struct gpio_chip bcm2835_gpio_chip = { |
e1b2dc70 SA |
355 | .label = MODULE_NAME, |
356 | .owner = THIS_MODULE, | |
98c85d58 JG |
357 | .request = gpiochip_generic_request, |
358 | .free = gpiochip_generic_free, | |
e1b2dc70 SA |
359 | .direction_input = bcm2835_gpio_direction_input, |
360 | .direction_output = bcm2835_gpio_direction_output, | |
20b3d2a7 | 361 | .get_direction = bcm2835_gpio_get_direction, |
e1b2dc70 SA |
362 | .get = bcm2835_gpio_get, |
363 | .set = bcm2835_gpio_set, | |
b6e5531c | 364 | .set_config = gpiochip_generic_config, |
e1b2dc70 SA |
365 | .base = -1, |
366 | .ngpio = BCM2835_NUM_GPIOS, | |
9fb1f39e | 367 | .can_sleep = false, |
e1b2dc70 SA |
368 | }; |
369 | ||
b1d84a3d SW |
370 | static const struct gpio_chip bcm2711_gpio_chip = { |
371 | .label = "pinctrl-bcm2711", | |
372 | .owner = THIS_MODULE, | |
373 | .request = gpiochip_generic_request, | |
374 | .free = gpiochip_generic_free, | |
375 | .direction_input = bcm2835_gpio_direction_input, | |
376 | .direction_output = bcm2835_gpio_direction_output, | |
377 | .get_direction = bcm2835_gpio_get_direction, | |
378 | .get = bcm2835_gpio_get, | |
379 | .set = bcm2835_gpio_set, | |
380 | .set_config = gpiochip_generic_config, | |
381 | .base = -1, | |
382 | .ngpio = BCM2711_NUM_GPIOS, | |
383 | .can_sleep = false, | |
384 | }; | |
385 | ||
85ae9e51 LW |
386 | static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, |
387 | unsigned int bank, u32 mask) | |
e1b2dc70 | 388 | { |
e1b2dc70 SA |
389 | unsigned long events; |
390 | unsigned offset; | |
391 | unsigned gpio; | |
e1b2dc70 SA |
392 | |
393 | events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); | |
00445b5d | 394 | events &= mask; |
e1b2dc70 SA |
395 | events &= pc->enabled_irq_map[bank]; |
396 | for_each_set_bit(offset, &events, 32) { | |
397 | gpio = (32 * bank) + offset; | |
9e9355bb | 398 | generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain, |
85ae9e51 | 399 | gpio)); |
e1b2dc70 | 400 | } |
00445b5d PE |
401 | } |
402 | ||
85ae9e51 | 403 | static void bcm2835_gpio_irq_handler(struct irq_desc *desc) |
00445b5d | 404 | { |
85ae9e51 LW |
405 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
406 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
407 | struct irq_chip *host_chip = irq_desc_get_chip(desc); | |
408 | int irq = irq_desc_get_irq(desc); | |
409 | int group; | |
410 | int i; | |
411 | ||
73345a18 LW |
412 | for (i = 0; i < BCM2835_NUM_IRQS; i++) { |
413 | if (chip->irq.parents[i] == irq) { | |
0d885e9d | 414 | group = i; |
85ae9e51 LW |
415 | break; |
416 | } | |
417 | } | |
418 | /* This should not happen, every IRQ has a bank */ | |
73345a18 | 419 | if (i == BCM2835_NUM_IRQS) |
85ae9e51 | 420 | BUG(); |
00445b5d | 421 | |
85ae9e51 LW |
422 | chained_irq_enter(host_chip, desc); |
423 | ||
424 | switch (group) { | |
00445b5d | 425 | case 0: /* IRQ0 covers GPIOs 0-27 */ |
85ae9e51 | 426 | bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff); |
00445b5d PE |
427 | break; |
428 | case 1: /* IRQ1 covers GPIOs 28-45 */ | |
85ae9e51 LW |
429 | bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000); |
430 | bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff); | |
00445b5d | 431 | break; |
b1d84a3d | 432 | case 2: /* IRQ2 covers GPIOs 46-57 */ |
85ae9e51 | 433 | bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000); |
00445b5d PE |
434 | break; |
435 | } | |
436 | ||
85ae9e51 | 437 | chained_irq_exit(host_chip, desc); |
e1b2dc70 SA |
438 | } |
439 | ||
920fecc1 FF |
440 | static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id) |
441 | { | |
442 | return IRQ_HANDLED; | |
443 | } | |
444 | ||
e1b2dc70 SA |
445 | static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, |
446 | unsigned reg, unsigned offset, bool enable) | |
447 | { | |
448 | u32 value; | |
449 | reg += GPIO_REG_OFFSET(offset) * 4; | |
450 | value = bcm2835_gpio_rd(pc, reg); | |
451 | if (enable) | |
452 | value |= BIT(GPIO_REG_SHIFT(offset)); | |
453 | else | |
454 | value &= ~(BIT(GPIO_REG_SHIFT(offset))); | |
455 | bcm2835_gpio_wr(pc, reg, value); | |
456 | } | |
457 | ||
458 | /* fast path for IRQ handler */ | |
459 | static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, | |
460 | unsigned offset, bool enable) | |
461 | { | |
462 | switch (pc->irq_type[offset]) { | |
463 | case IRQ_TYPE_EDGE_RISING: | |
464 | __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); | |
465 | break; | |
466 | ||
467 | case IRQ_TYPE_EDGE_FALLING: | |
468 | __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); | |
469 | break; | |
470 | ||
471 | case IRQ_TYPE_EDGE_BOTH: | |
472 | __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable); | |
473 | __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable); | |
474 | break; | |
475 | ||
476 | case IRQ_TYPE_LEVEL_HIGH: | |
477 | __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable); | |
478 | break; | |
479 | ||
480 | case IRQ_TYPE_LEVEL_LOW: | |
481 | __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable); | |
482 | break; | |
483 | } | |
484 | } | |
485 | ||
486 | static void bcm2835_gpio_irq_enable(struct irq_data *data) | |
487 | { | |
85ae9e51 LW |
488 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); |
489 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
e1b2dc70 SA |
490 | unsigned gpio = irqd_to_hwirq(data); |
491 | unsigned offset = GPIO_REG_SHIFT(gpio); | |
492 | unsigned bank = GPIO_REG_OFFSET(gpio); | |
493 | unsigned long flags; | |
494 | ||
3c7b30f7 | 495 | raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); |
e1b2dc70 SA |
496 | set_bit(offset, &pc->enabled_irq_map[bank]); |
497 | bcm2835_gpio_irq_config(pc, gpio, true); | |
3c7b30f7 | 498 | raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); |
e1b2dc70 SA |
499 | } |
500 | ||
501 | static void bcm2835_gpio_irq_disable(struct irq_data *data) | |
502 | { | |
85ae9e51 LW |
503 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); |
504 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
e1b2dc70 SA |
505 | unsigned gpio = irqd_to_hwirq(data); |
506 | unsigned offset = GPIO_REG_SHIFT(gpio); | |
507 | unsigned bank = GPIO_REG_OFFSET(gpio); | |
508 | unsigned long flags; | |
509 | ||
3c7b30f7 | 510 | raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); |
e1b2dc70 | 511 | bcm2835_gpio_irq_config(pc, gpio, false); |
714b1dd8 JB |
512 | /* Clear events that were latched prior to clearing event sources */ |
513 | bcm2835_gpio_set_bit(pc, GPEDS0, gpio); | |
e1b2dc70 | 514 | clear_bit(offset, &pc->enabled_irq_map[bank]); |
3c7b30f7 | 515 | raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); |
e1b2dc70 SA |
516 | } |
517 | ||
518 | static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc, | |
519 | unsigned offset, unsigned int type) | |
520 | { | |
521 | switch (type) { | |
522 | case IRQ_TYPE_NONE: | |
523 | case IRQ_TYPE_EDGE_RISING: | |
524 | case IRQ_TYPE_EDGE_FALLING: | |
525 | case IRQ_TYPE_EDGE_BOTH: | |
526 | case IRQ_TYPE_LEVEL_HIGH: | |
527 | case IRQ_TYPE_LEVEL_LOW: | |
528 | pc->irq_type[offset] = type; | |
529 | break; | |
530 | ||
531 | default: | |
532 | return -EINVAL; | |
533 | } | |
534 | return 0; | |
535 | } | |
536 | ||
537 | /* slower path for reconfiguring IRQ type */ | |
538 | static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc, | |
539 | unsigned offset, unsigned int type) | |
540 | { | |
541 | switch (type) { | |
542 | case IRQ_TYPE_NONE: | |
543 | if (pc->irq_type[offset] != type) { | |
544 | bcm2835_gpio_irq_config(pc, offset, false); | |
545 | pc->irq_type[offset] = type; | |
546 | } | |
547 | break; | |
548 | ||
549 | case IRQ_TYPE_EDGE_RISING: | |
550 | if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { | |
551 | /* RISING already enabled, disable FALLING */ | |
552 | pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; | |
553 | bcm2835_gpio_irq_config(pc, offset, false); | |
554 | pc->irq_type[offset] = type; | |
555 | } else if (pc->irq_type[offset] != type) { | |
556 | bcm2835_gpio_irq_config(pc, offset, false); | |
557 | pc->irq_type[offset] = type; | |
558 | bcm2835_gpio_irq_config(pc, offset, true); | |
559 | } | |
560 | break; | |
561 | ||
562 | case IRQ_TYPE_EDGE_FALLING: | |
563 | if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) { | |
564 | /* FALLING already enabled, disable RISING */ | |
565 | pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; | |
566 | bcm2835_gpio_irq_config(pc, offset, false); | |
567 | pc->irq_type[offset] = type; | |
568 | } else if (pc->irq_type[offset] != type) { | |
569 | bcm2835_gpio_irq_config(pc, offset, false); | |
570 | pc->irq_type[offset] = type; | |
571 | bcm2835_gpio_irq_config(pc, offset, true); | |
572 | } | |
573 | break; | |
574 | ||
575 | case IRQ_TYPE_EDGE_BOTH: | |
576 | if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) { | |
577 | /* RISING already enabled, enable FALLING too */ | |
578 | pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING; | |
579 | bcm2835_gpio_irq_config(pc, offset, true); | |
580 | pc->irq_type[offset] = type; | |
581 | } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) { | |
582 | /* FALLING already enabled, enable RISING too */ | |
583 | pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING; | |
584 | bcm2835_gpio_irq_config(pc, offset, true); | |
585 | pc->irq_type[offset] = type; | |
586 | } else if (pc->irq_type[offset] != type) { | |
587 | bcm2835_gpio_irq_config(pc, offset, false); | |
588 | pc->irq_type[offset] = type; | |
589 | bcm2835_gpio_irq_config(pc, offset, true); | |
590 | } | |
591 | break; | |
592 | ||
593 | case IRQ_TYPE_LEVEL_HIGH: | |
594 | case IRQ_TYPE_LEVEL_LOW: | |
595 | if (pc->irq_type[offset] != type) { | |
596 | bcm2835_gpio_irq_config(pc, offset, false); | |
597 | pc->irq_type[offset] = type; | |
598 | bcm2835_gpio_irq_config(pc, offset, true); | |
599 | } | |
600 | break; | |
601 | ||
602 | default: | |
603 | return -EINVAL; | |
604 | } | |
605 | return 0; | |
606 | } | |
607 | ||
608 | static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) | |
609 | { | |
85ae9e51 LW |
610 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); |
611 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
e1b2dc70 SA |
612 | unsigned gpio = irqd_to_hwirq(data); |
613 | unsigned offset = GPIO_REG_SHIFT(gpio); | |
614 | unsigned bank = GPIO_REG_OFFSET(gpio); | |
615 | unsigned long flags; | |
616 | int ret; | |
617 | ||
3c7b30f7 | 618 | raw_spin_lock_irqsave(&pc->irq_lock[bank], flags); |
e1b2dc70 SA |
619 | |
620 | if (test_bit(offset, &pc->enabled_irq_map[bank])) | |
621 | ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type); | |
622 | else | |
623 | ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); | |
624 | ||
b8a19382 | 625 | if (type & IRQ_TYPE_EDGE_BOTH) |
1aa74fd0 | 626 | irq_set_handler_locked(data, handle_edge_irq); |
b8a19382 | 627 | else |
1aa74fd0 | 628 | irq_set_handler_locked(data, handle_level_irq); |
b8a19382 | 629 | |
3c7b30f7 | 630 | raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags); |
e1b2dc70 SA |
631 | |
632 | return ret; | |
633 | } | |
634 | ||
b8a19382 CK |
635 | static void bcm2835_gpio_irq_ack(struct irq_data *data) |
636 | { | |
85ae9e51 LW |
637 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); |
638 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
b8a19382 CK |
639 | unsigned gpio = irqd_to_hwirq(data); |
640 | ||
641 | bcm2835_gpio_set_bit(pc, GPEDS0, gpio); | |
642 | } | |
643 | ||
920fecc1 FF |
644 | static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on) |
645 | { | |
646 | struct gpio_chip *chip = irq_data_get_irq_chip_data(data); | |
647 | struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); | |
648 | unsigned gpio = irqd_to_hwirq(data); | |
649 | unsigned int irqgroup; | |
650 | int ret = -EINVAL; | |
651 | ||
652 | if (!pc->wake_irq) | |
653 | return ret; | |
654 | ||
655 | if (gpio <= 27) | |
656 | irqgroup = 0; | |
657 | else if (gpio >= 28 && gpio <= 45) | |
658 | irqgroup = 1; | |
659 | else if (gpio >= 46 && gpio <= 57) | |
660 | irqgroup = 2; | |
661 | else | |
662 | return ret; | |
663 | ||
664 | if (on) | |
665 | ret = enable_irq_wake(pc->wake_irq[irqgroup]); | |
666 | else | |
667 | ret = disable_irq_wake(pc->wake_irq[irqgroup]); | |
668 | ||
669 | return ret; | |
670 | } | |
671 | ||
e1b2dc70 SA |
672 | static struct irq_chip bcm2835_gpio_irq_chip = { |
673 | .name = MODULE_NAME, | |
674 | .irq_enable = bcm2835_gpio_irq_enable, | |
675 | .irq_disable = bcm2835_gpio_irq_disable, | |
676 | .irq_set_type = bcm2835_gpio_irq_set_type, | |
b8a19382 CK |
677 | .irq_ack = bcm2835_gpio_irq_ack, |
678 | .irq_mask = bcm2835_gpio_irq_disable, | |
679 | .irq_unmask = bcm2835_gpio_irq_enable, | |
920fecc1 FF |
680 | .irq_set_wake = bcm2835_gpio_irq_set_wake, |
681 | .flags = IRQCHIP_MASK_ON_SUSPEND, | |
e1b2dc70 SA |
682 | }; |
683 | ||
684 | static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) | |
685 | { | |
b1d84a3d | 686 | return BCM2835_NUM_GPIOS; |
e1b2dc70 SA |
687 | } |
688 | ||
689 | static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev, | |
690 | unsigned selector) | |
691 | { | |
692 | return bcm2835_gpio_groups[selector]; | |
693 | } | |
694 | ||
695 | static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev, | |
696 | unsigned selector, | |
697 | const unsigned **pins, | |
698 | unsigned *num_pins) | |
699 | { | |
700 | *pins = &bcm2835_gpio_pins[selector].number; | |
701 | *num_pins = 1; | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
706 | static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, | |
707 | struct seq_file *s, | |
708 | unsigned offset) | |
709 | { | |
710 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
85ae9e51 | 711 | struct gpio_chip *chip = &pc->gpio_chip; |
e1b2dc70 SA |
712 | enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); |
713 | const char *fname = bcm2835_functions[fsel]; | |
714 | int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset); | |
f0fbe7bc | 715 | int irq = irq_find_mapping(chip->irq.domain, offset); |
e1b2dc70 SA |
716 | |
717 | seq_printf(s, "function %s in %s; irq %d (%s)", | |
718 | fname, value ? "hi" : "lo", | |
719 | irq, irq_type_names[pc->irq_type[offset]]); | |
720 | } | |
721 | ||
722 | static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev, | |
723 | struct pinctrl_map *maps, unsigned num_maps) | |
724 | { | |
725 | int i; | |
726 | ||
727 | for (i = 0; i < num_maps; i++) | |
728 | if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN) | |
729 | kfree(maps[i].data.configs.configs); | |
730 | ||
731 | kfree(maps); | |
732 | } | |
733 | ||
734 | static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc, | |
735 | struct device_node *np, u32 pin, u32 fnum, | |
736 | struct pinctrl_map **maps) | |
737 | { | |
738 | struct pinctrl_map *map = *maps; | |
739 | ||
740 | if (fnum >= ARRAY_SIZE(bcm2835_functions)) { | |
f5292d06 | 741 | dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum); |
e1b2dc70 SA |
742 | return -EINVAL; |
743 | } | |
744 | ||
745 | map->type = PIN_MAP_TYPE_MUX_GROUP; | |
746 | map->data.mux.group = bcm2835_gpio_groups[pin]; | |
747 | map->data.mux.function = bcm2835_functions[fnum]; | |
748 | (*maps)++; | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
753 | static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, | |
754 | struct device_node *np, u32 pin, u32 pull, | |
755 | struct pinctrl_map **maps) | |
756 | { | |
757 | struct pinctrl_map *map = *maps; | |
758 | unsigned long *configs; | |
759 | ||
760 | if (pull > 2) { | |
f5292d06 | 761 | dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull); |
e1b2dc70 SA |
762 | return -EINVAL; |
763 | } | |
764 | ||
765 | configs = kzalloc(sizeof(*configs), GFP_KERNEL); | |
766 | if (!configs) | |
767 | return -ENOMEM; | |
0de70495 | 768 | configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull); |
e1b2dc70 SA |
769 | |
770 | map->type = PIN_MAP_TYPE_CONFIGS_PIN; | |
771 | map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name; | |
772 | map->data.configs.configs = configs; | |
773 | map->data.configs.num_configs = 1; | |
774 | (*maps)++; | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
e1b2dc70 SA |
779 | static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, |
780 | struct device_node *np, | |
0de70495 | 781 | struct pinctrl_map **map, unsigned int *num_maps) |
e1b2dc70 SA |
782 | { |
783 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
784 | struct property *pins, *funcs, *pulls; | |
785 | int num_pins, num_funcs, num_pulls, maps_per_pin; | |
786 | struct pinctrl_map *maps, *cur_map; | |
787 | int i, err; | |
788 | u32 pin, func, pull; | |
789 | ||
0de70495 MC |
790 | /* Check for generic binding in this node */ |
791 | err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps); | |
792 | if (err || *num_maps) | |
793 | return err; | |
794 | ||
795 | /* Generic binding did not find anything continue with legacy parse */ | |
e1b2dc70 SA |
796 | pins = of_find_property(np, "brcm,pins", NULL); |
797 | if (!pins) { | |
f5292d06 | 798 | dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np); |
e1b2dc70 SA |
799 | return -EINVAL; |
800 | } | |
801 | ||
802 | funcs = of_find_property(np, "brcm,function", NULL); | |
803 | pulls = of_find_property(np, "brcm,pull", NULL); | |
804 | ||
805 | if (!funcs && !pulls) { | |
806 | dev_err(pc->dev, | |
f5292d06 RH |
807 | "%pOF: neither brcm,function nor brcm,pull specified\n", |
808 | np); | |
e1b2dc70 SA |
809 | return -EINVAL; |
810 | } | |
811 | ||
812 | num_pins = pins->length / 4; | |
813 | num_funcs = funcs ? (funcs->length / 4) : 0; | |
814 | num_pulls = pulls ? (pulls->length / 4) : 0; | |
815 | ||
816 | if (num_funcs > 1 && num_funcs != num_pins) { | |
817 | dev_err(pc->dev, | |
f5292d06 RH |
818 | "%pOF: brcm,function must have 1 or %d entries\n", |
819 | np, num_pins); | |
e1b2dc70 SA |
820 | return -EINVAL; |
821 | } | |
822 | ||
823 | if (num_pulls > 1 && num_pulls != num_pins) { | |
824 | dev_err(pc->dev, | |
f5292d06 RH |
825 | "%pOF: brcm,pull must have 1 or %d entries\n", |
826 | np, num_pins); | |
e1b2dc70 SA |
827 | return -EINVAL; |
828 | } | |
829 | ||
830 | maps_per_pin = 0; | |
831 | if (num_funcs) | |
832 | maps_per_pin++; | |
833 | if (num_pulls) | |
834 | maps_per_pin++; | |
6396bb22 KC |
835 | cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps), |
836 | GFP_KERNEL); | |
e1b2dc70 SA |
837 | if (!maps) |
838 | return -ENOMEM; | |
839 | ||
840 | for (i = 0; i < num_pins; i++) { | |
ce63d6d4 SW |
841 | err = of_property_read_u32_index(np, "brcm,pins", i, &pin); |
842 | if (err) | |
843 | goto out; | |
b1d84a3d | 844 | if (pin >= pc->pctl_desc.npins) { |
f5292d06 RH |
845 | dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n", |
846 | np, pin); | |
e1b2dc70 SA |
847 | err = -EINVAL; |
848 | goto out; | |
849 | } | |
850 | ||
851 | if (num_funcs) { | |
ce63d6d4 SW |
852 | err = of_property_read_u32_index(np, "brcm,function", |
853 | (num_funcs > 1) ? i : 0, &func); | |
854 | if (err) | |
855 | goto out; | |
e1b2dc70 SA |
856 | err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin, |
857 | func, &cur_map); | |
858 | if (err) | |
859 | goto out; | |
860 | } | |
861 | if (num_pulls) { | |
ce63d6d4 | 862 | err = of_property_read_u32_index(np, "brcm,pull", |
2c7e3306 | 863 | (num_pulls > 1) ? i : 0, &pull); |
ce63d6d4 SW |
864 | if (err) |
865 | goto out; | |
e1b2dc70 SA |
866 | err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin, |
867 | pull, &cur_map); | |
868 | if (err) | |
869 | goto out; | |
870 | } | |
871 | } | |
872 | ||
873 | *map = maps; | |
874 | *num_maps = num_pins * maps_per_pin; | |
875 | ||
876 | return 0; | |
877 | ||
878 | out: | |
53653c6b | 879 | bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin); |
e1b2dc70 SA |
880 | return err; |
881 | } | |
882 | ||
022ab148 | 883 | static const struct pinctrl_ops bcm2835_pctl_ops = { |
e1b2dc70 SA |
884 | .get_groups_count = bcm2835_pctl_get_groups_count, |
885 | .get_group_name = bcm2835_pctl_get_group_name, | |
886 | .get_group_pins = bcm2835_pctl_get_group_pins, | |
887 | .pin_dbg_show = bcm2835_pctl_pin_dbg_show, | |
888 | .dt_node_to_map = bcm2835_pctl_dt_node_to_map, | |
889 | .dt_free_map = bcm2835_pctl_dt_free_map, | |
890 | }; | |
891 | ||
ccca1ad5 PE |
892 | static int bcm2835_pmx_free(struct pinctrl_dev *pctldev, |
893 | unsigned offset) | |
894 | { | |
895 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
896 | ||
897 | /* disable by setting to GPIO_IN */ | |
898 | bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); | |
899 | return 0; | |
900 | } | |
901 | ||
e1b2dc70 SA |
902 | static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev) |
903 | { | |
904 | return BCM2835_FSEL_COUNT; | |
905 | } | |
906 | ||
907 | static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev, | |
908 | unsigned selector) | |
909 | { | |
910 | return bcm2835_functions[selector]; | |
911 | } | |
912 | ||
913 | static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev, | |
914 | unsigned selector, | |
915 | const char * const **groups, | |
916 | unsigned * const num_groups) | |
917 | { | |
918 | /* every pin can do every function */ | |
919 | *groups = bcm2835_gpio_groups; | |
b1d84a3d | 920 | *num_groups = BCM2835_NUM_GPIOS; |
e1b2dc70 SA |
921 | |
922 | return 0; | |
923 | } | |
924 | ||
03e9f0ca | 925 | static int bcm2835_pmx_set(struct pinctrl_dev *pctldev, |
e1b2dc70 SA |
926 | unsigned func_selector, |
927 | unsigned group_selector) | |
928 | { | |
929 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
930 | ||
931 | bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector); | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
e1b2dc70 SA |
936 | static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, |
937 | struct pinctrl_gpio_range *range, | |
938 | unsigned offset) | |
939 | { | |
940 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
941 | ||
942 | /* disable by setting to GPIO_IN */ | |
943 | bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); | |
944 | } | |
945 | ||
946 | static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
947 | struct pinctrl_gpio_range *range, | |
948 | unsigned offset, | |
949 | bool input) | |
950 | { | |
951 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
952 | enum bcm2835_fsel fsel = input ? | |
953 | BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT; | |
954 | ||
955 | bcm2835_pinctrl_fsel_set(pc, offset, fsel); | |
956 | ||
957 | return 0; | |
958 | } | |
959 | ||
022ab148 | 960 | static const struct pinmux_ops bcm2835_pmx_ops = { |
ccca1ad5 | 961 | .free = bcm2835_pmx_free, |
e1b2dc70 SA |
962 | .get_functions_count = bcm2835_pmx_get_functions_count, |
963 | .get_function_name = bcm2835_pmx_get_function_name, | |
964 | .get_function_groups = bcm2835_pmx_get_function_groups, | |
03e9f0ca | 965 | .set_mux = bcm2835_pmx_set, |
e1b2dc70 SA |
966 | .gpio_disable_free = bcm2835_pmx_gpio_disable_free, |
967 | .gpio_set_direction = bcm2835_pmx_gpio_set_direction, | |
968 | }; | |
969 | ||
970 | static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev, | |
971 | unsigned pin, unsigned long *config) | |
972 | { | |
973 | /* No way to read back config in HW */ | |
974 | return -ENOTSUPP; | |
975 | } | |
976 | ||
0de70495 MC |
977 | static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc, |
978 | unsigned int pin, unsigned int arg) | |
979 | { | |
980 | u32 off, bit; | |
981 | ||
982 | off = GPIO_REG_OFFSET(pin); | |
983 | bit = GPIO_REG_SHIFT(pin); | |
984 | ||
985 | bcm2835_gpio_wr(pc, GPPUD, arg & 3); | |
986 | /* | |
987 | * BCM2835 datasheet say to wait 150 cycles, but not of what. | |
988 | * But the VideoCore firmware delay for this operation | |
989 | * based nearly on the same amount of VPU cycles and this clock | |
990 | * runs at 250 MHz. | |
991 | */ | |
992 | udelay(1); | |
993 | bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); | |
994 | udelay(1); | |
995 | bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); | |
996 | } | |
997 | ||
e1b2dc70 | 998 | static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, |
0de70495 MC |
999 | unsigned int pin, unsigned long *configs, |
1000 | unsigned int num_configs) | |
e1b2dc70 SA |
1001 | { |
1002 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
0de70495 | 1003 | u32 param, arg; |
03b054e9 | 1004 | int i; |
e1b2dc70 | 1005 | |
03b054e9 | 1006 | for (i = 0; i < num_configs; i++) { |
0de70495 MC |
1007 | param = pinconf_to_config_param(configs[i]); |
1008 | arg = pinconf_to_config_argument(configs[i]); | |
1009 | ||
1010 | switch (param) { | |
1011 | /* Set legacy brcm,pull */ | |
1012 | case BCM2835_PINCONF_PARAM_PULL: | |
1013 | bcm2835_pull_config_set(pc, pin, arg); | |
1014 | break; | |
1015 | ||
1016 | /* Set pull generic bindings */ | |
1017 | case PIN_CONFIG_BIAS_DISABLE: | |
1018 | bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF); | |
1019 | break; | |
1020 | ||
1021 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
1022 | bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN); | |
1023 | break; | |
1024 | ||
1025 | case PIN_CONFIG_BIAS_PULL_UP: | |
1026 | bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP); | |
1027 | break; | |
03b054e9 | 1028 | |
90b60552 MC |
1029 | /* Set output-high or output-low */ |
1030 | case PIN_CONFIG_OUTPUT: | |
1031 | bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); | |
1032 | break; | |
1033 | ||
0de70495 | 1034 | default: |
b6e5531c | 1035 | return -ENOTSUPP; |
03b054e9 | 1036 | |
0de70495 | 1037 | } /* switch param type */ |
03b054e9 | 1038 | } /* for each config */ |
e1b2dc70 SA |
1039 | |
1040 | return 0; | |
1041 | } | |
1042 | ||
022ab148 | 1043 | static const struct pinconf_ops bcm2835_pinconf_ops = { |
1cb66f08 | 1044 | .is_generic = true, |
e1b2dc70 SA |
1045 | .pin_config_get = bcm2835_pinconf_get, |
1046 | .pin_config_set = bcm2835_pinconf_set, | |
1047 | }; | |
1048 | ||
e38a9a43 SW |
1049 | static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc, |
1050 | unsigned int pin, unsigned int arg) | |
1051 | { | |
1052 | u32 shifter; | |
1053 | u32 value; | |
1054 | u32 off; | |
1055 | ||
1056 | off = PUD_2711_REG_OFFSET(pin); | |
1057 | shifter = PUD_2711_REG_SHIFT(pin); | |
1058 | ||
1059 | value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4)); | |
1060 | value &= ~(PUD_2711_MASK << shifter); | |
1061 | value |= (arg << shifter); | |
1062 | bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value); | |
1063 | } | |
1064 | ||
1065 | static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev, | |
1066 | unsigned int pin, unsigned long *configs, | |
1067 | unsigned int num_configs) | |
1068 | { | |
1069 | struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); | |
1070 | u32 param, arg; | |
1071 | int i; | |
1072 | ||
1073 | for (i = 0; i < num_configs; i++) { | |
1074 | param = pinconf_to_config_param(configs[i]); | |
1075 | arg = pinconf_to_config_argument(configs[i]); | |
1076 | ||
1077 | switch (param) { | |
1078 | /* convert legacy brcm,pull */ | |
1079 | case BCM2835_PINCONF_PARAM_PULL: | |
1080 | if (arg == BCM2835_PUD_UP) | |
1081 | arg = BCM2711_PULL_UP; | |
1082 | else if (arg == BCM2835_PUD_DOWN) | |
1083 | arg = BCM2711_PULL_DOWN; | |
1084 | else | |
1085 | arg = BCM2711_PULL_NONE; | |
1086 | ||
1087 | bcm2711_pull_config_set(pc, pin, arg); | |
1088 | break; | |
1089 | ||
1090 | /* Set pull generic bindings */ | |
1091 | case PIN_CONFIG_BIAS_DISABLE: | |
1092 | bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE); | |
1093 | break; | |
1094 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
1095 | bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN); | |
1096 | break; | |
1097 | case PIN_CONFIG_BIAS_PULL_UP: | |
1098 | bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP); | |
1099 | break; | |
1100 | ||
1101 | /* Set output-high or output-low */ | |
1102 | case PIN_CONFIG_OUTPUT: | |
1103 | bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); | |
1104 | break; | |
1105 | ||
1106 | default: | |
1107 | return -ENOTSUPP; | |
1108 | } | |
1109 | } /* for each config */ | |
1110 | ||
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | static const struct pinconf_ops bcm2711_pinconf_ops = { | |
1115 | .is_generic = true, | |
1116 | .pin_config_get = bcm2835_pinconf_get, | |
1117 | .pin_config_set = bcm2711_pinconf_set, | |
1118 | }; | |
1119 | ||
90bfaf02 | 1120 | static const struct pinctrl_desc bcm2835_pinctrl_desc = { |
e1b2dc70 SA |
1121 | .name = MODULE_NAME, |
1122 | .pins = bcm2835_gpio_pins, | |
b1d84a3d | 1123 | .npins = BCM2835_NUM_GPIOS, |
e1b2dc70 SA |
1124 | .pctlops = &bcm2835_pctl_ops, |
1125 | .pmxops = &bcm2835_pmx_ops, | |
1126 | .confops = &bcm2835_pinconf_ops, | |
1127 | .owner = THIS_MODULE, | |
1128 | }; | |
1129 | ||
90bfaf02 | 1130 | static const struct pinctrl_desc bcm2711_pinctrl_desc = { |
b1d84a3d | 1131 | .name = "pinctrl-bcm2711", |
90bfaf02 | 1132 | .pins = bcm2835_gpio_pins, |
b1d84a3d | 1133 | .npins = BCM2711_NUM_GPIOS, |
90bfaf02 SW |
1134 | .pctlops = &bcm2835_pctl_ops, |
1135 | .pmxops = &bcm2835_pmx_ops, | |
1136 | .confops = &bcm2711_pinconf_ops, | |
1137 | .owner = THIS_MODULE, | |
1138 | }; | |
1139 | ||
1140 | static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = { | |
e1b2dc70 SA |
1141 | .name = MODULE_NAME, |
1142 | .npins = BCM2835_NUM_GPIOS, | |
1143 | }; | |
1144 | ||
b1d84a3d SW |
1145 | static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = { |
1146 | .name = "pinctrl-bcm2711", | |
1147 | .npins = BCM2711_NUM_GPIOS, | |
1148 | }; | |
1149 | ||
90bfaf02 SW |
1150 | struct bcm_plat_data { |
1151 | const struct gpio_chip *gpio_chip; | |
1152 | const struct pinctrl_desc *pctl_desc; | |
1153 | const struct pinctrl_gpio_range *gpio_range; | |
1154 | }; | |
1155 | ||
1156 | static const struct bcm_plat_data bcm2835_plat_data = { | |
1157 | .gpio_chip = &bcm2835_gpio_chip, | |
1158 | .pctl_desc = &bcm2835_pinctrl_desc, | |
1159 | .gpio_range = &bcm2835_pinctrl_gpio_range, | |
1160 | }; | |
1161 | ||
1162 | static const struct bcm_plat_data bcm2711_plat_data = { | |
b1d84a3d | 1163 | .gpio_chip = &bcm2711_gpio_chip, |
90bfaf02 | 1164 | .pctl_desc = &bcm2711_pinctrl_desc, |
b1d84a3d | 1165 | .gpio_range = &bcm2711_pinctrl_gpio_range, |
90bfaf02 SW |
1166 | }; |
1167 | ||
e38a9a43 SW |
1168 | static const struct of_device_id bcm2835_pinctrl_match[] = { |
1169 | { | |
1170 | .compatible = "brcm,bcm2835-gpio", | |
90bfaf02 | 1171 | .data = &bcm2835_plat_data, |
e38a9a43 SW |
1172 | }, |
1173 | { | |
1174 | .compatible = "brcm,bcm2711-gpio", | |
90bfaf02 | 1175 | .data = &bcm2711_plat_data, |
e38a9a43 | 1176 | }, |
562c856f FF |
1177 | { |
1178 | .compatible = "brcm,bcm7211-gpio", | |
1179 | .data = &bcm2711_plat_data, | |
1180 | }, | |
e38a9a43 SW |
1181 | {} |
1182 | }; | |
1183 | ||
150632b0 | 1184 | static int bcm2835_pinctrl_probe(struct platform_device *pdev) |
e1b2dc70 SA |
1185 | { |
1186 | struct device *dev = &pdev->dev; | |
1187 | struct device_node *np = dev->of_node; | |
90bfaf02 | 1188 | const struct bcm_plat_data *pdata; |
e1b2dc70 | 1189 | struct bcm2835_pinctrl *pc; |
73345a18 | 1190 | struct gpio_irq_chip *girq; |
e1b2dc70 SA |
1191 | struct resource iomem; |
1192 | int err, i; | |
e38a9a43 | 1193 | const struct of_device_id *match; |
920fecc1 | 1194 | int is_7211 = 0; |
e38a9a43 | 1195 | |
b1d84a3d SW |
1196 | BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS); |
1197 | BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS); | |
e1b2dc70 SA |
1198 | |
1199 | pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); | |
1200 | if (!pc) | |
1201 | return -ENOMEM; | |
1202 | ||
1203 | platform_set_drvdata(pdev, pc); | |
1204 | pc->dev = dev; | |
1205 | ||
1206 | err = of_address_to_resource(np, 0, &iomem); | |
1207 | if (err) { | |
1208 | dev_err(dev, "could not get IO memory\n"); | |
1209 | return err; | |
1210 | } | |
1211 | ||
9e0c1fb2 TR |
1212 | pc->base = devm_ioremap_resource(dev, &iomem); |
1213 | if (IS_ERR(pc->base)) | |
1214 | return PTR_ERR(pc->base); | |
e1b2dc70 | 1215 | |
90bfaf02 SW |
1216 | match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node); |
1217 | if (!match) | |
1218 | return -EINVAL; | |
1219 | ||
1220 | pdata = match->data; | |
920fecc1 | 1221 | is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio"); |
90bfaf02 SW |
1222 | |
1223 | pc->gpio_chip = *pdata->gpio_chip; | |
58383c78 | 1224 | pc->gpio_chip.parent = dev; |
e1b2dc70 SA |
1225 | pc->gpio_chip.of_node = np; |
1226 | ||
e1b2dc70 SA |
1227 | for (i = 0; i < BCM2835_NUM_BANKS; i++) { |
1228 | unsigned long events; | |
1229 | unsigned offset; | |
e1b2dc70 SA |
1230 | |
1231 | /* clear event detection flags */ | |
1232 | bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); | |
1233 | bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0); | |
1234 | bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0); | |
1235 | bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0); | |
1236 | bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0); | |
1237 | bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0); | |
1238 | ||
1239 | /* clear all the events */ | |
1240 | events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4); | |
1241 | for_each_set_bit(offset, &events, 32) | |
1242 | bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); | |
1243 | ||
3c7b30f7 | 1244 | raw_spin_lock_init(&pc->irq_lock[i]); |
00445b5d PE |
1245 | } |
1246 | ||
73345a18 LW |
1247 | girq = &pc->gpio_chip.irq; |
1248 | girq->chip = &bcm2835_gpio_irq_chip; | |
1249 | girq->parent_handler = bcm2835_gpio_irq_handler; | |
1250 | girq->num_parents = BCM2835_NUM_IRQS; | |
1251 | girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS, | |
1252 | sizeof(*girq->parents), | |
1253 | GFP_KERNEL); | |
1254 | if (!girq->parents) | |
1255 | return -ENOMEM; | |
920fecc1 FF |
1256 | |
1257 | if (is_7211) { | |
1258 | pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS, | |
1259 | sizeof(*pc->wake_irq), | |
1260 | GFP_KERNEL); | |
1261 | if (!pc->wake_irq) | |
1262 | return -ENOMEM; | |
1263 | } | |
1264 | ||
73345a18 LW |
1265 | /* |
1266 | * Use the same handler for all groups: this is necessary | |
1267 | * since we use one gpiochip to cover all lines - the | |
1268 | * irq handler then needs to figure out which group and | |
1269 | * bank that was firing the IRQ and look up the per-group | |
1270 | * and bank data. | |
1271 | */ | |
920fecc1 FF |
1272 | for (i = 0; i < BCM2835_NUM_IRQS; i++) { |
1273 | int len; | |
1274 | char *name; | |
1275 | ||
73345a18 | 1276 | girq->parents[i] = irq_of_parse_and_map(np, i); |
4bc80da5 PE |
1277 | if (!is_7211) { |
1278 | if (!girq->parents[i]) { | |
1279 | girq->num_parents = i; | |
1280 | break; | |
1281 | } | |
920fecc1 | 1282 | continue; |
4bc80da5 | 1283 | } |
920fecc1 FF |
1284 | /* Skip over the all banks interrupts */ |
1285 | pc->wake_irq[i] = irq_of_parse_and_map(np, i + | |
1286 | BCM2835_NUM_IRQS + 1); | |
1287 | ||
1288 | len = strlen(dev_name(pc->dev)) + 16; | |
1289 | name = devm_kzalloc(pc->dev, len, GFP_KERNEL); | |
1290 | if (!name) | |
1291 | return -ENOMEM; | |
1292 | ||
1293 | snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i); | |
1294 | ||
1295 | /* These are optional interrupts */ | |
1296 | err = devm_request_irq(dev, pc->wake_irq[i], | |
1297 | bcm2835_gpio_wake_irq_handler, | |
1298 | IRQF_SHARED, name, pc); | |
1299 | if (err) | |
1300 | dev_warn(dev, "unable to request wake IRQ %d\n", | |
1301 | pc->wake_irq[i]); | |
1302 | } | |
1303 | ||
73345a18 LW |
1304 | girq->default_type = IRQ_TYPE_NONE; |
1305 | girq->handler = handle_level_irq; | |
1306 | ||
e19a5f79 | 1307 | err = gpiochip_add_data(&pc->gpio_chip, pc); |
e1b2dc70 SA |
1308 | if (err) { |
1309 | dev_err(dev, "could not add GPIO chip\n"); | |
1310 | return err; | |
1311 | } | |
1312 | ||
90bfaf02 SW |
1313 | pc->pctl_desc = *pdata->pctl_desc; |
1314 | pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc); | |
323de9ef | 1315 | if (IS_ERR(pc->pctl_dev)) { |
e1b2dc70 | 1316 | gpiochip_remove(&pc->gpio_chip); |
323de9ef | 1317 | return PTR_ERR(pc->pctl_dev); |
e1b2dc70 SA |
1318 | } |
1319 | ||
90bfaf02 | 1320 | pc->gpio_range = *pdata->gpio_range; |
e1b2dc70 SA |
1321 | pc->gpio_range.base = pc->gpio_chip.base; |
1322 | pc->gpio_range.gc = &pc->gpio_chip; | |
1323 | pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range); | |
1324 | ||
1325 | return 0; | |
1326 | } | |
1327 | ||
e1b2dc70 SA |
1328 | static struct platform_driver bcm2835_pinctrl_driver = { |
1329 | .probe = bcm2835_pinctrl_probe, | |
e1b2dc70 SA |
1330 | .driver = { |
1331 | .name = MODULE_NAME, | |
e1b2dc70 | 1332 | .of_match_table = bcm2835_pinctrl_match, |
34f46848 | 1333 | .suppress_bind_attrs = true, |
e1b2dc70 SA |
1334 | }, |
1335 | }; | |
34f46848 | 1336 | builtin_platform_driver(bcm2835_pinctrl_driver); |