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pinctrl: bcm2835: declare pin config as generic
[linux-2.6-block.git] / drivers / pinctrl / bcm / pinctrl-bcm2835.c
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a62c3677 1// SPDX-License-Identifier: GPL-2.0+
e1b2dc70
SA		 2/*
3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4 *
5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6 *
7 * This driver is inspired by:
8 * pinctrl-nomadik.c, please see original file for copyright information
9 * pinctrl-tegra.c, please see original file for copyright information
e1b2dc70
SA		 10 */
11
12#include <linux/bitmap.h>
13#include <linux/bug.h>
14#include <linux/delay.h>
15#include <linux/device.h>
16#include <linux/err.h>
e19a5f79 17#include <linux/gpio/driver.h>
e1b2dc70
SA		 18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/irqdesc.h>
34f46848 21#include <linux/init.h>
e1b2dc70
SA		 22#include <linux/of_address.h>
23#include <linux/of.h>
24#include <linux/of_irq.h>
25#include <linux/pinctrl/consumer.h>
26#include <linux/pinctrl/machine.h>
27#include <linux/pinctrl/pinconf.h>
28#include <linux/pinctrl/pinctrl.h>
29#include <linux/pinctrl/pinmux.h>
0de70495 30#include <linux/pinctrl/pinconf-generic.h>
e1b2dc70
SA		 31#include <linux/platform_device.h>
32#include <linux/seq_file.h>
33#include <linux/slab.h>
34#include <linux/spinlock.h>
35#include <linux/types.h>
0de70495 36#include <dt-bindings/pinctrl/bcm2835.h>
e1b2dc70
SA		 37
38#define MODULE_NAME "pinctrl-bcm2835"
39#define BCM2835_NUM_GPIOS 54
40#define BCM2835_NUM_BANKS 2
00445b5d 41#define BCM2835_NUM_IRQS 3
e1b2dc70
SA		 42
43#define BCM2835_PIN_BITMAP_SZ \
44 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
45
46/* GPIO register offsets */
47#define GPFSEL0 0x0 /* Function Select */
48#define GPSET0 0x1c /* Pin Output Set */
49#define GPCLR0 0x28 /* Pin Output Clear */
50#define GPLEV0 0x34 /* Pin Level */
51#define GPEDS0 0x40 /* Pin Event Detect Status */
52#define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
53#define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
54#define GPHEN0 0x64 /* Pin High Detect Enable */
55#define GPLEN0 0x70 /* Pin Low Detect Enable */
56#define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
57#define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
58#define GPPUD 0x94 /* Pin Pull-up/down Enable */
59#define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
60
61#define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
62#define FSEL_SHIFT(p) (((p) % 10) * 3)
63#define GPIO_REG_OFFSET(p) ((p) / 32)
64#define GPIO_REG_SHIFT(p) ((p) % 32)
65
b40ac08f
NC		 66/* argument: bcm2835_pinconf_pull */
67#define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
e1b2dc70 68
e1b2dc70
SA		 69struct bcm2835_pinctrl {
70 struct device *dev;
71 void __iomem *base;
00445b5d 72 int irq[BCM2835_NUM_IRQS];
e1b2dc70
SA		 73
74 /* note: locking assumes each bank will have its own unsigned long */
75 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
76 unsigned int irq_type[BCM2835_NUM_GPIOS];
77
78 struct pinctrl_dev *pctl_dev;
e1b2dc70
SA		 79 struct gpio_chip gpio_chip;
80 struct pinctrl_gpio_range gpio_range;
81
3c7b30f7 82 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
e1b2dc70
SA		 83};
84
e1b2dc70
SA		 85/* pins are just named GPIO0..GPIO53 */
86#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
e8ed912e 87static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
e1b2dc70
SA		 88 BCM2835_GPIO_PIN(0),
89 BCM2835_GPIO_PIN(1),
90 BCM2835_GPIO_PIN(2),
91 BCM2835_GPIO_PIN(3),
92 BCM2835_GPIO_PIN(4),
93 BCM2835_GPIO_PIN(5),
94 BCM2835_GPIO_PIN(6),
95 BCM2835_GPIO_PIN(7),
96 BCM2835_GPIO_PIN(8),
97 BCM2835_GPIO_PIN(9),
98 BCM2835_GPIO_PIN(10),
99 BCM2835_GPIO_PIN(11),
100 BCM2835_GPIO_PIN(12),
101 BCM2835_GPIO_PIN(13),
102 BCM2835_GPIO_PIN(14),
103 BCM2835_GPIO_PIN(15),
104 BCM2835_GPIO_PIN(16),
105 BCM2835_GPIO_PIN(17),
106 BCM2835_GPIO_PIN(18),
107 BCM2835_GPIO_PIN(19),
108 BCM2835_GPIO_PIN(20),
109 BCM2835_GPIO_PIN(21),
110 BCM2835_GPIO_PIN(22),
111 BCM2835_GPIO_PIN(23),
112 BCM2835_GPIO_PIN(24),
113 BCM2835_GPIO_PIN(25),
114 BCM2835_GPIO_PIN(26),
115 BCM2835_GPIO_PIN(27),
116 BCM2835_GPIO_PIN(28),
117 BCM2835_GPIO_PIN(29),
118 BCM2835_GPIO_PIN(30),
119 BCM2835_GPIO_PIN(31),
120 BCM2835_GPIO_PIN(32),
121 BCM2835_GPIO_PIN(33),
122 BCM2835_GPIO_PIN(34),
123 BCM2835_GPIO_PIN(35),
124 BCM2835_GPIO_PIN(36),
125 BCM2835_GPIO_PIN(37),
126 BCM2835_GPIO_PIN(38),
127 BCM2835_GPIO_PIN(39),
128 BCM2835_GPIO_PIN(40),
129 BCM2835_GPIO_PIN(41),
130 BCM2835_GPIO_PIN(42),
131 BCM2835_GPIO_PIN(43),
132 BCM2835_GPIO_PIN(44),
133 BCM2835_GPIO_PIN(45),
134 BCM2835_GPIO_PIN(46),
135 BCM2835_GPIO_PIN(47),
136 BCM2835_GPIO_PIN(48),
137 BCM2835_GPIO_PIN(49),
138 BCM2835_GPIO_PIN(50),
139 BCM2835_GPIO_PIN(51),
140 BCM2835_GPIO_PIN(52),
141 BCM2835_GPIO_PIN(53),
142};
143
144/* one pin per group */
145static const char * const bcm2835_gpio_groups[] = {
146 "gpio0",
147 "gpio1",
148 "gpio2",
149 "gpio3",
150 "gpio4",
151 "gpio5",
152 "gpio6",
153 "gpio7",
154 "gpio8",
155 "gpio9",
156 "gpio10",
157 "gpio11",
158 "gpio12",
159 "gpio13",
160 "gpio14",
161 "gpio15",
162 "gpio16",
163 "gpio17",
164 "gpio18",
165 "gpio19",
166 "gpio20",
167 "gpio21",
168 "gpio22",
169 "gpio23",
170 "gpio24",
171 "gpio25",
172 "gpio26",
173 "gpio27",
174 "gpio28",
175 "gpio29",
176 "gpio30",
177 "gpio31",
178 "gpio32",
179 "gpio33",
180 "gpio34",
181 "gpio35",
182 "gpio36",
183 "gpio37",
184 "gpio38",
185 "gpio39",
186 "gpio40",
187 "gpio41",
188 "gpio42",
189 "gpio43",
190 "gpio44",
191 "gpio45",
192 "gpio46",
193 "gpio47",
194 "gpio48",
195 "gpio49",
196 "gpio50",
197 "gpio51",
198 "gpio52",
199 "gpio53",
200};
201
202enum bcm2835_fsel {
e1b2dc70
SA		 203 BCM2835_FSEL_COUNT = 8,
204 BCM2835_FSEL_MASK = 0x7,
205};
206
207static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
208 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
209 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
210 [BCM2835_FSEL_ALT0] = "alt0",
211 [BCM2835_FSEL_ALT1] = "alt1",
212 [BCM2835_FSEL_ALT2] = "alt2",
213 [BCM2835_FSEL_ALT3] = "alt3",
214 [BCM2835_FSEL_ALT4] = "alt4",
215 [BCM2835_FSEL_ALT5] = "alt5",
216};
217
218static const char * const irq_type_names[] = {
219 [IRQ_TYPE_NONE] = "none",
220 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
221 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
222 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
223 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
224 [IRQ_TYPE_LEVEL_LOW] = "level-low",
225};
226
227static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
228{
229 return readl(pc->base + reg);
230}
231
232static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
233 u32 val)
234{
235 writel(val, pc->base + reg);
236}
237
238static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
239 unsigned bit)
240{
241 reg += GPIO_REG_OFFSET(bit) * 4;
242 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
243}
244
245/* note NOT a read/modify/write cycle */
246static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
247 unsigned reg, unsigned bit)
248{
249 reg += GPIO_REG_OFFSET(bit) * 4;
250 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
251}
252
253static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
254 struct bcm2835_pinctrl *pc, unsigned pin)
255{
256 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
257 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
258
259 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
260 bcm2835_functions[status]);
261
262 return status;
263}
264
265static inline void bcm2835_pinctrl_fsel_set(
266 struct bcm2835_pinctrl *pc, unsigned pin,
267 enum bcm2835_fsel fsel)
268{
269 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
270 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
271
272 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
273 bcm2835_functions[cur]);
274
275 if (cur == fsel)
276 return;
277
278 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
279 /* always transition through GPIO_IN */
280 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
281 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
282
283 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
284 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
285 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
286 }
287
288 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
289 val |= fsel << FSEL_SHIFT(pin);
290
291 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
292 bcm2835_functions[fsel]);
293 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
294}
295
e1b2dc70
SA		 296static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
297{
298 return pinctrl_gpio_direction_input(chip->base + offset);
299}
300
301static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
302{
e19a5f79 303 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
e1b2dc70
SA		 304
305 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
306}
307
20b3d2a7
SW		 308static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
309{
310 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
311 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
312
313 /* Alternative function doesn't clearly provide a direction */
314 if (fsel > BCM2835_FSEL_GPIO_OUT)
315 return -EINVAL;
316
317 return (fsel == BCM2835_FSEL_GPIO_IN);
318}
319
e1b2dc70
SA		 320static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
321{
e19a5f79 322 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
e1b2dc70
SA		 323
324 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
325}
326
4c02cba1
SW		 327static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
328 unsigned offset, int value)
329{
330 bcm2835_gpio_set(chip, offset, value);
331 return pinctrl_gpio_direction_output(chip->base + offset);
332}
333
531bcf73 334static const struct gpio_chip bcm2835_gpio_chip = {
e1b2dc70
SA		 335 .label = MODULE_NAME,
336 .owner = THIS_MODULE,
98c85d58
JG		 337 .request = gpiochip_generic_request,
338 .free = gpiochip_generic_free,
e1b2dc70
SA		 339 .direction_input = bcm2835_gpio_direction_input,
340 .direction_output = bcm2835_gpio_direction_output,
20b3d2a7 341 .get_direction = bcm2835_gpio_get_direction,
e1b2dc70
SA		 342 .get = bcm2835_gpio_get,
343 .set = bcm2835_gpio_set,
e1b2dc70
SA		 344 .base = -1,
345 .ngpio = BCM2835_NUM_GPIOS,
9fb1f39e 346 .can_sleep = false,
e1b2dc70
SA		 347};
348
85ae9e51
LW		 349static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
350 unsigned int bank, u32 mask)
e1b2dc70 351{
e1b2dc70
SA		 352 unsigned long events;
353 unsigned offset;
354 unsigned gpio;
e1b2dc70
SA		 355
356 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
00445b5d 357 events &= mask;
e1b2dc70
SA		 358 events &= pc->enabled_irq_map[bank];
359 for_each_set_bit(offset, &events, 32) {
360 gpio = (32 * bank) + offset;
9e9355bb 361 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
85ae9e51 362 gpio));
e1b2dc70 363 }
00445b5d
PE		 364}
365
85ae9e51 366static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
00445b5d 367{
85ae9e51
LW		 368 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
369 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
370 struct irq_chip *host_chip = irq_desc_get_chip(desc);
371 int irq = irq_desc_get_irq(desc);
372 int group;
373 int i;
374
375 for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
376 if (pc->irq[i] == irq) {
0d885e9d 377 group = i;
85ae9e51
LW		 378 break;
379 }
380 }
381 /* This should not happen, every IRQ has a bank */
382 if (i == ARRAY_SIZE(pc->irq))
383 BUG();
00445b5d 384
85ae9e51
LW		 385 chained_irq_enter(host_chip, desc);
386
387 switch (group) {
00445b5d 388 case 0: /* IRQ0 covers GPIOs 0-27 */
85ae9e51 389 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
00445b5d
PE		 390 break;
391 case 1: /* IRQ1 covers GPIOs 28-45 */
85ae9e51
LW		 392 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
393 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
00445b5d
PE		 394 break;
395 case 2: /* IRQ2 covers GPIOs 46-53 */
85ae9e51 396 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
00445b5d
PE		 397 break;
398 }
399
85ae9e51 400 chained_irq_exit(host_chip, desc);
e1b2dc70
SA		 401}
402
403static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
404 unsigned reg, unsigned offset, bool enable)
405{
406 u32 value;
407 reg += GPIO_REG_OFFSET(offset) * 4;
408 value = bcm2835_gpio_rd(pc, reg);
409 if (enable)
410 value |= BIT(GPIO_REG_SHIFT(offset));
411 else
412 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
413 bcm2835_gpio_wr(pc, reg, value);
414}
415
416/* fast path for IRQ handler */
417static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
418 unsigned offset, bool enable)
419{
420 switch (pc->irq_type[offset]) {
421 case IRQ_TYPE_EDGE_RISING:
422 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
423 break;
424
425 case IRQ_TYPE_EDGE_FALLING:
426 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
427 break;
428
429 case IRQ_TYPE_EDGE_BOTH:
430 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
431 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
432 break;
433
434 case IRQ_TYPE_LEVEL_HIGH:
435 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
436 break;
437
438 case IRQ_TYPE_LEVEL_LOW:
439 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
440 break;
441 }
442}
443
444static void bcm2835_gpio_irq_enable(struct irq_data *data)
445{
85ae9e51
LW		 446 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
447 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
e1b2dc70
SA		 448 unsigned gpio = irqd_to_hwirq(data);
449 unsigned offset = GPIO_REG_SHIFT(gpio);
450 unsigned bank = GPIO_REG_OFFSET(gpio);
451 unsigned long flags;
452
3c7b30f7 453 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
e1b2dc70
SA		 454 set_bit(offset, &pc->enabled_irq_map[bank]);
455 bcm2835_gpio_irq_config(pc, gpio, true);
3c7b30f7 456 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
e1b2dc70
SA		 457}
458
459static void bcm2835_gpio_irq_disable(struct irq_data *data)
460{
85ae9e51
LW		 461 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
462 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
e1b2dc70
SA		 463 unsigned gpio = irqd_to_hwirq(data);
464 unsigned offset = GPIO_REG_SHIFT(gpio);
465 unsigned bank = GPIO_REG_OFFSET(gpio);
466 unsigned long flags;
467
3c7b30f7 468 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
e1b2dc70 469 bcm2835_gpio_irq_config(pc, gpio, false);
714b1dd8
JB		 470 /* Clear events that were latched prior to clearing event sources */
471 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
e1b2dc70 472 clear_bit(offset, &pc->enabled_irq_map[bank]);
3c7b30f7 473 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
e1b2dc70
SA		 474}
475
476static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
477 unsigned offset, unsigned int type)
478{
479 switch (type) {
480 case IRQ_TYPE_NONE:
481 case IRQ_TYPE_EDGE_RISING:
482 case IRQ_TYPE_EDGE_FALLING:
483 case IRQ_TYPE_EDGE_BOTH:
484 case IRQ_TYPE_LEVEL_HIGH:
485 case IRQ_TYPE_LEVEL_LOW:
486 pc->irq_type[offset] = type;
487 break;
488
489 default:
490 return -EINVAL;
491 }
492 return 0;
493}
494
495/* slower path for reconfiguring IRQ type */
496static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
497 unsigned offset, unsigned int type)
498{
499 switch (type) {
500 case IRQ_TYPE_NONE:
501 if (pc->irq_type[offset] != type) {
502 bcm2835_gpio_irq_config(pc, offset, false);
503 pc->irq_type[offset] = type;
504 }
505 break;
506
507 case IRQ_TYPE_EDGE_RISING:
508 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
509 /* RISING already enabled, disable FALLING */
510 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
511 bcm2835_gpio_irq_config(pc, offset, false);
512 pc->irq_type[offset] = type;
513 } else if (pc->irq_type[offset] != type) {
514 bcm2835_gpio_irq_config(pc, offset, false);
515 pc->irq_type[offset] = type;
516 bcm2835_gpio_irq_config(pc, offset, true);
517 }
518 break;
519
520 case IRQ_TYPE_EDGE_FALLING:
521 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
522 /* FALLING already enabled, disable RISING */
523 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
524 bcm2835_gpio_irq_config(pc, offset, false);
525 pc->irq_type[offset] = type;
526 } else if (pc->irq_type[offset] != type) {
527 bcm2835_gpio_irq_config(pc, offset, false);
528 pc->irq_type[offset] = type;
529 bcm2835_gpio_irq_config(pc, offset, true);
530 }
531 break;
532
533 case IRQ_TYPE_EDGE_BOTH:
534 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
535 /* RISING already enabled, enable FALLING too */
536 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
537 bcm2835_gpio_irq_config(pc, offset, true);
538 pc->irq_type[offset] = type;
539 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
540 /* FALLING already enabled, enable RISING too */
541 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
542 bcm2835_gpio_irq_config(pc, offset, true);
543 pc->irq_type[offset] = type;
544 } else if (pc->irq_type[offset] != type) {
545 bcm2835_gpio_irq_config(pc, offset, false);
546 pc->irq_type[offset] = type;
547 bcm2835_gpio_irq_config(pc, offset, true);
548 }
549 break;
550
551 case IRQ_TYPE_LEVEL_HIGH:
552 case IRQ_TYPE_LEVEL_LOW:
553 if (pc->irq_type[offset] != type) {
554 bcm2835_gpio_irq_config(pc, offset, false);
555 pc->irq_type[offset] = type;
556 bcm2835_gpio_irq_config(pc, offset, true);
557 }
558 break;
559
560 default:
561 return -EINVAL;
562 }
563 return 0;
564}
565
566static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
567{
85ae9e51
LW		 568 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
569 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
e1b2dc70
SA		 570 unsigned gpio = irqd_to_hwirq(data);
571 unsigned offset = GPIO_REG_SHIFT(gpio);
572 unsigned bank = GPIO_REG_OFFSET(gpio);
573 unsigned long flags;
574 int ret;
575
3c7b30f7 576 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
e1b2dc70
SA		 577
578 if (test_bit(offset, &pc->enabled_irq_map[bank]))
579 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
580 else
581 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
582
b8a19382 583 if (type & IRQ_TYPE_EDGE_BOTH)
1aa74fd0 584 irq_set_handler_locked(data, handle_edge_irq);
b8a19382 585 else
1aa74fd0 586 irq_set_handler_locked(data, handle_level_irq);
b8a19382 587
3c7b30f7 588 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
e1b2dc70
SA		 589
590 return ret;
591}
592
b8a19382
CK		 593static void bcm2835_gpio_irq_ack(struct irq_data *data)
594{
85ae9e51
LW		 595 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
596 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
b8a19382
CK		 597 unsigned gpio = irqd_to_hwirq(data);
598
599 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
600}
601
e1b2dc70
SA		 602static struct irq_chip bcm2835_gpio_irq_chip = {
603 .name = MODULE_NAME,
604 .irq_enable = bcm2835_gpio_irq_enable,
605 .irq_disable = bcm2835_gpio_irq_disable,
606 .irq_set_type = bcm2835_gpio_irq_set_type,
b8a19382
CK		 607 .irq_ack = bcm2835_gpio_irq_ack,
608 .irq_mask = bcm2835_gpio_irq_disable,
609 .irq_unmask = bcm2835_gpio_irq_enable,
e1b2dc70
SA		 610};
611
612static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
613{
614 return ARRAY_SIZE(bcm2835_gpio_groups);
615}
616
617static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
618 unsigned selector)
619{
620 return bcm2835_gpio_groups[selector];
621}
622
623static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
624 unsigned selector,
625 const unsigned **pins,
626 unsigned *num_pins)
627{
628 *pins = &bcm2835_gpio_pins[selector].number;
629 *num_pins = 1;
630
631 return 0;
632}
633
634static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
635 struct seq_file *s,
636 unsigned offset)
637{
638 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
85ae9e51 639 struct gpio_chip *chip = &pc->gpio_chip;
e1b2dc70
SA		 640 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
641 const char *fname = bcm2835_functions[fsel];
642 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
f0fbe7bc 643 int irq = irq_find_mapping(chip->irq.domain, offset);
e1b2dc70
SA		 644
645 seq_printf(s, "function %s in %s; irq %d (%s)",
646 fname, value ? "hi" : "lo",
647 irq, irq_type_names[pc->irq_type[offset]]);
648}
649
650static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
651 struct pinctrl_map *maps, unsigned num_maps)
652{
653 int i;
654
655 for (i = 0; i < num_maps; i++)
656 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
657 kfree(maps[i].data.configs.configs);
658
659 kfree(maps);
660}
661
662static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
663 struct device_node *np, u32 pin, u32 fnum,
664 struct pinctrl_map **maps)
665{
666 struct pinctrl_map *map = *maps;
667
668 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
f5292d06 669 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
e1b2dc70
SA		 670 return -EINVAL;
671 }
672
673 map->type = PIN_MAP_TYPE_MUX_GROUP;
674 map->data.mux.group = bcm2835_gpio_groups[pin];
675 map->data.mux.function = bcm2835_functions[fnum];
676 (*maps)++;
677
678 return 0;
679}
680
681static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
682 struct device_node *np, u32 pin, u32 pull,
683 struct pinctrl_map **maps)
684{
685 struct pinctrl_map *map = *maps;
686 unsigned long *configs;
687
688 if (pull > 2) {
f5292d06 689 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
e1b2dc70
SA		 690 return -EINVAL;
691 }
692
693 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
694 if (!configs)
695 return -ENOMEM;
0de70495 696 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
e1b2dc70
SA		 697
698 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
699 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
700 map->data.configs.configs = configs;
701 map->data.configs.num_configs = 1;
702 (*maps)++;
703
704 return 0;
705}
706
e1b2dc70
SA		 707static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
708 struct device_node *np,
0de70495 709 struct pinctrl_map **map, unsigned int *num_maps)
e1b2dc70
SA		 710{
711 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
712 struct property *pins, *funcs, *pulls;
713 int num_pins, num_funcs, num_pulls, maps_per_pin;
714 struct pinctrl_map *maps, *cur_map;
715 int i, err;
716 u32 pin, func, pull;
717
0de70495
MC		 718 /* Check for generic binding in this node */
719 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
720 if (err || *num_maps)
721 return err;
722
723 /* Generic binding did not find anything continue with legacy parse */
e1b2dc70
SA		 724 pins = of_find_property(np, "brcm,pins", NULL);
725 if (!pins) {
f5292d06 726 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
e1b2dc70
SA		 727 return -EINVAL;
728 }
729
730 funcs = of_find_property(np, "brcm,function", NULL);
731 pulls = of_find_property(np, "brcm,pull", NULL);
732
733 if (!funcs && !pulls) {
734 dev_err(pc->dev,
f5292d06
RH		 735 "%pOF: neither brcm,function nor brcm,pull specified\n",
736 np);
e1b2dc70
SA		 737 return -EINVAL;
738 }
739
740 num_pins = pins->length / 4;
741 num_funcs = funcs ? (funcs->length / 4) : 0;
742 num_pulls = pulls ? (pulls->length / 4) : 0;
743
744 if (num_funcs > 1 && num_funcs != num_pins) {
745 dev_err(pc->dev,
f5292d06
RH		 746 "%pOF: brcm,function must have 1 or %d entries\n",
747 np, num_pins);
e1b2dc70
SA		 748 return -EINVAL;
749 }
750
751 if (num_pulls > 1 && num_pulls != num_pins) {
752 dev_err(pc->dev,
f5292d06
RH		 753 "%pOF: brcm,pull must have 1 or %d entries\n",
754 np, num_pins);
e1b2dc70
SA		 755 return -EINVAL;
756 }
757
758 maps_per_pin = 0;
759 if (num_funcs)
760 maps_per_pin++;
761 if (num_pulls)
762 maps_per_pin++;
6396bb22
KC		 763 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
764 GFP_KERNEL);
e1b2dc70
SA		 765 if (!maps)
766 return -ENOMEM;
767
768 for (i = 0; i < num_pins; i++) {
ce63d6d4
SW		 769 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
770 if (err)
771 goto out;
e1b2dc70 772 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
f5292d06
RH		 773 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
774 np, pin);
e1b2dc70
SA		 775 err = -EINVAL;
776 goto out;
777 }
778
779 if (num_funcs) {
ce63d6d4
SW		 780 err = of_property_read_u32_index(np, "brcm,function",
781 (num_funcs > 1) ? i : 0, &func);
782 if (err)
783 goto out;
e1b2dc70
SA		 784 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
785 func, &cur_map);
786 if (err)
787 goto out;
788 }
789 if (num_pulls) {
ce63d6d4 790 err = of_property_read_u32_index(np, "brcm,pull",
2c7e3306 791 (num_pulls > 1) ? i : 0, &pull);
ce63d6d4
SW		 792 if (err)
793 goto out;
e1b2dc70
SA		 794 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
795 pull, &cur_map);
796 if (err)
797 goto out;
798 }
799 }
800
801 *map = maps;
802 *num_maps = num_pins * maps_per_pin;
803
804 return 0;
805
806out:
53653c6b 807 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
e1b2dc70
SA		 808 return err;
809}
810
022ab148 811static const struct pinctrl_ops bcm2835_pctl_ops = {
e1b2dc70
SA		 812 .get_groups_count = bcm2835_pctl_get_groups_count,
813 .get_group_name = bcm2835_pctl_get_group_name,
814 .get_group_pins = bcm2835_pctl_get_group_pins,
815 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
816 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
817 .dt_free_map = bcm2835_pctl_dt_free_map,
818};
819
ccca1ad5
PE		 820static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
821 unsigned offset)
822{
823 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
824
825 /* disable by setting to GPIO_IN */
826 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
827 return 0;
828}
829
e1b2dc70
SA		 830static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
831{
832 return BCM2835_FSEL_COUNT;
833}
834
835static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
836 unsigned selector)
837{
838 return bcm2835_functions[selector];
839}
840
841static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
842 unsigned selector,
843 const char * const **groups,
844 unsigned * const num_groups)
845{
846 /* every pin can do every function */
847 *groups = bcm2835_gpio_groups;
848 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
849
850 return 0;
851}
852
03e9f0ca 853static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
e1b2dc70
SA		 854 unsigned func_selector,
855 unsigned group_selector)
856{
857 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
858
859 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
860
861 return 0;
862}
863
e1b2dc70
SA		 864static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
865 struct pinctrl_gpio_range *range,
866 unsigned offset)
867{
868 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
869
870 /* disable by setting to GPIO_IN */
871 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
872}
873
874static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
875 struct pinctrl_gpio_range *range,
876 unsigned offset,
877 bool input)
878{
879 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
880 enum bcm2835_fsel fsel = input ?
881 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
882
883 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
884
885 return 0;
886}
887
022ab148 888static const struct pinmux_ops bcm2835_pmx_ops = {
ccca1ad5 889 .free = bcm2835_pmx_free,
e1b2dc70
SA		 890 .get_functions_count = bcm2835_pmx_get_functions_count,
891 .get_function_name = bcm2835_pmx_get_function_name,
892 .get_function_groups = bcm2835_pmx_get_function_groups,
03e9f0ca 893 .set_mux = bcm2835_pmx_set,
e1b2dc70
SA		 894 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
895 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
896};
897
898static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
899 unsigned pin, unsigned long *config)
900{
901 /* No way to read back config in HW */
902 return -ENOTSUPP;
903}
904
0de70495
MC		 905static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
906 unsigned int pin, unsigned int arg)
907{
908 u32 off, bit;
909
910 off = GPIO_REG_OFFSET(pin);
911 bit = GPIO_REG_SHIFT(pin);
912
913 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
914 /*
915 * BCM2835 datasheet say to wait 150 cycles, but not of what.
916 * But the VideoCore firmware delay for this operation
917 * based nearly on the same amount of VPU cycles and this clock
918 * runs at 250 MHz.
919 */
920 udelay(1);
921 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
922 udelay(1);
923 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
924}
925
e1b2dc70 926static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
0de70495
MC		 927 unsigned int pin, unsigned long *configs,
928 unsigned int num_configs)
e1b2dc70
SA		 929{
930 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
0de70495 931 u32 param, arg;
03b054e9 932 int i;
e1b2dc70 933
03b054e9 934 for (i = 0; i < num_configs; i++) {
0de70495
MC		 935 param = pinconf_to_config_param(configs[i]);
936 arg = pinconf_to_config_argument(configs[i]);
937
938 switch (param) {
939 /* Set legacy brcm,pull */
940 case BCM2835_PINCONF_PARAM_PULL:
941 bcm2835_pull_config_set(pc, pin, arg);
942 break;
943
944 /* Set pull generic bindings */
945 case PIN_CONFIG_BIAS_DISABLE:
946 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
947 break;
948
949 case PIN_CONFIG_BIAS_PULL_DOWN:
950 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
951 break;
952
953 case PIN_CONFIG_BIAS_PULL_UP:
954 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
955 break;
03b054e9 956
90b60552
MC		 957 /* Set output-high or output-low */
958 case PIN_CONFIG_OUTPUT:
959 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
960 break;
961
0de70495 962 default:
03b054e9
SY		 963 return -EINVAL;
964
0de70495 965 } /* switch param type */
03b054e9 966 } /* for each config */
e1b2dc70
SA		 967
968 return 0;
969}
970
022ab148 971static const struct pinconf_ops bcm2835_pinconf_ops = {
1cb66f08 972 .is_generic = true,
e1b2dc70
SA		 973 .pin_config_get = bcm2835_pinconf_get,
974 .pin_config_set = bcm2835_pinconf_set,
975};
976
977static struct pinctrl_desc bcm2835_pinctrl_desc = {
978 .name = MODULE_NAME,
979 .pins = bcm2835_gpio_pins,
980 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
981 .pctlops = &bcm2835_pctl_ops,
982 .pmxops = &bcm2835_pmx_ops,
983 .confops = &bcm2835_pinconf_ops,
984 .owner = THIS_MODULE,
985};
986
84db00ba 987static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
e1b2dc70
SA		 988 .name = MODULE_NAME,
989 .npins = BCM2835_NUM_GPIOS,
990};
991
150632b0 992static int bcm2835_pinctrl_probe(struct platform_device *pdev)
e1b2dc70
SA		 993{
994 struct device *dev = &pdev->dev;
995 struct device_node *np = dev->of_node;
996 struct bcm2835_pinctrl *pc;
997 struct resource iomem;
998 int err, i;
999 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
1000 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
1001
1002 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1003 if (!pc)
1004 return -ENOMEM;
1005
1006 platform_set_drvdata(pdev, pc);
1007 pc->dev = dev;
1008
1009 err = of_address_to_resource(np, 0, &iomem);
1010 if (err) {
1011 dev_err(dev, "could not get IO memory\n");
1012 return err;
1013 }
1014
9e0c1fb2
TR		 1015 pc->base = devm_ioremap_resource(dev, &iomem);
1016 if (IS_ERR(pc->base))
1017 return PTR_ERR(pc->base);
e1b2dc70
SA		 1018
1019 pc->gpio_chip = bcm2835_gpio_chip;
58383c78 1020 pc->gpio_chip.parent = dev;
e1b2dc70
SA		 1021 pc->gpio_chip.of_node = np;
1022
e1b2dc70
SA		 1023 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1024 unsigned long events;
1025 unsigned offset;
e1b2dc70
SA		 1026
1027 /* clear event detection flags */
1028 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1029 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1030 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1031 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1032 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1033 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1034
1035 /* clear all the events */
1036 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1037 for_each_set_bit(offset, &events, 32)
1038 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1039
3c7b30f7 1040 raw_spin_lock_init(&pc->irq_lock[i]);
00445b5d
PE		 1041 }
1042
e19a5f79 1043 err = gpiochip_add_data(&pc->gpio_chip, pc);
e1b2dc70
SA		 1044 if (err) {
1045 dev_err(dev, "could not add GPIO chip\n");
1046 return err;
1047 }
1048
85ae9e51
LW		 1049 err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
1050 0, handle_level_irq, IRQ_TYPE_NONE);
1051 if (err) {
1052 dev_info(dev, "could not add irqchip\n");
1053 return err;
1054 }
1055
1056 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1057 pc->irq[i] = irq_of_parse_and_map(np, i);
37a2f8e5
SW		 1058
1059 if (pc->irq[i] == 0)
1060 continue;
1061
85ae9e51
LW		 1062 /*
1063 * Use the same handler for all groups: this is necessary
1064 * since we use one gpiochip to cover all lines - the
1065 * irq handler then needs to figure out which group and
1066 * bank that was firing the IRQ and look up the per-group
1067 * and bank data.
1068 */
1069 gpiochip_set_chained_irqchip(&pc->gpio_chip,
1070 &bcm2835_gpio_irq_chip,
1071 pc->irq[i],
1072 bcm2835_gpio_irq_handler);
1073 }
1074
5f276f67 1075 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
323de9ef 1076 if (IS_ERR(pc->pctl_dev)) {
e1b2dc70 1077 gpiochip_remove(&pc->gpio_chip);
323de9ef 1078 return PTR_ERR(pc->pctl_dev);
e1b2dc70
SA		 1079 }
1080
1081 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1082 pc->gpio_range.base = pc->gpio_chip.base;
1083 pc->gpio_range.gc = &pc->gpio_chip;
1084 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1085
1086 return 0;
1087}
1088
baa9946e 1089static const struct of_device_id bcm2835_pinctrl_match[] = {
e1b2dc70
SA		 1090 { .compatible = "brcm,bcm2835-gpio" },
1091 {}
1092};
e1b2dc70
SA		 1093
1094static struct platform_driver bcm2835_pinctrl_driver = {
1095 .probe = bcm2835_pinctrl_probe,
e1b2dc70
SA		 1096 .driver = {
1097 .name = MODULE_NAME,
e1b2dc70 1098 .of_match_table = bcm2835_pinctrl_match,
34f46848 1099 .suppress_bind_attrs = true,
e1b2dc70
SA		 1100 },
1101};
34f46848 1102builtin_platform_driver(bcm2835_pinctrl_driver);
Linux 6.x block layer and io_uring tree(s)