Commit | Line | Data |
---|---|---|
eee0e5da | 1 | // SPDX-License-Identifier: GPL-2.0 |
f3b5a8d9 YS |
2 | /* |
3 | * Renesas R-Car Gen3 for USB2.0 PHY driver | |
4 | * | |
7e0540f4 | 5 | * Copyright (C) 2015-2017 Renesas Electronics Corporation |
f3b5a8d9 YS |
6 | * |
7 | * This is based on the phy-rcar-gen2 driver: | |
8 | * Copyright (C) 2014 Renesas Solutions Corp. | |
9 | * Copyright (C) 2014 Cogent Embedded, Inc. | |
f3b5a8d9 YS |
10 | */ |
11 | ||
176aa360 | 12 | #include <linux/extcon-provider.h> |
9f391c57 | 13 | #include <linux/interrupt.h> |
f3b5a8d9 YS |
14 | #include <linux/io.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_address.h> | |
9adaaa9e | 18 | #include <linux/of_device.h> |
f3b5a8d9 YS |
19 | #include <linux/phy/phy.h> |
20 | #include <linux/platform_device.h> | |
441a681b | 21 | #include <linux/pm_runtime.h> |
6dcfd7c3 | 22 | #include <linux/regulator/consumer.h> |
7e0540f4 | 23 | #include <linux/usb/of.h> |
c14f8a40 | 24 | #include <linux/workqueue.h> |
f3b5a8d9 YS |
25 | |
26 | /******* USB2.0 Host registers (original offset is +0x200) *******/ | |
27 | #define USB2_INT_ENABLE 0x000 | |
28 | #define USB2_USBCTR 0x00c | |
29 | #define USB2_SPD_RSM_TIMSET 0x10c | |
30 | #define USB2_OC_TIMSET 0x110 | |
1114e2d3 | 31 | #define USB2_COMMCTRL 0x600 |
9f391c57 YS |
32 | #define USB2_OBINTSTA 0x604 |
33 | #define USB2_OBINTEN 0x608 | |
1114e2d3 YS |
34 | #define USB2_VBCTRL 0x60c |
35 | #define USB2_LINECTRL1 0x610 | |
36 | #define USB2_ADPCTRL 0x630 | |
f3b5a8d9 YS |
37 | |
38 | /* INT_ENABLE */ | |
9f391c57 | 39 | #define USB2_INT_ENABLE_UCOM_INTEN BIT(3) |
f3b5a8d9 YS |
40 | #define USB2_INT_ENABLE_USBH_INTB_EN BIT(2) |
41 | #define USB2_INT_ENABLE_USBH_INTA_EN BIT(1) | |
9f391c57 YS |
42 | #define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_UCOM_INTEN | \ |
43 | USB2_INT_ENABLE_USBH_INTB_EN | \ | |
f3b5a8d9 YS |
44 | USB2_INT_ENABLE_USBH_INTA_EN) |
45 | ||
46 | /* USBCTR */ | |
47 | #define USB2_USBCTR_DIRPD BIT(2) | |
48 | #define USB2_USBCTR_PLL_RST BIT(1) | |
49 | ||
50 | /* SPD_RSM_TIMSET */ | |
51 | #define USB2_SPD_RSM_TIMSET_INIT 0x014e029b | |
52 | ||
53 | /* OC_TIMSET */ | |
54 | #define USB2_OC_TIMSET_INIT 0x000209ab | |
55 | ||
1114e2d3 YS |
56 | /* COMMCTRL */ |
57 | #define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */ | |
58 | ||
9f391c57 YS |
59 | /* OBINTSTA and OBINTEN */ |
60 | #define USB2_OBINT_SESSVLDCHG BIT(12) | |
61 | #define USB2_OBINT_IDDIGCHG BIT(11) | |
62 | #define USB2_OBINT_BITS (USB2_OBINT_SESSVLDCHG | \ | |
63 | USB2_OBINT_IDDIGCHG) | |
64 | ||
1114e2d3 YS |
65 | /* VBCTRL */ |
66 | #define USB2_VBCTRL_DRVVBUSSEL BIT(8) | |
67 | ||
68 | /* LINECTRL1 */ | |
69 | #define USB2_LINECTRL1_DPRPD_EN BIT(19) | |
70 | #define USB2_LINECTRL1_DP_RPD BIT(18) | |
71 | #define USB2_LINECTRL1_DMRPD_EN BIT(17) | |
72 | #define USB2_LINECTRL1_DM_RPD BIT(16) | |
9bb86777 | 73 | #define USB2_LINECTRL1_OPMODE_NODRV BIT(6) |
1114e2d3 YS |
74 | |
75 | /* ADPCTRL */ | |
76 | #define USB2_ADPCTRL_OTGSESSVLD BIT(20) | |
77 | #define USB2_ADPCTRL_IDDIG BIT(19) | |
78 | #define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */ | |
79 | #define USB2_ADPCTRL_DRVVBUS BIT(4) | |
80 | ||
f3b5a8d9 | 81 | struct rcar_gen3_chan { |
801a69c7 | 82 | void __iomem *base; |
2b38543c | 83 | struct extcon_dev *extcon; |
f3b5a8d9 | 84 | struct phy *phy; |
6dcfd7c3 | 85 | struct regulator *vbus; |
c14f8a40 | 86 | struct work_struct work; |
73801b90 | 87 | enum usb_dr_mode dr_mode; |
c14f8a40 | 88 | bool extcon_host; |
979b519c | 89 | bool is_otg_channel; |
cfdc6634 | 90 | bool uses_otg_pins; |
f3b5a8d9 YS |
91 | }; |
92 | ||
979b519c YS |
93 | /* |
94 | * Combination about is_otg_channel and uses_otg_pins: | |
95 | * | |
96 | * Parameters || Behaviors | |
97 | * is_otg_channel | uses_otg_pins || irqs | role sysfs | |
98 | * ---------------------+---------------++--------------+------------ | |
99 | * true | true || enabled | enabled | |
100 | * true | false || disabled | enabled | |
101 | * false | any || disabled | disabled | |
102 | */ | |
103 | ||
c14f8a40 YS |
104 | static void rcar_gen3_phy_usb2_work(struct work_struct *work) |
105 | { | |
106 | struct rcar_gen3_chan *ch = container_of(work, struct rcar_gen3_chan, | |
107 | work); | |
108 | ||
109 | if (ch->extcon_host) { | |
c6f30a5b CC |
110 | extcon_set_state_sync(ch->extcon, EXTCON_USB_HOST, true); |
111 | extcon_set_state_sync(ch->extcon, EXTCON_USB, false); | |
c14f8a40 | 112 | } else { |
c6f30a5b CC |
113 | extcon_set_state_sync(ch->extcon, EXTCON_USB_HOST, false); |
114 | extcon_set_state_sync(ch->extcon, EXTCON_USB, true); | |
c14f8a40 YS |
115 | } |
116 | } | |
117 | ||
1114e2d3 YS |
118 | static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host) |
119 | { | |
801a69c7 | 120 | void __iomem *usb2_base = ch->base; |
1114e2d3 YS |
121 | u32 val = readl(usb2_base + USB2_COMMCTRL); |
122 | ||
123 | dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, host); | |
124 | if (host) | |
125 | val &= ~USB2_COMMCTRL_OTG_PERI; | |
126 | else | |
127 | val |= USB2_COMMCTRL_OTG_PERI; | |
128 | writel(val, usb2_base + USB2_COMMCTRL); | |
129 | } | |
130 | ||
131 | static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm) | |
132 | { | |
801a69c7 | 133 | void __iomem *usb2_base = ch->base; |
1114e2d3 YS |
134 | u32 val = readl(usb2_base + USB2_LINECTRL1); |
135 | ||
136 | dev_vdbg(&ch->phy->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm); | |
137 | val &= ~(USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD); | |
138 | if (dp) | |
139 | val |= USB2_LINECTRL1_DP_RPD; | |
140 | if (dm) | |
141 | val |= USB2_LINECTRL1_DM_RPD; | |
142 | writel(val, usb2_base + USB2_LINECTRL1); | |
143 | } | |
144 | ||
145 | static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus) | |
146 | { | |
801a69c7 | 147 | void __iomem *usb2_base = ch->base; |
1114e2d3 YS |
148 | u32 val = readl(usb2_base + USB2_ADPCTRL); |
149 | ||
150 | dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, vbus); | |
151 | if (vbus) | |
152 | val |= USB2_ADPCTRL_DRVVBUS; | |
153 | else | |
154 | val &= ~USB2_ADPCTRL_DRVVBUS; | |
155 | writel(val, usb2_base + USB2_ADPCTRL); | |
156 | } | |
157 | ||
7ab0305d YS |
158 | static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable) |
159 | { | |
160 | void __iomem *usb2_base = ch->base; | |
161 | u32 val = readl(usb2_base + USB2_OBINTEN); | |
162 | ||
a602152c | 163 | if (ch->uses_otg_pins && enable) |
7ab0305d YS |
164 | val |= USB2_OBINT_BITS; |
165 | else | |
166 | val &= ~USB2_OBINT_BITS; | |
167 | writel(val, usb2_base + USB2_OBINTEN); | |
168 | } | |
169 | ||
1114e2d3 YS |
170 | static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch) |
171 | { | |
172 | rcar_gen3_set_linectrl(ch, 1, 1); | |
173 | rcar_gen3_set_host_mode(ch, 1); | |
174 | rcar_gen3_enable_vbus_ctrl(ch, 1); | |
2b38543c | 175 | |
c14f8a40 YS |
176 | ch->extcon_host = true; |
177 | schedule_work(&ch->work); | |
1114e2d3 YS |
178 | } |
179 | ||
180 | static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch) | |
181 | { | |
182 | rcar_gen3_set_linectrl(ch, 0, 1); | |
183 | rcar_gen3_set_host_mode(ch, 0); | |
184 | rcar_gen3_enable_vbus_ctrl(ch, 0); | |
2b38543c | 185 | |
c14f8a40 YS |
186 | ch->extcon_host = false; |
187 | schedule_work(&ch->work); | |
1114e2d3 YS |
188 | } |
189 | ||
9bb86777 YS |
190 | static void rcar_gen3_init_for_b_host(struct rcar_gen3_chan *ch) |
191 | { | |
192 | void __iomem *usb2_base = ch->base; | |
193 | u32 val; | |
194 | ||
195 | val = readl(usb2_base + USB2_LINECTRL1); | |
196 | writel(val | USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1); | |
197 | ||
198 | rcar_gen3_set_linectrl(ch, 1, 1); | |
199 | rcar_gen3_set_host_mode(ch, 1); | |
200 | rcar_gen3_enable_vbus_ctrl(ch, 0); | |
201 | ||
202 | val = readl(usb2_base + USB2_LINECTRL1); | |
203 | writel(val & ~USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1); | |
204 | } | |
205 | ||
206 | static void rcar_gen3_init_for_a_peri(struct rcar_gen3_chan *ch) | |
207 | { | |
208 | rcar_gen3_set_linectrl(ch, 0, 1); | |
209 | rcar_gen3_set_host_mode(ch, 0); | |
210 | rcar_gen3_enable_vbus_ctrl(ch, 1); | |
211 | } | |
212 | ||
213 | static void rcar_gen3_init_from_a_peri_to_a_host(struct rcar_gen3_chan *ch) | |
214 | { | |
7ab0305d | 215 | rcar_gen3_control_otg_irq(ch, 0); |
9bb86777 | 216 | |
09938ea9 | 217 | rcar_gen3_enable_vbus_ctrl(ch, 1); |
9bb86777 YS |
218 | rcar_gen3_init_for_host(ch); |
219 | ||
7ab0305d | 220 | rcar_gen3_control_otg_irq(ch, 1); |
9bb86777 YS |
221 | } |
222 | ||
1114e2d3 YS |
223 | static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch) |
224 | { | |
a602152c YS |
225 | if (!ch->uses_otg_pins) |
226 | return (ch->dr_mode == USB_DR_MODE_HOST) ? false : true; | |
227 | ||
801a69c7 | 228 | return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG); |
1114e2d3 YS |
229 | } |
230 | ||
231 | static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch) | |
232 | { | |
6762925d | 233 | if (!rcar_gen3_check_id(ch)) |
1114e2d3 YS |
234 | rcar_gen3_init_for_host(ch); |
235 | else | |
236 | rcar_gen3_init_for_peri(ch); | |
237 | } | |
238 | ||
9bb86777 YS |
239 | static bool rcar_gen3_is_host(struct rcar_gen3_chan *ch) |
240 | { | |
241 | return !(readl(ch->base + USB2_COMMCTRL) & USB2_COMMCTRL_OTG_PERI); | |
242 | } | |
243 | ||
b56acc82 YS |
244 | static enum phy_mode rcar_gen3_get_phy_mode(struct rcar_gen3_chan *ch) |
245 | { | |
246 | if (rcar_gen3_is_host(ch)) | |
247 | return PHY_MODE_USB_HOST; | |
248 | ||
249 | return PHY_MODE_USB_DEVICE; | |
250 | } | |
251 | ||
9bb86777 YS |
252 | static ssize_t role_store(struct device *dev, struct device_attribute *attr, |
253 | const char *buf, size_t count) | |
254 | { | |
255 | struct rcar_gen3_chan *ch = dev_get_drvdata(dev); | |
b56acc82 YS |
256 | bool is_b_device; |
257 | enum phy_mode cur_mode, new_mode; | |
9bb86777 | 258 | |
979b519c | 259 | if (!ch->is_otg_channel || !ch->phy->init_count) |
9bb86777 YS |
260 | return -EIO; |
261 | ||
9bb86777 | 262 | if (!strncmp(buf, "host", strlen("host"))) |
b56acc82 | 263 | new_mode = PHY_MODE_USB_HOST; |
9bb86777 | 264 | else if (!strncmp(buf, "peripheral", strlen("peripheral"))) |
b56acc82 | 265 | new_mode = PHY_MODE_USB_DEVICE; |
9bb86777 YS |
266 | else |
267 | return -EINVAL; | |
268 | ||
b56acc82 YS |
269 | /* is_b_device: true is B-Device. false is A-Device. */ |
270 | is_b_device = rcar_gen3_check_id(ch); | |
271 | cur_mode = rcar_gen3_get_phy_mode(ch); | |
272 | ||
9bb86777 | 273 | /* If current and new mode is the same, this returns the error */ |
b56acc82 | 274 | if (cur_mode == new_mode) |
9bb86777 YS |
275 | return -EINVAL; |
276 | ||
b56acc82 | 277 | if (new_mode == PHY_MODE_USB_HOST) { /* And is_host must be false */ |
9bb86777 YS |
278 | if (!is_b_device) /* A-Peripheral */ |
279 | rcar_gen3_init_from_a_peri_to_a_host(ch); | |
280 | else /* B-Peripheral */ | |
281 | rcar_gen3_init_for_b_host(ch); | |
282 | } else { /* And is_host must be true */ | |
283 | if (!is_b_device) /* A-Host */ | |
284 | rcar_gen3_init_for_a_peri(ch); | |
285 | else /* B-Host */ | |
286 | rcar_gen3_init_for_peri(ch); | |
287 | } | |
288 | ||
289 | return count; | |
290 | } | |
291 | ||
292 | static ssize_t role_show(struct device *dev, struct device_attribute *attr, | |
293 | char *buf) | |
294 | { | |
295 | struct rcar_gen3_chan *ch = dev_get_drvdata(dev); | |
296 | ||
979b519c | 297 | if (!ch->is_otg_channel || !ch->phy->init_count) |
9bb86777 YS |
298 | return -EIO; |
299 | ||
300 | return sprintf(buf, "%s\n", rcar_gen3_is_host(ch) ? "host" : | |
301 | "peripheral"); | |
302 | } | |
303 | static DEVICE_ATTR_RW(role); | |
304 | ||
1114e2d3 YS |
305 | static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch) |
306 | { | |
801a69c7 | 307 | void __iomem *usb2_base = ch->base; |
1114e2d3 YS |
308 | u32 val; |
309 | ||
72c0339c YS |
310 | /* Should not use functions of read-modify-write a register */ |
311 | val = readl(usb2_base + USB2_LINECTRL1); | |
312 | val = (val & ~USB2_LINECTRL1_DP_RPD) | USB2_LINECTRL1_DPRPD_EN | | |
313 | USB2_LINECTRL1_DMRPD_EN | USB2_LINECTRL1_DM_RPD; | |
314 | writel(val, usb2_base + USB2_LINECTRL1); | |
315 | ||
1114e2d3 YS |
316 | val = readl(usb2_base + USB2_VBCTRL); |
317 | writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL); | |
318 | val = readl(usb2_base + USB2_ADPCTRL); | |
319 | writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL); | |
72c0339c YS |
320 | |
321 | msleep(20); | |
322 | ||
323 | writel(0xffffffff, usb2_base + USB2_OBINTSTA); | |
324 | writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTEN); | |
1114e2d3 YS |
325 | |
326 | rcar_gen3_device_recognition(ch); | |
327 | } | |
328 | ||
f3b5a8d9 YS |
329 | static int rcar_gen3_phy_usb2_init(struct phy *p) |
330 | { | |
331 | struct rcar_gen3_chan *channel = phy_get_drvdata(p); | |
801a69c7 | 332 | void __iomem *usb2_base = channel->base; |
f3b5a8d9 YS |
333 | |
334 | /* Initialize USB2 part */ | |
335 | writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE); | |
336 | writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET); | |
337 | writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET); | |
338 | ||
b9564016 | 339 | /* Initialize otg part */ |
979b519c | 340 | if (channel->is_otg_channel) |
1114e2d3 | 341 | rcar_gen3_init_otg(channel); |
f3b5a8d9 YS |
342 | |
343 | return 0; | |
344 | } | |
345 | ||
346 | static int rcar_gen3_phy_usb2_exit(struct phy *p) | |
347 | { | |
348 | struct rcar_gen3_chan *channel = phy_get_drvdata(p); | |
349 | ||
801a69c7 | 350 | writel(0, channel->base + USB2_INT_ENABLE); |
f3b5a8d9 YS |
351 | |
352 | return 0; | |
353 | } | |
354 | ||
355 | static int rcar_gen3_phy_usb2_power_on(struct phy *p) | |
356 | { | |
357 | struct rcar_gen3_chan *channel = phy_get_drvdata(p); | |
801a69c7 | 358 | void __iomem *usb2_base = channel->base; |
f3b5a8d9 | 359 | u32 val; |
6dcfd7c3 YS |
360 | int ret; |
361 | ||
362 | if (channel->vbus) { | |
363 | ret = regulator_enable(channel->vbus); | |
364 | if (ret) | |
365 | return ret; | |
366 | } | |
f3b5a8d9 YS |
367 | |
368 | val = readl(usb2_base + USB2_USBCTR); | |
369 | val |= USB2_USBCTR_PLL_RST; | |
370 | writel(val, usb2_base + USB2_USBCTR); | |
371 | val &= ~USB2_USBCTR_PLL_RST; | |
372 | writel(val, usb2_base + USB2_USBCTR); | |
373 | ||
f3b5a8d9 YS |
374 | return 0; |
375 | } | |
376 | ||
6dcfd7c3 YS |
377 | static int rcar_gen3_phy_usb2_power_off(struct phy *p) |
378 | { | |
379 | struct rcar_gen3_chan *channel = phy_get_drvdata(p); | |
380 | int ret = 0; | |
381 | ||
382 | if (channel->vbus) | |
383 | ret = regulator_disable(channel->vbus); | |
384 | ||
385 | return ret; | |
386 | } | |
387 | ||
a8df2768 | 388 | static const struct phy_ops rcar_gen3_phy_usb2_ops = { |
f3b5a8d9 YS |
389 | .init = rcar_gen3_phy_usb2_init, |
390 | .exit = rcar_gen3_phy_usb2_exit, | |
391 | .power_on = rcar_gen3_phy_usb2_power_on, | |
6dcfd7c3 | 392 | .power_off = rcar_gen3_phy_usb2_power_off, |
f3b5a8d9 YS |
393 | .owner = THIS_MODULE, |
394 | }; | |
395 | ||
9f391c57 YS |
396 | static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch) |
397 | { | |
398 | struct rcar_gen3_chan *ch = _ch; | |
801a69c7 | 399 | void __iomem *usb2_base = ch->base; |
9f391c57 YS |
400 | u32 status = readl(usb2_base + USB2_OBINTSTA); |
401 | irqreturn_t ret = IRQ_NONE; | |
402 | ||
403 | if (status & USB2_OBINT_BITS) { | |
404 | dev_vdbg(&ch->phy->dev, "%s: %08x\n", __func__, status); | |
405 | writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA); | |
406 | rcar_gen3_device_recognition(ch); | |
407 | ret = IRQ_HANDLED; | |
408 | } | |
409 | ||
410 | return ret; | |
411 | } | |
412 | ||
f3b5a8d9 | 413 | static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = { |
8dde0008 YS |
414 | { .compatible = "renesas,usb2-phy-r8a7795" }, |
415 | { .compatible = "renesas,usb2-phy-r8a7796" }, | |
416 | { .compatible = "renesas,usb2-phy-r8a77965" }, | |
417 | { .compatible = "renesas,rcar-gen3-usb2-phy" }, | |
f3b5a8d9 YS |
418 | { } |
419 | }; | |
420 | MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table); | |
421 | ||
2b38543c YS |
422 | static const unsigned int rcar_gen3_phy_cable[] = { |
423 | EXTCON_USB, | |
424 | EXTCON_USB_HOST, | |
425 | EXTCON_NONE, | |
426 | }; | |
427 | ||
f3b5a8d9 YS |
428 | static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) |
429 | { | |
430 | struct device *dev = &pdev->dev; | |
431 | struct rcar_gen3_chan *channel; | |
432 | struct phy_provider *provider; | |
433 | struct resource *res; | |
441a681b | 434 | int irq, ret = 0; |
f3b5a8d9 YS |
435 | |
436 | if (!dev->of_node) { | |
437 | dev_err(dev, "This driver needs device tree\n"); | |
438 | return -EINVAL; | |
439 | } | |
440 | ||
441 | channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL); | |
442 | if (!channel) | |
443 | return -ENOMEM; | |
444 | ||
b9564016 | 445 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
801a69c7 YS |
446 | channel->base = devm_ioremap_resource(dev, res); |
447 | if (IS_ERR(channel->base)) | |
448 | return PTR_ERR(channel->base); | |
f3b5a8d9 | 449 | |
b9564016 YS |
450 | /* call request_irq for OTG */ |
451 | irq = platform_get_irq(pdev, 0); | |
452 | if (irq >= 0) { | |
c14f8a40 | 453 | INIT_WORK(&channel->work, rcar_gen3_phy_usb2_work); |
b9564016 YS |
454 | irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq, |
455 | IRQF_SHARED, dev_name(dev), channel); | |
9f391c57 YS |
456 | if (irq < 0) |
457 | dev_err(dev, "No irq handler (%d)\n", irq); | |
7e0540f4 YS |
458 | } |
459 | ||
73801b90 YS |
460 | channel->dr_mode = of_usb_get_dr_mode_by_phy(dev->of_node, 0); |
461 | if (channel->dr_mode != USB_DR_MODE_UNKNOWN) { | |
7e0540f4 YS |
462 | int ret; |
463 | ||
979b519c | 464 | channel->is_otg_channel = true; |
8dde0008 YS |
465 | channel->uses_otg_pins = !of_property_read_bool(dev->of_node, |
466 | "renesas,no-otg-pins"); | |
2b38543c YS |
467 | channel->extcon = devm_extcon_dev_allocate(dev, |
468 | rcar_gen3_phy_cable); | |
469 | if (IS_ERR(channel->extcon)) | |
470 | return PTR_ERR(channel->extcon); | |
471 | ||
472 | ret = devm_extcon_dev_register(dev, channel->extcon); | |
473 | if (ret < 0) { | |
474 | dev_err(dev, "Failed to register extcon\n"); | |
475 | return ret; | |
476 | } | |
f3b5a8d9 YS |
477 | } |
478 | ||
441a681b YS |
479 | /* |
480 | * devm_phy_create() will call pm_runtime_enable(&phy->dev); | |
481 | * And then, phy-core will manage runtime pm for this device. | |
482 | */ | |
483 | pm_runtime_enable(dev); | |
f3b5a8d9 YS |
484 | channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops); |
485 | if (IS_ERR(channel->phy)) { | |
486 | dev_err(dev, "Failed to create USB2 PHY\n"); | |
441a681b YS |
487 | ret = PTR_ERR(channel->phy); |
488 | goto error; | |
f3b5a8d9 YS |
489 | } |
490 | ||
6dcfd7c3 YS |
491 | channel->vbus = devm_regulator_get_optional(dev, "vbus"); |
492 | if (IS_ERR(channel->vbus)) { | |
441a681b YS |
493 | if (PTR_ERR(channel->vbus) == -EPROBE_DEFER) { |
494 | ret = PTR_ERR(channel->vbus); | |
495 | goto error; | |
496 | } | |
6dcfd7c3 YS |
497 | channel->vbus = NULL; |
498 | } | |
499 | ||
9bb86777 | 500 | platform_set_drvdata(pdev, channel); |
f3b5a8d9 YS |
501 | phy_set_drvdata(channel->phy, channel); |
502 | ||
503 | provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); | |
9bb86777 | 504 | if (IS_ERR(provider)) { |
f3b5a8d9 | 505 | dev_err(dev, "Failed to register PHY provider\n"); |
441a681b YS |
506 | ret = PTR_ERR(provider); |
507 | goto error; | |
979b519c | 508 | } else if (channel->is_otg_channel) { |
9bb86777 YS |
509 | int ret; |
510 | ||
511 | ret = device_create_file(dev, &dev_attr_role); | |
512 | if (ret < 0) | |
441a681b | 513 | goto error; |
9bb86777 | 514 | } |
f3b5a8d9 | 515 | |
441a681b YS |
516 | return 0; |
517 | ||
518 | error: | |
519 | pm_runtime_disable(dev); | |
520 | ||
521 | return ret; | |
f3b5a8d9 YS |
522 | } |
523 | ||
9bb86777 YS |
524 | static int rcar_gen3_phy_usb2_remove(struct platform_device *pdev) |
525 | { | |
526 | struct rcar_gen3_chan *channel = platform_get_drvdata(pdev); | |
527 | ||
979b519c | 528 | if (channel->is_otg_channel) |
9bb86777 YS |
529 | device_remove_file(&pdev->dev, &dev_attr_role); |
530 | ||
441a681b YS |
531 | pm_runtime_disable(&pdev->dev); |
532 | ||
9bb86777 YS |
533 | return 0; |
534 | }; | |
535 | ||
f3b5a8d9 YS |
536 | static struct platform_driver rcar_gen3_phy_usb2_driver = { |
537 | .driver = { | |
538 | .name = "phy_rcar_gen3_usb2", | |
539 | .of_match_table = rcar_gen3_phy_usb2_match_table, | |
540 | }, | |
541 | .probe = rcar_gen3_phy_usb2_probe, | |
9bb86777 | 542 | .remove = rcar_gen3_phy_usb2_remove, |
f3b5a8d9 YS |
543 | }; |
544 | module_platform_driver(rcar_gen3_phy_usb2_driver); | |
545 | ||
546 | MODULE_LICENSE("GPL v2"); | |
547 | MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY"); | |
548 | MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>"); |