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dt-bindings: phy-qcom-qmp: Add SDM845 PCIe to binding
[linux-block.git] / drivers / phy / qualcomm / phy-qcom-qmp.c
CommitLineData
3405bd71 1// SPDX-License-Identifier: GPL-2.0
e78f3d15
VG		 2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
e78f3d15
VG		 4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#include <dt-bindings/phy/phy.h>
24
e2248617 25#include "phy-qcom-qmp.h"
e78f3d15
VG		 26
27/* QPHY_SW_RESET bit */
28#define SW_RESET BIT(0)
29/* QPHY_POWER_DOWN_CONTROL */
30#define SW_PWRDN BIT(0)
31#define REFCLK_DRV_DSBL BIT(1)
32/* QPHY_START_CONTROL bits */
33#define SERDES_START BIT(0)
34#define PCS_START BIT(1)
35#define PLL_READY_GATE_EN BIT(3)
36/* QPHY_PCS_STATUS bit */
37#define PHYSTATUS BIT(6)
14ced7e3 38/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
e78f3d15
VG		 39#define PCS_READY BIT(0)
40
efb05a50
MG		 41/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
42/* DP PHY soft reset */
43#define SW_DPPHY_RESET BIT(0)
44/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
45#define SW_DPPHY_RESET_MUX BIT(1)
46/* USB3 PHY soft reset */
47#define SW_USB3PHY_RESET BIT(2)
48/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
49#define SW_USB3PHY_RESET_MUX BIT(3)
50
51/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
52#define USB3_MODE BIT(0) /* enables USB3 mode */
53#define DP_MODE BIT(1) /* enables DP mode */
54
ac0d2399
MG		 55/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
56#define ARCVR_DTCT_EN BIT(0)
57#define ALFPS_DTCT_EN BIT(1)
58#define ARCVR_DTCT_EVENT_SEL BIT(4)
59
60/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
61#define IRQ_CLEAR BIT(0)
62
63/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
64#define RCVR_DETECT BIT(0)
65
66/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
67#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
efb05a50 68
cd217ee6 69#define PHY_INIT_COMPLETE_TIMEOUT 10000
e78f3d15
VG		 70#define POWER_DOWN_DELAY_US_MIN 10
71#define POWER_DOWN_DELAY_US_MAX 11
72
73#define MAX_PROP_NAME 32
74
5e17b95d
EG		 75/* Define the assumed distance between lanes for underspecified device trees. */
76#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
77
e78f3d15
VG		 78struct qmp_phy_init_tbl {
79 unsigned int offset;
80 unsigned int val;
81 /*
82 * register part of layout ?
83 * if yes, then offset gives index in the reg-layout
84 */
85 int in_layout;
86};
87
88#define QMP_PHY_INIT_CFG(o, v) \
89 { \
90 .offset = o, \
91 .val = v, \
92 }
93
94#define QMP_PHY_INIT_CFG_L(o, v) \
95 { \
96 .offset = o, \
97 .val = v, \
98 .in_layout = 1, \
99 }
100
101/* set of registers with offsets different per-PHY */
102enum qphy_reg_layout {
103 /* Common block control registers */
104 QPHY_COM_SW_RESET,
105 QPHY_COM_POWER_DOWN_CONTROL,
106 QPHY_COM_START_CONTROL,
107 QPHY_COM_PCS_READY_STATUS,
108 /* PCS registers */
109 QPHY_PLL_LOCK_CHK_DLY_TIME,
110 QPHY_FLL_CNTRL1,
111 QPHY_FLL_CNTRL2,
112 QPHY_FLL_CNT_VAL_L,
113 QPHY_FLL_CNT_VAL_H_TOL,
114 QPHY_FLL_MAN_CODE,
115 QPHY_SW_RESET,
116 QPHY_START_CTRL,
117 QPHY_PCS_READY_STATUS,
14ced7e3 118 QPHY_PCS_STATUS,
ac0d2399
MG		 119 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
120 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
121 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
e78f3d15
VG		 122};
123
124static const unsigned int pciephy_regs_layout[] = {
125 [QPHY_COM_SW_RESET] = 0x400,
126 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
127 [QPHY_COM_START_CONTROL] = 0x408,
128 [QPHY_COM_PCS_READY_STATUS] = 0x448,
129 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
130 [QPHY_FLL_CNTRL1] = 0xc4,
131 [QPHY_FLL_CNTRL2] = 0xc8,
132 [QPHY_FLL_CNT_VAL_L] = 0xcc,
133 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
134 [QPHY_FLL_MAN_CODE] = 0xd4,
135 [QPHY_SW_RESET] = 0x00,
136 [QPHY_START_CTRL] = 0x08,
14ced7e3 137 [QPHY_PCS_STATUS] = 0x174,
e78f3d15
VG		 138};
139
140static const unsigned int usb3phy_regs_layout[] = {
141 [QPHY_FLL_CNTRL1] = 0xc0,
142 [QPHY_FLL_CNTRL2] = 0xc4,
143 [QPHY_FLL_CNT_VAL_L] = 0xc8,
144 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
145 [QPHY_FLL_MAN_CODE] = 0xd0,
146 [QPHY_SW_RESET] = 0x00,
147 [QPHY_START_CTRL] = 0x08,
14ced7e3 148 [QPHY_PCS_STATUS] = 0x17c,
ac0d2399
MG		 149 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
150 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
151 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
e78f3d15
VG		 152};
153
efb05a50
MG		 154static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
155 [QPHY_SW_RESET] = 0x00,
156 [QPHY_START_CTRL] = 0x08,
14ced7e3 157 [QPHY_PCS_STATUS] = 0x174,
ac0d2399
MG		 158 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
159 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
160 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
efb05a50
MG		 161};
162
cc31cdbe
CG		 163static const unsigned int sdm845_ufsphy_regs_layout[] = {
164 [QPHY_START_CTRL] = 0x00,
165 [QPHY_PCS_READY_STATUS] = 0x160,
166};
167
a88c85ee 168static const unsigned int sm8150_ufsphy_regs_layout[] = {
730430dc
VK		 169 [QPHY_START_CTRL] = QPHY_V4_PHY_START,
170 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_READY_STATUS,
d0312fdb 171 [QPHY_SW_RESET] = QPHY_V4_SW_RESET,
a88c85ee
VK		 172};
173
e78f3d15
VG		 174static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
175 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
176 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
177 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
178 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
179 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
180 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
181 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
182 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
183 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
184 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
185 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
186 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
187 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
188 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
189 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
190 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
191 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
192 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
193 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
194 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
195 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
196 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
197 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
198 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
199 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
200 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
201 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
202 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
203 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
204 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
205 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
206 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
207 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
208 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
209 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
210 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
211 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
212 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
213 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
214 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
215 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
216 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
217 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
218};
219
220static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
221 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
222 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
223};
224
225static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
226 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
227 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
228 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
229 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
230 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
231 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
232 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
233 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
234 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
235 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
236};
237
238static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
239 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
240 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
241 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
242
243 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
244
245 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
246 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
247 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
248 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
249 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
250};
251
73d7ec89
MG		 252static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
259 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
260 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
261 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
262 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
263 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
264 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
265 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
266 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
289 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
290 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
291 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
295};
296
297static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
298 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
299 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
300 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
301 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
302};
303
304static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
305 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
306 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
307 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
308 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
309 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
310 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
311 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
312 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
313 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
314 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
315 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
316 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
317 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
318 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
319};
320
321static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
325 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
326 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
327 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
332};
333
e78f3d15
VG		 334static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
335 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
336 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
337 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
338 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
339 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
340 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
341 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
342 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
343 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
344 /* PLL and Loop filter settings */
345 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
346 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
347 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
348 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
349 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
350 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
351 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
352 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
353 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
354 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
355 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
356 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
357 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
358 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
359 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
360 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
361 /* SSC settings */
362 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
363 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
364 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
365 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
366 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
367 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
368 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
369};
370
371static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
372 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
373 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
374 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
375};
376
377static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
378 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
379 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
380 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
381 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
382 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
383 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
384 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
385 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
386 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
387 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
388};
389
390static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
391 /* FLL settings */
392 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
393 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
394 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
395 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
396 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
397
398 /* Lock Det settings */
399 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
400 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
401 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
402 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
403};
404
eef243d0
VN		 405static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
406 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
407 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
408 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
409 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
410 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
411 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
412 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
413 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
414 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
415 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
416 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
417 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
418 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
419 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
420 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
421 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
422 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
423 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
424 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
425 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
426 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
427 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
428 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
429 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
430 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
431 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
432 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
433 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
434 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
435 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
436 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
437 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
438 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
439 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
440 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
441 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
442 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
443 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
444 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
445 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
446 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
447 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
448};
449
450static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
451 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
452 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
453 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
454 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
455};
456
457static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
458 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
459 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
460 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
461 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
462 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
463 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
464 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
465 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
466};
467
468static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
469 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
470 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
471 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
472 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
473 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
474 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
475 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
476 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
477 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
478 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
479 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
480 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
481 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
482};
483
efb05a50
MG		 484static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
485 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
486 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
487 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
488 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
489 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
490 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
491 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
492 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
493 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
494 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
495 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
496 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
497 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
498 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
499 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
500 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
501 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
502 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
503 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
521};
522
523static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
524 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
525 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
526 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
527 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
528 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
529};
530
531static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
532 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
533 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
534 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
535 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
536 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
537 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
538 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
539 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
540 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
541};
542
543static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
544 /* FLL settings */
545 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
546 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
547 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
548 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
549 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
550
551 /* Lock Det settings */
552 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
553 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
554 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
555 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
556
557 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
558 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
559 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
560 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
561 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
562 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
563 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
564 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
565 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
566 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
567 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
568 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
569 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
570 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
571 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
572 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
573 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
576
577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
588};
589
f6721e5c
MG		 590static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
591 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
592 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
593 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
594 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
595 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
596 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
597 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
598 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
599 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
600 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
601 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
602 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
603 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
604 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
605 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
606 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
607 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
608 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
609 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
610 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
611 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
612 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
613 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
614 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
615 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
616 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
617 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
618 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
619 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
620 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
621 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
622 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
623 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
624 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
625 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
626 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
627};
628
629static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
630 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
631 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
632 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
633 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
634 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
635};
636
637static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
638 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
639 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
640 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
641 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
642 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
643 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
644 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
645 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
646 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
647 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
648 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
649};
650
651static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
652 /* FLL settings */
653 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
654 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
655 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
656 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
657 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
658
659 /* Lock Det settings */
660 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
661 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
662 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
663 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
664
665 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
666 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
667 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
668 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
669 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
670 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
671 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
672 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
673 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
674 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
675 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
676 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
677 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
678 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
679 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
680 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
681 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
682 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
683 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
684
685 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
686 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
687 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
688 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
689 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
690 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
691 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
692 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
693 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
694 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
695 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
696
697 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
698 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
699};
700
cc31cdbe
CG		 701static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
702 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
703 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
704 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
705 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
706 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
707 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
708 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
709 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
710 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
711 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
712 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
713 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
714 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
715 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
716 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
717 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
718 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
719 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
720 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
721 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
722 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
723 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
724 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
725 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
726 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
727 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
728 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
729 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
730 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
731 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
732 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
733 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
734 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
735 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
736 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
737 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
738
739 /* Rate B */
740 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
741};
742
743static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
744 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
745 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
746 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
747};
748
749static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
750 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
751 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
752 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
753 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
754 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
755 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
756 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
757 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
758 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
759 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
760 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
761 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
762 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
763 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
764 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
765 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
766};
767
768static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
769 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
770 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
771 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
772 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
773 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
774 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
775 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
776 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
777};
f6721e5c 778
a51969fa
JH		 779static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
780 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
781 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
782 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
783 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
784 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
785 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
786 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
787 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
788 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
789 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
790 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
791 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
792 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
793 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
794 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
795 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
796 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
797 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
798 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
799 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
800 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
801 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
802 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
803 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
804 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
805 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
806 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
807 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
808 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
809 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
810 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
811 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
812 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
813 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
814 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
815 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
816 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
817 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
818};
819
820static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
821 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
822 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
823 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
824 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
825};
826
827static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
828 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
829 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
830 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
831 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
832 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
833 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
834 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
835 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
836 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
837 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
838 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
839 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
840 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
841 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
842 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
843 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
844 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
845};
846
847static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
848 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
849 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
850 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
851 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
852 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
853 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
854 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
855 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
856 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
857 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
858 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
859 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
860 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
861 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
862 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
863 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
864 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
865 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
866 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
867 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
868 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
869 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
870 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
871 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
872 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
873 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
874 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
875 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
876 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
877 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
878 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
879 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
880 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
881 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
882 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
883 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
884 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
885 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
886};
887
a88c85ee 888static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
a88c85ee
VK		 889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
893 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
894 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
895 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
896 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
898 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
899 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
900 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
901 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
902 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
903 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
904 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
905 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
906 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
907 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
908 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
909 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
910 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
911 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
912 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
913
914 /* Rate B */
915 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
916};
917
918static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
919 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
920 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
921 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
922 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
923 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
924 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
925};
926
927static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
943 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
944 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
948 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
949 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
950 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
951 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
952 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
953 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
954 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
955 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
956 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
957 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
958 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
959 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
960 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
961 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
962
963};
964
965static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
966 QMP_PHY_INIT_CFG(QPHY_V4_RX_SIGDET_CTRL2, 0x6d),
967 QMP_PHY_INIT_CFG(QPHY_V4_TX_LARGE_AMP_DRV_LVL, 0x0a),
968 QMP_PHY_INIT_CFG(QPHY_V4_TX_SMALL_AMP_DRV_LVL, 0x02),
969 QMP_PHY_INIT_CFG(QPHY_V4_TX_MID_TERM_CTRL1, 0x43),
970 QMP_PHY_INIT_CFG(QPHY_V4_DEBUG_BUS_CLKSEL, 0x1f),
971 QMP_PHY_INIT_CFG(QPHY_V4_RX_MIN_HIBERN8_TIME, 0xff),
972 QMP_PHY_INIT_CFG(QPHY_V4_MULTI_LANE_CTRL1, 0x02),
973};
a51969fa 974
e78f3d15
VG		 975/* struct qmp_phy_cfg - per-PHY initialization config */
976struct qmp_phy_cfg {
977 /* phy-type - PCIE/UFS/USB */
978 unsigned int type;
979 /* number of lanes provided by phy */
980 int nlanes;
981
982 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
983 const struct qmp_phy_init_tbl *serdes_tbl;
984 int serdes_tbl_num;
985 const struct qmp_phy_init_tbl *tx_tbl;
986 int tx_tbl_num;
987 const struct qmp_phy_init_tbl *rx_tbl;
988 int rx_tbl_num;
989 const struct qmp_phy_init_tbl *pcs_tbl;
990 int pcs_tbl_num;
991
992 /* clock ids to be requested */
993 const char * const *clk_list;
994 int num_clks;
995 /* resets to be requested */
996 const char * const *reset_list;
997 int num_resets;
998 /* regulators to be requested */
999 const char * const *vreg_list;
1000 int num_vregs;
1001
1002 /* array of registers with different offsets */
1003 const unsigned int *regs;
1004
1005 unsigned int start_ctrl;
1006 unsigned int pwrdn_ctrl;
e78f3d15
VG		 1007 unsigned int mask_com_pcs_ready;
1008
1009 /* true, if PHY has a separate PHY_COM control block */
1010 bool has_phy_com_ctrl;
1011 /* true, if PHY has a reset for individual lanes */
1012 bool has_lane_rst;
1013 /* true, if PHY needs delay after POWER_DOWN */
1014 bool has_pwrdn_delay;
1015 /* power_down delay in usec */
1016 int pwrdn_delay_min;
1017 int pwrdn_delay_max;
efb05a50
MG		 1018
1019 /* true, if PHY has a separate DP_COM control block */
1020 bool has_phy_dp_com_ctrl;
6b045268
CG		 1021 /* true, if PHY has secondary tx/rx lanes to be configured */
1022 bool is_dual_lane_phy;
cc31cdbe
CG		 1023
1024 /* true, if PCS block has no separate SW_RESET register */
1025 bool no_pcs_sw_reset;
e78f3d15
VG		 1026};
1027
1028/**
1029 * struct qmp_phy - per-lane phy descriptor
1030 *
1031 * @phy: generic phy
1032 * @tx: iomapped memory space for lane's tx
1033 * @rx: iomapped memory space for lane's rx
1034 * @pcs: iomapped memory space for lane's pcs
5e17b95d
EG		 1035 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
1036 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
ac0d2399 1037 * @pcs_misc: iomapped memory space for lane's pcs_misc
e78f3d15
VG		 1038 * @pipe_clk: pipe lock
1039 * @index: lane index
1040 * @qmp: QMP phy to which this lane belongs
1041 * @lane_rst: lane's reset controller
1042 */
1043struct qmp_phy {
1044 struct phy *phy;
1045 void __iomem *tx;
1046 void __iomem *rx;
1047 void __iomem *pcs;
5e17b95d
EG		 1048 void __iomem *tx2;
1049 void __iomem *rx2;
ac0d2399 1050 void __iomem *pcs_misc;
e78f3d15
VG		 1051 struct clk *pipe_clk;
1052 unsigned int index;
1053 struct qcom_qmp *qmp;
1054 struct reset_control *lane_rst;
1055};
1056
1057/**
1058 * struct qcom_qmp - structure holding QMP phy block attributes
1059 *
1060 * @dev: device
1061 * @serdes: iomapped memory space for phy's serdes
efb05a50 1062 * @dp_com: iomapped memory space for phy's dp_com control block
e78f3d15
VG		 1063 *
1064 * @clks: array of clocks required by phy
1065 * @resets: array of resets required by phy
1066 * @vregs: regulator supplies bulk data
1067 *
1068 * @cfg: phy specific configuration
1069 * @phys: array of per-lane phy descriptors
1070 * @phy_mutex: mutex lock for PHY common block initialization
1071 * @init_count: phy common block initialization count
ac0d2399
MG		 1072 * @phy_initialized: indicate if PHY has been initialized
1073 * @mode: current PHY mode
c9b58979 1074 * @ufs_reset: optional UFS PHY reset handle
e78f3d15
VG		 1075 */
1076struct qcom_qmp {
1077 struct device *dev;
1078 void __iomem *serdes;
efb05a50 1079 void __iomem *dp_com;
e78f3d15 1080
10939b10 1081 struct clk_bulk_data *clks;
e78f3d15
VG		 1082 struct reset_control **resets;
1083 struct regulator_bulk_data *vregs;
1084
1085 const struct qmp_phy_cfg *cfg;
1086 struct qmp_phy **phys;
1087
1088 struct mutex phy_mutex;
1089 int init_count;
ac0d2399
MG		 1090 bool phy_initialized;
1091 enum phy_mode mode;
c9b58979
EG		 1092
1093 struct reset_control *ufs_reset;
e78f3d15
VG		 1094};
1095
1096static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1097{
1098 u32 reg;
1099
1100 reg = readl(base + offset);
1101 reg |= val;
1102 writel(reg, base + offset);
1103
1104 /* ensure that above write is through */
1105 readl(base + offset);
1106}
1107
1108static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1109{
1110 u32 reg;
1111
1112 reg = readl(base + offset);
1113 reg &= ~val;
1114 writel(reg, base + offset);
1115
1116 /* ensure that above write is through */
1117 readl(base + offset);
1118}
1119
1120/* list of clocks required by phy */
1121static const char * const msm8996_phy_clk_l[] = {
1122 "aux", "cfg_ahb", "ref",
1123};
1124
efb05a50
MG		 1125static const char * const qmp_v3_phy_clk_l[] = {
1126 "aux", "cfg_ahb", "ref", "com_aux",
1127};
1128
cc31cdbe
CG		 1129static const char * const sdm845_ufs_phy_clk_l[] = {
1130 "ref", "ref_aux",
1131};
1132
e78f3d15
VG		 1133/* list of resets */
1134static const char * const msm8996_pciephy_reset_l[] = {
1135 "phy", "common", "cfg",
1136};
1137
1138static const char * const msm8996_usb3phy_reset_l[] = {
1139 "phy", "common",
1140};
1141
1142/* list of regulators */
6b045268 1143static const char * const qmp_phy_vreg_l[] = {
e78f3d15
VG		 1144 "vdda-phy", "vdda-pll",
1145};
1146
1147static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
1148 .type = PHY_TYPE_PCIE,
1149 .nlanes = 3,
1150
1151 .serdes_tbl = msm8996_pcie_serdes_tbl,
1152 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
1153 .tx_tbl = msm8996_pcie_tx_tbl,
1154 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
1155 .rx_tbl = msm8996_pcie_rx_tbl,
1156 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
1157 .pcs_tbl = msm8996_pcie_pcs_tbl,
1158 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
1159 .clk_list = msm8996_phy_clk_l,
1160 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1161 .reset_list = msm8996_pciephy_reset_l,
1162 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
6b045268
CG		 1163 .vreg_list = qmp_phy_vreg_l,
1164 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
e78f3d15
VG		 1165 .regs = pciephy_regs_layout,
1166
1167 .start_ctrl = PCS_START | PLL_READY_GATE_EN,
1168 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1169 .mask_com_pcs_ready = PCS_READY,
1170
1171 .has_phy_com_ctrl = true,
1172 .has_lane_rst = true,
1173 .has_pwrdn_delay = true,
1174 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1175 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1176};
1177
1178static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1179 .type = PHY_TYPE_USB3,
1180 .nlanes = 1,
1181
1182 .serdes_tbl = msm8996_usb3_serdes_tbl,
1183 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1184 .tx_tbl = msm8996_usb3_tx_tbl,
1185 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1186 .rx_tbl = msm8996_usb3_rx_tbl,
1187 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1188 .pcs_tbl = msm8996_usb3_pcs_tbl,
1189 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1190 .clk_list = msm8996_phy_clk_l,
1191 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1192 .reset_list = msm8996_usb3phy_reset_l,
1193 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
6b045268
CG		 1194 .vreg_list = qmp_phy_vreg_l,
1195 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
e78f3d15
VG		 1196 .regs = usb3phy_regs_layout,
1197
1198 .start_ctrl = SERDES_START | PCS_START,
1199 .pwrdn_ctrl = SW_PWRDN,
e78f3d15
VG		 1200};
1201
eef243d0
VN		 1202/* list of resets */
1203static const char * const ipq8074_pciephy_reset_l[] = {
1204 "phy", "common",
1205};
1206
1207static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
1208 .type = PHY_TYPE_PCIE,
1209 .nlanes = 1,
1210
1211 .serdes_tbl = ipq8074_pcie_serdes_tbl,
1212 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
1213 .tx_tbl = ipq8074_pcie_tx_tbl,
1214 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
1215 .rx_tbl = ipq8074_pcie_rx_tbl,
1216 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
1217 .pcs_tbl = ipq8074_pcie_pcs_tbl,
1218 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
1219 .clk_list = NULL,
1220 .num_clks = 0,
1221 .reset_list = ipq8074_pciephy_reset_l,
1222 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1223 .vreg_list = NULL,
1224 .num_vregs = 0,
1225 .regs = pciephy_regs_layout,
1226
1227 .start_ctrl = SERDES_START | PCS_START,
1228 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
eef243d0
VN		 1229
1230 .has_phy_com_ctrl = false,
1231 .has_lane_rst = false,
1232 .has_pwrdn_delay = true,
1233 .pwrdn_delay_min = 995, /* us */
1234 .pwrdn_delay_max = 1005, /* us */
1235};
1236
efb05a50
MG		 1237static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
1238 .type = PHY_TYPE_USB3,
1239 .nlanes = 1,
1240
1241 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1242 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1243 .tx_tbl = qmp_v3_usb3_tx_tbl,
1244 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1245 .rx_tbl = qmp_v3_usb3_rx_tbl,
1246 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1247 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1248 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1249 .clk_list = qmp_v3_phy_clk_l,
1250 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1251 .reset_list = msm8996_usb3phy_reset_l,
1252 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
6b045268
CG		 1253 .vreg_list = qmp_phy_vreg_l,
1254 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
efb05a50
MG		 1255 .regs = qmp_v3_usb3phy_regs_layout,
1256
1257 .start_ctrl = SERDES_START | PCS_START,
1258 .pwrdn_ctrl = SW_PWRDN,
efb05a50 1259
f6721e5c 1260 .has_pwrdn_delay = true,
efb05a50
MG		 1261 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1262 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1263
1264 .has_phy_dp_com_ctrl = true,
6b045268 1265 .is_dual_lane_phy = true,
efb05a50
MG		 1266};
1267
f6721e5c
MG		 1268static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1269 .type = PHY_TYPE_USB3,
1270 .nlanes = 1,
1271
1272 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
1273 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1274 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
1275 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1276 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
1277 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1278 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
1279 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1280 .clk_list = qmp_v3_phy_clk_l,
1281 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1282 .reset_list = msm8996_usb3phy_reset_l,
1283 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
6b045268
CG		 1284 .vreg_list = qmp_phy_vreg_l,
1285 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
f6721e5c
MG		 1286 .regs = qmp_v3_usb3phy_regs_layout,
1287
1288 .start_ctrl = SERDES_START | PCS_START,
1289 .pwrdn_ctrl = SW_PWRDN,
f6721e5c
MG		 1290
1291 .has_pwrdn_delay = true,
1292 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1293 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1294};
1295
cc31cdbe
CG		 1296static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1297 .type = PHY_TYPE_UFS,
1298 .nlanes = 2,
1299
1300 .serdes_tbl = sdm845_ufsphy_serdes_tbl,
1301 .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
1302 .tx_tbl = sdm845_ufsphy_tx_tbl,
1303 .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
1304 .rx_tbl = sdm845_ufsphy_rx_tbl,
1305 .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
1306 .pcs_tbl = sdm845_ufsphy_pcs_tbl,
1307 .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
1308 .clk_list = sdm845_ufs_phy_clk_l,
1309 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1310 .vreg_list = qmp_phy_vreg_l,
1311 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1312 .regs = sdm845_ufsphy_regs_layout,
1313
1314 .start_ctrl = SERDES_START,
1315 .pwrdn_ctrl = SW_PWRDN,
cc31cdbe
CG		 1316
1317 .is_dual_lane_phy = true,
cc31cdbe
CG		 1318 .no_pcs_sw_reset = true,
1319};
1320
73d7ec89
MG		 1321static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
1322 .type = PHY_TYPE_PCIE,
1323 .nlanes = 1,
1324
1325 .serdes_tbl = msm8998_pcie_serdes_tbl,
1326 .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
1327 .tx_tbl = msm8998_pcie_tx_tbl,
1328 .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
1329 .rx_tbl = msm8998_pcie_rx_tbl,
1330 .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
1331 .pcs_tbl = msm8998_pcie_pcs_tbl,
1332 .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
1333 .clk_list = msm8996_phy_clk_l,
1334 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1335 .reset_list = ipq8074_pciephy_reset_l,
1336 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1337 .vreg_list = qmp_phy_vreg_l,
1338 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1339 .regs = pciephy_regs_layout,
1340
1341 .start_ctrl = SERDES_START | PCS_START,
1342 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
73d7ec89
MG		 1343};
1344
a51969fa
JH		 1345static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1346 .type = PHY_TYPE_USB3,
1347 .nlanes = 1,
1348
1349 .serdes_tbl = msm8998_usb3_serdes_tbl,
1350 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1351 .tx_tbl = msm8998_usb3_tx_tbl,
1352 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1353 .rx_tbl = msm8998_usb3_rx_tbl,
1354 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1355 .pcs_tbl = msm8998_usb3_pcs_tbl,
1356 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1357 .clk_list = msm8996_phy_clk_l,
1358 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1359 .reset_list = msm8996_usb3phy_reset_l,
1360 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1361 .vreg_list = qmp_phy_vreg_l,
1362 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1363 .regs = qmp_v3_usb3phy_regs_layout,
1364
1365 .start_ctrl = SERDES_START | PCS_START,
1366 .pwrdn_ctrl = SW_PWRDN,
a51969fa
JH		 1367
1368 .is_dual_lane_phy = true,
1369};
1370
a88c85ee
VK		 1371static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
1372 .type = PHY_TYPE_UFS,
1373 .nlanes = 2,
1374
1375 .serdes_tbl = sm8150_ufsphy_serdes_tbl,
1376 .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
1377 .tx_tbl = sm8150_ufsphy_tx_tbl,
1378 .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
1379 .rx_tbl = sm8150_ufsphy_rx_tbl,
1380 .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
1381 .pcs_tbl = sm8150_ufsphy_pcs_tbl,
1382 .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
1383 .clk_list = sdm845_ufs_phy_clk_l,
1384 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1385 .vreg_list = qmp_phy_vreg_l,
1386 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1387 .regs = sm8150_ufsphy_regs_layout,
1388
1389 .start_ctrl = SERDES_START,
1390 .pwrdn_ctrl = SW_PWRDN,
1391
1392 .is_dual_lane_phy = true,
a88c85ee
VK		 1393};
1394
e78f3d15
VG		 1395static void qcom_qmp_phy_configure(void __iomem *base,
1396 const unsigned int *regs,
1397 const struct qmp_phy_init_tbl tbl[],
1398 int num)
1399{
1400 int i;
1401 const struct qmp_phy_init_tbl *t = tbl;
1402
1403 if (!t)
1404 return;
1405
1406 for (i = 0; i < num; i++, t++) {
1407 if (t->in_layout)
1408 writel(t->val, base + regs[t->offset]);
1409 else
1410 writel(t->val, base + t->offset);
1411 }
1412}
1413
0d58280c 1414static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
e78f3d15 1415{
0d58280c 1416 struct qcom_qmp *qmp = qphy->qmp;
e78f3d15
VG		 1417 const struct qmp_phy_cfg *cfg = qmp->cfg;
1418 void __iomem *serdes = qmp->serdes;
0d58280c 1419 void __iomem *pcs = qphy->pcs;
efb05a50 1420 void __iomem *dp_com = qmp->dp_com;
e78f3d15
VG		 1421 int ret, i;
1422
1423 mutex_lock(&qmp->phy_mutex);
1424 if (qmp->init_count++) {
1425 mutex_unlock(&qmp->phy_mutex);
1426 return 0;
1427 }
1428
717dab9d
MG		 1429 /* turn on regulator supplies */
1430 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1431 if (ret) {
1432 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1433 goto err_reg_enable;
1434 }
1435
c6549f0e
MG		 1436 for (i = 0; i < cfg->num_resets; i++) {
1437 ret = reset_control_assert(qmp->resets[i]);
1438 if (ret) {
1439 dev_err(qmp->dev, "%s reset assert failed\n",
1440 cfg->reset_list[i]);
1441 goto err_rst_assert;
1442 }
717dab9d
MG		 1443 }
1444
c6549f0e 1445 for (i = cfg->num_resets - 1; i >= 0; i--) {
e78f3d15
VG		 1446 ret = reset_control_deassert(qmp->resets[i]);
1447 if (ret) {
1448 dev_err(qmp->dev, "%s reset deassert failed\n",
1449 qmp->cfg->reset_list[i]);
e78f3d15
VG		 1450 goto err_rst;
1451 }
1452 }
1453
c6549f0e
MG		 1454 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1455 if (ret) {
1456 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1457 goto err_rst;
1458 }
1459
efb05a50
MG		 1460 if (cfg->has_phy_dp_com_ctrl) {
1461 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
1462 SW_PWRDN);
1463 /* override hardware control for reset of qmp phy */
1464 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1465 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1466 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1467
1468 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
1469 USB3_MODE | DP_MODE);
1470
1471 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
1472 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1473 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1474 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1475 }
1476
0d58280c
CG		 1477 if (cfg->has_phy_com_ctrl)
1478 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1479 SW_PWRDN);
1480 else
1481 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1482
e78f3d15
VG		 1483 /* Serdes configuration */
1484 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
1485 cfg->serdes_tbl_num);
1486
1487 if (cfg->has_phy_com_ctrl) {
1488 void __iomem *status;
1489 unsigned int mask, val;
1490
1491 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
1492 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1493 SERDES_START | PCS_START);
1494
1495 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
1496 mask = cfg->mask_com_pcs_ready;
1497
1498 ret = readl_poll_timeout(status, val, (val & mask), 10,
1499 PHY_INIT_COMPLETE_TIMEOUT);
1500 if (ret) {
1501 dev_err(qmp->dev,
1502 "phy common block init timed-out\n");
c6549f0e 1503 goto err_com_init;
e78f3d15
VG		 1504 }
1505 }
1506
1507 mutex_unlock(&qmp->phy_mutex);
1508
1509 return 0;
1510
c6549f0e
MG		 1511err_com_init:
1512 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
8387c576 1513err_rst:
c6549f0e 1514 while (++i < cfg->num_resets)
e78f3d15 1515 reset_control_assert(qmp->resets[i]);
c6549f0e 1516err_rst_assert:
717dab9d
MG		 1517 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1518err_reg_enable:
e78f3d15 1519 mutex_unlock(&qmp->phy_mutex);
8387c576 1520
e78f3d15
VG		 1521 return ret;
1522}
1523
1524static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
1525{
1526 const struct qmp_phy_cfg *cfg = qmp->cfg;
1527 void __iomem *serdes = qmp->serdes;
1528 int i = cfg->num_resets;
1529
1530 mutex_lock(&qmp->phy_mutex);
1531 if (--qmp->init_count) {
1532 mutex_unlock(&qmp->phy_mutex);
1533 return 0;
1534 }
1535
c9b58979 1536 reset_control_assert(qmp->ufs_reset);
e78f3d15
VG		 1537 if (cfg->has_phy_com_ctrl) {
1538 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1539 SERDES_START | PCS_START);
1540 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
1541 SW_RESET);
1542 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1543 SW_PWRDN);
1544 }
1545
1546 while (--i >= 0)
1547 reset_control_assert(qmp->resets[i]);
1548
717dab9d
MG		 1549 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1550
1551 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1552
e78f3d15
VG		 1553 mutex_unlock(&qmp->phy_mutex);
1554
1555 return 0;
1556}
1557
3f6d1767 1558static int qcom_qmp_phy_enable(struct phy *phy)
e78f3d15
VG		 1559{
1560 struct qmp_phy *qphy = phy_get_drvdata(phy);
1561 struct qcom_qmp *qmp = qphy->qmp;
1562 const struct qmp_phy_cfg *cfg = qmp->cfg;
1563 void __iomem *tx = qphy->tx;
1564 void __iomem *rx = qphy->rx;
1565 void __iomem *pcs = qphy->pcs;
efb05a50 1566 void __iomem *dp_com = qmp->dp_com;
e78f3d15 1567 void __iomem *status;
14ced7e3 1568 unsigned int mask, val, ready;
10939b10 1569 int ret;
e78f3d15
VG		 1570
1571 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1572
c9b58979
EG		 1573 if (cfg->no_pcs_sw_reset) {
1574 /*
1575 * Get UFS reset, which is delayed until now to avoid a
1576 * circular dependency where UFS needs its PHY, but the PHY
1577 * needs this UFS reset.
1578 */
1579 if (!qmp->ufs_reset) {
1580 qmp->ufs_reset =
1581 devm_reset_control_get_exclusive(qmp->dev,
1582 "ufsphy");
1583
1584 if (IS_ERR(qmp->ufs_reset)) {
1585 ret = PTR_ERR(qmp->ufs_reset);
1586 dev_err(qmp->dev,
1587 "failed to get UFS reset: %d\n",
1588 ret);
1589
1590 qmp->ufs_reset = NULL;
1591 return ret;
1592 }
1593 }
1594
1595 ret = reset_control_assert(qmp->ufs_reset);
1596 if (ret)
1597 goto err_lane_rst;
1598 }
1599
0d58280c 1600 ret = qcom_qmp_phy_com_init(qphy);
e78f3d15 1601 if (ret)
717dab9d 1602 return ret;
e78f3d15
VG		 1603
1604 if (cfg->has_lane_rst) {
1605 ret = reset_control_deassert(qphy->lane_rst);
1606 if (ret) {
1607 dev_err(qmp->dev, "lane%d reset deassert failed\n",
1608 qphy->index);
1609 goto err_lane_rst;
1610 }
1611 }
1612
fdf37e1a
MG		 1613 ret = clk_prepare_enable(qphy->pipe_clk);
1614 if (ret) {
1615 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1616 goto err_clk_enable;
1617 }
1618
e78f3d15
VG		 1619 /* Tx, Rx, and PCS configurations */
1620 qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
efb05a50 1621 /* Configuration for other LANE for USB-DP combo PHY */
6b045268 1622 if (cfg->is_dual_lane_phy)
5e17b95d 1623 qcom_qmp_phy_configure(qphy->tx2, cfg->regs,
efb05a50
MG		 1624 cfg->tx_tbl, cfg->tx_tbl_num);
1625
e78f3d15 1626 qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
6b045268 1627 if (cfg->is_dual_lane_phy)
5e17b95d 1628 qcom_qmp_phy_configure(qphy->rx2, cfg->regs,
efb05a50
MG		 1629 cfg->rx_tbl, cfg->rx_tbl_num);
1630
e78f3d15 1631 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
c9b58979
EG		 1632 ret = reset_control_deassert(qmp->ufs_reset);
1633 if (ret)
1634 goto err_lane_rst;
e78f3d15
VG		 1635
1636 /*
1637 * Pull out PHY from POWER DOWN state.
1638 * This is active low enable signal to power-down PHY.
1639 */
0d58280c
CG		 1640 if(cfg->type == PHY_TYPE_PCIE)
1641 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
e78f3d15
VG		 1642
1643 if (cfg->has_pwrdn_delay)
1644 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
1645
e78f3d15 1646 /* Pull PHY out of reset state */
3f6d1767
EG		 1647 if (!cfg->no_pcs_sw_reset)
1648 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1649
efb05a50
MG		 1650 if (cfg->has_phy_dp_com_ctrl)
1651 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
e78f3d15 1652
76ddd300
MG		 1653 /* start SerDes and Phy-Coding-Sublayer */
1654 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1655
14ced7e3
BA		 1656 if (cfg->type == PHY_TYPE_UFS) {
1657 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1658 mask = PCS_READY;
1659 ready = PCS_READY;
1660 } else {
1661 status = pcs + cfg->regs[QPHY_PCS_STATUS];
1662 mask = PHYSTATUS;
1663 ready = 0;
1664 }
e78f3d15 1665
14ced7e3 1666 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
e78f3d15
VG		 1667 PHY_INIT_COMPLETE_TIMEOUT);
1668 if (ret) {
1669 dev_err(qmp->dev, "phy initialization timed-out\n");
1670 goto err_pcs_ready;
1671 }
ac0d2399 1672 qmp->phy_initialized = true;
3f6d1767 1673 return 0;
e78f3d15
VG		 1674
1675err_pcs_ready:
3f6d1767 1676 reset_control_assert(qmp->ufs_reset);
fdf37e1a
MG		 1677 clk_disable_unprepare(qphy->pipe_clk);
1678err_clk_enable:
e78f3d15
VG		 1679 if (cfg->has_lane_rst)
1680 reset_control_assert(qphy->lane_rst);
1681err_lane_rst:
1682 qcom_qmp_phy_com_exit(qmp);
e78f3d15
VG		 1683
1684 return ret;
1685}
1686
3f6d1767 1687static int qcom_qmp_phy_disable(struct phy *phy)
e78f3d15
VG		 1688{
1689 struct qmp_phy *qphy = phy_get_drvdata(phy);
1690 struct qcom_qmp *qmp = qphy->qmp;
1691 const struct qmp_phy_cfg *cfg = qmp->cfg;
e78f3d15 1692
f8ba22a3
VG		 1693 clk_disable_unprepare(qphy->pipe_clk);
1694
e78f3d15 1695 /* PHY reset */
cc31cdbe
CG		 1696 if (!cfg->no_pcs_sw_reset)
1697 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
e78f3d15
VG		 1698
1699 /* stop SerDes and Phy-Coding-Sublayer */
1700 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1701
1702 /* Put PHY into POWER DOWN state: active low */
1703 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1704
1705 if (cfg->has_lane_rst)
1706 reset_control_assert(qphy->lane_rst);
1707
1708 qcom_qmp_phy_com_exit(qmp);
1709
ac0d2399
MG		 1710 qmp->phy_initialized = false;
1711
1712 return 0;
1713}
1714
79a5a18a
GS		 1715static int qcom_qmp_phy_set_mode(struct phy *phy,
1716 enum phy_mode mode, int submode)
ac0d2399
MG		 1717{
1718 struct qmp_phy *qphy = phy_get_drvdata(phy);
1719 struct qcom_qmp *qmp = qphy->qmp;
1720
1721 qmp->mode = mode;
1722
1723 return 0;
1724}
1725
1726static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
1727{
1728 struct qcom_qmp *qmp = qphy->qmp;
1729 const struct qmp_phy_cfg *cfg = qmp->cfg;
1730 void __iomem *pcs = qphy->pcs;
1731 void __iomem *pcs_misc = qphy->pcs_misc;
1732 u32 intr_mask;
1733
1734 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1735 qmp->mode == PHY_MODE_USB_DEVICE_SS)
1736 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1737 else
1738 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1739
1740 /* Clear any pending interrupts status */
1741 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1742 /* Writing 1 followed by 0 clears the interrupt */
1743 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1744
1745 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1746 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1747
1748 /* Enable required PHY autonomous mode interrupts */
1749 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1750
1751 /* Enable i/o clamp_n for autonomous mode */
1752 if (pcs_misc)
1753 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1754}
1755
1756static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
1757{
1758 struct qcom_qmp *qmp = qphy->qmp;
1759 const struct qmp_phy_cfg *cfg = qmp->cfg;
1760 void __iomem *pcs = qphy->pcs;
1761 void __iomem *pcs_misc = qphy->pcs_misc;
1762
1763 /* Disable i/o clamp_n on resume for normal mode */
1764 if (pcs_misc)
1765 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1766
1767 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1768 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1769
1770 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1771 /* Writing 1 followed by 0 clears the interrupt */
1772 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1773}
1774
1775static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
1776{
1777 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1778 struct qmp_phy *qphy = qmp->phys[0];
1779 const struct qmp_phy_cfg *cfg = qmp->cfg;
1780
1781 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1782
1783 /* Supported only for USB3 PHY */
1784 if (cfg->type != PHY_TYPE_USB3)
1785 return 0;
1786
1787 if (!qmp->phy_initialized) {
1788 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1789 return 0;
1790 }
1791
1792 qcom_qmp_phy_enable_autonomous_mode(qphy);
1793
1794 clk_disable_unprepare(qphy->pipe_clk);
1795 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1796
1797 return 0;
1798}
1799
1800static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
1801{
1802 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1803 struct qmp_phy *qphy = qmp->phys[0];
1804 const struct qmp_phy_cfg *cfg = qmp->cfg;
1805 int ret = 0;
1806
1807 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1808
1809 /* Supported only for USB3 PHY */
1810 if (cfg->type != PHY_TYPE_USB3)
1811 return 0;
1812
1813 if (!qmp->phy_initialized) {
1814 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1815 return 0;
1816 }
1817
1818 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1819 if (ret) {
1820 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1821 return ret;
1822 }
1823
1824 ret = clk_prepare_enable(qphy->pipe_clk);
1825 if (ret) {
1826 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1827 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1828 return ret;
1829 }
1830
1831 qcom_qmp_phy_disable_autonomous_mode(qphy);
1832
e78f3d15
VG		 1833 return 0;
1834}
1835
1836static int qcom_qmp_phy_vreg_init(struct device *dev)
1837{
1838 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1839 int num = qmp->cfg->num_vregs;
1840 int i;
1841
9605bc46 1842 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
e78f3d15
VG		 1843 if (!qmp->vregs)
1844 return -ENOMEM;
1845
1846 for (i = 0; i < num; i++)
1847 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
1848
1849 return devm_regulator_bulk_get(dev, num, qmp->vregs);
1850}
1851
1852static int qcom_qmp_phy_reset_init(struct device *dev)
1853{
1854 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1855 int i;
1856
1857 qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
1858 sizeof(*qmp->resets), GFP_KERNEL);
1859 if (!qmp->resets)
1860 return -ENOMEM;
1861
1862 for (i = 0; i < qmp->cfg->num_resets; i++) {
1863 struct reset_control *rst;
1864 const char *name = qmp->cfg->reset_list[i];
1865
1866 rst = devm_reset_control_get(dev, name);
1867 if (IS_ERR(rst)) {
1868 dev_err(dev, "failed to get %s reset\n", name);
1869 return PTR_ERR(rst);
1870 }
1871 qmp->resets[i] = rst;
1872 }
1873
1874 return 0;
1875}
1876
1877static int qcom_qmp_phy_clk_init(struct device *dev)
1878{
1879 struct qcom_qmp *qmp = dev_get_drvdata(dev);
10939b10
VG		 1880 int num = qmp->cfg->num_clks;
1881 int i;
e78f3d15 1882
10939b10 1883 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
e78f3d15
VG		 1884 if (!qmp->clks)
1885 return -ENOMEM;
1886
10939b10
VG		 1887 for (i = 0; i < num; i++)
1888 qmp->clks[i].id = qmp->cfg->clk_list[i];
e78f3d15 1889
10939b10 1890 return devm_clk_bulk_get(dev, num, qmp->clks);
e78f3d15
VG		 1891}
1892
2e38c2e7
EG		 1893static void phy_pipe_clk_release_provider(void *res)
1894{
1895 of_clk_del_provider(res);
1896}
1897
e78f3d15
VG		 1898/*
1899 * Register a fixed rate pipe clock.
1900 *
1901 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1902 * controls it. The <s>_pipe_clk coming out of the GCC is requested
1903 * by the PHY driver for its operations.
1904 * We register the <s>_pipe_clksrc here. The gcc driver takes care
1905 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
1906 * Below picture shows this relationship.
1907 *
1908 * +---------------+
1909 * | PHY block |<<---------------------------------------+
1910 * | | |
1911 * | +-------+ | +-----+ |
1912 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
1913 * clk | +-------+ | +-----+
1914 * +---------------+
1915 */
2a9316b0 1916static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
e78f3d15 1917{
e78f3d15
VG		 1918 struct clk_fixed_rate *fixed;
1919 struct clk_init_data init = { };
2a9316b0 1920 int ret;
e78f3d15 1921
2a9316b0
VN		 1922 if ((qmp->cfg->type != PHY_TYPE_USB3) &&
1923 (qmp->cfg->type != PHY_TYPE_PCIE)) {
e78f3d15
VG		 1924 /* not all phys register pipe clocks, so return success */
1925 return 0;
1926 }
1927
2a9316b0
VN		 1928 ret = of_property_read_string(np, "clock-output-names", &init.name);
1929 if (ret) {
ac9ba7dc 1930 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2a9316b0
VN		 1931 return ret;
1932 }
1933
e78f3d15
VG		 1934 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
1935 if (!fixed)
1936 return -ENOMEM;
1937
e78f3d15
VG		 1938 init.ops = &clk_fixed_rate_ops;
1939
1940 /* controllers using QMP phys use 125MHz pipe clock interface */
1941 fixed->fixed_rate = 125000000;
1942 fixed->hw.init = &init;
1943
2e38c2e7
EG		 1944 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
1945 if (ret)
1946 return ret;
1947
1948 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
1949 if (ret)
1950 return ret;
1951
1952 /*
1953 * Roll a devm action because the clock provider is the child node, but
1954 * the child node is not actually a device.
1955 */
1956 ret = devm_add_action(qmp->dev, phy_pipe_clk_release_provider, np);
1957 if (ret)
1958 phy_pipe_clk_release_provider(np);
1959
1960 return ret;
e78f3d15
VG		 1961}
1962
1963static const struct phy_ops qcom_qmp_phy_gen_ops = {
3f6d1767
EG		 1964 .init = qcom_qmp_phy_enable,
1965 .exit = qcom_qmp_phy_disable,
1966 .set_mode = qcom_qmp_phy_set_mode,
1967 .owner = THIS_MODULE,
1968};
1969
1970static const struct phy_ops qcom_qmp_ufs_ops = {
1971 .power_on = qcom_qmp_phy_enable,
1972 .power_off = qcom_qmp_phy_disable,
ac0d2399 1973 .set_mode = qcom_qmp_phy_set_mode,
e78f3d15
VG		 1974 .owner = THIS_MODULE,
1975};
1976
1977static
1978int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
1979{
1980 struct qcom_qmp *qmp = dev_get_drvdata(dev);
1981 struct phy *generic_phy;
1982 struct qmp_phy *qphy;
3f6d1767 1983 const struct phy_ops *ops = &qcom_qmp_phy_gen_ops;
e78f3d15
VG		 1984 char prop_name[MAX_PROP_NAME];
1985 int ret;
1986
1987 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
1988 if (!qphy)
1989 return -ENOMEM;
1990
1991 /*
1992 * Get memory resources for each phy lane:
5e17b95d
EG		 1993 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
1994 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
1995 * For single lane PHYs: pcs_misc (optional) -> 3.
e78f3d15
VG		 1996 */
1997 qphy->tx = of_iomap(np, 0);
53bf9590
WY		 1998 if (!qphy->tx)
1999 return -ENOMEM;
e78f3d15
VG		 2000
2001 qphy->rx = of_iomap(np, 1);
53bf9590
WY		 2002 if (!qphy->rx)
2003 return -ENOMEM;
e78f3d15
VG		 2004
2005 qphy->pcs = of_iomap(np, 2);
53bf9590
WY		 2006 if (!qphy->pcs)
2007 return -ENOMEM;
e78f3d15 2008
5e17b95d
EG		 2009 /*
2010 * If this is a dual-lane PHY, then there should be registers for the
2011 * second lane. Some old device trees did not specify this, so fall
2012 * back to old legacy behavior of assuming they can be reached at an
2013 * offset from the first lane.
2014 */
2015 if (qmp->cfg->is_dual_lane_phy) {
2016 qphy->tx2 = of_iomap(np, 3);
2017 qphy->rx2 = of_iomap(np, 4);
2018 if (!qphy->tx2 || !qphy->rx2) {
2019 dev_warn(dev,
2020 "Underspecified device tree, falling back to legacy register regions\n");
2021
2022 /* In the old version, pcs_misc is at index 3. */
2023 qphy->pcs_misc = qphy->tx2;
2024 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
2025 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
2026
2027 } else {
2028 qphy->pcs_misc = of_iomap(np, 5);
2029 }
2030
2031 } else {
2032 qphy->pcs_misc = of_iomap(np, 3);
2033 }
2034
ac0d2399
MG		 2035 if (!qphy->pcs_misc)
2036 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2037
e78f3d15
VG		 2038 /*
2039 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
2040 * based phys, so they essentially have pipe clock. So,
2041 * we return error in case phy is USB3 or PIPE type.
2042 * Otherwise, we initialize pipe clock to NULL for
2043 * all phys that don't need this.
2044 */
2045 snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
2046 qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
2047 if (IS_ERR(qphy->pipe_clk)) {
2048 if (qmp->cfg->type == PHY_TYPE_PCIE ||
2049 qmp->cfg->type == PHY_TYPE_USB3) {
2050 ret = PTR_ERR(qphy->pipe_clk);
2051 if (ret != -EPROBE_DEFER)
2052 dev_err(dev,
2053 "failed to get lane%d pipe_clk, %d\n",
2054 id, ret);
2055 return ret;
2056 }
2057 qphy->pipe_clk = NULL;
2058 }
2059
2060 /* Get lane reset, if any */
2061 if (qmp->cfg->has_lane_rst) {
2062 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
2063 qphy->lane_rst = of_reset_control_get(np, prop_name);
2064 if (IS_ERR(qphy->lane_rst)) {
2065 dev_err(dev, "failed to get lane%d reset\n", id);
2066 return PTR_ERR(qphy->lane_rst);
2067 }
2068 }
2069
3f6d1767
EG		 2070 if (qmp->cfg->type == PHY_TYPE_UFS)
2071 ops = &qcom_qmp_ufs_ops;
2072
2073 generic_phy = devm_phy_create(dev, np, ops);
e78f3d15
VG		 2074 if (IS_ERR(generic_phy)) {
2075 ret = PTR_ERR(generic_phy);
2076 dev_err(dev, "failed to create qphy %d\n", ret);
2077 return ret;
2078 }
2079
2080 qphy->phy = generic_phy;
2081 qphy->index = id;
2082 qphy->qmp = qmp;
2083 qmp->phys[id] = qphy;
2084 phy_set_drvdata(generic_phy, qphy);
2085
2086 return 0;
2087}
2088
2089static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
2090 {
2091 .compatible = "qcom,msm8996-qmp-pcie-phy",
2092 .data = &msm8996_pciephy_cfg,
2093 }, {
2094 .compatible = "qcom,msm8996-qmp-usb3-phy",
2095 .data = &msm8996_usb3phy_cfg,
73d7ec89
MG		 2096 }, {
2097 .compatible = "qcom,msm8998-qmp-pcie-phy",
2098 .data = &msm8998_pciephy_cfg,
203d9b11
MG		 2099 }, {
2100 .compatible = "qcom,msm8998-qmp-ufs-phy",
2101 .data = &sdm845_ufsphy_cfg,
eef243d0
VN		 2102 }, {
2103 .compatible = "qcom,ipq8074-qmp-pcie-phy",
2104 .data = &ipq8074_pciephy_cfg,
efb05a50 2105 }, {
f6721e5c 2106 .compatible = "qcom,sdm845-qmp-usb3-phy",
efb05a50 2107 .data = &qmp_v3_usb3phy_cfg,
f6721e5c
MG		 2108 }, {
2109 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2110 .data = &qmp_v3_usb3_uniphy_cfg,
cc31cdbe
CG		 2111 }, {
2112 .compatible = "qcom,sdm845-qmp-ufs-phy",
2113 .data = &sdm845_ufsphy_cfg,
a51969fa
JH		 2114 }, {
2115 .compatible = "qcom,msm8998-qmp-usb3-phy",
2116 .data = &msm8998_usb3phy_cfg,
a88c85ee
VK		 2117 }, {
2118 .compatible = "qcom,sm8150-qmp-ufs-phy",
2119 .data = &sm8150_ufsphy_cfg,
e78f3d15
VG		 2120 },
2121 { },
2122};
2123MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
2124
ac0d2399
MG		 2125static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
2126 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
2127 qcom_qmp_phy_runtime_resume, NULL)
2128};
2129
e78f3d15
VG		 2130static int qcom_qmp_phy_probe(struct platform_device *pdev)
2131{
2132 struct qcom_qmp *qmp;
2133 struct device *dev = &pdev->dev;
2134 struct resource *res;
2135 struct device_node *child;
2136 struct phy_provider *phy_provider;
2137 void __iomem *base;
2138 int num, id;
2139 int ret;
2140
2141 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2142 if (!qmp)
2143 return -ENOMEM;
2144
2145 qmp->dev = dev;
2146 dev_set_drvdata(dev, qmp);
2147
efb05a50
MG		 2148 /* Get the specific init parameters of QMP phy */
2149 qmp->cfg = of_device_get_match_data(dev);
2150 if (!qmp->cfg)
2151 return -EINVAL;
2152
e78f3d15
VG		 2153 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2154 base = devm_ioremap_resource(dev, res);
2155 if (IS_ERR(base))
2156 return PTR_ERR(base);
2157
2158 /* per PHY serdes; usually located at base address */
2159 qmp->serdes = base;
2160
efb05a50
MG		 2161 /* per PHY dp_com; if PHY has dp_com control block */
2162 if (qmp->cfg->has_phy_dp_com_ctrl) {
2163 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2164 "dp_com");
2165 base = devm_ioremap_resource(dev, res);
2166 if (IS_ERR(base))
2167 return PTR_ERR(base);
e78f3d15 2168
efb05a50
MG		 2169 qmp->dp_com = base;
2170 }
2171
2172 mutex_init(&qmp->phy_mutex);
e78f3d15
VG		 2173
2174 ret = qcom_qmp_phy_clk_init(dev);
2175 if (ret)
2176 return ret;
2177
2178 ret = qcom_qmp_phy_reset_init(dev);
2179 if (ret)
2180 return ret;
2181
2182 ret = qcom_qmp_phy_vreg_init(dev);
2183 if (ret) {
22fa10e5
DA		 2184 if (ret != -EPROBE_DEFER)
2185 dev_err(dev, "failed to get regulator supplies: %d\n",
2186 ret);
e78f3d15
VG		 2187 return ret;
2188 }
2189
2190 num = of_get_available_child_count(dev->of_node);
2191 /* do we have a rogue child node ? */
2192 if (num > qmp->cfg->nlanes)
2193 return -EINVAL;
2194
2195 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
2196 if (!qmp->phys)
2197 return -ENOMEM;
2198
2199 id = 0;
ac0d2399
MG		 2200 pm_runtime_set_active(dev);
2201 pm_runtime_enable(dev);
2202 /*
2203 * Prevent runtime pm from being ON by default. Users can enable
2204 * it using power/control in sysfs.
2205 */
2206 pm_runtime_forbid(dev);
2207
e78f3d15
VG		 2208 for_each_available_child_of_node(dev->of_node, child) {
2209 /* Create per-lane phy */
2210 ret = qcom_qmp_phy_create(dev, child, id);
2211 if (ret) {
2212 dev_err(dev, "failed to create lane%d phy, %d\n",
2213 id, ret);
be0345b2 2214 goto err_node_put;
e78f3d15
VG		 2215 }
2216
2217 /*
2218 * Register the pipe clock provided by phy.
2219 * See function description to see details of this pipe clock.
2220 */
2a9316b0 2221 ret = phy_pipe_clk_register(qmp, child);
e78f3d15
VG		 2222 if (ret) {
2223 dev_err(qmp->dev,
2224 "failed to register pipe clock source\n");
be0345b2 2225 goto err_node_put;
e78f3d15
VG		 2226 }
2227 id++;
2228 }
2229
2230 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2231 if (!IS_ERR(phy_provider))
2232 dev_info(dev, "Registered Qcom-QMP phy\n");
ac0d2399
MG		 2233 else
2234 pm_runtime_disable(dev);
e78f3d15
VG		 2235
2236 return PTR_ERR_OR_ZERO(phy_provider);
be0345b2
ND		 2237
2238err_node_put:
2239 pm_runtime_disable(dev);
2240 of_node_put(child);
2241 return ret;
e78f3d15
VG		 2242}
2243
2244static struct platform_driver qcom_qmp_phy_driver = {
2245 .probe = qcom_qmp_phy_probe,
2246 .driver = {
2247 .name = "qcom-qmp-phy",
ac0d2399 2248 .pm = &qcom_qmp_phy_pm_ops,
e78f3d15
VG		 2249 .of_match_table = qcom_qmp_phy_of_match_table,
2250 },
2251};
2252
2253module_platform_driver(qcom_qmp_phy_driver);
2254
2255MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2256MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
2257MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)