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phy: qcom-qmp-usb: rework reset handling
[linux-2.6-block.git] / drivers / phy / qualcomm / phy-qcom-qmp-usb.c
CommitLineData
94a407cc
DB		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
94a407cc
DB		 15#include <linux/of_address.h>
16#include <linux/phy/phy.h>
17#include <linux/platform_device.h>
18#include <linux/regulator/consumer.h>
19#include <linux/reset.h>
20#include <linux/slab.h>
21
94a407cc 22#include "phy-qcom-qmp.h"
eb5793fb
DB		 23#include "phy-qcom-qmp-pcs-misc-v3.h"
24#include "phy-qcom-qmp-pcs-usb-v4.h"
25#include "phy-qcom-qmp-pcs-usb-v5.h"
94a407cc
DB		 26
27/* QPHY_SW_RESET bit */
28#define SW_RESET BIT(0)
29/* QPHY_POWER_DOWN_CONTROL */
30#define SW_PWRDN BIT(0)
94a407cc
DB		 31/* QPHY_START_CONTROL bits */
32#define SERDES_START BIT(0)
33#define PCS_START BIT(1)
94a407cc
DB		 34/* QPHY_PCS_STATUS bit */
35#define PHYSTATUS BIT(6)
94a407cc
DB		 36
37/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
38/* DP PHY soft reset */
39#define SW_DPPHY_RESET BIT(0)
40/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
41#define SW_DPPHY_RESET_MUX BIT(1)
42/* USB3 PHY soft reset */
43#define SW_USB3PHY_RESET BIT(2)
44/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
45#define SW_USB3PHY_RESET_MUX BIT(3)
46
47/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
48#define USB3_MODE BIT(0) /* enables USB3 mode */
49#define DP_MODE BIT(1) /* enables DP mode */
50
51/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
52#define ARCVR_DTCT_EN BIT(0)
53#define ALFPS_DTCT_EN BIT(1)
54#define ARCVR_DTCT_EVENT_SEL BIT(4)
55
56/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
57#define IRQ_CLEAR BIT(0)
58
94a407cc
DB		 59/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
60#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
61
62#define PHY_INIT_COMPLETE_TIMEOUT 10000
94a407cc 63
94a407cc
DB		 64struct qmp_phy_init_tbl {
65 unsigned int offset;
66 unsigned int val;
94a407cc
DB		 67 /*
68 * mask of lanes for which this register is written
69 * for cases when second lane needs different values
70 */
71 u8 lane_mask;
72};
73
74#define QMP_PHY_INIT_CFG(o, v) \
75 { \
76 .offset = o, \
77 .val = v, \
78 .lane_mask = 0xff, \
79 }
80
94a407cc
DB		 81#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
82 { \
83 .offset = o, \
84 .val = v, \
85 .lane_mask = l, \
86 }
87
88/* set of registers with offsets different per-PHY */
89enum qphy_reg_layout {
94a407cc 90 /* PCS registers */
94a407cc
DB		 91 QPHY_SW_RESET,
92 QPHY_START_CTRL,
94a407cc
DB		 93 QPHY_PCS_STATUS,
94 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
95 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
94a407cc 96 QPHY_PCS_POWER_DOWN_CONTROL,
94a407cc
DB		 97 /* Keep last to ensure regs_layout arrays are properly initialized */
98 QPHY_LAYOUT_SIZE
99};
100
83cb72b4
DB		 101static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
102 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
103 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
104 [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS,
105 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,
106 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,
107 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
94a407cc
DB		 108};
109
110static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
83cb72b4
DB		 111 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
112 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
113 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
114 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
115 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
116 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
94a407cc
DB		 117};
118
94a407cc 119static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
83cb72b4
DB		 120 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
121 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
122 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
123 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
94a407cc 124
fc646236 125 /* In PCS_USB */
83cb72b4
DB		 126 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
127 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
94a407cc
DB		 128};
129
14d98d3b
DB		 130static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
131 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
132 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
133 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
134 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
135
136 /* In PCS_USB */
137 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
138 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
94a407cc
DB		 139};
140
a8874ada
VN		 141static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
142 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
143 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
144 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
145 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
146 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
147 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
148 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
149 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
150 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
151 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
152 /* PLL and Loop filter settings */
153 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
154 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
155 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
156 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
157 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
158 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
159 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
160 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
161 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
162 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
163 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
164 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
165 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
166 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
167 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
168 /* SSC settings */
169 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
170 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
171 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
172 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
173 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
174 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
175 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
176};
177
178static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
179 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
180 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
181 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
182};
183
184static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
185 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
186 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
187 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
188 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
189 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
190 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
191 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
192 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
193 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
194 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
195};
196
197static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
212 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
215 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
216 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
217 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
218 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
219 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
220 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
221};
222
94a407cc
DB		 223static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
224 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
225 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
226 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
227 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
228 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
229 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
230 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
231 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
232 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
233 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
234 /* PLL and Loop filter settings */
235 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
236 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
237 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
238 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
239 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
240 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
241 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
242 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
243 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
244 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
245 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
246 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
247 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
248 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
249 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
250 /* SSC settings */
251 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
252 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
253 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
254 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
255 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
256 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
257 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
258};
259
260static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
261 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
262 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
263 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
264 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
265 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
266 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
267 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
268 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
269 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
270};
271
272static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
273 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
274 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
275 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
277 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
278 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
279 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
280 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
281 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
282 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
296};
297
94a407cc
DB		 298static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
299 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
300 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
301 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
302 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
303 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
304 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
305 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
306 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
307 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
308 /* PLL and Loop filter settings */
309 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
310 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
311 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
312 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
313 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
314 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
315 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
316 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
317 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
318 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
319 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
320 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
321 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
322 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
323 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
324 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
325 /* SSC settings */
326 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
327 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
328 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
329 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
330 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
331 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
332 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
333};
334
335static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
336 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
337 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
338 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
339};
340
341static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
342 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
343 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
344 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
345 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
346 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
347 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
348 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
349 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
350 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
351 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
352};
353
354static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
355 /* FLL settings */
d36e341a
DB		 356 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
357 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
358 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
359 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
360 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
94a407cc
DB		 361
362 /* Lock Det settings */
6cad2983
DB		 363 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
364 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
365 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
366 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
94a407cc
DB		 367};
368
94a407cc
DB		 369static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
370 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
371 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
372 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
373 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
374 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
375 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
376 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
377 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
378 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
379 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
380 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
381 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
382 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
383 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
384 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
385 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
386 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
387 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
388 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
389 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
390 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
391 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
392 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
393 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
394 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
395 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
406};
407
408static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
409 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
410 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
411 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
412 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
413 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
414};
415
416static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
417 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
418 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
419 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
420 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
421 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
422 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
423 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
424 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
425 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
426 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
427 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
428};
429
430static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
431 /* FLL settings */
432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
434 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
437
438 /* Lock Det settings */
439 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
440 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
441 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
442 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
443
444 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
445 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
446 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
447 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
454 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
463
464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
475
476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
478};
479
94a407cc
DB		 480static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
481 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
482 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
483 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
484 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
485 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
486 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
487 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
488 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
489 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
490 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
491 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
492 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
493 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
494 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
495 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
496 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
497 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
498 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
499 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
500 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
501 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
502 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
503 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
519};
520
521static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
522 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
523 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
524 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
525 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
526};
527
528static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
529 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
530 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
531 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
532 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
533 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
534 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
535 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
536 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
537 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
538 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
539 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
540 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
541 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
542 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
543 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
544 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
545 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
546};
547
548static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
549 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
550 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
551 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
552 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
553 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
554 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
555 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
556 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
557 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
558 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
559 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
560 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
561 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
562 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
563 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
564 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
565 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
fc270d13 566 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
94a407cc
DB		 567 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
568 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
569 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
570 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
571 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
572 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
573 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
576 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
587};
588
94a407cc
DB		 589static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
590 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
591 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
592 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
593 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
594 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
595 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
596 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
597 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
598 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
599 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
600 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
601 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
602 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
603 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
604 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
605 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
606 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
607 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
608 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
609 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
610 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
611 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
612 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
613 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
614 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
615 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
616 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
617 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
618 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
619 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
620 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
621 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
622 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
623 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
624 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
625 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
626 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
630};
631
632static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
633 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
634 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
635 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
636 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
637};
638
639static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
640 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
641 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
642 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
676};
677
678static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
679 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
680 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
681 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
94a407cc
DB		 686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
689 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
693};
694
fc646236
DB		 695static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
696 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
697 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
698};
699
94a407cc
DB		 700static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
701 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
702 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
703 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
704 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
705 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
706 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
707};
708
709static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
710 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
711 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
712 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
713 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
714 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
715 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
716 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
717 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
718 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
719 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
720 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
721 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
722 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
723 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
724 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
725 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
726 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
8c924330 727 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
94a407cc 728 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
8c924330
DB		 729 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
730 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
731 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
732 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
94a407cc 733 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
8c924330 734 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
94a407cc 735 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
8c924330
DB		 736 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
737 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
738 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
739 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
740 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
741 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
94a407cc 742 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
8c924330
DB		 743 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
744 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
745 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
94a407cc
DB		 746};
747
8c924330
DB		 748static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
749 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
750 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
751 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
752 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
753 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
754 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
755 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
756 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
8c924330
DB		 757 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
758 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
759 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
760 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
761 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
762 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
94a407cc
DB		 763};
764
fc646236
DB		 765static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
766 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
767 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
768};
769
94a407cc
DB		 770static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
771 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
772 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
773 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
774 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
775 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
776};
777
778static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
779 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
815};
816
94a407cc
DB		 817static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
818 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
819 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
820 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
821 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
822 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
823 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
824 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
825};
826
827static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
828 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
829 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
830 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
831 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
832 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
833 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
834 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
835 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
836 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
837 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
838 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
839 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
840 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
841 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
842 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
843 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
844 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
845 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
846 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
847 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
848 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
849 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
850 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
851 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
852 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
853 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
854 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
855 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
856 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
857 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
858 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
859};
860
94a407cc
DB		 861static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
862 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
863 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
864 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
865 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
866 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
867 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
868 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
869};
870
871static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
872 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
873 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
874 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
875 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
876 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
877 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
878 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
879 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
880 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
881 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
882 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
883 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
884 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
885 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
886 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
887 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
888 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
889 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
890 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
891 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
892 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
893 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
894 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
895 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
896 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
897 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
898 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
899 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
900 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
901 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
902 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
903};
904
905static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
906 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
907 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
908 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
909 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
910 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
911 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
912 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
913 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
94a407cc
DB		 914 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
915 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
916 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
917 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
918 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
919 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
920};
921
fc646236
DB		 922static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
923 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
924 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
925};
926
94a407cc
DB		 927static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
928 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
929 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
930 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
931 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
932 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
933 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
934 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
935 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
936 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
937 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
938 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
939 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
940 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
941 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
942 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
943 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
944 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
945 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
946 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
947 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
948 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
949 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
950 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
951 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
952 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
953 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
954 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
955 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
956 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
957 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
958 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
959 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
960 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
961 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
962 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
963 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
964 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
965 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
966};
967
968static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
969 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
970 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
971 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
972 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
973 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
974};
975
976static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
977 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
a9c5f22f 978 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
94a407cc
DB		 979 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
980 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
981 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
982 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
983 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
984 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
985 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
986 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
987 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
988 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
989 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
990 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
991 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
992 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
993 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
994};
995
996static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
997 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
998 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
999 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
1000 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1001 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1002 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1003 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1004 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
1005 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1006 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1007 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1008 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1009 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1010 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1011 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1012 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1013 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1014 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1015 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1016 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1017 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
1018};
1019
c0c7769c
BA		 1020static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
1021 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1022 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1023 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1024 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1025 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),
1026 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),
1027 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),
1028 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1029 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1030 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1031 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1032 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1033 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1034 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1035 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1036 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1037 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1038 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),
1039 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),
1040 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1041 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),
1042 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1043 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),
1044 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1045 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1046 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1047 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1048 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1049 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1050 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1051 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1052 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1053 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1054 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1055 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1056 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1057 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1058 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1059 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1060};
1061
1062static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
1063 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1064 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1065 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1066 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1067 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1068 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1069 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1070};
1071
1072static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
1073 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1074 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1075 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1076 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1077 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1078 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1079 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1080 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1081 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1082 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1083 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1084 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1085 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1086 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1087 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1088 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1089 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1090 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1091 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a),
1092 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1093 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1094 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1095 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1096 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1097 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1098 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1099 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1100 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1101 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1102 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1103 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1104};
1105
1106static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
1107 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1108 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1109 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1110 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1111 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1112 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1113 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1114 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1115 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1116 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1117 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1118 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1119 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1120 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1121 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1122 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1123};
1124
8bd2d6e1
SH		 1125static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = {
1126 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1127 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89),
1128 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1129 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1130 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1131 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1132 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1133 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1134 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1135 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1136 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),
1137 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1138 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1139 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1140 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1141 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1142 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1143};
1144
c0a6c252
JH		 1145struct qmp_usb_offsets {
1146 u16 serdes;
1147 u16 pcs;
1178c93c 1148 u16 pcs_misc;
c0a6c252
JH		 1149 u16 pcs_usb;
1150 u16 tx;
1151 u16 rx;
1178c93c
BS		 1152 /* for PHYs with >= 2 lanes */
1153 u16 tx2;
1154 u16 rx2;
c0a6c252
JH		 1155};
1156
94a407cc
DB		 1157/* struct qmp_phy_cfg - per-PHY initialization config */
1158struct qmp_phy_cfg {
a73a19ea 1159 int lanes;
94a407cc 1160
c0a6c252
JH		 1161 const struct qmp_usb_offsets *offsets;
1162
94a407cc
DB		 1163 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1164 const struct qmp_phy_init_tbl *serdes_tbl;
1165 int serdes_tbl_num;
94a407cc
DB		 1166 const struct qmp_phy_init_tbl *tx_tbl;
1167 int tx_tbl_num;
94a407cc
DB		 1168 const struct qmp_phy_init_tbl *rx_tbl;
1169 int rx_tbl_num;
94a407cc
DB		 1170 const struct qmp_phy_init_tbl *pcs_tbl;
1171 int pcs_tbl_num;
fc646236
DB		 1172 const struct qmp_phy_init_tbl *pcs_usb_tbl;
1173 int pcs_usb_tbl_num;
94a407cc 1174
94a407cc
DB		 1175 /* regulators to be requested */
1176 const char * const *vreg_list;
1177 int num_vregs;
1178
1179 /* array of registers with different offsets */
1180 const unsigned int *regs;
1181
94a407cc
DB		 1182 /* true, if PHY needs delay after POWER_DOWN */
1183 bool has_pwrdn_delay;
94a407cc 1184
fc646236
DB		 1185 /* Offset from PCS to PCS_USB region */
1186 unsigned int pcs_usb_offset;
94a407cc
DB		 1187};
1188
2a55ec4f
JH		 1189struct qmp_usb {
1190 struct device *dev;
1191
94a407cc 1192 const struct qmp_phy_cfg *cfg;
2a55ec4f 1193
94a407cc 1194 void __iomem *serdes;
2a55ec4f
JH		 1195 void __iomem *pcs;
1196 void __iomem *pcs_misc;
1197 void __iomem *pcs_usb;
94a407cc
DB		 1198 void __iomem *tx;
1199 void __iomem *rx;
94a407cc
DB		 1200 void __iomem *tx2;
1201 void __iomem *rx2;
94a407cc 1202
2a55ec4f 1203 struct clk *pipe_clk;
94a407cc 1204 struct clk_bulk_data *clks;
7233090a 1205 int num_clks;
fcf63482 1206 int num_resets;
e991c2ee 1207 struct reset_control_bulk_data *resets;
94a407cc
DB		 1208 struct regulator_bulk_data *vregs;
1209
2a55ec4f
JH		 1210 enum phy_mode mode;
1211
1212 struct phy *phy;
64e1f12b
JH		 1213
1214 struct clk_fixed_rate pipe_clk_fixed;
94a407cc
DB		 1215};
1216
94a407cc
DB		 1217static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1218{
1219 u32 reg;
1220
1221 reg = readl(base + offset);
1222 reg |= val;
1223 writel(reg, base + offset);
1224
1225 /* ensure that above write is through */
1226 readl(base + offset);
1227}
1228
1229static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1230{
1231 u32 reg;
1232
1233 reg = readl(base + offset);
1234 reg &= ~val;
1235 writel(reg, base + offset);
1236
1237 /* ensure that above write is through */
1238 readl(base + offset);
1239}
1240
1241/* list of clocks required by phy */
7233090a 1242static const char * const qmp_usb_phy_clk_l[] = {
94a407cc
DB		 1243 "aux", "cfg_ahb", "ref", "com_aux",
1244};
1245
94a407cc 1246/* list of resets */
fcf63482 1247static const char * const usb3phy_legacy_reset_l[] = {
94a407cc
DB		 1248 "phy", "common",
1249};
1250
fcf63482 1251static const char * const usb3phy_reset_l[] = {
94a407cc
DB		 1252 "phy_phy", "phy",
1253};
1254
94a407cc
DB		 1255/* list of regulators */
1256static const char * const qmp_phy_vreg_l[] = {
1257 "vdda-phy", "vdda-pll",
1258};
1259
a8874ada
VN		 1260static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
1261 .serdes = 0,
1262 .pcs = 0x800,
1263 .pcs_usb = 0x800,
1264 .tx = 0x200,
1265 .rx = 0x400,
1266};
1267
1178c93c
BS		 1268static const struct qmp_usb_offsets qmp_usb_offsets_v3 = {
1269 .serdes = 0,
1270 .pcs = 0xc00,
1271 .pcs_misc = 0xa00,
1272 .tx = 0x200,
1273 .rx = 0x400,
1274 .tx2 = 0x600,
1275 .rx2 = 0x800,
1276};
1277
c0a6c252
JH		 1278static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
1279 .serdes = 0,
1280 .pcs = 0x0200,
1281 .pcs_usb = 0x1200,
1282 .tx = 0x0e00,
1283 .rx = 0x1000,
1284};
1285
94a407cc 1286static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
a73a19ea 1287 .lanes = 1,
94a407cc
DB		 1288
1289 .serdes_tbl = ipq8074_usb3_serdes_tbl,
1290 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1291 .tx_tbl = msm8996_usb3_tx_tbl,
1292 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1293 .rx_tbl = ipq8074_usb3_rx_tbl,
1294 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1295 .pcs_tbl = ipq8074_usb3_pcs_tbl,
1296 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
94a407cc
DB		 1297 .vreg_list = qmp_phy_vreg_l,
1298 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
922adfd5 1299 .regs = qmp_v3_usb3phy_regs_layout,
94a407cc
DB		 1300};
1301
a8874ada
VN		 1302static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
1303 .lanes = 1,
1304
1305 .offsets = &qmp_usb_offsets_ipq9574,
1306
1307 .serdes_tbl = ipq9574_usb3_serdes_tbl,
1308 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1309 .tx_tbl = ipq9574_usb3_tx_tbl,
1310 .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
1311 .rx_tbl = ipq9574_usb3_rx_tbl,
1312 .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
1313 .pcs_tbl = ipq9574_usb3_pcs_tbl,
1314 .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
a8874ada
VN		 1315 .vreg_list = qmp_phy_vreg_l,
1316 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1317 .regs = qmp_v3_usb3phy_regs_layout,
1318};
1319
94a407cc 1320static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
a73a19ea 1321 .lanes = 1,
94a407cc
DB		 1322
1323 .serdes_tbl = msm8996_usb3_serdes_tbl,
1324 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1325 .tx_tbl = msm8996_usb3_tx_tbl,
1326 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1327 .rx_tbl = msm8996_usb3_rx_tbl,
1328 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1329 .pcs_tbl = msm8996_usb3_pcs_tbl,
1330 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
94a407cc
DB		 1331 .vreg_list = qmp_phy_vreg_l,
1332 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
83cb72b4 1333 .regs = qmp_v2_usb3phy_regs_layout,
94a407cc
DB		 1334};
1335
8bd2d6e1
SH		 1336static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = {
1337 .lanes = 1,
1338
1339 .offsets = &qmp_usb_offsets_v5,
1340
1341 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1342 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1343 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
1344 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1345 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
1346 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1347 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl,
1348 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),
8bd2d6e1
SH		 1349 .vreg_list = qmp_phy_vreg_l,
1350 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1351 .regs = qmp_v5_usb3phy_regs_layout,
1352};
1353
c0c7769c 1354static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
a73a19ea 1355 .lanes = 1,
c0c7769c 1356
c0a6c252
JH		 1357 .offsets = &qmp_usb_offsets_v5,
1358
c0c7769c
BA		 1359 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1360 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1361 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
1362 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1363 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
1364 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1365 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl,
1366 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
c0c7769c
BA		 1367 .vreg_list = qmp_phy_vreg_l,
1368 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
14d98d3b 1369 .regs = qmp_v5_usb3phy_regs_layout,
c0c7769c
BA		 1370};
1371
94a407cc 1372static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
a73a19ea 1373 .lanes = 1,
94a407cc
DB		 1374
1375 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
1376 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1377 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
1378 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1379 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
1380 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1381 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
1382 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
94a407cc
DB		 1383 .vreg_list = qmp_phy_vreg_l,
1384 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1385 .regs = qmp_v3_usb3phy_regs_layout,
1386
94a407cc 1387 .has_pwrdn_delay = true,
94a407cc
DB		 1388};
1389
94a407cc 1390static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
a73a19ea 1391 .lanes = 2,
94a407cc
DB		 1392
1393 .serdes_tbl = msm8998_usb3_serdes_tbl,
1394 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1395 .tx_tbl = msm8998_usb3_tx_tbl,
1396 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1397 .rx_tbl = msm8998_usb3_rx_tbl,
1398 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1399 .pcs_tbl = msm8998_usb3_pcs_tbl,
1400 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
94a407cc
DB		 1401 .vreg_list = qmp_phy_vreg_l,
1402 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
8c924330 1403 .regs = qmp_v3_usb3phy_regs_layout,
94a407cc
DB		 1404};
1405
94a407cc 1406static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
a73a19ea 1407 .lanes = 1,
94a407cc
DB		 1408
1409 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1410 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1411 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
1412 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1413 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
1414 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1415 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
1416 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
fc646236
DB		 1417 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl,
1418 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1419 .vreg_list = qmp_phy_vreg_l,
1420 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1421 .regs = qmp_v4_usb3phy_regs_layout,
1422 .pcs_usb_offset = 0x600,
94a407cc 1423
94a407cc 1424 .has_pwrdn_delay = true,
94a407cc
DB		 1425};
1426
94a407cc 1427static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
a73a19ea 1428 .lanes = 1,
94a407cc
DB		 1429
1430 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1431 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1432 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
1433 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1434 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
1435 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1436 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1437 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
fc646236
DB		 1438 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1439 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1440 .vreg_list = qmp_phy_vreg_l,
1441 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1442 .regs = qmp_v4_usb3phy_regs_layout,
1443 .pcs_usb_offset = 0x600,
94a407cc 1444
94a407cc 1445 .has_pwrdn_delay = true,
94a407cc
DB		 1446};
1447
94a407cc 1448static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
a73a19ea 1449 .lanes = 1,
94a407cc
DB		 1450
1451 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1452 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1453 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
1454 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1455 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
1456 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1457 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1458 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
fc646236
DB		 1459 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1460 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1461 .vreg_list = qmp_phy_vreg_l,
1462 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1463 .regs = qmp_v4_usb3phy_regs_layout,
1464 .pcs_usb_offset = 0x600,
94a407cc 1465
94a407cc 1466 .has_pwrdn_delay = true,
94a407cc
DB		 1467};
1468
94a407cc 1469static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
a73a19ea 1470 .lanes = 1,
94a407cc
DB		 1471
1472 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1473 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1474 .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
1475 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1476 .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
1477 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1478 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1479 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
fc646236
DB		 1480 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1481 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1482 .vreg_list = qmp_phy_vreg_l,
1483 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
0dcaef53 1484 .regs = qmp_v5_usb3phy_regs_layout,
fc646236 1485 .pcs_usb_offset = 0x1000,
94a407cc 1486
94a407cc 1487 .has_pwrdn_delay = true,
94a407cc
DB		 1488};
1489
94a407cc 1490static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
a73a19ea 1491 .lanes = 1,
94a407cc
DB		 1492
1493 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1494 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1495 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
1496 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1497 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
1498 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1499 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1500 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
fc646236
DB		 1501 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1502 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1503 .vreg_list = qmp_phy_vreg_l,
1504 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
14d98d3b 1505 .regs = qmp_v5_usb3phy_regs_layout,
fc646236 1506 .pcs_usb_offset = 0x1000,
94a407cc 1507
94a407cc 1508 .has_pwrdn_delay = true,
94a407cc
DB		 1509};
1510
94a407cc 1511static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
a73a19ea 1512 .lanes = 2,
94a407cc 1513
1178c93c
BS		 1514 .offsets = &qmp_usb_offsets_v3,
1515
94a407cc
DB		 1516 .serdes_tbl = qcm2290_usb3_serdes_tbl,
1517 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
1518 .tx_tbl = qcm2290_usb3_tx_tbl,
1519 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
1520 .rx_tbl = qcm2290_usb3_rx_tbl,
1521 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
1522 .pcs_tbl = qcm2290_usb3_pcs_tbl,
1523 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
94a407cc
DB		 1524 .vreg_list = qmp_phy_vreg_l,
1525 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
14d98d3b 1526 .regs = qmp_v3_usb3phy_regs_layout,
94a407cc
DB		 1527};
1528
b767dedc 1529static void qmp_usb_configure_lane(void __iomem *base,
94a407cc
DB		 1530 const struct qmp_phy_init_tbl tbl[],
1531 int num,
1532 u8 lane_mask)
1533{
1534 int i;
1535 const struct qmp_phy_init_tbl *t = tbl;
1536
1537 if (!t)
1538 return;
1539
1540 for (i = 0; i < num; i++, t++) {
1541 if (!(t->lane_mask & lane_mask))
1542 continue;
1543
9d452c3a 1544 writel(t->val, base + t->offset);
94a407cc
DB		 1545 }
1546}
1547
b767dedc 1548static void qmp_usb_configure(void __iomem *base,
94a407cc
DB		 1549 const struct qmp_phy_init_tbl tbl[],
1550 int num)
1551{
9d452c3a 1552 qmp_usb_configure_lane(base, tbl, num, 0xff);
94a407cc
DB		 1553}
1554
2a55ec4f 1555static int qmp_usb_serdes_init(struct qmp_usb *qmp)
94a407cc 1556{
2a55ec4f
JH		 1557 const struct qmp_phy_cfg *cfg = qmp->cfg;
1558 void __iomem *serdes = qmp->serdes;
94a407cc
DB		 1559 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1560 int serdes_tbl_num = cfg->serdes_tbl_num;
94a407cc 1561
9d452c3a 1562 qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num);
94a407cc
DB		 1563
1564 return 0;
1565}
1566
fe2da191 1567static int qmp_usb_init(struct phy *phy)
94a407cc 1568{
2a55ec4f
JH		 1569 struct qmp_usb *qmp = phy_get_drvdata(phy);
1570 const struct qmp_phy_cfg *cfg = qmp->cfg;
1571 void __iomem *pcs = qmp->pcs;
e991c2ee 1572 int ret;
94a407cc 1573
94a407cc
DB		 1574 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1575 if (ret) {
1576 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
65753f38 1577 return ret;
94a407cc
DB		 1578 }
1579
fcf63482 1580 ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets);
e991c2ee
DB		 1581 if (ret) {
1582 dev_err(qmp->dev, "reset assert failed\n");
1583 goto err_disable_regulators;
94a407cc
DB		 1584 }
1585
fcf63482 1586 ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets);
e991c2ee
DB		 1587 if (ret) {
1588 dev_err(qmp->dev, "reset deassert failed\n");
1589 goto err_disable_regulators;
94a407cc
DB		 1590 }
1591
7233090a 1592 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
94a407cc
DB		 1593 if (ret)
1594 goto err_assert_reset;
1595
47b009db 1596 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
94a407cc 1597
94a407cc
DB		 1598 return 0;
1599
1600err_assert_reset:
fcf63482 1601 reset_control_bulk_assert(qmp->num_resets, qmp->resets);
94a407cc
DB		 1602err_disable_regulators:
1603 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
94a407cc
DB		 1604
1605 return ret;
1606}
1607
fe2da191 1608static int qmp_usb_exit(struct phy *phy)
94a407cc 1609{
2a55ec4f
JH		 1610 struct qmp_usb *qmp = phy_get_drvdata(phy);
1611 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 1612
fcf63482 1613 reset_control_bulk_assert(qmp->num_resets, qmp->resets);
94a407cc 1614
7233090a 1615 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
94a407cc
DB		 1616
1617 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1618
94a407cc
DB		 1619 return 0;
1620}
1621
b767dedc 1622static int qmp_usb_power_on(struct phy *phy)
94a407cc 1623{
2a55ec4f
JH		 1624 struct qmp_usb *qmp = phy_get_drvdata(phy);
1625 const struct qmp_phy_cfg *cfg = qmp->cfg;
1626 void __iomem *tx = qmp->tx;
1627 void __iomem *rx = qmp->rx;
1628 void __iomem *pcs = qmp->pcs;
94a407cc 1629 void __iomem *status;
f5ef85ad 1630 unsigned int val;
94a407cc
DB		 1631 int ret;
1632
2a55ec4f 1633 qmp_usb_serdes_init(qmp);
94a407cc 1634
2a55ec4f 1635 ret = clk_prepare_enable(qmp->pipe_clk);
94a407cc
DB		 1636 if (ret) {
1637 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
faf83af5 1638 return ret;
94a407cc
DB		 1639 }
1640
1641 /* Tx, Rx, and PCS configurations */
9d452c3a 1642 qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
9d452c3a 1643 qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
94a407cc 1644
876420fb
JH		 1645 if (cfg->lanes >= 2) {
1646 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
2a55ec4f 1647 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
876420fb 1648 }
94a407cc 1649
9d452c3a 1650 qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
94a407cc 1651
94a407cc 1652 if (cfg->has_pwrdn_delay)
38cd167d 1653 usleep_range(10, 20);
94a407cc 1654
86f5dddd 1655 /* Pull PHY out of reset state */
faf83af5
DB		 1656 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1657
86f5dddd 1658 /* start SerDes and Phy-Coding-Sublayer */
47b009db 1659 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
94a407cc 1660
86f5dddd 1661 status = pcs + cfg->regs[QPHY_PCS_STATUS];
7612890b 1662 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
86f5dddd
DB		 1663 PHY_INIT_COMPLETE_TIMEOUT);
1664 if (ret) {
1665 dev_err(qmp->dev, "phy initialization timed-out\n");
1666 goto err_disable_pipe_clk;
94a407cc 1667 }
86f5dddd 1668
94a407cc
DB		 1669 return 0;
1670
1671err_disable_pipe_clk:
2a55ec4f 1672 clk_disable_unprepare(qmp->pipe_clk);
94a407cc
DB		 1673
1674 return ret;
1675}
1676
b767dedc 1677static int qmp_usb_power_off(struct phy *phy)
94a407cc 1678{
2a55ec4f
JH		 1679 struct qmp_usb *qmp = phy_get_drvdata(phy);
1680 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 1681
2a55ec4f 1682 clk_disable_unprepare(qmp->pipe_clk);
94a407cc 1683
86f5dddd 1684 /* PHY reset */
2a55ec4f 1685 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
94a407cc 1686
86f5dddd 1687 /* stop SerDes and Phy-Coding-Sublayer */
2a55ec4f 1688 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
47b009db 1689 SERDES_START | PCS_START);
94a407cc 1690
86f5dddd 1691 /* Put PHY into POWER DOWN state: active low */
2a55ec4f 1692 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
47b009db 1693 SW_PWRDN);
94a407cc
DB		 1694
1695 return 0;
1696}
1697
b767dedc 1698static int qmp_usb_enable(struct phy *phy)
94a407cc
DB		 1699{
1700 int ret;
1701
b767dedc 1702 ret = qmp_usb_init(phy);
94a407cc
DB		 1703 if (ret)
1704 return ret;
1705
b767dedc 1706 ret = qmp_usb_power_on(phy);
94a407cc 1707 if (ret)
b767dedc 1708 qmp_usb_exit(phy);
94a407cc
DB		 1709
1710 return ret;
1711}
1712
b767dedc 1713static int qmp_usb_disable(struct phy *phy)
94a407cc
DB		 1714{
1715 int ret;
1716
b767dedc 1717 ret = qmp_usb_power_off(phy);
94a407cc
DB		 1718 if (ret)
1719 return ret;
b767dedc 1720 return qmp_usb_exit(phy);
94a407cc
DB		 1721}
1722
b767dedc 1723static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
94a407cc 1724{
2a55ec4f 1725 struct qmp_usb *qmp = phy_get_drvdata(phy);
94a407cc 1726
2a55ec4f 1727 qmp->mode = mode;
94a407cc
DB		 1728
1729 return 0;
1730}
1731
8fe2b2b7
JH		 1732static const struct phy_ops qmp_usb_phy_ops = {
1733 .init = qmp_usb_enable,
1734 .exit = qmp_usb_disable,
1735 .set_mode = qmp_usb_set_mode,
1736 .owner = THIS_MODULE,
1737};
1738
2a55ec4f 1739static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)
94a407cc 1740{
2a55ec4f
JH		 1741 const struct qmp_phy_cfg *cfg = qmp->cfg;
1742 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1743 void __iomem *pcs_misc = qmp->pcs_misc;
94a407cc
DB		 1744 u32 intr_mask;
1745
2a55ec4f
JH		 1746 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1747 qmp->mode == PHY_MODE_USB_DEVICE_SS)
94a407cc
DB		 1748 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1749 else
1750 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1751
1752 /* Clear any pending interrupts status */
fc646236 1753 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 1754 /* Writing 1 followed by 0 clears the interrupt */
fc646236 1755 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 1756
fc646236 1757 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
94a407cc
DB		 1758 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1759
1760 /* Enable required PHY autonomous mode interrupts */
fc646236 1761 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
94a407cc
DB		 1762
1763 /* Enable i/o clamp_n for autonomous mode */
1764 if (pcs_misc)
1765 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1766}
1767
2a55ec4f 1768static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
94a407cc 1769{
2a55ec4f
JH		 1770 const struct qmp_phy_cfg *cfg = qmp->cfg;
1771 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1772 void __iomem *pcs_misc = qmp->pcs_misc;
94a407cc
DB		 1773
1774 /* Disable i/o clamp_n on resume for normal mode */
1775 if (pcs_misc)
1776 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1777
fc646236 1778 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
94a407cc
DB		 1779 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1780
fc646236 1781 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 1782 /* Writing 1 followed by 0 clears the interrupt */
fc646236 1783 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc
DB		 1784}
1785
b767dedc 1786static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)
94a407cc 1787{
2a55ec4f 1788 struct qmp_usb *qmp = dev_get_drvdata(dev);
94a407cc 1789
2a55ec4f 1790 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
94a407cc 1791
2a55ec4f 1792 if (!qmp->phy->init_count) {
94a407cc
DB		 1793 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1794 return 0;
1795 }
1796
2a55ec4f 1797 qmp_usb_enable_autonomous_mode(qmp);
94a407cc 1798
2a55ec4f 1799 clk_disable_unprepare(qmp->pipe_clk);
7233090a 1800 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
94a407cc
DB		 1801
1802 return 0;
1803}
1804
b767dedc 1805static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)
94a407cc 1806{
2a55ec4f 1807 struct qmp_usb *qmp = dev_get_drvdata(dev);
94a407cc
DB		 1808 int ret = 0;
1809
2a55ec4f 1810 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
94a407cc 1811
2a55ec4f 1812 if (!qmp->phy->init_count) {
94a407cc
DB		 1813 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1814 return 0;
1815 }
1816
7233090a 1817 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
94a407cc
DB		 1818 if (ret)
1819 return ret;
1820
2a55ec4f 1821 ret = clk_prepare_enable(qmp->pipe_clk);
94a407cc
DB		 1822 if (ret) {
1823 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
7233090a 1824 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
94a407cc
DB		 1825 return ret;
1826 }
1827
2a55ec4f 1828 qmp_usb_disable_autonomous_mode(qmp);
94a407cc
DB		 1829
1830 return 0;
1831}
1832
9c9beef1
JH		 1833static const struct dev_pm_ops qmp_usb_pm_ops = {
1834 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,
1835 qmp_usb_runtime_resume, NULL)
1836};
1837
413db06c 1838static int qmp_usb_vreg_init(struct qmp_usb *qmp)
94a407cc 1839{
413db06c
JH		 1840 const struct qmp_phy_cfg *cfg = qmp->cfg;
1841 struct device *dev = qmp->dev;
94a407cc
DB		 1842 int num = cfg->num_vregs;
1843 int i;
1844
1845 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1846 if (!qmp->vregs)
1847 return -ENOMEM;
1848
1849 for (i = 0; i < num; i++)
1850 qmp->vregs[i].supply = cfg->vreg_list[i];
1851
1852 return devm_regulator_bulk_get(dev, num, qmp->vregs);
1853}
1854
fcf63482
DB		 1855static int qmp_usb_reset_init(struct qmp_usb *qmp,
1856 const char *const *reset_list,
1857 int num_resets)
94a407cc 1858{
413db06c 1859 struct device *dev = qmp->dev;
94a407cc 1860 int i;
e991c2ee 1861 int ret;
94a407cc 1862
fcf63482 1863 qmp->resets = devm_kcalloc(dev, num_resets,
94a407cc
DB		 1864 sizeof(*qmp->resets), GFP_KERNEL);
1865 if (!qmp->resets)
1866 return -ENOMEM;
1867
fcf63482
DB		 1868 for (i = 0; i < num_resets; i++)
1869 qmp->resets[i].id = reset_list[i];
1870
1871 qmp->num_resets = num_resets;
94a407cc 1872
fcf63482 1873 ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets);
e991c2ee
DB		 1874 if (ret)
1875 return dev_err_probe(dev, ret, "failed to get resets\n");
94a407cc
DB		 1876
1877 return 0;
1878}
1879
413db06c 1880static int qmp_usb_clk_init(struct qmp_usb *qmp)
94a407cc 1881{
413db06c 1882 struct device *dev = qmp->dev;
7233090a 1883 int num = ARRAY_SIZE(qmp_usb_phy_clk_l);
94a407cc
DB		 1884 int i;
1885
1886 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1887 if (!qmp->clks)
1888 return -ENOMEM;
1889
1890 for (i = 0; i < num; i++)
7233090a 1891 qmp->clks[i].id = qmp_usb_phy_clk_l[i];
94a407cc 1892
7233090a
DB		 1893 qmp->num_clks = num;
1894
1895 return devm_clk_bulk_get_optional(dev, num, qmp->clks);
94a407cc
DB		 1896}
1897
1898static void phy_clk_release_provider(void *res)
1899{
1900 of_clk_del_provider(res);
1901}
1902
1903/*
1904 * Register a fixed rate pipe clock.
1905 *
1906 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1907 * controls it. The <s>_pipe_clk coming out of the GCC is requested
1908 * by the PHY driver for its operations.
1909 * We register the <s>_pipe_clksrc here. The gcc driver takes care
1910 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
1911 * Below picture shows this relationship.
1912 *
1913 * +---------------+
1914 * | PHY block |<<---------------------------------------+
1915 * | | |
1916 * | +-------+ | +-----+ |
1917 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
1918 * clk | +-------+ | +-----+
1919 * +---------------+
1920 */
2a55ec4f 1921static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np)
94a407cc 1922{
64e1f12b 1923 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
94a407cc
DB		 1924 struct clk_init_data init = { };
1925 int ret;
1926
1927 ret = of_property_read_string(np, "clock-output-names", &init.name);
1928 if (ret) {
1929 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
1930 return ret;
1931 }
1932
94a407cc
DB		 1933 init.ops = &clk_fixed_rate_ops;
1934
1935 /* controllers using QMP phys use 125MHz pipe clock interface */
1936 fixed->fixed_rate = 125000000;
1937 fixed->hw.init = &init;
1938
1939 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
1940 if (ret)
1941 return ret;
1942
1943 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
1944 if (ret)
1945 return ret;
1946
1947 /*
1948 * Roll a devm action because the clock provider is the child node, but
1949 * the child node is not actually a device.
1950 */
1951 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
1952}
1953
a5d6b1ac
JH		 1954static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
1955 int index, bool exclusive)
1956{
1957 struct resource res;
1958
1959 if (!exclusive) {
1960 if (of_address_to_resource(np, index, &res))
1961 return IOMEM_ERR_PTR(-EINVAL);
1962
1963 return devm_ioremap(dev, res.start, resource_size(&res));
1964 }
1965
1966 return devm_of_iomap(dev, np, index, NULL);
1967}
1968
183462e8 1969static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np)
94a407cc 1970{
183462e8 1971 struct platform_device *pdev = to_platform_device(qmp->dev);
413db06c
JH		 1972 const struct qmp_phy_cfg *cfg = qmp->cfg;
1973 struct device *dev = qmp->dev;
a5d6b1ac 1974 bool exclusive = true;
7233090a 1975 int ret;
183462e8
JH		 1976
1977 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
1978 if (IS_ERR(qmp->serdes))
1979 return PTR_ERR(qmp->serdes);
1980
a5d6b1ac
JH		 1981 /*
1982 * FIXME: These bindings should be fixed to not rely on overlapping
1983 * mappings for PCS.
1984 */
1985 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
1986 exclusive = false;
1987 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
1988 exclusive = false;
1989
94a407cc 1990 /*
8d3bf724 1991 * Get memory resources for the PHY:
94a407cc
DB		 1992 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
1993 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
1994 * For single lane PHYs: pcs_misc (optional) -> 3.
1995 */
2a55ec4f
JH		 1996 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
1997 if (IS_ERR(qmp->tx))
1998 return PTR_ERR(qmp->tx);
94a407cc 1999
2a55ec4f
JH		 2000 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2001 if (IS_ERR(qmp->rx))
2002 return PTR_ERR(qmp->rx);
94a407cc 2003
2a55ec4f
JH		 2004 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
2005 if (IS_ERR(qmp->pcs))
2006 return PTR_ERR(qmp->pcs);
94a407cc 2007
fc646236 2008 if (cfg->pcs_usb_offset)
2a55ec4f 2009 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
fc646236 2010
a73a19ea 2011 if (cfg->lanes >= 2) {
2a55ec4f
JH		 2012 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2013 if (IS_ERR(qmp->tx2))
2014 return PTR_ERR(qmp->tx2);
94a407cc 2015
2a55ec4f
JH		 2016 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2017 if (IS_ERR(qmp->rx2))
2018 return PTR_ERR(qmp->rx2);
94a407cc 2019
2a55ec4f 2020 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
94a407cc 2021 } else {
2a55ec4f 2022 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
94a407cc
DB		 2023 }
2024
2a55ec4f 2025 if (IS_ERR(qmp->pcs_misc)) {
94a407cc 2026 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2a55ec4f 2027 qmp->pcs_misc = NULL;
a5d6b1ac 2028 }
94a407cc 2029
2a55ec4f
JH		 2030 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
2031 if (IS_ERR(qmp->pipe_clk)) {
2032 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2033 "failed to get pipe clock\n");
94a407cc
DB		 2034 }
2035
7233090a
DB		 2036 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
2037 if (ret < 0)
2038 return ret;
2039
2040 qmp->num_clks = ret;
2041
fcf63482
DB		 2042 ret = qmp_usb_reset_init(qmp, usb3phy_legacy_reset_l,
2043 ARRAY_SIZE(usb3phy_legacy_reset_l));
2044 if (ret)
2045 return ret;
2046
94a407cc
DB		 2047 return 0;
2048}
2049
c0a6c252
JH		 2050static int qmp_usb_parse_dt(struct qmp_usb *qmp)
2051{
2052 struct platform_device *pdev = to_platform_device(qmp->dev);
2053 const struct qmp_phy_cfg *cfg = qmp->cfg;
2054 const struct qmp_usb_offsets *offs = cfg->offsets;
2055 struct device *dev = qmp->dev;
2056 void __iomem *base;
7233090a 2057 int ret;
c0a6c252
JH		 2058
2059 if (!offs)
2060 return -EINVAL;
2061
2062 base = devm_platform_ioremap_resource(pdev, 0);
2063 if (IS_ERR(base))
2064 return PTR_ERR(base);
2065
2066 qmp->serdes = base + offs->serdes;
2067 qmp->pcs = base + offs->pcs;
1178c93c 2068 qmp->pcs_misc = base + offs->pcs_misc;
c0a6c252
JH		 2069 qmp->pcs_usb = base + offs->pcs_usb;
2070 qmp->tx = base + offs->tx;
2071 qmp->rx = base + offs->rx;
2072
1178c93c
BS		 2073 if (cfg->lanes >= 2) {
2074 qmp->tx2 = base + offs->tx2;
2075 qmp->rx2 = base + offs->rx2;
2076 }
2077
7233090a
DB		 2078 ret = qmp_usb_clk_init(qmp);
2079 if (ret)
2080 return ret;
2081
c0a6c252
JH		 2082 qmp->pipe_clk = devm_clk_get(dev, "pipe");
2083 if (IS_ERR(qmp->pipe_clk)) {
2084 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2085 "failed to get pipe clock\n");
2086 }
2087
fcf63482
DB		 2088 ret = qmp_usb_reset_init(qmp, usb3phy_reset_l,
2089 ARRAY_SIZE(usb3phy_reset_l));
2090 if (ret)
2091 return ret;
2092
c0a6c252
JH		 2093 return 0;
2094}
2095
b767dedc 2096static int qmp_usb_probe(struct platform_device *pdev)
94a407cc 2097{
94a407cc 2098 struct device *dev = &pdev->dev;
94a407cc 2099 struct phy_provider *phy_provider;
c0a6c252 2100 struct device_node *np;
2a55ec4f 2101 struct qmp_usb *qmp;
94a407cc
DB		 2102 int ret;
2103
2104 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2105 if (!qmp)
2106 return -ENOMEM;
2107
2108 qmp->dev = dev;
94a407cc 2109
413db06c
JH		 2110 qmp->cfg = of_device_get_match_data(dev);
2111 if (!qmp->cfg)
8c924330 2112 return -EINVAL;
94a407cc 2113
413db06c 2114 ret = qmp_usb_vreg_init(qmp);
add7000b 2115 if (ret)
28d74fc3 2116 return ret;
94a407cc 2117
c0a6c252
JH		 2118 /* Check for legacy binding with child node. */
2119 np = of_get_next_available_child(dev->of_node, NULL);
2120 if (np) {
2121 ret = qmp_usb_parse_dt_legacy(qmp, np);
2122 } else {
2123 np = of_node_get(dev->of_node);
2124 ret = qmp_usb_parse_dt(qmp);
2125 }
2126 if (ret)
2127 goto err_node_put;
94a407cc 2128
94a407cc 2129 pm_runtime_set_active(dev);
e57655e6
JH		 2130 ret = devm_pm_runtime_enable(dev);
2131 if (ret)
8ec02ba8 2132 goto err_node_put;
94a407cc
DB		 2133 /*
2134 * Prevent runtime pm from being ON by default. Users can enable
2135 * it using power/control in sysfs.
2136 */
2137 pm_runtime_forbid(dev);
2138
c0a6c252 2139 ret = phy_pipe_clk_register(qmp, np);
8ec02ba8
JH		 2140 if (ret)
2141 goto err_node_put;
2142
c0a6c252 2143 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops);
183462e8
JH		 2144 if (IS_ERR(qmp->phy)) {
2145 ret = PTR_ERR(qmp->phy);
2146 dev_err(dev, "failed to create PHY: %d\n", ret);
2147 goto err_node_put;
2148 }
2149
2150 phy_set_drvdata(qmp->phy, qmp);
2151
c0a6c252 2152 of_node_put(np);
94a407cc
DB		 2153
2154 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
94a407cc
DB		 2155
2156 return PTR_ERR_OR_ZERO(phy_provider);
2157
2158err_node_put:
c0a6c252 2159 of_node_put(np);
94a407cc
DB		 2160 return ret;
2161}
2162
95dd63b8
JH		 2163static const struct of_device_id qmp_usb_of_match_table[] = {
2164 {
2165 .compatible = "qcom,ipq6018-qmp-usb3-phy",
2166 .data = &ipq8074_usb3phy_cfg,
2167 }, {
2168 .compatible = "qcom,ipq8074-qmp-usb3-phy",
2169 .data = &ipq8074_usb3phy_cfg,
2170 }, {
a8874ada
VN		 2171 .compatible = "qcom,ipq9574-qmp-usb3-phy",
2172 .data = &ipq9574_usb3phy_cfg,
2173 }, {
95dd63b8
JH		 2174 .compatible = "qcom,msm8996-qmp-usb3-phy",
2175 .data = &msm8996_usb3phy_cfg,
2176 }, {
2177 .compatible = "qcom,msm8998-qmp-usb3-phy",
2178 .data = &msm8998_usb3phy_cfg,
2179 }, {
2180 .compatible = "qcom,qcm2290-qmp-usb3-phy",
2181 .data = &qcm2290_usb3phy_cfg,
8bd2d6e1
SH		 2182 }, {
2183 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy",
2184 .data = &sa8775p_usb3_uniphy_cfg,
95dd63b8
JH		 2185 }, {
2186 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
2187 .data = &sc8280xp_usb3_uniphy_cfg,
95dd63b8
JH		 2188 }, {
2189 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2190 .data = &qmp_v3_usb3_uniphy_cfg,
2191 }, {
2192 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2193 .data = &sdx55_usb3_uniphy_cfg,
2194 }, {
2195 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2196 .data = &sdx65_usb3_uniphy_cfg,
2197 }, {
724dbe3c
BS		 2198 .compatible = "qcom,sm6115-qmp-usb3-phy",
2199 .data = &qcm2290_usb3phy_cfg,
95dd63b8
JH		 2200 }, {
2201 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2202 .data = &sm8150_usb3_uniphy_cfg,
95dd63b8
JH		 2203 }, {
2204 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2205 .data = &sm8250_usb3_uniphy_cfg,
95dd63b8
JH		 2206 }, {
2207 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2208 .data = &sm8350_usb3_uniphy_cfg,
95dd63b8
JH		 2209 },
2210 { },
2211};
2212MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);
2213
b767dedc
JH		 2214static struct platform_driver qmp_usb_driver = {
2215 .probe = qmp_usb_probe,
94a407cc 2216 .driver = {
8c924330 2217 .name = "qcom-qmp-usb-phy",
b767dedc
JH		 2218 .pm = &qmp_usb_pm_ops,
2219 .of_match_table = qmp_usb_of_match_table,
94a407cc
DB		 2220 },
2221};
2222
b767dedc 2223module_platform_driver(qmp_usb_driver);
94a407cc
DB		 2224
2225MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
8c924330 2226MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
94a407cc 2227MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)