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phy: qcom-qmp-ufs: Use dev_err_probe() to simplify code
[linux-2.6-block.git] / drivers / phy / qualcomm / phy-qcom-qmp-usb.c
CommitLineData
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DB		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#include <dt-bindings/phy/phy.h>
24
25#include "phy-qcom-qmp.h"
26
27/* QPHY_SW_RESET bit */
28#define SW_RESET BIT(0)
29/* QPHY_POWER_DOWN_CONTROL */
30#define SW_PWRDN BIT(0)
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DB		 31/* QPHY_START_CONTROL bits */
32#define SERDES_START BIT(0)
33#define PCS_START BIT(1)
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DB		 34/* QPHY_PCS_STATUS bit */
35#define PHYSTATUS BIT(6)
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DB		 36
37/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
38/* DP PHY soft reset */
39#define SW_DPPHY_RESET BIT(0)
40/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
41#define SW_DPPHY_RESET_MUX BIT(1)
42/* USB3 PHY soft reset */
43#define SW_USB3PHY_RESET BIT(2)
44/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
45#define SW_USB3PHY_RESET_MUX BIT(3)
46
47/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
48#define USB3_MODE BIT(0) /* enables USB3 mode */
49#define DP_MODE BIT(1) /* enables DP mode */
50
51/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
52#define ARCVR_DTCT_EN BIT(0)
53#define ALFPS_DTCT_EN BIT(1)
54#define ARCVR_DTCT_EVENT_SEL BIT(4)
55
56/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
57#define IRQ_CLEAR BIT(0)
58
59/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
60#define RCVR_DETECT BIT(0)
61
62/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
63#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
64
65#define PHY_INIT_COMPLETE_TIMEOUT 10000
66#define POWER_DOWN_DELAY_US_MIN 10
67#define POWER_DOWN_DELAY_US_MAX 11
68
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DB		 69struct qmp_phy_init_tbl {
70 unsigned int offset;
71 unsigned int val;
72 /*
73 * register part of layout ?
74 * if yes, then offset gives index in the reg-layout
75 */
76 bool in_layout;
77 /*
78 * mask of lanes for which this register is written
79 * for cases when second lane needs different values
80 */
81 u8 lane_mask;
82};
83
84#define QMP_PHY_INIT_CFG(o, v) \
85 { \
86 .offset = o, \
87 .val = v, \
88 .lane_mask = 0xff, \
89 }
90
91#define QMP_PHY_INIT_CFG_L(o, v) \
92 { \
93 .offset = o, \
94 .val = v, \
95 .in_layout = true, \
96 .lane_mask = 0xff, \
97 }
98
99#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
100 { \
101 .offset = o, \
102 .val = v, \
103 .lane_mask = l, \
104 }
105
106/* set of registers with offsets different per-PHY */
107enum qphy_reg_layout {
94a407cc 108 /* PCS registers */
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DB		 109 QPHY_SW_RESET,
110 QPHY_START_CTRL,
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DB		 111 QPHY_PCS_STATUS,
112 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
113 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
114 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
115 QPHY_PCS_POWER_DOWN_CONTROL,
116 /* PCS_MISC registers */
117 QPHY_PCS_MISC_TYPEC_CTRL,
118 /* Keep last to ensure regs_layout arrays are properly initialized */
119 QPHY_LAYOUT_SIZE
120};
121
94a407cc 122static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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DB		 123 [QPHY_SW_RESET] = 0x00,
124 [QPHY_START_CTRL] = 0x08,
125 [QPHY_PCS_STATUS] = 0x17c,
126 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
127 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
128 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
129};
130
131static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
132 [QPHY_SW_RESET] = 0x00,
133 [QPHY_START_CTRL] = 0x08,
134 [QPHY_PCS_STATUS] = 0x174,
135 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
136 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
137 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
138};
139
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DB		 140static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
141 [QPHY_SW_RESET] = 0x00,
142 [QPHY_START_CTRL] = 0x44,
143 [QPHY_PCS_STATUS] = 0x14,
144 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
94a407cc 145
fc646236
DB		 146 /* In PCS_USB */
147 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
148 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
94a407cc
DB		 149};
150
151static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
152 [QPHY_SW_RESET] = 0x00,
153 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
154 [QPHY_START_CTRL] = 0x08,
155 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
156 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
157 [QPHY_PCS_STATUS] = 0x174,
158 [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
159};
160
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DB		 161static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
162 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
163 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
164 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
165 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
166 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
167 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
168 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
169 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
170 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
171 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
172 /* PLL and Loop filter settings */
173 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
174 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
175 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
176 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
177 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
178 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
179 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
180 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
181 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
182 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
183 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
184 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
185 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
186 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
187 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
188 /* SSC settings */
189 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
190 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
191 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
192 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
193 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
194 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
195 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
196};
197
198static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
199 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
200 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
201 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
202 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
203 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
204 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
205 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
206 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
207 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
208};
209
210static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
212 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
215 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
216 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
217 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
218 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
219 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
220 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
221 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
222 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
223 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
224 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
225 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
226 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
227 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
228 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
229 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
230 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
231 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
232 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
233 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
234};
235
94a407cc
DB		 236static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
237 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
238 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
239 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
240 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
241 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
242 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
243 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
244 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
245 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
246 /* PLL and Loop filter settings */
247 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
248 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
249 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
250 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
251 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
252 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
253 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
254 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
255 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
256 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
257 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
258 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
259 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
260 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
261 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
262 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
263 /* SSC settings */
264 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
265 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
266 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
267 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
268 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
269 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
270 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
271};
272
273static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
274 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
275 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
276 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
277};
278
279static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
280 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
281 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
282 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
283 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
284 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
285 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
286 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
287 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
288 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
289 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
290};
291
292static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
293 /* FLL settings */
d36e341a
DB		 294 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
295 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
296 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
297 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
298 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
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DB		 299
300 /* Lock Det settings */
6cad2983
DB		 301 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
302 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
303 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
304 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
94a407cc
DB		 305};
306
94a407cc
DB		 307static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
319 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
320 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
321 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
325 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
326 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
327 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
328 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
329 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
330 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
331 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
332 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
333 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
334 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
335 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
336 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
337 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
338 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
339 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
340 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
341 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
342 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
343 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
344};
345
346static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
347 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
348 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
349 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
350 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
351 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
352};
353
94a407cc
DB		 354static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
355 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
356 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
357 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
358 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
359 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
360 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
361 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
362 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
363 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
364};
365
366static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
367 /* FLL settings */
368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
373
374 /* Lock Det settings */
375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
379
380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
399
400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
404 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
406 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
407 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
408 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
409 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
410 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
411};
412
413static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
438 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
439 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
440 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
443 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
444 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
445 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
446 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
447 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
448 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
449 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
450};
451
452static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
453 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
454 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
455 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
456 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
457 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
458};
459
460static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
461 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
462 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
463 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
464 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
465 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
466 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
467 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
468 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
469 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
470 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
471 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
472};
473
474static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
475 /* FLL settings */
476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
481
482 /* Lock Det settings */
483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
487
488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
500 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
501 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
503 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
504 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
505 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
506 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
507
508 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
509 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
510 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
511 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
512 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
513 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
514 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
515 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
516 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
517 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
518 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
519
520 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
521 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
522};
523
94a407cc
DB		 524static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
556 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
557 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
558 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
559 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
560 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
561 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
562 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
563};
564
565static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
566 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
567 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
568 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
569 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
570};
571
572static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
578 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
579 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
580 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
581 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
582 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
583 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
584 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
585 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
586 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
587 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
588 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
589 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
590};
591
592static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
fc270d13 610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
94a407cc
DB		 611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
612 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
613 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
614 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
615 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
616 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
617 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
618 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
619 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
620 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
621 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
622 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
623 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
624 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
625 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
626 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
627 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
628 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
629 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
630 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
631};
632
94a407cc
DB		 633static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
652 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
653 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
654 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
655 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
656 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
657 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
658 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
659 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
660 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
661 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
662 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
663 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
664 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
665 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
666 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
667 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
668 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
669 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
670 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
671 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
672 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
673 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
674};
675
676static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
677 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
678 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
679 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
680 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
681 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
682};
683
684static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
708 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
709 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
710 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
711 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
712 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
713 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
714 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
715 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
716 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
717 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
718 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
719 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
720 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
721};
722
723static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
724 /* Lock Det settings */
725 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
726 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
727 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
728
729 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
730 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
731 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
732 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
733 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
734 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
735 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
736 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
fc646236
DB		 737};
738
739static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
94a407cc
DB		 740 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
741 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
742};
743
744static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
776 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
780 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
781 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
782 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
783 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
784 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
785};
786
787static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
788 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
789 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
790 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
791 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
792};
793
794static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
822 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
823 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
824 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
825 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
826 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
827 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
828 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
829 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
830 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
831};
832
833static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
834 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
835 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
836 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
837 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
838 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
839 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
840 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
94a407cc
DB		 841 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
842 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
843 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
844 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
845 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
846 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
847 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
848};
849
fc646236
DB		 850static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
851 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
852 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
853};
854
94a407cc
DB		 855static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
856 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
857 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
858 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
859 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
860 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
861 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
862 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
863 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
864};
865
866static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
868 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
869 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
870 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
871 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
872 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
873 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
874 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
875 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
876 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
877 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
878 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
879 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
880 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
881 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
882 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
883 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
884 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
885 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
886 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
887 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
888 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
889 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
890 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
891 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
892 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
893 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
894 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
895 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
896 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
897 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
898 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
899 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
900 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
901 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
902 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
903 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
904 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
905};
906
907static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
908 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
909 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
910 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
911 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
912 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
913 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
914 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
915 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
916 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
917 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
918 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
919 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
fc646236
DB		 920};
921
922static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
94a407cc
DB		 923 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
924 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
925};
926
927static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
928 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
929 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
930 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
931 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
932 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
933 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
934};
935
936static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
943 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
944 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
948 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
949 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
950 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
951 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
952 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
953 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
8c924330 954 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
94a407cc 955 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
8c924330
DB		 956 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
957 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
958 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
959 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
94a407cc 960 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
8c924330 961 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
94a407cc 962 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
8c924330
DB		 963 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
964 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
965 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
966 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
967 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
968 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
94a407cc 969 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
8c924330
DB		 970 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
971 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
972 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
94a407cc
DB		 973};
974
8c924330
DB		 975static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
976 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
977 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
978 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
979 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
980 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
981 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
982 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
983 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
8c924330
DB		 984 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
985 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
986 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
987 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
988 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
989 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
94a407cc
DB		 990};
991
fc646236
DB		 992static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
993 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
994 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
995};
996
94a407cc
DB		 997static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
998 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
999 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1000 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
1001 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1002 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
1003};
1004
1005static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
1006 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
1007 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1008 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
1009 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
1010 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
1011 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1012 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1013 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1014 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1015 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1016 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1017 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
1018 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1019 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
1020 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
1021 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1022 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1023 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1024 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1025 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
1026 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1027 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1028 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1029 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1030 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1031 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1032 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1033 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1034 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1035 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1036 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1037 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1038 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1039 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1040 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1041 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1042};
1043
94a407cc
DB		 1044static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
1045 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1046 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1047 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1048 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1049 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1050 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1051 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
1052};
1053
1054static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
1055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
1056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1058 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1059 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1060 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1061 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1062 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1063 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1064 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1065 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1066 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1067 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1068 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1069 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1070 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1071 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1072 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1073 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1074 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1075 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1076 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1077 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1078 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1079 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1080 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1081 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1082 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1083 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1084 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1085 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1086};
1087
94a407cc
DB		 1088static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
1089 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
1090 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
1091 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
1092 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1093 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
1094 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1095 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
1096 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
1097 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
1098 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1099};
1100
1101static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
1102 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1103 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1104 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1105 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1106 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1107 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1108 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1109 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1110 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1111 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1112 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1113 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1114 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1115 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1116 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1117 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1118 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1119 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1120 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1121 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1122 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1123 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
1124 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
1125 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
1126 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
1127 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
1128 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
1129 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1130 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1131 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
1132 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
1133 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1134 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
1135 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1136 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1137 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
1138 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1139 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
1140};
1141
1142static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
94a407cc
DB		 1143 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1144 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1145 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1146 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1147 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1148 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1149 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1150 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1151 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1152 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1153 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1154 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1155 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1156 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
fc646236
DB		 1157};
1158
1159static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
1160 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
1161 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
94a407cc
DB		 1162 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1163 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1164};
1165
1166static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
1167 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1168 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1169 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1170 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1171 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1172 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1173 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1174};
1175
1176static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
1177 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1178 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1179 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1180 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1181 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1182 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1183 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1184 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1185 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1186 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1187 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1188 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1189 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1190 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1191 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1192 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1193 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1194 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1195 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1196 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1197 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1198 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1199 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1200 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1201 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1202 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1203 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1204 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1205 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1206 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1207 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1208};
1209
1210static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
1211 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1212 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1213 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1214 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1215 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1216 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1217 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1218 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
94a407cc
DB		 1219 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1220 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1221 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1222 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1223 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1224 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1225};
1226
fc646236
DB		 1227static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
1228 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1229 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1230};
1231
94a407cc
DB		 1232static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
1233 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
1234 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1235 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
1236 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
1237 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
1238 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
1239 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
1240 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
1241 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
1242 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
1243 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
1244 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
1245 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
1246 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
1247 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
1248 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
1249 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
1250 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1251 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
1252 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
1253 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
1254 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
1255 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
1256 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
1257 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
1258 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
1259 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
1260 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
1261 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
1262 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
1263 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
1264 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
1265 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
1266 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
1267 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
1268 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
1269 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
1270 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
1271};
1272
1273static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
1274 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1275 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1276 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1277 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1278 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
1279};
1280
1281static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
1282 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1283 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
1284 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1285 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1286 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1287 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1288 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1289 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
1290 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1291 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1292 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1293 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1294 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
1295 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1296 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1297 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1298 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
1299};
1300
1301static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
1302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
1304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
1305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
1310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
1323};
1324
c0c7769c
BA		 1325static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
1326 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1327 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1328 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1329 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1330 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),
1331 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),
1332 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),
1333 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1334 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1335 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1336 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1337 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1338 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1339 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1340 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1341 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1342 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1343 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),
1344 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),
1345 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1346 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),
1347 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1348 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),
1349 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1350 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1351 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1352 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1353 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1354 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1355 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1356 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1357 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1358 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1359 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1360 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1361 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1362 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1363 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1364 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1365};
1366
1367static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
1368 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1369 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1370 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1371 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1372 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1373 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1374 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1375};
1376
1377static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
1378 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1379 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1380 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1381 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1382 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1383 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1384 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1385 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1386 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1387 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1388 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1389 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1390 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1391 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1392 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1393 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1394 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1395 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1396 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a),
1397 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1398 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1399 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1400 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1401 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1402 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1403 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1404 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1405 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1406 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1407 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1408 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1409};
1410
1411static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
1412 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1413 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1414 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1415 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1416 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1417 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1418 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1419 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1420 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1421 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1422 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1423 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1424 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1425 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1426 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1427 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1428};
1429
94a407cc
DB		 1430/* struct qmp_phy_cfg - per-PHY initialization config */
1431struct qmp_phy_cfg {
a73a19ea 1432 int lanes;
94a407cc
DB		 1433
1434 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1435 const struct qmp_phy_init_tbl *serdes_tbl;
1436 int serdes_tbl_num;
94a407cc
DB		 1437 const struct qmp_phy_init_tbl *tx_tbl;
1438 int tx_tbl_num;
94a407cc
DB		 1439 const struct qmp_phy_init_tbl *rx_tbl;
1440 int rx_tbl_num;
94a407cc
DB		 1441 const struct qmp_phy_init_tbl *pcs_tbl;
1442 int pcs_tbl_num;
fc646236
DB		 1443 const struct qmp_phy_init_tbl *pcs_usb_tbl;
1444 int pcs_usb_tbl_num;
94a407cc
DB		 1445
1446 /* clock ids to be requested */
1447 const char * const *clk_list;
1448 int num_clks;
1449 /* resets to be requested */
1450 const char * const *reset_list;
1451 int num_resets;
1452 /* regulators to be requested */
1453 const char * const *vreg_list;
1454 int num_vregs;
1455
1456 /* array of registers with different offsets */
1457 const unsigned int *regs;
1458
1459 unsigned int start_ctrl;
1460 unsigned int pwrdn_ctrl;
94a407cc
DB		 1461 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
1462 unsigned int phy_status;
1463
94a407cc
DB		 1464 /* true, if PHY needs delay after POWER_DOWN */
1465 bool has_pwrdn_delay;
1466 /* power_down delay in usec */
1467 int pwrdn_delay_min;
1468 int pwrdn_delay_max;
1469
1470 /* true, if PHY has a separate DP_COM control block */
1471 bool has_phy_dp_com_ctrl;
fc646236
DB		 1472
1473 /* Offset from PCS to PCS_USB region */
1474 unsigned int pcs_usb_offset;
94a407cc
DB		 1475};
1476
1477/**
1478 * struct qmp_phy - per-lane phy descriptor
1479 *
1480 * @phy: generic phy
1481 * @cfg: phy specific configuration
1482 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
1483 * @tx: iomapped memory space for lane's tx
1484 * @rx: iomapped memory space for lane's rx
1485 * @pcs: iomapped memory space for lane's pcs
1486 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
1487 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
1488 * @pcs_misc: iomapped memory space for lane's pcs_misc
fc646236 1489 * @pcs_usb: iomapped memory space for lane's pcs_usb
94a407cc 1490 * @pipe_clk: pipe clock
94a407cc 1491 * @qmp: QMP phy to which this lane belongs
94a407cc 1492 * @mode: current PHY mode
94a407cc
DB		 1493 */
1494struct qmp_phy {
1495 struct phy *phy;
1496 const struct qmp_phy_cfg *cfg;
1497 void __iomem *serdes;
1498 void __iomem *tx;
1499 void __iomem *rx;
1500 void __iomem *pcs;
1501 void __iomem *tx2;
1502 void __iomem *rx2;
1503 void __iomem *pcs_misc;
fc646236 1504 void __iomem *pcs_usb;
94a407cc 1505 struct clk *pipe_clk;
94a407cc 1506 struct qcom_qmp *qmp;
94a407cc 1507 enum phy_mode mode;
94a407cc
DB		 1508};
1509
1510/**
1511 * struct qcom_qmp - structure holding QMP phy block attributes
1512 *
1513 * @dev: device
1514 * @dp_com: iomapped memory space for phy's dp_com control block
1515 *
1516 * @clks: array of clocks required by phy
1517 * @resets: array of resets required by phy
1518 * @vregs: regulator supplies bulk data
1519 *
1520 * @phys: array of per-lane phy descriptors
94a407cc
DB		 1521 */
1522struct qcom_qmp {
1523 struct device *dev;
1524 void __iomem *dp_com;
1525
1526 struct clk_bulk_data *clks;
e991c2ee 1527 struct reset_control_bulk_data *resets;
94a407cc
DB		 1528 struct regulator_bulk_data *vregs;
1529
1530 struct qmp_phy **phys;
94a407cc
DB		 1531};
1532
94a407cc
DB		 1533static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1534{
1535 u32 reg;
1536
1537 reg = readl(base + offset);
1538 reg |= val;
1539 writel(reg, base + offset);
1540
1541 /* ensure that above write is through */
1542 readl(base + offset);
1543}
1544
1545static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1546{
1547 u32 reg;
1548
1549 reg = readl(base + offset);
1550 reg &= ~val;
1551 writel(reg, base + offset);
1552
1553 /* ensure that above write is through */
1554 readl(base + offset);
1555}
1556
1557/* list of clocks required by phy */
1558static const char * const msm8996_phy_clk_l[] = {
1559 "aux", "cfg_ahb", "ref",
1560};
1561
94a407cc
DB		 1562static const char * const qmp_v3_phy_clk_l[] = {
1563 "aux", "cfg_ahb", "ref", "com_aux",
1564};
1565
94a407cc
DB		 1566static const char * const qmp_v4_phy_clk_l[] = {
1567 "aux", "ref_clk_src", "ref", "com_aux",
1568};
1569
1570/* the primary usb3 phy on sm8250 doesn't have a ref clock */
1571static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
1572 "aux", "ref_clk_src", "com_aux"
1573};
1574
94a407cc
DB		 1575/* usb3 phy on sdx55 doesn't have com_aux clock */
1576static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
1577 "aux", "cfg_ahb", "ref"
1578};
1579
1580static const char * const qcm2290_usb3phy_clk_l[] = {
1581 "cfg_ahb", "ref", "com_aux",
1582};
1583
1584/* list of resets */
94a407cc
DB		 1585static const char * const msm8996_usb3phy_reset_l[] = {
1586 "phy", "common",
1587};
1588
1589static const char * const sc7180_usb3phy_reset_l[] = {
1590 "phy",
1591};
1592
1593static const char * const qcm2290_usb3phy_reset_l[] = {
1594 "phy_phy", "phy",
1595};
1596
94a407cc
DB		 1597/* list of regulators */
1598static const char * const qmp_phy_vreg_l[] = {
1599 "vdda-phy", "vdda-pll",
1600};
1601
1602static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
a73a19ea 1603 .lanes = 1,
94a407cc
DB		 1604
1605 .serdes_tbl = ipq8074_usb3_serdes_tbl,
1606 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1607 .tx_tbl = msm8996_usb3_tx_tbl,
1608 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1609 .rx_tbl = ipq8074_usb3_rx_tbl,
1610 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1611 .pcs_tbl = ipq8074_usb3_pcs_tbl,
1612 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1613 .clk_list = msm8996_phy_clk_l,
1614 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1615 .reset_list = msm8996_usb3phy_reset_l,
1616 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1617 .vreg_list = qmp_phy_vreg_l,
1618 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1619 .regs = usb3phy_regs_layout,
1620
1621 .start_ctrl = SERDES_START | PCS_START,
1622 .pwrdn_ctrl = SW_PWRDN,
1623 .phy_status = PHYSTATUS,
1624};
1625
94a407cc 1626static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
a73a19ea 1627 .lanes = 1,
94a407cc
DB		 1628
1629 .serdes_tbl = msm8996_usb3_serdes_tbl,
1630 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1631 .tx_tbl = msm8996_usb3_tx_tbl,
1632 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1633 .rx_tbl = msm8996_usb3_rx_tbl,
1634 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1635 .pcs_tbl = msm8996_usb3_pcs_tbl,
1636 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1637 .clk_list = msm8996_phy_clk_l,
1638 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1639 .reset_list = msm8996_usb3phy_reset_l,
1640 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1641 .vreg_list = qmp_phy_vreg_l,
1642 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1643 .regs = usb3phy_regs_layout,
1644
1645 .start_ctrl = SERDES_START | PCS_START,
1646 .pwrdn_ctrl = SW_PWRDN,
1647 .phy_status = PHYSTATUS,
1648};
1649
94a407cc 1650static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
a73a19ea 1651 .lanes = 2,
94a407cc
DB		 1652
1653 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1654 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1655 .tx_tbl = qmp_v3_usb3_tx_tbl,
1656 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1657 .rx_tbl = qmp_v3_usb3_rx_tbl,
1658 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1659 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1660 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1661 .clk_list = qmp_v3_phy_clk_l,
1662 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1663 .reset_list = msm8996_usb3phy_reset_l,
1664 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1665 .vreg_list = qmp_phy_vreg_l,
1666 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1667 .regs = qmp_v3_usb3phy_regs_layout,
1668
1669 .start_ctrl = SERDES_START | PCS_START,
1670 .pwrdn_ctrl = SW_PWRDN,
1671 .phy_status = PHYSTATUS,
1672
1673 .has_pwrdn_delay = true,
1674 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1675 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1676
1677 .has_phy_dp_com_ctrl = true,
94a407cc
DB		 1678};
1679
1680static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
a73a19ea 1681 .lanes = 2,
94a407cc
DB		 1682
1683 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1684 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1685 .tx_tbl = qmp_v3_usb3_tx_tbl,
1686 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1687 .rx_tbl = qmp_v3_usb3_rx_tbl,
1688 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1689 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1690 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1691 .clk_list = qmp_v3_phy_clk_l,
1692 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1693 .reset_list = sc7180_usb3phy_reset_l,
1694 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
1695 .vreg_list = qmp_phy_vreg_l,
1696 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1697 .regs = qmp_v3_usb3phy_regs_layout,
1698
1699 .start_ctrl = SERDES_START | PCS_START,
1700 .pwrdn_ctrl = SW_PWRDN,
1701 .phy_status = PHYSTATUS,
1702
1703 .has_pwrdn_delay = true,
1704 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1705 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1706
1707 .has_phy_dp_com_ctrl = true,
94a407cc
DB		 1708};
1709
c0c7769c 1710static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
a73a19ea 1711 .lanes = 1,
c0c7769c
BA		 1712
1713 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1714 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1715 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
1716 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1717 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
1718 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1719 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl,
1720 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
1721 .clk_list = qmp_v4_phy_clk_l,
1722 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1723 .reset_list = msm8996_usb3phy_reset_l,
1724 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1725 .vreg_list = qmp_phy_vreg_l,
1726 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1727 .regs = qmp_v4_usb3phy_regs_layout,
1728
1729 .start_ctrl = SERDES_START | PCS_START,
1730 .pwrdn_ctrl = SW_PWRDN,
1731 .phy_status = PHYSTATUS,
1732
1733 .has_pwrdn_delay = true,
1734 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1735 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1736};
1737
94a407cc 1738static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
a73a19ea 1739 .lanes = 1,
94a407cc
DB		 1740
1741 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
1742 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1743 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
1744 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1745 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
1746 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1747 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
1748 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1749 .clk_list = qmp_v3_phy_clk_l,
1750 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1751 .reset_list = msm8996_usb3phy_reset_l,
1752 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1753 .vreg_list = qmp_phy_vreg_l,
1754 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1755 .regs = qmp_v3_usb3phy_regs_layout,
1756
1757 .start_ctrl = SERDES_START | PCS_START,
1758 .pwrdn_ctrl = SW_PWRDN,
1759 .phy_status = PHYSTATUS,
1760
1761 .has_pwrdn_delay = true,
1762 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1763 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1764};
1765
94a407cc 1766static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
a73a19ea 1767 .lanes = 2,
94a407cc
DB		 1768
1769 .serdes_tbl = msm8998_usb3_serdes_tbl,
1770 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1771 .tx_tbl = msm8998_usb3_tx_tbl,
1772 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1773 .rx_tbl = msm8998_usb3_rx_tbl,
1774 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1775 .pcs_tbl = msm8998_usb3_pcs_tbl,
1776 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1777 .clk_list = msm8996_phy_clk_l,
1778 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1779 .reset_list = msm8996_usb3phy_reset_l,
1780 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1781 .vreg_list = qmp_phy_vreg_l,
1782 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
8c924330 1783 .regs = qmp_v3_usb3phy_regs_layout,
94a407cc 1784
8c924330
DB		 1785 .start_ctrl = SERDES_START | PCS_START,
1786 .pwrdn_ctrl = SW_PWRDN,
94a407cc 1787 .phy_status = PHYSTATUS,
94a407cc
DB		 1788};
1789
1790static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
a73a19ea 1791 .lanes = 2,
94a407cc
DB		 1792
1793 .serdes_tbl = sm8150_usb3_serdes_tbl,
1794 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1795 .tx_tbl = sm8150_usb3_tx_tbl,
1796 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
1797 .rx_tbl = sm8150_usb3_rx_tbl,
1798 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
1799 .pcs_tbl = sm8150_usb3_pcs_tbl,
1800 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
fc646236
DB		 1801 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
1802 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
94a407cc
DB		 1803 .clk_list = qmp_v4_phy_clk_l,
1804 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1805 .reset_list = msm8996_usb3phy_reset_l,
1806 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1807 .vreg_list = qmp_phy_vreg_l,
1808 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1809 .regs = qmp_v4_usb3phy_regs_layout,
fc646236 1810 .pcs_usb_offset = 0x300,
94a407cc
DB		 1811
1812 .start_ctrl = SERDES_START | PCS_START,
1813 .pwrdn_ctrl = SW_PWRDN,
1814 .phy_status = PHYSTATUS,
1815
1816
1817 .has_pwrdn_delay = true,
1818 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1819 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1820
1821 .has_phy_dp_com_ctrl = true,
94a407cc
DB		 1822};
1823
94a407cc 1824static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
a73a19ea 1825 .lanes = 1,
94a407cc
DB		 1826
1827 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1828 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1829 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
1830 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1831 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
1832 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1833 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
1834 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
fc646236
DB		 1835 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl,
1836 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1837 .clk_list = qmp_v4_phy_clk_l,
1838 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1839 .reset_list = msm8996_usb3phy_reset_l,
1840 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1841 .vreg_list = qmp_phy_vreg_l,
1842 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1843 .regs = qmp_v4_usb3phy_regs_layout,
1844 .pcs_usb_offset = 0x600,
94a407cc
DB		 1845
1846 .start_ctrl = SERDES_START | PCS_START,
1847 .pwrdn_ctrl = SW_PWRDN,
1848 .phy_status = PHYSTATUS,
1849
1850 .has_pwrdn_delay = true,
1851 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1852 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1853};
1854
1855static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
a73a19ea 1856 .lanes = 2,
94a407cc
DB		 1857
1858 .serdes_tbl = sm8150_usb3_serdes_tbl,
1859 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1860 .tx_tbl = sm8250_usb3_tx_tbl,
1861 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
1862 .rx_tbl = sm8250_usb3_rx_tbl,
1863 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
1864 .pcs_tbl = sm8250_usb3_pcs_tbl,
1865 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
fc646236
DB		 1866 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
1867 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
94a407cc
DB		 1868 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
1869 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
1870 .reset_list = msm8996_usb3phy_reset_l,
1871 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1872 .vreg_list = qmp_phy_vreg_l,
1873 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1874 .regs = qmp_v4_usb3phy_regs_layout,
fc646236 1875 .pcs_usb_offset = 0x300,
94a407cc
DB		 1876
1877 .start_ctrl = SERDES_START | PCS_START,
1878 .pwrdn_ctrl = SW_PWRDN,
1879 .phy_status = PHYSTATUS,
1880
1881 .has_pwrdn_delay = true,
1882 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1883 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1884
1885 .has_phy_dp_com_ctrl = true,
94a407cc
DB		 1886};
1887
1888static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
a73a19ea 1889 .lanes = 1,
94a407cc
DB		 1890
1891 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1892 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1893 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
1894 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1895 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
1896 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1897 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1898 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
fc646236
DB		 1899 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1900 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1901 .clk_list = qmp_v4_phy_clk_l,
1902 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1903 .reset_list = msm8996_usb3phy_reset_l,
1904 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1905 .vreg_list = qmp_phy_vreg_l,
1906 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1907 .regs = qmp_v4_usb3phy_regs_layout,
1908 .pcs_usb_offset = 0x600,
94a407cc
DB		 1909
1910 .start_ctrl = SERDES_START | PCS_START,
1911 .pwrdn_ctrl = SW_PWRDN,
1912 .phy_status = PHYSTATUS,
1913
1914 .has_pwrdn_delay = true,
1915 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1916 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1917};
1918
94a407cc 1919static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
a73a19ea 1920 .lanes = 1,
94a407cc
DB		 1921
1922 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1923 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1924 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
1925 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1926 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
1927 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1928 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1929 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
fc646236
DB		 1930 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1931 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1932 .clk_list = qmp_v4_sdx55_usbphy_clk_l,
1933 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1934 .reset_list = msm8996_usb3phy_reset_l,
1935 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1936 .vreg_list = qmp_phy_vreg_l,
1937 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1938 .regs = qmp_v4_usb3phy_regs_layout,
1939 .pcs_usb_offset = 0x600,
94a407cc
DB		 1940
1941 .start_ctrl = SERDES_START | PCS_START,
1942 .pwrdn_ctrl = SW_PWRDN,
1943 .phy_status = PHYSTATUS,
1944
1945 .has_pwrdn_delay = true,
1946 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1947 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1948};
1949
94a407cc 1950static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
a73a19ea 1951 .lanes = 1,
94a407cc
DB		 1952
1953 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1954 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1955 .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
1956 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1957 .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
1958 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1959 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1960 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
fc646236
DB		 1961 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1962 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1963 .clk_list = qmp_v4_sdx55_usbphy_clk_l,
1964 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1965 .reset_list = msm8996_usb3phy_reset_l,
1966 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1967 .vreg_list = qmp_phy_vreg_l,
1968 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1969 .regs = qmp_v4_usb3phy_regs_layout,
1970 .pcs_usb_offset = 0x1000,
94a407cc
DB		 1971
1972 .start_ctrl = SERDES_START | PCS_START,
1973 .pwrdn_ctrl = SW_PWRDN,
1974 .phy_status = PHYSTATUS,
1975
1976 .has_pwrdn_delay = true,
1977 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
1978 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
1979};
1980
94a407cc 1981static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
a73a19ea 1982 .lanes = 2,
94a407cc
DB		 1983
1984 .serdes_tbl = sm8150_usb3_serdes_tbl,
1985 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1986 .tx_tbl = sm8350_usb3_tx_tbl,
1987 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
1988 .rx_tbl = sm8350_usb3_rx_tbl,
1989 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
1990 .pcs_tbl = sm8350_usb3_pcs_tbl,
1991 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
fc646236
DB		 1992 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl,
1993 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
94a407cc
DB		 1994 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
1995 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
1996 .reset_list = msm8996_usb3phy_reset_l,
1997 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1998 .vreg_list = qmp_phy_vreg_l,
1999 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2000 .regs = qmp_v4_usb3phy_regs_layout,
fc646236 2001 .pcs_usb_offset = 0x300,
94a407cc
DB		 2002
2003 .start_ctrl = SERDES_START | PCS_START,
2004 .pwrdn_ctrl = SW_PWRDN,
2005 .phy_status = PHYSTATUS,
2006
2007 .has_pwrdn_delay = true,
2008 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
2009 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
2010
2011 .has_phy_dp_com_ctrl = true,
94a407cc
DB		 2012};
2013
2014static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
a73a19ea 2015 .lanes = 1,
94a407cc
DB		 2016
2017 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
2018 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
2019 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
2020 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
2021 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
2022 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
2023 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
2024 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
fc646236
DB		 2025 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
2026 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 2027 .clk_list = qmp_v4_phy_clk_l,
2028 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
2029 .reset_list = msm8996_usb3phy_reset_l,
2030 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2031 .vreg_list = qmp_phy_vreg_l,
2032 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 2033 .regs = qmp_v4_usb3phy_regs_layout,
2034 .pcs_usb_offset = 0x1000,
94a407cc
DB		 2035
2036 .start_ctrl = SERDES_START | PCS_START,
2037 .pwrdn_ctrl = SW_PWRDN,
2038 .phy_status = PHYSTATUS,
2039
2040 .has_pwrdn_delay = true,
2041 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
2042 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
2043};
2044
94a407cc 2045static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
a73a19ea 2046 .lanes = 2,
94a407cc
DB		 2047
2048 .serdes_tbl = qcm2290_usb3_serdes_tbl,
2049 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
2050 .tx_tbl = qcm2290_usb3_tx_tbl,
2051 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
2052 .rx_tbl = qcm2290_usb3_rx_tbl,
2053 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
2054 .pcs_tbl = qcm2290_usb3_pcs_tbl,
2055 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
2056 .clk_list = qcm2290_usb3phy_clk_l,
2057 .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
2058 .reset_list = qcm2290_usb3phy_reset_l,
2059 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
2060 .vreg_list = qmp_phy_vreg_l,
2061 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2062 .regs = qcm2290_usb3phy_regs_layout,
2063
2064 .start_ctrl = SERDES_START | PCS_START,
2065 .pwrdn_ctrl = SW_PWRDN,
2066 .phy_status = PHYSTATUS,
94a407cc
DB		 2067};
2068
b767dedc 2069static void qmp_usb_configure_lane(void __iomem *base,
94a407cc
DB		 2070 const unsigned int *regs,
2071 const struct qmp_phy_init_tbl tbl[],
2072 int num,
2073 u8 lane_mask)
2074{
2075 int i;
2076 const struct qmp_phy_init_tbl *t = tbl;
2077
2078 if (!t)
2079 return;
2080
2081 for (i = 0; i < num; i++, t++) {
2082 if (!(t->lane_mask & lane_mask))
2083 continue;
2084
2085 if (t->in_layout)
2086 writel(t->val, base + regs[t->offset]);
2087 else
2088 writel(t->val, base + t->offset);
2089 }
2090}
2091
b767dedc 2092static void qmp_usb_configure(void __iomem *base,
94a407cc
DB		 2093 const unsigned int *regs,
2094 const struct qmp_phy_init_tbl tbl[],
2095 int num)
2096{
b767dedc 2097 qmp_usb_configure_lane(base, regs, tbl, num, 0xff);
94a407cc
DB		 2098}
2099
b767dedc 2100static int qmp_usb_serdes_init(struct qmp_phy *qphy)
94a407cc 2101{
94a407cc
DB		 2102 const struct qmp_phy_cfg *cfg = qphy->cfg;
2103 void __iomem *serdes = qphy->serdes;
94a407cc
DB		 2104 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
2105 int serdes_tbl_num = cfg->serdes_tbl_num;
94a407cc 2106
b767dedc 2107 qmp_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
94a407cc
DB		 2108
2109 return 0;
2110}
2111
fe2da191 2112static int qmp_usb_init(struct phy *phy)
94a407cc 2113{
fe2da191 2114 struct qmp_phy *qphy = phy_get_drvdata(phy);
94a407cc
DB		 2115 struct qcom_qmp *qmp = qphy->qmp;
2116 const struct qmp_phy_cfg *cfg = qphy->cfg;
94a407cc
DB		 2117 void __iomem *pcs = qphy->pcs;
2118 void __iomem *dp_com = qmp->dp_com;
e991c2ee 2119 int ret;
94a407cc 2120
94a407cc
DB		 2121 /* turn on regulator supplies */
2122 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2123 if (ret) {
2124 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
65753f38 2125 return ret;
94a407cc
DB		 2126 }
2127
e991c2ee
DB		 2128 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2129 if (ret) {
2130 dev_err(qmp->dev, "reset assert failed\n");
2131 goto err_disable_regulators;
94a407cc
DB		 2132 }
2133
e991c2ee
DB		 2134 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2135 if (ret) {
2136 dev_err(qmp->dev, "reset deassert failed\n");
2137 goto err_disable_regulators;
94a407cc
DB		 2138 }
2139
2140 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2141 if (ret)
2142 goto err_assert_reset;
2143
2144 if (cfg->has_phy_dp_com_ctrl) {
2145 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
2146 SW_PWRDN);
2147 /* override hardware control for reset of qmp phy */
2148 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2149 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2150 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2151
2152 /* Default type-c orientation, i.e CC1 */
2153 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
2154
2155 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
2156 USB3_MODE | DP_MODE);
2157
2158 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
2159 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2160 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2161 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2162
2163 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
2164 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2165 }
2166
faf83af5
DB		 2167 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
2168 qphy_setbits(pcs,
2169 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2170 cfg->pwrdn_ctrl);
2171 else
6cad2983 2172 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
faf83af5 2173 cfg->pwrdn_ctrl);
94a407cc 2174
94a407cc
DB		 2175 return 0;
2176
2177err_assert_reset:
e991c2ee 2178 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
94a407cc
DB		 2179err_disable_regulators:
2180 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
94a407cc
DB		 2181
2182 return ret;
2183}
2184
fe2da191 2185static int qmp_usb_exit(struct phy *phy)
94a407cc 2186{
fe2da191 2187 struct qmp_phy *qphy = phy_get_drvdata(phy);
94a407cc
DB		 2188 struct qcom_qmp *qmp = qphy->qmp;
2189 const struct qmp_phy_cfg *cfg = qphy->cfg;
94a407cc 2190
e991c2ee 2191 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
94a407cc
DB		 2192
2193 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2194
2195 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2196
94a407cc
DB		 2197 return 0;
2198}
2199
b767dedc 2200static int qmp_usb_power_on(struct phy *phy)
94a407cc
DB		 2201{
2202 struct qmp_phy *qphy = phy_get_drvdata(phy);
2203 struct qcom_qmp *qmp = qphy->qmp;
2204 const struct qmp_phy_cfg *cfg = qphy->cfg;
2205 void __iomem *tx = qphy->tx;
2206 void __iomem *rx = qphy->rx;
2207 void __iomem *pcs = qphy->pcs;
94a407cc
DB		 2208 void __iomem *status;
2209 unsigned int mask, val, ready;
2210 int ret;
2211
b767dedc 2212 qmp_usb_serdes_init(qphy);
94a407cc 2213
94a407cc
DB		 2214 ret = clk_prepare_enable(qphy->pipe_clk);
2215 if (ret) {
2216 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
faf83af5 2217 return ret;
94a407cc
DB		 2218 }
2219
2220 /* Tx, Rx, and PCS configurations */
b767dedc 2221 qmp_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1);
94a407cc 2222
a73a19ea 2223 if (cfg->lanes >= 2) {
b767dedc
JH		 2224 qmp_usb_configure_lane(qphy->tx2, cfg->regs,
2225 cfg->tx_tbl, cfg->tx_tbl_num, 2);
94a407cc
DB		 2226 }
2227
b767dedc 2228 qmp_usb_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1);
94a407cc 2229
a73a19ea 2230 if (cfg->lanes >= 2) {
b767dedc
JH		 2231 qmp_usb_configure_lane(qphy->rx2, cfg->regs,
2232 cfg->rx_tbl, cfg->rx_tbl_num, 2);
94a407cc
DB		 2233 }
2234
2235 /* Configure link rate, swing, etc. */
b767dedc 2236 qmp_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
94a407cc 2237
94a407cc
DB		 2238 if (cfg->has_pwrdn_delay)
2239 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
2240
86f5dddd 2241 /* Pull PHY out of reset state */
faf83af5
DB		 2242 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2243
86f5dddd
DB		 2244 /* start SerDes and Phy-Coding-Sublayer */
2245 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
94a407cc 2246
86f5dddd
DB		 2247 status = pcs + cfg->regs[QPHY_PCS_STATUS];
2248 mask = cfg->phy_status;
2249 ready = 0;
2250
2251 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
2252 PHY_INIT_COMPLETE_TIMEOUT);
2253 if (ret) {
2254 dev_err(qmp->dev, "phy initialization timed-out\n");
2255 goto err_disable_pipe_clk;
94a407cc 2256 }
86f5dddd 2257
94a407cc
DB		 2258 return 0;
2259
2260err_disable_pipe_clk:
2261 clk_disable_unprepare(qphy->pipe_clk);
94a407cc
DB		 2262
2263 return ret;
2264}
2265
b767dedc 2266static int qmp_usb_power_off(struct phy *phy)
94a407cc
DB		 2267{
2268 struct qmp_phy *qphy = phy_get_drvdata(phy);
2269 const struct qmp_phy_cfg *cfg = qphy->cfg;
2270
2271 clk_disable_unprepare(qphy->pipe_clk);
2272
86f5dddd 2273 /* PHY reset */
faf83af5 2274 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
94a407cc 2275
86f5dddd
DB		 2276 /* stop SerDes and Phy-Coding-Sublayer */
2277 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
94a407cc 2278
86f5dddd
DB		 2279 /* Put PHY into POWER DOWN state: active low */
2280 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
2281 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2282 cfg->pwrdn_ctrl);
2283 } else {
6cad2983 2284 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
86f5dddd 2285 cfg->pwrdn_ctrl);
94a407cc
DB		 2286 }
2287
2288 return 0;
2289}
2290
b767dedc 2291static int qmp_usb_enable(struct phy *phy)
94a407cc
DB		 2292{
2293 int ret;
2294
b767dedc 2295 ret = qmp_usb_init(phy);
94a407cc
DB		 2296 if (ret)
2297 return ret;
2298
b767dedc 2299 ret = qmp_usb_power_on(phy);
94a407cc 2300 if (ret)
b767dedc 2301 qmp_usb_exit(phy);
94a407cc
DB		 2302
2303 return ret;
2304}
2305
b767dedc 2306static int qmp_usb_disable(struct phy *phy)
94a407cc
DB		 2307{
2308 int ret;
2309
b767dedc 2310 ret = qmp_usb_power_off(phy);
94a407cc
DB		 2311 if (ret)
2312 return ret;
b767dedc 2313 return qmp_usb_exit(phy);
94a407cc
DB		 2314}
2315
b767dedc 2316static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
94a407cc
DB		 2317{
2318 struct qmp_phy *qphy = phy_get_drvdata(phy);
2319
2320 qphy->mode = mode;
2321
2322 return 0;
2323}
2324
b767dedc 2325static void qmp_usb_enable_autonomous_mode(struct qmp_phy *qphy)
94a407cc
DB		 2326{
2327 const struct qmp_phy_cfg *cfg = qphy->cfg;
fc646236 2328 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
94a407cc
DB		 2329 void __iomem *pcs_misc = qphy->pcs_misc;
2330 u32 intr_mask;
2331
2332 if (qphy->mode == PHY_MODE_USB_HOST_SS ||
2333 qphy->mode == PHY_MODE_USB_DEVICE_SS)
2334 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2335 else
2336 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2337
2338 /* Clear any pending interrupts status */
fc646236 2339 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 2340 /* Writing 1 followed by 0 clears the interrupt */
fc646236 2341 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 2342
fc646236 2343 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
94a407cc
DB		 2344 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2345
2346 /* Enable required PHY autonomous mode interrupts */
fc646236 2347 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
94a407cc
DB		 2348
2349 /* Enable i/o clamp_n for autonomous mode */
2350 if (pcs_misc)
2351 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2352}
2353
b767dedc 2354static void qmp_usb_disable_autonomous_mode(struct qmp_phy *qphy)
94a407cc
DB		 2355{
2356 const struct qmp_phy_cfg *cfg = qphy->cfg;
fc646236 2357 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
94a407cc
DB		 2358 void __iomem *pcs_misc = qphy->pcs_misc;
2359
2360 /* Disable i/o clamp_n on resume for normal mode */
2361 if (pcs_misc)
2362 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2363
fc646236 2364 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
94a407cc
DB		 2365 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2366
fc646236 2367 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 2368 /* Writing 1 followed by 0 clears the interrupt */
fc646236 2369 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc
DB		 2370}
2371
b767dedc 2372static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)
94a407cc
DB		 2373{
2374 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2375 struct qmp_phy *qphy = qmp->phys[0];
2376 const struct qmp_phy_cfg *cfg = qphy->cfg;
2377
2378 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
2379
65753f38 2380 if (!qphy->phy->init_count) {
94a407cc
DB		 2381 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2382 return 0;
2383 }
2384
b767dedc 2385 qmp_usb_enable_autonomous_mode(qphy);
94a407cc
DB		 2386
2387 clk_disable_unprepare(qphy->pipe_clk);
2388 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2389
2390 return 0;
2391}
2392
b767dedc 2393static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)
94a407cc
DB		 2394{
2395 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2396 struct qmp_phy *qphy = qmp->phys[0];
2397 const struct qmp_phy_cfg *cfg = qphy->cfg;
2398 int ret = 0;
2399
2400 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
2401
65753f38 2402 if (!qphy->phy->init_count) {
94a407cc
DB		 2403 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2404 return 0;
2405 }
2406
2407 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2408 if (ret)
2409 return ret;
2410
2411 ret = clk_prepare_enable(qphy->pipe_clk);
2412 if (ret) {
2413 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2414 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2415 return ret;
2416 }
2417
b767dedc 2418 qmp_usb_disable_autonomous_mode(qphy);
94a407cc
DB		 2419
2420 return 0;
2421}
2422
b767dedc 2423static int qmp_usb_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
94a407cc
DB		 2424{
2425 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2426 int num = cfg->num_vregs;
2427 int i;
2428
2429 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2430 if (!qmp->vregs)
2431 return -ENOMEM;
2432
2433 for (i = 0; i < num; i++)
2434 qmp->vregs[i].supply = cfg->vreg_list[i];
2435
2436 return devm_regulator_bulk_get(dev, num, qmp->vregs);
2437}
2438
b767dedc 2439static int qmp_usb_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
94a407cc
DB		 2440{
2441 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2442 int i;
e991c2ee 2443 int ret;
94a407cc
DB		 2444
2445 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
2446 sizeof(*qmp->resets), GFP_KERNEL);
2447 if (!qmp->resets)
2448 return -ENOMEM;
2449
e991c2ee
DB		 2450 for (i = 0; i < cfg->num_resets; i++)
2451 qmp->resets[i].id = cfg->reset_list[i];
94a407cc 2452
e991c2ee
DB		 2453 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
2454 if (ret)
2455 return dev_err_probe(dev, ret, "failed to get resets\n");
94a407cc
DB		 2456
2457 return 0;
2458}
2459
b767dedc 2460static int qmp_usb_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
94a407cc
DB		 2461{
2462 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2463 int num = cfg->num_clks;
2464 int i;
2465
2466 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2467 if (!qmp->clks)
2468 return -ENOMEM;
2469
2470 for (i = 0; i < num; i++)
2471 qmp->clks[i].id = cfg->clk_list[i];
2472
2473 return devm_clk_bulk_get(dev, num, qmp->clks);
2474}
2475
2476static void phy_clk_release_provider(void *res)
2477{
2478 of_clk_del_provider(res);
2479}
2480
2481/*
2482 * Register a fixed rate pipe clock.
2483 *
2484 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2485 * controls it. The <s>_pipe_clk coming out of the GCC is requested
2486 * by the PHY driver for its operations.
2487 * We register the <s>_pipe_clksrc here. The gcc driver takes care
2488 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2489 * Below picture shows this relationship.
2490 *
2491 * +---------------+
2492 * | PHY block |<<---------------------------------------+
2493 * | | |
2494 * | +-------+ | +-----+ |
2495 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2496 * clk | +-------+ | +-----+
2497 * +---------------+
2498 */
2499static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
2500{
2501 struct clk_fixed_rate *fixed;
2502 struct clk_init_data init = { };
2503 int ret;
2504
2505 ret = of_property_read_string(np, "clock-output-names", &init.name);
2506 if (ret) {
2507 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2508 return ret;
2509 }
2510
2511 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
2512 if (!fixed)
2513 return -ENOMEM;
2514
2515 init.ops = &clk_fixed_rate_ops;
2516
2517 /* controllers using QMP phys use 125MHz pipe clock interface */
2518 fixed->fixed_rate = 125000000;
2519 fixed->hw.init = &init;
2520
2521 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2522 if (ret)
2523 return ret;
2524
2525 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2526 if (ret)
2527 return ret;
2528
2529 /*
2530 * Roll a devm action because the clock provider is the child node, but
2531 * the child node is not actually a device.
2532 */
2533 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2534}
2535
b767dedc
JH		 2536static const struct phy_ops qmp_usb_ops = {
2537 .init = qmp_usb_enable,
2538 .exit = qmp_usb_disable,
2539 .set_mode = qmp_usb_set_mode,
94a407cc
DB		 2540 .owner = THIS_MODULE,
2541};
2542
a5d6b1ac
JH		 2543static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
2544 int index, bool exclusive)
2545{
2546 struct resource res;
2547
2548 if (!exclusive) {
2549 if (of_address_to_resource(np, index, &res))
2550 return IOMEM_ERR_PTR(-EINVAL);
2551
2552 return devm_ioremap(dev, res.start, resource_size(&res));
2553 }
2554
2555 return devm_of_iomap(dev, np, index, NULL);
2556}
2557
94a407cc 2558static
b767dedc 2559int qmp_usb_create(struct device *dev, struct device_node *np, int id,
94a407cc
DB		 2560 void __iomem *serdes, const struct qmp_phy_cfg *cfg)
2561{
2562 struct qcom_qmp *qmp = dev_get_drvdata(dev);
2563 struct phy *generic_phy;
2564 struct qmp_phy *qphy;
a5d6b1ac 2565 bool exclusive = true;
94a407cc
DB		 2566 int ret;
2567
a5d6b1ac
JH		 2568 /*
2569 * FIXME: These bindings should be fixed to not rely on overlapping
2570 * mappings for PCS.
2571 */
2572 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
2573 exclusive = false;
2574 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
2575 exclusive = false;
2576
94a407cc
DB		 2577 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
2578 if (!qphy)
2579 return -ENOMEM;
2580
2581 qphy->cfg = cfg;
2582 qphy->serdes = serdes;
2583 /*
2584 * Get memory resources for each phy lane:
2585 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2586 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2587 * For single lane PHYs: pcs_misc (optional) -> 3.
2588 */
a5d6b1ac
JH		 2589 qphy->tx = devm_of_iomap(dev, np, 0, NULL);
2590 if (IS_ERR(qphy->tx))
2591 return PTR_ERR(qphy->tx);
94a407cc 2592
a5d6b1ac
JH		 2593 qphy->rx = devm_of_iomap(dev, np, 1, NULL);
2594 if (IS_ERR(qphy->rx))
2595 return PTR_ERR(qphy->rx);
94a407cc 2596
a5d6b1ac
JH		 2597 qphy->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
2598 if (IS_ERR(qphy->pcs))
2599 return PTR_ERR(qphy->pcs);
94a407cc 2600
fc646236
DB		 2601 if (cfg->pcs_usb_offset)
2602 qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset;
2603
a73a19ea 2604 if (cfg->lanes >= 2) {
a5d6b1ac 2605 qphy->tx2 = devm_of_iomap(dev, np, 3, NULL);
264dac74
JH		 2606 if (IS_ERR(qphy->tx2))
2607 return PTR_ERR(qphy->tx2);
94a407cc 2608
264dac74
JH		 2609 qphy->rx2 = devm_of_iomap(dev, np, 4, NULL);
2610 if (IS_ERR(qphy->rx2))
2611 return PTR_ERR(qphy->rx2);
94a407cc 2612
264dac74 2613 qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
94a407cc 2614 } else {
a5d6b1ac 2615 qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
94a407cc
DB		 2616 }
2617
a5d6b1ac 2618 if (IS_ERR(qphy->pcs_misc)) {
94a407cc 2619 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
a5d6b1ac
JH		 2620 qphy->pcs_misc = NULL;
2621 }
94a407cc 2622
c8c5d5e8 2623 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
94a407cc 2624 if (IS_ERR(qphy->pipe_clk)) {
5d5b7d50
JH		 2625 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
2626 "failed to get lane%d pipe clock\n", id);
94a407cc
DB		 2627 }
2628
b767dedc 2629 generic_phy = devm_phy_create(dev, np, &qmp_usb_ops);
94a407cc
DB		 2630 if (IS_ERR(generic_phy)) {
2631 ret = PTR_ERR(generic_phy);
2632 dev_err(dev, "failed to create qphy %d\n", ret);
2633 return ret;
2634 }
2635
2636 qphy->phy = generic_phy;
94a407cc
DB		 2637 qphy->qmp = qmp;
2638 qmp->phys[id] = qphy;
2639 phy_set_drvdata(generic_phy, qphy);
2640
2641 return 0;
2642}
2643
b767dedc 2644static const struct of_device_id qmp_usb_of_match_table[] = {
94a407cc
DB		 2645 {
2646 .compatible = "qcom,ipq8074-qmp-usb3-phy",
2647 .data = &ipq8074_usb3phy_cfg,
94a407cc
DB		 2648 }, {
2649 .compatible = "qcom,msm8996-qmp-usb3-phy",
2650 .data = &msm8996_usb3phy_cfg,
94a407cc
DB		 2651 }, {
2652 .compatible = "qcom,ipq6018-qmp-usb3-phy",
2653 .data = &ipq8074_usb3phy_cfg,
2654 }, {
2655 .compatible = "qcom,sc7180-qmp-usb3-phy",
2656 .data = &sc7180_usb3phy_cfg,
94a407cc
DB		 2657 }, {
2658 .compatible = "qcom,sc8180x-qmp-usb3-phy",
2659 .data = &sm8150_usb3phy_cfg,
c0c7769c
BA		 2660 }, {
2661 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
2662 .data = &sc8280xp_usb3_uniphy_cfg,
94a407cc
DB		 2663 }, {
2664 .compatible = "qcom,sdm845-qmp-usb3-phy",
2665 .data = &qmp_v3_usb3phy_cfg,
2666 }, {
2667 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2668 .data = &qmp_v3_usb3_uniphy_cfg,
94a407cc
DB		 2669 }, {
2670 .compatible = "qcom,msm8998-qmp-usb3-phy",
2671 .data = &msm8998_usb3phy_cfg,
94a407cc
DB		 2672 }, {
2673 .compatible = "qcom,sm8150-qmp-usb3-phy",
2674 .data = &sm8150_usb3phy_cfg,
2675 }, {
2676 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2677 .data = &sm8150_usb3_uniphy_cfg,
2678 }, {
2679 .compatible = "qcom,sm8250-qmp-usb3-phy",
2680 .data = &sm8250_usb3phy_cfg,
94a407cc
DB		 2681 }, {
2682 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2683 .data = &sm8250_usb3_uniphy_cfg,
94a407cc
DB		 2684 }, {
2685 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2686 .data = &sdx55_usb3_uniphy_cfg,
2687 }, {
2688 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2689 .data = &sdx65_usb3_uniphy_cfg,
2690 }, {
2691 .compatible = "qcom,sm8350-qmp-usb3-phy",
2692 .data = &sm8350_usb3phy_cfg,
2693 }, {
2694 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2695 .data = &sm8350_usb3_uniphy_cfg,
94a407cc
DB		 2696 }, {
2697 .compatible = "qcom,sm8450-qmp-usb3-phy",
2698 .data = &sm8350_usb3phy_cfg,
2699 }, {
2700 .compatible = "qcom,qcm2290-qmp-usb3-phy",
2701 .data = &qcm2290_usb3phy_cfg,
2702 },
2703 { },
2704};
b767dedc 2705MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);
94a407cc 2706
b767dedc
JH		 2707static const struct dev_pm_ops qmp_usb_pm_ops = {
2708 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,
2709 qmp_usb_runtime_resume, NULL)
94a407cc
DB		 2710};
2711
b767dedc 2712static int qmp_usb_probe(struct platform_device *pdev)
94a407cc
DB		 2713{
2714 struct qcom_qmp *qmp;
2715 struct device *dev = &pdev->dev;
2716 struct device_node *child;
2717 struct phy_provider *phy_provider;
2718 void __iomem *serdes;
94a407cc 2719 const struct qmp_phy_cfg *cfg = NULL;
65753f38 2720 int num, id;
94a407cc
DB		 2721 int ret;
2722
2723 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2724 if (!qmp)
2725 return -ENOMEM;
2726
2727 qmp->dev = dev;
2728 dev_set_drvdata(dev, qmp);
2729
2730 /* Get the specific init parameters of QMP phy */
2731 cfg = of_device_get_match_data(dev);
8c924330
DB		 2732 if (!cfg)
2733 return -EINVAL;
94a407cc
DB		 2734
2735 /* per PHY serdes; usually located at base address */
86f5dddd 2736 serdes = devm_platform_ioremap_resource(pdev, 0);
94a407cc
DB		 2737 if (IS_ERR(serdes))
2738 return PTR_ERR(serdes);
2739
2740 /* per PHY dp_com; if PHY has dp_com control block */
86f5dddd 2741 if (cfg->has_phy_dp_com_ctrl) {
94a407cc
DB		 2742 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
2743 if (IS_ERR(qmp->dp_com))
2744 return PTR_ERR(qmp->dp_com);
2745 }
2746
b767dedc 2747 ret = qmp_usb_clk_init(dev, cfg);
94a407cc
DB		 2748 if (ret)
2749 return ret;
2750
b767dedc 2751 ret = qmp_usb_reset_init(dev, cfg);
94a407cc
DB		 2752 if (ret)
2753 return ret;
2754
b767dedc 2755 ret = qmp_usb_vreg_init(dev, cfg);
94a407cc
DB		 2756 if (ret) {
2757 if (ret != -EPROBE_DEFER)
2758 dev_err(dev, "failed to get regulator supplies: %d\n",
2759 ret);
2760 return ret;
2761 }
2762
2763 num = of_get_available_child_count(dev->of_node);
2764 /* do we have a rogue child node ? */
65753f38 2765 if (num > 1)
94a407cc
DB		 2766 return -EINVAL;
2767
2768 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
2769 if (!qmp->phys)
2770 return -ENOMEM;
2771
2772 pm_runtime_set_active(dev);
e57655e6
JH		 2773 ret = devm_pm_runtime_enable(dev);
2774 if (ret)
2775 return ret;
94a407cc
DB		 2776 /*
2777 * Prevent runtime pm from being ON by default. Users can enable
2778 * it using power/control in sysfs.
2779 */
2780 pm_runtime_forbid(dev);
2781
2782 id = 0;
2783 for_each_available_child_of_node(dev->of_node, child) {
94a407cc 2784 /* Create per-lane phy */
b767dedc 2785 ret = qmp_usb_create(dev, child, id, serdes, cfg);
94a407cc
DB		 2786 if (ret) {
2787 dev_err(dev, "failed to create lane%d phy, %d\n",
2788 id, ret);
2789 goto err_node_put;
2790 }
2791
2792 /*
2793 * Register the pipe clock provided by phy.
2794 * See function description to see details of this pipe clock.
2795 */
86f5dddd
DB		 2796 ret = phy_pipe_clk_register(qmp, child);
2797 if (ret) {
2798 dev_err(qmp->dev,
2799 "failed to register pipe clock source\n");
2800 goto err_node_put;
94a407cc 2801 }
86f5dddd 2802
94a407cc
DB		 2803 id++;
2804 }
2805
2806 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
94a407cc
DB		 2807
2808 return PTR_ERR_OR_ZERO(phy_provider);
2809
2810err_node_put:
94a407cc
DB		 2811 of_node_put(child);
2812 return ret;
2813}
2814
b767dedc
JH		 2815static struct platform_driver qmp_usb_driver = {
2816 .probe = qmp_usb_probe,
94a407cc 2817 .driver = {
8c924330 2818 .name = "qcom-qmp-usb-phy",
b767dedc
JH		 2819 .pm = &qmp_usb_pm_ops,
2820 .of_match_table = qmp_usb_of_match_table,
94a407cc
DB		 2821 },
2822};
2823
b767dedc 2824module_platform_driver(qmp_usb_driver);
94a407cc
DB		 2825
2826MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
8c924330 2827MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
94a407cc 2828MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)