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phy: qcom-qmp-usb: clean up probe initialisation
[linux-2.6-block.git] / drivers / phy / qualcomm / phy-qcom-qmp-usb.c
CommitLineData
94a407cc
DB		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#include <dt-bindings/phy/phy.h>
24
25#include "phy-qcom-qmp.h"
26
27/* QPHY_SW_RESET bit */
28#define SW_RESET BIT(0)
29/* QPHY_POWER_DOWN_CONTROL */
30#define SW_PWRDN BIT(0)
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DB		 31/* QPHY_START_CONTROL bits */
32#define SERDES_START BIT(0)
33#define PCS_START BIT(1)
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DB		 34/* QPHY_PCS_STATUS bit */
35#define PHYSTATUS BIT(6)
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DB		 36
37/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
38/* DP PHY soft reset */
39#define SW_DPPHY_RESET BIT(0)
40/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
41#define SW_DPPHY_RESET_MUX BIT(1)
42/* USB3 PHY soft reset */
43#define SW_USB3PHY_RESET BIT(2)
44/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
45#define SW_USB3PHY_RESET_MUX BIT(3)
46
47/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
48#define USB3_MODE BIT(0) /* enables USB3 mode */
49#define DP_MODE BIT(1) /* enables DP mode */
50
51/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
52#define ARCVR_DTCT_EN BIT(0)
53#define ALFPS_DTCT_EN BIT(1)
54#define ARCVR_DTCT_EVENT_SEL BIT(4)
55
56/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
57#define IRQ_CLEAR BIT(0)
58
59/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
60#define RCVR_DETECT BIT(0)
61
62/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
63#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
64
65#define PHY_INIT_COMPLETE_TIMEOUT 10000
94a407cc 66
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DB		 67struct qmp_phy_init_tbl {
68 unsigned int offset;
69 unsigned int val;
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DB		 70 /*
71 * mask of lanes for which this register is written
72 * for cases when second lane needs different values
73 */
74 u8 lane_mask;
75};
76
77#define QMP_PHY_INIT_CFG(o, v) \
78 { \
79 .offset = o, \
80 .val = v, \
81 .lane_mask = 0xff, \
82 }
83
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DB		 84#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
85 { \
86 .offset = o, \
87 .val = v, \
88 .lane_mask = l, \
89 }
90
91/* set of registers with offsets different per-PHY */
92enum qphy_reg_layout {
94a407cc 93 /* PCS registers */
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DB		 94 QPHY_SW_RESET,
95 QPHY_START_CTRL,
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DB		 96 QPHY_PCS_STATUS,
97 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
98 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
99 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
100 QPHY_PCS_POWER_DOWN_CONTROL,
101 /* PCS_MISC registers */
102 QPHY_PCS_MISC_TYPEC_CTRL,
103 /* Keep last to ensure regs_layout arrays are properly initialized */
104 QPHY_LAYOUT_SIZE
105};
106
94a407cc 107static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
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DB		 108 [QPHY_SW_RESET] = 0x00,
109 [QPHY_START_CTRL] = 0x08,
110 [QPHY_PCS_STATUS] = 0x17c,
111 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
112 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
113 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
645d3d04 114 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
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DB		 115};
116
117static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
118 [QPHY_SW_RESET] = 0x00,
119 [QPHY_START_CTRL] = 0x08,
120 [QPHY_PCS_STATUS] = 0x174,
121 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
122 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
123 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
645d3d04 124 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
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DB		 125};
126
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DB		 127static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
128 [QPHY_SW_RESET] = 0x00,
129 [QPHY_START_CTRL] = 0x44,
130 [QPHY_PCS_STATUS] = 0x14,
131 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
94a407cc 132
fc646236
DB		 133 /* In PCS_USB */
134 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
135 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
94a407cc
DB		 136};
137
138static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
139 [QPHY_SW_RESET] = 0x00,
140 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
141 [QPHY_START_CTRL] = 0x08,
142 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
143 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
144 [QPHY_PCS_STATUS] = 0x174,
145 [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
146};
147
94a407cc
DB		 148static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
149 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
150 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
151 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
152 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
153 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
154 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
155 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
156 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
157 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
158 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
159 /* PLL and Loop filter settings */
160 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
161 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
162 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
163 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
164 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
165 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
166 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
167 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
168 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
169 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
170 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
171 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
172 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
173 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
174 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
175 /* SSC settings */
176 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
177 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
178 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
179 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
180 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
181 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
182 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
183};
184
185static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
186 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
187 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
188 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
189 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
190 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
191 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
192 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
193 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
194 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
195};
196
197static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
212 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
215 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
216 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
217 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
218 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
219 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
220 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
221};
222
94a407cc
DB		 223static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
224 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
225 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
226 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
227 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
228 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
229 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
230 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
231 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
232 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
233 /* PLL and Loop filter settings */
234 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
235 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
236 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
237 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
238 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
239 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
240 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
241 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
242 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
243 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
244 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
245 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
246 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
247 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
248 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
249 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
250 /* SSC settings */
251 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
252 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
253 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
254 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
255 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
256 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
257 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
258};
259
260static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
261 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
262 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
263 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
264};
265
266static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
267 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
268 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
269 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
270 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
271 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
272 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
273 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
274 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
275 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
276 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
277};
278
279static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
280 /* FLL settings */
d36e341a
DB		 281 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
282 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
283 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
284 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
285 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
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DB		 286
287 /* Lock Det settings */
6cad2983
DB		 288 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
289 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
290 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
291 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
94a407cc
DB		 292};
293
94a407cc
DB		 294static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
319 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
320 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
321 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
325 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
326 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
327 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
328 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
329 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
330 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
331};
332
333static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
334 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
335 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
336 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
337 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
338 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
339};
340
94a407cc
DB		 341static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
342 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
343 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
344 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
345 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
346 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
347 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
348 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
349 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
350 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
351};
352
353static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
354 /* FLL settings */
355 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
356 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
357 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
358 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
359 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
360
361 /* Lock Det settings */
362 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
364 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
366
367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
374 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
386
387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
398};
399
400static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
437};
438
439static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
440 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
441 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
442 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
443 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
444 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
445};
446
447static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
448 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
449 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
450 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
451 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
452 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
453 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
454 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
455 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
456 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
457 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
458 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
459};
460
461static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
462 /* FLL settings */
463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
468
469 /* Lock Det settings */
470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
474
475 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
494
495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
500 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
501 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
503 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
504 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
505 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
506
507 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
508 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
509};
510
94a407cc
DB		 511static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
550};
551
552static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
553 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
554 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
555 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
556 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
557};
558
559static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
560 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
561 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
562 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
563 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
564 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
565 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
577};
578
579static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
fc270d13 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
94a407cc
DB		 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
612 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
613 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
614 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
615 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
616 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
617 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
618};
619
94a407cc
DB		 620static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
621 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
622 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
623 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
624 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
625 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
626 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
652 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
653 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
654 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
655 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
656 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
657 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
658 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
659 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
660 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
661};
662
663static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
664 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
665 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
666 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
667 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
668 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
669};
670
671static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
708};
709
710static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
711 /* Lock Det settings */
712 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
713 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
715
716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
722 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
fc646236
DB		 724};
725
726static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
94a407cc
DB		 727 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
728 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
729};
730
731static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
732 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
772};
773
774static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
775 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
776 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
777 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
778 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
779};
780
781static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
818};
819
820static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
821 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
822 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
823 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
824 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
825 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
826 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
827 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
94a407cc
DB		 828 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
829 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
830 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
831 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
832 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
833 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
834 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
835};
836
fc646236
DB		 837static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
838 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
839 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
840};
841
94a407cc
DB		 842static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
843 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
844 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
845 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
846 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
847 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
848 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
849 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
850 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
851};
852
853static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
854 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
855 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
856 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
857 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
858 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
859 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
860 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
861 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
862 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
866 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
868 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
869 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
870 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
871 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
872 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
873 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
874 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
875 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
876 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
877 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
878 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
879 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
880 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
881 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
882 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
883 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
884 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
885 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
886 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
887 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
888 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
889 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
890 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
891 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
892};
893
894static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
895 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
896 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
897 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
898 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
899 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
900 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
901 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
902 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
903 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
904 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
905 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
906 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
fc646236
DB		 907};
908
909static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
94a407cc
DB		 910 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
911 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
912};
913
914static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
915 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
916 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
917 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
918 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
919 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
920 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
921};
922
923static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
924 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
8c924330 941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
94a407cc 942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
8c924330
DB		 943 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
944 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
94a407cc 947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
8c924330 948 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
94a407cc 949 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
8c924330
DB		 950 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
951 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
952 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
953 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
954 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
955 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
94a407cc 956 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
8c924330
DB		 957 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
958 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
959 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
94a407cc
DB		 960};
961
8c924330
DB		 962static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
963 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
964 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
965 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
966 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
967 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
968 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
969 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
970 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
8c924330
DB		 971 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
972 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
973 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
974 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
975 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
976 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
94a407cc
DB		 977};
978
fc646236
DB		 979static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
980 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
981 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
982};
983
94a407cc
DB		 984static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
985 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
986 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
987 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
988 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
989 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
990};
991
992static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
993 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
994 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
995 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
996 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
997 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
998 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
999 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1000 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1001 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1002 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1003 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1004 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
1005 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1006 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
1007 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
1008 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1009 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1010 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1011 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1012 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
1013 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1014 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1015 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1016 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1017 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1018 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1019 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1020 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1021 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1022 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1023 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1024 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1025 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1026 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1027 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1028 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1029};
1030
94a407cc
DB		 1031static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
1032 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1033 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1034 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1035 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1036 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1037 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1038 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
1039};
1040
1041static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
1042 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
1043 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1044 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1045 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1046 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1047 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1048 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1049 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1050 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1051 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1052 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1053 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1054 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1058 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1059 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1060 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1061 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1062 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1063 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1064 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1065 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1066 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1067 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1068 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1069 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1070 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1071 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1072 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1073};
1074
94a407cc
DB		 1075static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
1076 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
1077 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
1078 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
1079 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1080 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
1081 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1082 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
1083 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
1084 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
1085 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1086};
1087
1088static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
1089 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1090 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1091 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1092 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1093 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1094 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1095 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1096 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1097 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1098 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1099 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1100 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1101 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1102 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1103 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1104 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1105 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1106 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1107 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1108 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1109 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1110 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
1111 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
1112 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
1113 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
1114 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
1115 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
1116 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1117 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1118 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
1119 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
1120 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1121 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
1122 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1123 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1124 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
1125 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1126 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
1127};
1128
1129static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
94a407cc
DB		 1130 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1131 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1132 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1133 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1134 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1135 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1136 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1137 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1138 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1139 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1140 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1141 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1142 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1143 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
fc646236
DB		 1144};
1145
1146static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
1147 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
1148 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
94a407cc
DB		 1149 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1150 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1151};
1152
1153static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
1154 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1155 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1156 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1157 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1158 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1159 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1160 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1161};
1162
1163static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
1164 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1169 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1170 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1171 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1172 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1173 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1174 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1175 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1176 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1177 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1178 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1179 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1180 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1181 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1182 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1183 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1184 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1185 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1186 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1187 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1188 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1189 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1190 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1191 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1192 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1193 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1194 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1195};
1196
1197static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
1198 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1199 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1200 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1201 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1202 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1203 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1204 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1205 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
94a407cc
DB		 1206 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1207 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1208 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1209 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1210 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1211 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1212};
1213
fc646236
DB		 1214static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
1215 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1216 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1217};
1218
94a407cc
DB		 1219static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
1220 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
1221 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1222 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
1223 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
1224 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
1225 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
1226 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
1227 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
1228 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
1229 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
1230 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
1231 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
1232 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
1233 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
1234 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
1235 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
1236 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
1237 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1238 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
1239 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
1240 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
1241 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
1242 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
1243 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
1244 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
1245 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
1246 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
1247 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
1248 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
1249 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
1250 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
1251 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
1252 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
1253 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
1254 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
1255 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
1256 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
1257 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
1258};
1259
1260static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
1261 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1262 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1263 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1264 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1265 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
1266};
1267
1268static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
1269 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1270 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
1271 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1272 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1273 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1274 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1275 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1276 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
1277 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1278 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1279 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1280 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1281 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
1282 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1283 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1284 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1285 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
1286};
1287
1288static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
1289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
1291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
1292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
1297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1299 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1300 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
1310};
1311
c0c7769c
BA		 1312static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),
1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),
1319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),
1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1325 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1326 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1327 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1328 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1329 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1330 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),
1331 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),
1332 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1333 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),
1334 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1335 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),
1336 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1337 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1338 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1339 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1340 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1341 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1342 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1343 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1344 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1345 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1346 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1347 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1348 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1349 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1350 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1351 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1352};
1353
1354static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
1355 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1356 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1357 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1358 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1359 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1360 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1361 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1362};
1363
1364static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
1365 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1366 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1367 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1368 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1369 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1370 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1371 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1372 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1373 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1374 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1375 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1376 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1377 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1378 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1379 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1380 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1381 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1382 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1383 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a),
1384 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1385 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1386 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1387 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1388 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1389 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1390 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1391 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1392 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1393 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1394 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1395 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1396};
1397
1398static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
1399 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1400 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1401 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1402 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1403 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1404 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1405 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1406 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1407 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1408 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1409 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1410 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1411 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1412 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1413 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1414 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1415};
1416
94a407cc
DB		 1417/* struct qmp_phy_cfg - per-PHY initialization config */
1418struct qmp_phy_cfg {
a73a19ea 1419 int lanes;
94a407cc
DB		 1420
1421 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1422 const struct qmp_phy_init_tbl *serdes_tbl;
1423 int serdes_tbl_num;
94a407cc
DB		 1424 const struct qmp_phy_init_tbl *tx_tbl;
1425 int tx_tbl_num;
94a407cc
DB		 1426 const struct qmp_phy_init_tbl *rx_tbl;
1427 int rx_tbl_num;
94a407cc
DB		 1428 const struct qmp_phy_init_tbl *pcs_tbl;
1429 int pcs_tbl_num;
fc646236
DB		 1430 const struct qmp_phy_init_tbl *pcs_usb_tbl;
1431 int pcs_usb_tbl_num;
94a407cc
DB		 1432
1433 /* clock ids to be requested */
1434 const char * const *clk_list;
1435 int num_clks;
1436 /* resets to be requested */
1437 const char * const *reset_list;
1438 int num_resets;
1439 /* regulators to be requested */
1440 const char * const *vreg_list;
1441 int num_vregs;
1442
1443 /* array of registers with different offsets */
1444 const unsigned int *regs;
1445
94a407cc
DB		 1446 /* true, if PHY needs delay after POWER_DOWN */
1447 bool has_pwrdn_delay;
94a407cc
DB		 1448
1449 /* true, if PHY has a separate DP_COM control block */
1450 bool has_phy_dp_com_ctrl;
fc646236
DB		 1451
1452 /* Offset from PCS to PCS_USB region */
1453 unsigned int pcs_usb_offset;
94a407cc
DB		 1454};
1455
2a55ec4f
JH		 1456struct qmp_usb {
1457 struct device *dev;
1458
94a407cc 1459 const struct qmp_phy_cfg *cfg;
2a55ec4f 1460
94a407cc 1461 void __iomem *serdes;
2a55ec4f
JH		 1462 void __iomem *pcs;
1463 void __iomem *pcs_misc;
1464 void __iomem *pcs_usb;
94a407cc
DB		 1465 void __iomem *tx;
1466 void __iomem *rx;
94a407cc
DB		 1467 void __iomem *tx2;
1468 void __iomem *rx2;
94a407cc 1469
94a407cc
DB		 1470 void __iomem *dp_com;
1471
2a55ec4f 1472 struct clk *pipe_clk;
94a407cc 1473 struct clk_bulk_data *clks;
e991c2ee 1474 struct reset_control_bulk_data *resets;
94a407cc
DB		 1475 struct regulator_bulk_data *vregs;
1476
2a55ec4f
JH		 1477 enum phy_mode mode;
1478
1479 struct phy *phy;
94a407cc
DB		 1480};
1481
94a407cc
DB		 1482static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1483{
1484 u32 reg;
1485
1486 reg = readl(base + offset);
1487 reg |= val;
1488 writel(reg, base + offset);
1489
1490 /* ensure that above write is through */
1491 readl(base + offset);
1492}
1493
1494static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1495{
1496 u32 reg;
1497
1498 reg = readl(base + offset);
1499 reg &= ~val;
1500 writel(reg, base + offset);
1501
1502 /* ensure that above write is through */
1503 readl(base + offset);
1504}
1505
1506/* list of clocks required by phy */
1507static const char * const msm8996_phy_clk_l[] = {
1508 "aux", "cfg_ahb", "ref",
1509};
1510
94a407cc
DB		 1511static const char * const qmp_v3_phy_clk_l[] = {
1512 "aux", "cfg_ahb", "ref", "com_aux",
1513};
1514
94a407cc
DB		 1515static const char * const qmp_v4_phy_clk_l[] = {
1516 "aux", "ref_clk_src", "ref", "com_aux",
1517};
1518
1519/* the primary usb3 phy on sm8250 doesn't have a ref clock */
1520static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
1521 "aux", "ref_clk_src", "com_aux"
1522};
1523
94a407cc
DB		 1524/* usb3 phy on sdx55 doesn't have com_aux clock */
1525static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
1526 "aux", "cfg_ahb", "ref"
1527};
1528
1529static const char * const qcm2290_usb3phy_clk_l[] = {
1530 "cfg_ahb", "ref", "com_aux",
1531};
1532
1533/* list of resets */
94a407cc
DB		 1534static const char * const msm8996_usb3phy_reset_l[] = {
1535 "phy", "common",
1536};
1537
1538static const char * const sc7180_usb3phy_reset_l[] = {
1539 "phy",
1540};
1541
1542static const char * const qcm2290_usb3phy_reset_l[] = {
1543 "phy_phy", "phy",
1544};
1545
94a407cc
DB		 1546/* list of regulators */
1547static const char * const qmp_phy_vreg_l[] = {
1548 "vdda-phy", "vdda-pll",
1549};
1550
1551static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
a73a19ea 1552 .lanes = 1,
94a407cc
DB		 1553
1554 .serdes_tbl = ipq8074_usb3_serdes_tbl,
1555 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1556 .tx_tbl = msm8996_usb3_tx_tbl,
1557 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1558 .rx_tbl = ipq8074_usb3_rx_tbl,
1559 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1560 .pcs_tbl = ipq8074_usb3_pcs_tbl,
1561 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1562 .clk_list = msm8996_phy_clk_l,
1563 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1564 .reset_list = msm8996_usb3phy_reset_l,
1565 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1566 .vreg_list = qmp_phy_vreg_l,
1567 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
922adfd5 1568 .regs = qmp_v3_usb3phy_regs_layout,
94a407cc
DB		 1569};
1570
94a407cc 1571static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
a73a19ea 1572 .lanes = 1,
94a407cc
DB		 1573
1574 .serdes_tbl = msm8996_usb3_serdes_tbl,
1575 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1576 .tx_tbl = msm8996_usb3_tx_tbl,
1577 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1578 .rx_tbl = msm8996_usb3_rx_tbl,
1579 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1580 .pcs_tbl = msm8996_usb3_pcs_tbl,
1581 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1582 .clk_list = msm8996_phy_clk_l,
1583 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1584 .reset_list = msm8996_usb3phy_reset_l,
1585 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1586 .vreg_list = qmp_phy_vreg_l,
1587 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1588 .regs = usb3phy_regs_layout,
94a407cc
DB		 1589};
1590
94a407cc 1591static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
a73a19ea 1592 .lanes = 2,
94a407cc
DB		 1593
1594 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1595 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1596 .tx_tbl = qmp_v3_usb3_tx_tbl,
1597 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1598 .rx_tbl = qmp_v3_usb3_rx_tbl,
1599 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1600 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1601 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1602 .clk_list = qmp_v3_phy_clk_l,
1603 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1604 .reset_list = msm8996_usb3phy_reset_l,
1605 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1606 .vreg_list = qmp_phy_vreg_l,
1607 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1608 .regs = qmp_v3_usb3phy_regs_layout,
1609
94a407cc 1610 .has_pwrdn_delay = true,
94a407cc 1611 .has_phy_dp_com_ctrl = true,
94a407cc
DB		 1612};
1613
1614static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
a73a19ea 1615 .lanes = 2,
94a407cc
DB		 1616
1617 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1618 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1619 .tx_tbl = qmp_v3_usb3_tx_tbl,
1620 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1621 .rx_tbl = qmp_v3_usb3_rx_tbl,
1622 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1623 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1624 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1625 .clk_list = qmp_v3_phy_clk_l,
1626 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1627 .reset_list = sc7180_usb3phy_reset_l,
1628 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
1629 .vreg_list = qmp_phy_vreg_l,
1630 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1631 .regs = qmp_v3_usb3phy_regs_layout,
1632
94a407cc 1633 .has_pwrdn_delay = true,
94a407cc 1634 .has_phy_dp_com_ctrl = true,
94a407cc
DB		 1635};
1636
c0c7769c 1637static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
a73a19ea 1638 .lanes = 1,
c0c7769c
BA		 1639
1640 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1641 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1642 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
1643 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1644 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
1645 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1646 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl,
1647 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
1648 .clk_list = qmp_v4_phy_clk_l,
1649 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1650 .reset_list = msm8996_usb3phy_reset_l,
1651 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1652 .vreg_list = qmp_phy_vreg_l,
1653 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1654 .regs = qmp_v4_usb3phy_regs_layout,
4c6b3af3 1655 .pcs_usb_offset = 0x1000,
c0c7769c
BA		 1656};
1657
94a407cc 1658static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
a73a19ea 1659 .lanes = 1,
94a407cc
DB		 1660
1661 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
1662 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1663 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
1664 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1665 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
1666 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1667 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
1668 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1669 .clk_list = qmp_v3_phy_clk_l,
1670 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
1671 .reset_list = msm8996_usb3phy_reset_l,
1672 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1673 .vreg_list = qmp_phy_vreg_l,
1674 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1675 .regs = qmp_v3_usb3phy_regs_layout,
1676
94a407cc 1677 .has_pwrdn_delay = true,
94a407cc
DB		 1678};
1679
94a407cc 1680static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
a73a19ea 1681 .lanes = 2,
94a407cc
DB		 1682
1683 .serdes_tbl = msm8998_usb3_serdes_tbl,
1684 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1685 .tx_tbl = msm8998_usb3_tx_tbl,
1686 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1687 .rx_tbl = msm8998_usb3_rx_tbl,
1688 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1689 .pcs_tbl = msm8998_usb3_pcs_tbl,
1690 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1691 .clk_list = msm8996_phy_clk_l,
1692 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1693 .reset_list = msm8996_usb3phy_reset_l,
1694 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1695 .vreg_list = qmp_phy_vreg_l,
1696 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
8c924330 1697 .regs = qmp_v3_usb3phy_regs_layout,
94a407cc
DB		 1698};
1699
1700static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
a73a19ea 1701 .lanes = 2,
94a407cc
DB		 1702
1703 .serdes_tbl = sm8150_usb3_serdes_tbl,
1704 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1705 .tx_tbl = sm8150_usb3_tx_tbl,
1706 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
1707 .rx_tbl = sm8150_usb3_rx_tbl,
1708 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
1709 .pcs_tbl = sm8150_usb3_pcs_tbl,
1710 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
fc646236
DB		 1711 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
1712 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
94a407cc
DB		 1713 .clk_list = qmp_v4_phy_clk_l,
1714 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1715 .reset_list = msm8996_usb3phy_reset_l,
1716 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1717 .vreg_list = qmp_phy_vreg_l,
1718 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1719 .regs = qmp_v4_usb3phy_regs_layout,
fc646236 1720 .pcs_usb_offset = 0x300,
94a407cc 1721
94a407cc 1722 .has_pwrdn_delay = true,
94a407cc 1723 .has_phy_dp_com_ctrl = true,
94a407cc
DB		 1724};
1725
94a407cc 1726static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
a73a19ea 1727 .lanes = 1,
94a407cc
DB		 1728
1729 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1730 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1731 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
1732 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1733 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
1734 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1735 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
1736 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
fc646236
DB		 1737 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl,
1738 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1739 .clk_list = qmp_v4_phy_clk_l,
1740 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1741 .reset_list = msm8996_usb3phy_reset_l,
1742 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1743 .vreg_list = qmp_phy_vreg_l,
1744 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1745 .regs = qmp_v4_usb3phy_regs_layout,
1746 .pcs_usb_offset = 0x600,
94a407cc 1747
94a407cc 1748 .has_pwrdn_delay = true,
94a407cc
DB		 1749};
1750
1751static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
a73a19ea 1752 .lanes = 2,
94a407cc
DB		 1753
1754 .serdes_tbl = sm8150_usb3_serdes_tbl,
1755 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1756 .tx_tbl = sm8250_usb3_tx_tbl,
1757 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
1758 .rx_tbl = sm8250_usb3_rx_tbl,
1759 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
1760 .pcs_tbl = sm8250_usb3_pcs_tbl,
1761 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
fc646236
DB		 1762 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
1763 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
94a407cc
DB		 1764 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
1765 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
1766 .reset_list = msm8996_usb3phy_reset_l,
1767 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1768 .vreg_list = qmp_phy_vreg_l,
1769 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1770 .regs = qmp_v4_usb3phy_regs_layout,
fc646236 1771 .pcs_usb_offset = 0x300,
94a407cc 1772
94a407cc 1773 .has_pwrdn_delay = true,
94a407cc 1774 .has_phy_dp_com_ctrl = true,
94a407cc
DB		 1775};
1776
1777static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
a73a19ea 1778 .lanes = 1,
94a407cc
DB		 1779
1780 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1781 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1782 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
1783 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1784 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
1785 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1786 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1787 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
fc646236
DB		 1788 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1789 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1790 .clk_list = qmp_v4_phy_clk_l,
1791 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1792 .reset_list = msm8996_usb3phy_reset_l,
1793 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1794 .vreg_list = qmp_phy_vreg_l,
1795 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1796 .regs = qmp_v4_usb3phy_regs_layout,
1797 .pcs_usb_offset = 0x600,
94a407cc 1798
94a407cc 1799 .has_pwrdn_delay = true,
94a407cc
DB		 1800};
1801
94a407cc 1802static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
a73a19ea 1803 .lanes = 1,
94a407cc
DB		 1804
1805 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1806 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1807 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
1808 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1809 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
1810 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1811 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1812 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
fc646236
DB		 1813 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1814 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1815 .clk_list = qmp_v4_sdx55_usbphy_clk_l,
1816 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1817 .reset_list = msm8996_usb3phy_reset_l,
1818 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1819 .vreg_list = qmp_phy_vreg_l,
1820 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1821 .regs = qmp_v4_usb3phy_regs_layout,
1822 .pcs_usb_offset = 0x600,
94a407cc 1823
94a407cc 1824 .has_pwrdn_delay = true,
94a407cc
DB		 1825};
1826
94a407cc 1827static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
a73a19ea 1828 .lanes = 1,
94a407cc
DB		 1829
1830 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1831 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1832 .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
1833 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1834 .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
1835 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1836 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1837 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
fc646236
DB		 1838 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1839 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1840 .clk_list = qmp_v4_sdx55_usbphy_clk_l,
1841 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1842 .reset_list = msm8996_usb3phy_reset_l,
1843 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1844 .vreg_list = qmp_phy_vreg_l,
1845 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1846 .regs = qmp_v4_usb3phy_regs_layout,
1847 .pcs_usb_offset = 0x1000,
94a407cc 1848
94a407cc 1849 .has_pwrdn_delay = true,
94a407cc
DB		 1850};
1851
94a407cc 1852static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
a73a19ea 1853 .lanes = 2,
94a407cc
DB		 1854
1855 .serdes_tbl = sm8150_usb3_serdes_tbl,
1856 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1857 .tx_tbl = sm8350_usb3_tx_tbl,
1858 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
1859 .rx_tbl = sm8350_usb3_rx_tbl,
1860 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
1861 .pcs_tbl = sm8350_usb3_pcs_tbl,
1862 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
fc646236
DB		 1863 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl,
1864 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
94a407cc
DB		 1865 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
1866 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
1867 .reset_list = msm8996_usb3phy_reset_l,
1868 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1869 .vreg_list = qmp_phy_vreg_l,
1870 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1871 .regs = qmp_v4_usb3phy_regs_layout,
fc646236 1872 .pcs_usb_offset = 0x300,
94a407cc 1873
94a407cc 1874 .has_pwrdn_delay = true,
94a407cc 1875 .has_phy_dp_com_ctrl = true,
94a407cc
DB		 1876};
1877
1878static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
a73a19ea 1879 .lanes = 1,
94a407cc
DB		 1880
1881 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1882 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1883 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
1884 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1885 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
1886 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1887 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1888 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
fc646236
DB		 1889 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1890 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
94a407cc
DB		 1891 .clk_list = qmp_v4_phy_clk_l,
1892 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
1893 .reset_list = msm8996_usb3phy_reset_l,
1894 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1895 .vreg_list = qmp_phy_vreg_l,
1896 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
fc646236
DB		 1897 .regs = qmp_v4_usb3phy_regs_layout,
1898 .pcs_usb_offset = 0x1000,
94a407cc 1899
94a407cc 1900 .has_pwrdn_delay = true,
94a407cc
DB		 1901};
1902
94a407cc 1903static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
a73a19ea 1904 .lanes = 2,
94a407cc
DB		 1905
1906 .serdes_tbl = qcm2290_usb3_serdes_tbl,
1907 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
1908 .tx_tbl = qcm2290_usb3_tx_tbl,
1909 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
1910 .rx_tbl = qcm2290_usb3_rx_tbl,
1911 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
1912 .pcs_tbl = qcm2290_usb3_pcs_tbl,
1913 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
1914 .clk_list = qcm2290_usb3phy_clk_l,
1915 .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
1916 .reset_list = qcm2290_usb3phy_reset_l,
1917 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1918 .vreg_list = qmp_phy_vreg_l,
1919 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1920 .regs = qcm2290_usb3phy_regs_layout,
94a407cc
DB		 1921};
1922
b767dedc 1923static void qmp_usb_configure_lane(void __iomem *base,
94a407cc
DB		 1924 const struct qmp_phy_init_tbl tbl[],
1925 int num,
1926 u8 lane_mask)
1927{
1928 int i;
1929 const struct qmp_phy_init_tbl *t = tbl;
1930
1931 if (!t)
1932 return;
1933
1934 for (i = 0; i < num; i++, t++) {
1935 if (!(t->lane_mask & lane_mask))
1936 continue;
1937
9d452c3a 1938 writel(t->val, base + t->offset);
94a407cc
DB		 1939 }
1940}
1941
b767dedc 1942static void qmp_usb_configure(void __iomem *base,
94a407cc
DB		 1943 const struct qmp_phy_init_tbl tbl[],
1944 int num)
1945{
9d452c3a 1946 qmp_usb_configure_lane(base, tbl, num, 0xff);
94a407cc
DB		 1947}
1948
2a55ec4f 1949static int qmp_usb_serdes_init(struct qmp_usb *qmp)
94a407cc 1950{
2a55ec4f
JH		 1951 const struct qmp_phy_cfg *cfg = qmp->cfg;
1952 void __iomem *serdes = qmp->serdes;
94a407cc
DB		 1953 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1954 int serdes_tbl_num = cfg->serdes_tbl_num;
94a407cc 1955
9d452c3a 1956 qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num);
94a407cc
DB		 1957
1958 return 0;
1959}
1960
fe2da191 1961static int qmp_usb_init(struct phy *phy)
94a407cc 1962{
2a55ec4f
JH		 1963 struct qmp_usb *qmp = phy_get_drvdata(phy);
1964 const struct qmp_phy_cfg *cfg = qmp->cfg;
1965 void __iomem *pcs = qmp->pcs;
94a407cc 1966 void __iomem *dp_com = qmp->dp_com;
e991c2ee 1967 int ret;
94a407cc 1968
94a407cc
DB		 1969 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1970 if (ret) {
1971 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
65753f38 1972 return ret;
94a407cc
DB		 1973 }
1974
e991c2ee
DB		 1975 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
1976 if (ret) {
1977 dev_err(qmp->dev, "reset assert failed\n");
1978 goto err_disable_regulators;
94a407cc
DB		 1979 }
1980
e991c2ee
DB		 1981 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
1982 if (ret) {
1983 dev_err(qmp->dev, "reset deassert failed\n");
1984 goto err_disable_regulators;
94a407cc
DB		 1985 }
1986
1987 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1988 if (ret)
1989 goto err_assert_reset;
1990
1991 if (cfg->has_phy_dp_com_ctrl) {
1992 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
1993 SW_PWRDN);
1994 /* override hardware control for reset of qmp phy */
1995 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1996 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1997 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1998
1999 /* Default type-c orientation, i.e CC1 */
2000 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
2001
2002 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
2003 USB3_MODE | DP_MODE);
2004
2005 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
2006 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2007 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2008 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2009
2010 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
2011 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2012 }
2013
47b009db 2014 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
94a407cc 2015
94a407cc
DB		 2016 return 0;
2017
2018err_assert_reset:
e991c2ee 2019 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
94a407cc
DB		 2020err_disable_regulators:
2021 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
94a407cc
DB		 2022
2023 return ret;
2024}
2025
fe2da191 2026static int qmp_usb_exit(struct phy *phy)
94a407cc 2027{
2a55ec4f
JH		 2028 struct qmp_usb *qmp = phy_get_drvdata(phy);
2029 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 2030
e991c2ee 2031 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
94a407cc
DB		 2032
2033 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2034
2035 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2036
94a407cc
DB		 2037 return 0;
2038}
2039
b767dedc 2040static int qmp_usb_power_on(struct phy *phy)
94a407cc 2041{
2a55ec4f
JH		 2042 struct qmp_usb *qmp = phy_get_drvdata(phy);
2043 const struct qmp_phy_cfg *cfg = qmp->cfg;
2044 void __iomem *tx = qmp->tx;
2045 void __iomem *rx = qmp->rx;
2046 void __iomem *pcs = qmp->pcs;
94a407cc 2047 void __iomem *status;
f5ef85ad 2048 unsigned int val;
94a407cc
DB		 2049 int ret;
2050
2a55ec4f 2051 qmp_usb_serdes_init(qmp);
94a407cc 2052
2a55ec4f 2053 ret = clk_prepare_enable(qmp->pipe_clk);
94a407cc
DB		 2054 if (ret) {
2055 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
faf83af5 2056 return ret;
94a407cc
DB		 2057 }
2058
2059 /* Tx, Rx, and PCS configurations */
9d452c3a 2060 qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
94a407cc 2061
9d452c3a 2062 if (cfg->lanes >= 2)
2a55ec4f 2063 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
94a407cc 2064
9d452c3a 2065 qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
94a407cc 2066
9d452c3a 2067 if (cfg->lanes >= 2)
2a55ec4f 2068 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
94a407cc 2069
9d452c3a 2070 qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
94a407cc 2071
94a407cc 2072 if (cfg->has_pwrdn_delay)
38cd167d 2073 usleep_range(10, 20);
94a407cc 2074
86f5dddd 2075 /* Pull PHY out of reset state */
faf83af5
DB		 2076 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2077
86f5dddd 2078 /* start SerDes and Phy-Coding-Sublayer */
47b009db 2079 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
94a407cc 2080
86f5dddd 2081 status = pcs + cfg->regs[QPHY_PCS_STATUS];
7612890b 2082 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
86f5dddd
DB		 2083 PHY_INIT_COMPLETE_TIMEOUT);
2084 if (ret) {
2085 dev_err(qmp->dev, "phy initialization timed-out\n");
2086 goto err_disable_pipe_clk;
94a407cc 2087 }
86f5dddd 2088
94a407cc
DB		 2089 return 0;
2090
2091err_disable_pipe_clk:
2a55ec4f 2092 clk_disable_unprepare(qmp->pipe_clk);
94a407cc
DB		 2093
2094 return ret;
2095}
2096
b767dedc 2097static int qmp_usb_power_off(struct phy *phy)
94a407cc 2098{
2a55ec4f
JH		 2099 struct qmp_usb *qmp = phy_get_drvdata(phy);
2100 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 2101
2a55ec4f 2102 clk_disable_unprepare(qmp->pipe_clk);
94a407cc 2103
86f5dddd 2104 /* PHY reset */
2a55ec4f 2105 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
94a407cc 2106
86f5dddd 2107 /* stop SerDes and Phy-Coding-Sublayer */
2a55ec4f 2108 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
47b009db 2109 SERDES_START | PCS_START);
94a407cc 2110
86f5dddd 2111 /* Put PHY into POWER DOWN state: active low */
2a55ec4f 2112 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
47b009db 2113 SW_PWRDN);
94a407cc
DB		 2114
2115 return 0;
2116}
2117
b767dedc 2118static int qmp_usb_enable(struct phy *phy)
94a407cc
DB		 2119{
2120 int ret;
2121
b767dedc 2122 ret = qmp_usb_init(phy);
94a407cc
DB		 2123 if (ret)
2124 return ret;
2125
b767dedc 2126 ret = qmp_usb_power_on(phy);
94a407cc 2127 if (ret)
b767dedc 2128 qmp_usb_exit(phy);
94a407cc
DB		 2129
2130 return ret;
2131}
2132
b767dedc 2133static int qmp_usb_disable(struct phy *phy)
94a407cc
DB		 2134{
2135 int ret;
2136
b767dedc 2137 ret = qmp_usb_power_off(phy);
94a407cc
DB		 2138 if (ret)
2139 return ret;
b767dedc 2140 return qmp_usb_exit(phy);
94a407cc
DB		 2141}
2142
b767dedc 2143static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
94a407cc 2144{
2a55ec4f 2145 struct qmp_usb *qmp = phy_get_drvdata(phy);
94a407cc 2146
2a55ec4f 2147 qmp->mode = mode;
94a407cc
DB		 2148
2149 return 0;
2150}
2151
2a55ec4f 2152static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)
94a407cc 2153{
2a55ec4f
JH		 2154 const struct qmp_phy_cfg *cfg = qmp->cfg;
2155 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2156 void __iomem *pcs_misc = qmp->pcs_misc;
94a407cc
DB		 2157 u32 intr_mask;
2158
2a55ec4f
JH		 2159 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2160 qmp->mode == PHY_MODE_USB_DEVICE_SS)
94a407cc
DB		 2161 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2162 else
2163 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2164
2165 /* Clear any pending interrupts status */
fc646236 2166 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 2167 /* Writing 1 followed by 0 clears the interrupt */
fc646236 2168 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 2169
fc646236 2170 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
94a407cc
DB		 2171 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2172
2173 /* Enable required PHY autonomous mode interrupts */
fc646236 2174 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
94a407cc
DB		 2175
2176 /* Enable i/o clamp_n for autonomous mode */
2177 if (pcs_misc)
2178 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2179}
2180
2a55ec4f 2181static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
94a407cc 2182{
2a55ec4f
JH		 2183 const struct qmp_phy_cfg *cfg = qmp->cfg;
2184 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2185 void __iomem *pcs_misc = qmp->pcs_misc;
94a407cc
DB		 2186
2187 /* Disable i/o clamp_n on resume for normal mode */
2188 if (pcs_misc)
2189 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2190
fc646236 2191 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
94a407cc
DB		 2192 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2193
fc646236 2194 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 2195 /* Writing 1 followed by 0 clears the interrupt */
fc646236 2196 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc
DB		 2197}
2198
b767dedc 2199static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)
94a407cc 2200{
2a55ec4f
JH		 2201 struct qmp_usb *qmp = dev_get_drvdata(dev);
2202 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 2203
2a55ec4f 2204 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
94a407cc 2205
2a55ec4f 2206 if (!qmp->phy->init_count) {
94a407cc
DB		 2207 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2208 return 0;
2209 }
2210
2a55ec4f 2211 qmp_usb_enable_autonomous_mode(qmp);
94a407cc 2212
2a55ec4f 2213 clk_disable_unprepare(qmp->pipe_clk);
94a407cc
DB		 2214 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2215
2216 return 0;
2217}
2218
b767dedc 2219static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)
94a407cc 2220{
2a55ec4f
JH		 2221 struct qmp_usb *qmp = dev_get_drvdata(dev);
2222 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc
DB		 2223 int ret = 0;
2224
2a55ec4f 2225 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
94a407cc 2226
2a55ec4f 2227 if (!qmp->phy->init_count) {
94a407cc
DB		 2228 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2229 return 0;
2230 }
2231
2232 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2233 if (ret)
2234 return ret;
2235
2a55ec4f 2236 ret = clk_prepare_enable(qmp->pipe_clk);
94a407cc
DB		 2237 if (ret) {
2238 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2239 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2240 return ret;
2241 }
2242
2a55ec4f 2243 qmp_usb_disable_autonomous_mode(qmp);
94a407cc
DB		 2244
2245 return 0;
2246}
2247
9c9beef1
JH		 2248static const struct dev_pm_ops qmp_usb_pm_ops = {
2249 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,
2250 qmp_usb_runtime_resume, NULL)
2251};
2252
413db06c 2253static int qmp_usb_vreg_init(struct qmp_usb *qmp)
94a407cc 2254{
413db06c
JH		 2255 const struct qmp_phy_cfg *cfg = qmp->cfg;
2256 struct device *dev = qmp->dev;
94a407cc
DB		 2257 int num = cfg->num_vregs;
2258 int i;
2259
2260 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2261 if (!qmp->vregs)
2262 return -ENOMEM;
2263
2264 for (i = 0; i < num; i++)
2265 qmp->vregs[i].supply = cfg->vreg_list[i];
2266
2267 return devm_regulator_bulk_get(dev, num, qmp->vregs);
2268}
2269
413db06c 2270static int qmp_usb_reset_init(struct qmp_usb *qmp)
94a407cc 2271{
413db06c
JH		 2272 const struct qmp_phy_cfg *cfg = qmp->cfg;
2273 struct device *dev = qmp->dev;
94a407cc 2274 int i;
e991c2ee 2275 int ret;
94a407cc
DB		 2276
2277 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
2278 sizeof(*qmp->resets), GFP_KERNEL);
2279 if (!qmp->resets)
2280 return -ENOMEM;
2281
e991c2ee
DB		 2282 for (i = 0; i < cfg->num_resets; i++)
2283 qmp->resets[i].id = cfg->reset_list[i];
94a407cc 2284
e991c2ee
DB		 2285 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
2286 if (ret)
2287 return dev_err_probe(dev, ret, "failed to get resets\n");
94a407cc
DB		 2288
2289 return 0;
2290}
2291
413db06c 2292static int qmp_usb_clk_init(struct qmp_usb *qmp)
94a407cc 2293{
413db06c
JH		 2294 const struct qmp_phy_cfg *cfg = qmp->cfg;
2295 struct device *dev = qmp->dev;
94a407cc
DB		 2296 int num = cfg->num_clks;
2297 int i;
2298
2299 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2300 if (!qmp->clks)
2301 return -ENOMEM;
2302
2303 for (i = 0; i < num; i++)
2304 qmp->clks[i].id = cfg->clk_list[i];
2305
2306 return devm_clk_bulk_get(dev, num, qmp->clks);
2307}
2308
2309static void phy_clk_release_provider(void *res)
2310{
2311 of_clk_del_provider(res);
2312}
2313
2314/*
2315 * Register a fixed rate pipe clock.
2316 *
2317 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2318 * controls it. The <s>_pipe_clk coming out of the GCC is requested
2319 * by the PHY driver for its operations.
2320 * We register the <s>_pipe_clksrc here. The gcc driver takes care
2321 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2322 * Below picture shows this relationship.
2323 *
2324 * +---------------+
2325 * | PHY block |<<---------------------------------------+
2326 * | | |
2327 * | +-------+ | +-----+ |
2328 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2329 * clk | +-------+ | +-----+
2330 * +---------------+
2331 */
2a55ec4f 2332static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np)
94a407cc
DB		 2333{
2334 struct clk_fixed_rate *fixed;
2335 struct clk_init_data init = { };
2336 int ret;
2337
2338 ret = of_property_read_string(np, "clock-output-names", &init.name);
2339 if (ret) {
2340 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2341 return ret;
2342 }
2343
2344 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
2345 if (!fixed)
2346 return -ENOMEM;
2347
2348 init.ops = &clk_fixed_rate_ops;
2349
2350 /* controllers using QMP phys use 125MHz pipe clock interface */
2351 fixed->fixed_rate = 125000000;
2352 fixed->hw.init = &init;
2353
2354 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2355 if (ret)
2356 return ret;
2357
2358 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2359 if (ret)
2360 return ret;
2361
2362 /*
2363 * Roll a devm action because the clock provider is the child node, but
2364 * the child node is not actually a device.
2365 */
2366 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2367}
2368
b767dedc
JH		 2369static const struct phy_ops qmp_usb_ops = {
2370 .init = qmp_usb_enable,
2371 .exit = qmp_usb_disable,
2372 .set_mode = qmp_usb_set_mode,
94a407cc
DB		 2373 .owner = THIS_MODULE,
2374};
2375
a5d6b1ac
JH		 2376static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
2377 int index, bool exclusive)
2378{
2379 struct resource res;
2380
2381 if (!exclusive) {
2382 if (of_address_to_resource(np, index, &res))
2383 return IOMEM_ERR_PTR(-EINVAL);
2384
2385 return devm_ioremap(dev, res.start, resource_size(&res));
2386 }
2387
2388 return devm_of_iomap(dev, np, index, NULL);
2389}
2390
413db06c 2391static int qmp_usb_create(struct qmp_usb *qmp, struct device_node *np)
94a407cc 2392{
413db06c
JH		 2393 const struct qmp_phy_cfg *cfg = qmp->cfg;
2394 struct device *dev = qmp->dev;
94a407cc 2395 struct phy *generic_phy;
a5d6b1ac 2396 bool exclusive = true;
94a407cc
DB		 2397 int ret;
2398
a5d6b1ac
JH		 2399 /*
2400 * FIXME: These bindings should be fixed to not rely on overlapping
2401 * mappings for PCS.
2402 */
2403 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
2404 exclusive = false;
2405 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
2406 exclusive = false;
2407
94a407cc 2408 /*
8d3bf724 2409 * Get memory resources for the PHY:
94a407cc
DB		 2410 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2411 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2412 * For single lane PHYs: pcs_misc (optional) -> 3.
2413 */
2a55ec4f
JH		 2414 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2415 if (IS_ERR(qmp->tx))
2416 return PTR_ERR(qmp->tx);
94a407cc 2417
2a55ec4f
JH		 2418 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2419 if (IS_ERR(qmp->rx))
2420 return PTR_ERR(qmp->rx);
94a407cc 2421
2a55ec4f
JH		 2422 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
2423 if (IS_ERR(qmp->pcs))
2424 return PTR_ERR(qmp->pcs);
94a407cc 2425
fc646236 2426 if (cfg->pcs_usb_offset)
2a55ec4f 2427 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
fc646236 2428
a73a19ea 2429 if (cfg->lanes >= 2) {
2a55ec4f
JH		 2430 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2431 if (IS_ERR(qmp->tx2))
2432 return PTR_ERR(qmp->tx2);
94a407cc 2433
2a55ec4f
JH		 2434 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2435 if (IS_ERR(qmp->rx2))
2436 return PTR_ERR(qmp->rx2);
94a407cc 2437
2a55ec4f 2438 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
94a407cc 2439 } else {
2a55ec4f 2440 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
94a407cc
DB		 2441 }
2442
2a55ec4f 2443 if (IS_ERR(qmp->pcs_misc)) {
94a407cc 2444 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2a55ec4f 2445 qmp->pcs_misc = NULL;
a5d6b1ac 2446 }
94a407cc 2447
2a55ec4f
JH		 2448 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
2449 if (IS_ERR(qmp->pipe_clk)) {
2450 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2451 "failed to get pipe clock\n");
94a407cc
DB		 2452 }
2453
b767dedc 2454 generic_phy = devm_phy_create(dev, np, &qmp_usb_ops);
94a407cc
DB		 2455 if (IS_ERR(generic_phy)) {
2456 ret = PTR_ERR(generic_phy);
2a55ec4f 2457 dev_err(dev, "failed to create PHY: %d\n", ret);
94a407cc
DB		 2458 return ret;
2459 }
2460
2a55ec4f
JH		 2461 qmp->phy = generic_phy;
2462 phy_set_drvdata(generic_phy, qmp);
94a407cc
DB		 2463
2464 return 0;
2465}
2466
b767dedc 2467static int qmp_usb_probe(struct platform_device *pdev)
94a407cc 2468{
94a407cc
DB		 2469 struct device *dev = &pdev->dev;
2470 struct device_node *child;
2471 struct phy_provider *phy_provider;
2a55ec4f 2472 struct qmp_usb *qmp;
94a407cc
DB		 2473 int ret;
2474
2475 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2476 if (!qmp)
2477 return -ENOMEM;
2478
2479 qmp->dev = dev;
94a407cc 2480
413db06c
JH		 2481 qmp->cfg = of_device_get_match_data(dev);
2482 if (!qmp->cfg)
8c924330 2483 return -EINVAL;
94a407cc 2484
413db06c
JH		 2485 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2486 if (IS_ERR(qmp->serdes))
2487 return PTR_ERR(qmp->serdes);
94a407cc 2488
413db06c 2489 if (qmp->cfg->has_phy_dp_com_ctrl) {
94a407cc
DB		 2490 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
2491 if (IS_ERR(qmp->dp_com))
2492 return PTR_ERR(qmp->dp_com);
2493 }
2494
413db06c 2495 ret = qmp_usb_clk_init(qmp);
94a407cc
DB		 2496 if (ret)
2497 return ret;
2498
413db06c 2499 ret = qmp_usb_reset_init(qmp);
94a407cc
DB		 2500 if (ret)
2501 return ret;
2502
413db06c 2503 ret = qmp_usb_vreg_init(qmp);
add7000b 2504 if (ret)
28d74fc3 2505 return ret;
94a407cc 2506
8ec02ba8
JH		 2507 child = of_get_next_available_child(dev->of_node, NULL);
2508 if (!child)
94a407cc
DB		 2509 return -EINVAL;
2510
94a407cc 2511 pm_runtime_set_active(dev);
e57655e6
JH		 2512 ret = devm_pm_runtime_enable(dev);
2513 if (ret)
8ec02ba8 2514 goto err_node_put;
94a407cc
DB		 2515 /*
2516 * Prevent runtime pm from being ON by default. Users can enable
2517 * it using power/control in sysfs.
2518 */
2519 pm_runtime_forbid(dev);
2520
413db06c 2521 ret = qmp_usb_create(qmp, child);
8ec02ba8
JH		 2522 if (ret)
2523 goto err_node_put;
2524
2525 ret = phy_pipe_clk_register(qmp, child);
2526 if (ret)
2527 goto err_node_put;
2528
2529 of_node_put(child);
94a407cc
DB		 2530
2531 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
94a407cc
DB		 2532
2533 return PTR_ERR_OR_ZERO(phy_provider);
2534
2535err_node_put:
94a407cc
DB		 2536 of_node_put(child);
2537 return ret;
2538}
2539
95dd63b8
JH		 2540static const struct of_device_id qmp_usb_of_match_table[] = {
2541 {
2542 .compatible = "qcom,ipq6018-qmp-usb3-phy",
2543 .data = &ipq8074_usb3phy_cfg,
2544 }, {
2545 .compatible = "qcom,ipq8074-qmp-usb3-phy",
2546 .data = &ipq8074_usb3phy_cfg,
2547 }, {
2548 .compatible = "qcom,msm8996-qmp-usb3-phy",
2549 .data = &msm8996_usb3phy_cfg,
2550 }, {
2551 .compatible = "qcom,msm8998-qmp-usb3-phy",
2552 .data = &msm8998_usb3phy_cfg,
2553 }, {
2554 .compatible = "qcom,qcm2290-qmp-usb3-phy",
2555 .data = &qcm2290_usb3phy_cfg,
2556 }, {
2557 .compatible = "qcom,sc7180-qmp-usb3-phy",
2558 .data = &sc7180_usb3phy_cfg,
2559 }, {
2560 .compatible = "qcom,sc8180x-qmp-usb3-phy",
2561 .data = &sm8150_usb3phy_cfg,
2562 }, {
2563 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
2564 .data = &sc8280xp_usb3_uniphy_cfg,
2565 }, {
2566 .compatible = "qcom,sdm845-qmp-usb3-phy",
2567 .data = &qmp_v3_usb3phy_cfg,
2568 }, {
2569 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2570 .data = &qmp_v3_usb3_uniphy_cfg,
2571 }, {
2572 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2573 .data = &sdx55_usb3_uniphy_cfg,
2574 }, {
2575 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2576 .data = &sdx65_usb3_uniphy_cfg,
2577 }, {
2578 .compatible = "qcom,sm8150-qmp-usb3-phy",
2579 .data = &sm8150_usb3phy_cfg,
2580 }, {
2581 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2582 .data = &sm8150_usb3_uniphy_cfg,
2583 }, {
2584 .compatible = "qcom,sm8250-qmp-usb3-phy",
2585 .data = &sm8250_usb3phy_cfg,
2586 }, {
2587 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2588 .data = &sm8250_usb3_uniphy_cfg,
2589 }, {
2590 .compatible = "qcom,sm8350-qmp-usb3-phy",
2591 .data = &sm8350_usb3phy_cfg,
2592 }, {
2593 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2594 .data = &sm8350_usb3_uniphy_cfg,
2595 }, {
2596 .compatible = "qcom,sm8450-qmp-usb3-phy",
2597 .data = &sm8350_usb3phy_cfg,
2598 },
2599 { },
2600};
2601MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);
2602
b767dedc
JH		 2603static struct platform_driver qmp_usb_driver = {
2604 .probe = qmp_usb_probe,
94a407cc 2605 .driver = {
8c924330 2606 .name = "qcom-qmp-usb-phy",
b767dedc
JH		 2607 .pm = &qmp_usb_pm_ops,
2608 .of_match_table = qmp_usb_of_match_table,
94a407cc
DB		 2609 },
2610};
2611
b767dedc 2612module_platform_driver(qmp_usb_driver);
94a407cc
DB		 2613
2614MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
8c924330 2615MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
94a407cc 2616MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)