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phy: qcom-qmp-pcie: add support for sc8280xp 4-lane PHYs
[linux-2.6-block.git] / drivers / phy / qualcomm / phy-qcom-qmp-pcie.c
CommitLineData
94a407cc
DB		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
6c37a02b 13#include <linux/mfd/syscon.h>
94a407cc
DB		 14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/of_address.h>
11bf53a3 18#include <linux/phy/pcie.h>
94a407cc
DB		 19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
6c37a02b 21#include <linux/regmap.h>
94a407cc
DB		 22#include <linux/regulator/consumer.h>
23#include <linux/reset.h>
24#include <linux/slab.h>
25
26#include <dt-bindings/phy/phy.h>
27
28#include "phy-qcom-qmp.h"
29
30/* QPHY_SW_RESET bit */
31#define SW_RESET BIT(0)
32/* QPHY_POWER_DOWN_CONTROL */
33#define SW_PWRDN BIT(0)
34#define REFCLK_DRV_DSBL BIT(1)
35/* QPHY_START_CONTROL bits */
36#define SERDES_START BIT(0)
37#define PCS_START BIT(1)
94a407cc
DB		 38/* QPHY_PCS_STATUS bit */
39#define PHYSTATUS BIT(6)
40#define PHYSTATUS_4_20 BIT(7)
94a407cc 41
94a407cc 42#define PHY_INIT_COMPLETE_TIMEOUT 10000
94a407cc 43
94a407cc
DB		 44struct qmp_phy_init_tbl {
45 unsigned int offset;
46 unsigned int val;
94a407cc
DB		 47 /*
48 * mask of lanes for which this register is written
49 * for cases when second lane needs different values
50 */
51 u8 lane_mask;
52};
53
54#define QMP_PHY_INIT_CFG(o, v) \
55 { \
56 .offset = o, \
57 .val = v, \
58 .lane_mask = 0xff, \
59 }
60
94a407cc
DB		 61#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
62 { \
63 .offset = o, \
64 .val = v, \
65 .lane_mask = l, \
66 }
67
68/* set of registers with offsets different per-PHY */
69enum qphy_reg_layout {
94a407cc 70 /* PCS registers */
94a407cc
DB		 71 QPHY_SW_RESET,
72 QPHY_START_CTRL,
94a407cc 73 QPHY_PCS_STATUS,
94a407cc 74 QPHY_PCS_POWER_DOWN_CONTROL,
94a407cc
DB		 75 /* Keep last to ensure regs_layout arrays are properly initialized */
76 QPHY_LAYOUT_SIZE
77};
78
94a407cc
DB		 79static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
80 [QPHY_SW_RESET] = 0x00,
81 [QPHY_START_CTRL] = 0x44,
82 [QPHY_PCS_STATUS] = 0x14,
83 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
84};
85
86static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
94a407cc
DB		 87 [QPHY_SW_RESET] = 0x00,
88 [QPHY_START_CTRL] = 0x08,
89 [QPHY_PCS_STATUS] = 0x174,
6d5b1e20 90 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
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DB		 91};
92
94a407cc
DB		 93static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
94 [QPHY_SW_RESET] = 0x00,
95 [QPHY_START_CTRL] = 0x08,
96 [QPHY_PCS_STATUS] = 0x174,
6d5b1e20 97 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
94a407cc
DB		 98};
99
100static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
101 [QPHY_SW_RESET] = 0x00,
102 [QPHY_START_CTRL] = 0x08,
103 [QPHY_PCS_STATUS] = 0x2ac,
6d5b1e20 104 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
94a407cc
DB		 105};
106
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DB		 107static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
108 [QPHY_SW_RESET] = 0x00,
109 [QPHY_START_CTRL] = 0x44,
110 [QPHY_PCS_STATUS] = 0x14,
111 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
112};
113
94a407cc
DB		 114static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
157};
158
159static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
160 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
161 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
162 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
163 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
164};
165
166static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
167 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
168 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
169 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
170 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
171 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
172 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
173 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
174 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
175 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
176 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
177 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
178 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
179 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
180 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
181};
182
183static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
187 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
194};
195
94a407cc
DB		 196static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
197 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
198 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
199 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
200 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
201 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
202 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
203 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
204 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
205 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
206 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
207 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
208 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
209 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
210 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
211 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
212 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
213 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
214 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
215 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
216 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
217 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
218 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
219 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
220 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
221 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
222 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
223 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
224 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
225 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
226 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
227 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
228 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
229 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
230 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
231 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
232 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
233 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
234 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
235 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
236 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
237 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
238 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
239 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
240 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
241 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
242 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
243};
244
245static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
079328a9
DB		 246 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
247 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
248 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
94a407cc
DB		 249};
250
251static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
079328a9
DB		 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01),
268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
280 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
281 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
94a407cc
DB		 282};
283
284static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
60f23414
DB		 285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
286 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
287 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
288 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
289 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
290 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
291 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
af664324
DB		 292};
293
294static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
60f23414
DB		 295 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
296 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
297 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
298 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
299 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
300 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
301 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
302 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
303 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
94a407cc
DB		 304};
305
306static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
307 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
308 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
309 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
310 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
311 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
312 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
313 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
314 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
315 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
316 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
317 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
318 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
319 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
320 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
321 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
322 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
323 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
324 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
325 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
326 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
327 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
328 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
329 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
330 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
331 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
332 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
333 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
334 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
335 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
336 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
337 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
338 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
339 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
340 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
341 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
342 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
343 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
344 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
345 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
346 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
347};
348
349static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
350 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
351 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
352 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
353 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
f7c5cedb 354 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36),
94a407cc
DB		 355 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
356};
357
358static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
359 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
360 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
361 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
362 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
363 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
364 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
365 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
366};
367
368static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
6cad2983
DB		 369 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
370 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
371 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
372 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
373 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
374 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
375 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
c1ab64aa 376 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
6cad2983
DB		 377 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
378 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
379 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
94a407cc
DB		 380};
381
334fad18
RM		 382static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
383 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
384 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
385 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
386 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
387 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
388 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
389 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
390 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
391 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
392 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
393 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
394 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
395 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
396 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
397 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
398 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
399 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
400 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
401 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
402 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
403 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
404 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
405 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
406 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
407 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
408 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
409 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
410 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
411 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
412 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
413 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
414 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
415 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
416 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
417 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
418 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
419 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
420 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
421 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
422 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
423 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
424 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
425 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
426 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
427 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
428 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
429 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
430 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
431 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
432 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
433 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
434 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
435 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
436 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
437 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
438 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
439 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
440};
441
442static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
079328a9
DB		 443 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
444 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
445 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10),
446 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
334fad18
RM		 447};
448
449static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
079328a9
DB		 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe),
454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4),
455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2),
473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
334fad18
RM		 480};
481
482static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
60f23414
DB		 483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83),
484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9),
485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42),
486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40),
487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
495 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb),
497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
499 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
500 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
501 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
505 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
506 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
334fad18
RM		 507};
508
94a407cc
DB		 509static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
552};
553
554static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
555 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
556 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
557 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
558 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
559};
560
561static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
562 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
563 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
564 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
565 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
578};
579
580static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
582
583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
588
589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
596
597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
600
601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
602};
603
604static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
610};
611
612static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
613 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
614 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
615 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
616 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
617 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
618 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
619 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
620 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
621 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
622 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
623 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
624 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
625 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
658};
659
660static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
661 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
667 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
668 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
669 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
717};
718
719static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
720};
721
722static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
726 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
727 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
728 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
729 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
730};
731
b35a5311
DB		 732static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
94a407cc
DB		 775};
776
b35a5311
DB		 777static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
778 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
779 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
94a407cc
DB		 780};
781
b35a5311
DB		 782static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
94a407cc
DB		 819};
820
b35a5311
DB		 821static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
822 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
823 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
824 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
825 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
826 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
94a407cc
DB		 827};
828
b35a5311
DB		 829static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
830 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
831 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
832 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
833 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
834 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
835 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
836 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
94a407cc
DB		 837};
838
d0a846ba
JH		 839static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = {
840 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
841 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
842 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
843 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
844 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
845 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
846 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
847 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
848 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
849 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
850 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
851 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
852 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
853 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
854 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
855 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
856 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
857 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
858 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
859 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
860 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
861 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
862 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
863 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
864 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
865 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
866 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
867 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
868 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
869 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
870 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
871 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
872 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
873 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
874 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
875 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
876 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9),
877 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
878 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94),
879 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
880 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
881};
882
883static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
884 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
885};
886
887static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
888 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
889};
890
6c37a02b
JH		 891static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = {
892 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
893};
894
d0a846ba
JH		 895static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = {
896 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
897 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
898 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
899 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
900 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
901};
902
903static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = {
904 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
905 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
906 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
907 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
908 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
909 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
910 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
911 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
912 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
913 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
914 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
915 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
916 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
917 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
918 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
919 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
920 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
921 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
922};
923
924static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = {
925 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
926 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
927 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
928};
929
930static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
931 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
932 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
933 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
934 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
935};
936
937static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = {
938 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
939 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
940 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
941 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
942 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
943 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
944};
945
946static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = {
947 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
948 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
949 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
950 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
951 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
952 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
953 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
954 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
955 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
956 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
957 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
958 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
959 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
960 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
961 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
962 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
963 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
964};
965
966static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = {
967 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
968 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88),
969 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
970 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f),
971};
972
973static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
974 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
975 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
976 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
977 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
978};
979
94a407cc
DB		 980static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
981 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
982 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
983 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
984 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
985 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
986 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1022};
1023
1024static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
1025 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
1026};
1027
1028static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
1029 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1030 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
1031 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1032};
1033
1034static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
1035 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1036 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
1037 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
1038 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1039 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1040 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
1041 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
1042 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
1043 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1044 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
1045 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1046 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1047 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1048 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
1049 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
1050 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1051 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
1052 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
1053 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
1054 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
1055 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1056 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
1057 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
1058 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
1059 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1060 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1061 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
1062 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
1063 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1064 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
1065};
1066
1067static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
1068 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
1069 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
1070 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1071 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
1072 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
1073 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1074};
1075
1076static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
1077 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1078 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
1079 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
1080};
1081
1082static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
1083 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
1084 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
1085};
1086
1087static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
1088 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1089 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1090 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1091 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
1092 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
1093 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
1094 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1095};
1096
1097static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1098 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1099 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
1100};
1101
1102static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
1103 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1104};
1105
1106static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
1107 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
1108 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1109 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
1110 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1111};
1112
1113static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
1114 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
1115 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
1116};
1117
1118static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1119 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
1120 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1121};
1122
94a407cc
DB		 1123static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
1124 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
1125 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
1126 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
1127 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1128 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
1129 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
1130 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
1131 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
1132 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
1133 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
1134 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
1135 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
1136 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
1137 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
1138 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
1139 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
1140 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
1141 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
1142 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
1143 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
1144 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1145 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1146 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1147 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1148 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1149 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
1150 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1151 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
1152 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
1153 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
1154 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
1195c1da 1155 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),
94a407cc
DB		 1156 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
1157 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
1158 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
1159 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
1160 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
1161 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
1162 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
1163};
1164
1165static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
1166 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
1167 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
1168 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
1169 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
1170 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
1171};
1172
1173static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
1174 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
1175 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
1176 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
1177 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
1178 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
1179 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
1180 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
1181 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
1182 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
1183 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
1184 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
1185 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
1186 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
1187 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
1188 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
1189 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
1190 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
1191 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
1192 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
1193 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
1194 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
1195 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
1196 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
1197 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1198 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
1199};
1200
1201static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
1202 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
1203 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
1204 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
1205 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
1206};
1207
1208static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
1209 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
1210 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
1211 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
1212 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
1213 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1214 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
1215 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1216};
1217
94a407cc
DB		 1218static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
1219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
1226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
1227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1229 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1230 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1231 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1232 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1233 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1234 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1235 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
1236 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1237 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
1238 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1239 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1240 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1241 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1242 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1243 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1244 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1245 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1246 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1247 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1248 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1249 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1250 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1251 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1252 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
1253 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1254 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1255 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1256 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1257 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1258 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1259 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1260 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1261};
1262
1263static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
1264 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1265 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1266 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1267 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
1268 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
1269};
1270
1271static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
1272 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1273 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1274 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1275 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1276 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1277 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1278 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
1279 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
1280 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1281 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1282 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1283 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
1284 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1285 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1286 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1287 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1288 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1289 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1290 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
1291 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
1292 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
1293 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1294};
1295
1296static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
1297 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
1298 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1299 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
1300};
1301
1302static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1303 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1304 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1305 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
1306 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1307};
1308
1309static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
f5682f13
DB		 1310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
1322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
1323};
1324
1325static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = {
94a407cc
DB		 1326 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1327 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1328 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1329 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1330 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
1331 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
94a407cc 1332 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
94a407cc
DB		 1333 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1334 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1335 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1336 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1337 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1338 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1339 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
94a407cc
DB		 1340 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1341 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1342 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1343 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1344 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1345 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
1346 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1347 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1348 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1349 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1350 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
1351 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
94a407cc 1352 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
94a407cc 1353 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
94a407cc
DB		 1354};
1355
1356static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
1357 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
1358 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
1359 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1360 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1361};
1362
1363static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
1364 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
1365 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1366 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
1367 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
1368 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
1369 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
1370 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
1371 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
1372 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
1373 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
1374 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
1375 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
1376 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
1377 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
1378 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
1379 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
1380 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
1381 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
1382 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
1383 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
1384 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
1385 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
1386 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
1387 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
1388
1389 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
1390
1391 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1392
1393 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1394 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1395 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1396 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1397 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1398 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1399 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1400 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1401
1402 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1403 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
1404 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1405 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1406 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
1407 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
1408 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
1409 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
1410 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
1411};
1412
94a407cc
DB		 1413static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
1414 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
1415 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
1416 QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
1417 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
1418};
1419
1420static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
94a407cc
DB		 1421 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1422 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
1423 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
1424 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
1425};
1426
f5682f13
DB		 1427static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = {
1428 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1429 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1430};
1431
1432static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = {
1433 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
1434 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
1435 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
1436 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
1437 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
1438 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
1439 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
1440 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
1441 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
1442 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
1443 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
1444 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
1445 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
1446 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
1447 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
1448 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1449 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1450 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1451 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1452 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1453};
1454
1455static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = {
1456 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
1457};
1458
d0a846ba
JH		 1459struct qmp_pcie_offsets {
1460 u16 serdes;
1461 u16 pcs;
1462 u16 pcs_misc;
1463 u16 tx;
1464 u16 rx;
1465 u16 tx2;
1466 u16 rx2;
1467};
1468
d8c9a1e9 1469struct qmp_phy_cfg_tbls {
2566ad8e
DB		 1470 const struct qmp_phy_init_tbl *serdes;
1471 int serdes_num;
1472 const struct qmp_phy_init_tbl *tx;
1473 int tx_num;
1474 const struct qmp_phy_init_tbl *rx;
1475 int rx_num;
1476 const struct qmp_phy_init_tbl *pcs;
1477 int pcs_num;
1478 const struct qmp_phy_init_tbl *pcs_misc;
1479 int pcs_misc_num;
1480};
1481
94a407cc
DB		 1482/* struct qmp_phy_cfg - per-PHY initialization config */
1483struct qmp_phy_cfg {
f02543fa 1484 int lanes;
94a407cc 1485
d0a846ba
JH		 1486 const struct qmp_pcie_offsets *offsets;
1487
2566ad8e 1488 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
d8c9a1e9 1489 const struct qmp_phy_cfg_tbls tbls;
2566ad8e 1490 /*
11bf53a3
DB		 1491 * Additional init sequences for PHY blocks, providing additional
1492 * register programming. They are used for providing separate sequences
1493 * for the Root Complex and End Point use cases.
1494 *
1495 * If EP mode is not supported, both tables can be left unset.
2566ad8e 1496 */
d8c9a1e9
JH		 1497 const struct qmp_phy_cfg_tbls *tbls_rc;
1498 const struct qmp_phy_cfg_tbls *tbls_ep;
94a407cc 1499
6c37a02b
JH		 1500 const struct qmp_phy_init_tbl *serdes_4ln_tbl;
1501 int serdes_4ln_num;
1502
94a407cc
DB		 1503 /* clock ids to be requested */
1504 const char * const *clk_list;
1505 int num_clks;
1506 /* resets to be requested */
1507 const char * const *reset_list;
1508 int num_resets;
1509 /* regulators to be requested */
1510 const char * const *vreg_list;
1511 int num_vregs;
1512
1513 /* array of registers with different offsets */
1514 const unsigned int *regs;
1515
94a407cc 1516 unsigned int pwrdn_ctrl;
94a407cc
DB		 1517 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
1518 unsigned int phy_status;
1519
51bd3306 1520 bool skip_start_delay;
94a407cc 1521
2ec9bc8d
RM		 1522 /* QMP PHY pipe clock interface rate */
1523 unsigned long pipe_clock_rate;
94a407cc
DB		 1524};
1525
2fdedef3
JH		 1526struct qmp_pcie {
1527 struct device *dev;
1528
94a407cc 1529 const struct qmp_phy_cfg *cfg;
6c37a02b 1530 bool tcsr_4ln_config;
2fdedef3 1531
94a407cc 1532 void __iomem *serdes;
2fdedef3
JH		 1533 void __iomem *pcs;
1534 void __iomem *pcs_misc;
94a407cc
DB		 1535 void __iomem *tx;
1536 void __iomem *rx;
94a407cc
DB		 1537 void __iomem *tx2;
1538 void __iomem *rx2;
94a407cc 1539
6c37a02b
JH		 1540 void __iomem *port_b;
1541
b35a5311 1542 struct clk_bulk_data *clks;
9e420f1e
JH		 1543 struct clk_bulk_data pipe_clks[2];
1544 int num_pipe_clks;
1545
189ac6b8 1546 struct reset_control_bulk_data *resets;
b35a5311 1547 struct regulator_bulk_data *vregs;
94a407cc 1548
2fdedef3
JH		 1549 struct phy *phy;
1550 int mode;
94a407cc
DB		 1551};
1552
b35a5311
DB		 1553static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1554{
1555 u32 reg;
94a407cc 1556
b35a5311
DB		 1557 reg = readl(base + offset);
1558 reg |= val;
1559 writel(reg, base + offset);
94a407cc 1560
b35a5311
DB		 1561 /* ensure that above write is through */
1562 readl(base + offset);
1563}
94a407cc 1564
b35a5311
DB		 1565static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1566{
1567 u32 reg;
94a407cc 1568
b35a5311
DB		 1569 reg = readl(base + offset);
1570 reg &= ~val;
1571 writel(reg, base + offset);
94a407cc 1572
b35a5311
DB		 1573 /* ensure that above write is through */
1574 readl(base + offset);
1575}
94a407cc 1576
b35a5311 1577/* list of clocks required by phy */
5b76f5ec
JH		 1578static const char * const ipq8074_pciephy_clk_l[] = {
1579 "aux", "cfg_ahb",
1580};
1581
b35a5311
DB		 1582static const char * const msm8996_phy_clk_l[] = {
1583 "aux", "cfg_ahb", "ref",
94a407cc
DB		 1584};
1585
d0a846ba
JH		 1586static const char * const sc8280xp_pciephy_clk_l[] = {
1587 "aux", "cfg_ahb", "ref", "rchng",
1588};
94a407cc 1589
b35a5311
DB		 1590static const char * const sdm845_pciephy_clk_l[] = {
1591 "aux", "cfg_ahb", "ref", "refgen",
1592};
94a407cc 1593
b35a5311
DB		 1594/* list of regulators */
1595static const char * const qmp_phy_vreg_l[] = {
1596 "vdda-phy", "vdda-pll",
94a407cc
DB		 1597};
1598
94a407cc
DB		 1599/* list of resets */
1600static const char * const ipq8074_pciephy_reset_l[] = {
1601 "phy", "common",
1602};
1603
b35a5311
DB		 1604static const char * const sdm845_pciephy_reset_l[] = {
1605 "phy",
1606};
1607
d0a846ba
JH		 1608static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
1609 .serdes = 0,
1610 .pcs = 0x0200,
1611 .pcs_misc = 0x0600,
1612 .tx = 0x0e00,
1613 .rx = 0x1000,
1614 .tx2 = 0x1600,
1615 .rx2 = 0x1800,
1616};
1617
94a407cc 1618static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
f02543fa 1619 .lanes = 1,
94a407cc 1620
d8c9a1e9 1621 .tbls = {
2566ad8e
DB		 1622 .serdes = ipq8074_pcie_serdes_tbl,
1623 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
1624 .tx = ipq8074_pcie_tx_tbl,
1625 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
1626 .rx = ipq8074_pcie_rx_tbl,
1627 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
1628 .pcs = ipq8074_pcie_pcs_tbl,
1629 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
1630 },
94a407cc
DB		 1631 .clk_list = ipq8074_pciephy_clk_l,
1632 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
1633 .reset_list = ipq8074_pciephy_reset_l,
1634 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1635 .vreg_list = NULL,
1636 .num_vregs = 0,
1637 .regs = pciephy_regs_layout,
1638
94a407cc
DB		 1639 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1640 .phy_status = PHYSTATUS,
94a407cc
DB		 1641};
1642
334fad18 1643static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
f02543fa 1644 .lanes = 1,
334fad18 1645
d8c9a1e9 1646 .tbls = {
2566ad8e
DB		 1647 .serdes = ipq8074_pcie_gen3_serdes_tbl,
1648 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
1649 .tx = ipq8074_pcie_gen3_tx_tbl,
1650 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
1651 .rx = ipq8074_pcie_gen3_rx_tbl,
1652 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
1653 .pcs = ipq8074_pcie_gen3_pcs_tbl,
1654 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
1655 },
334fad18
RM		 1656 .clk_list = ipq8074_pciephy_clk_l,
1657 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
1658 .reset_list = ipq8074_pciephy_reset_l,
1659 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1660 .vreg_list = NULL,
1661 .num_vregs = 0,
1662 .regs = ipq_pciephy_gen3_regs_layout,
1663
334fad18 1664 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
94b7288e 1665 .phy_status = PHYSTATUS,
334fad18 1666
334fad18
RM		 1667 .pipe_clock_rate = 250000000,
1668};
1669
94a407cc 1670static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
f02543fa 1671 .lanes = 1,
94a407cc 1672
d8c9a1e9 1673 .tbls = {
2566ad8e
DB		 1674 .serdes = ipq6018_pcie_serdes_tbl,
1675 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
1676 .tx = ipq6018_pcie_tx_tbl,
1677 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
1678 .rx = ipq6018_pcie_rx_tbl,
1679 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
1680 .pcs = ipq6018_pcie_pcs_tbl,
1681 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
1682 .pcs_misc = ipq6018_pcie_pcs_misc_tbl,
1683 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
1684 },
94a407cc
DB		 1685 .clk_list = ipq8074_pciephy_clk_l,
1686 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
1687 .reset_list = ipq8074_pciephy_reset_l,
1688 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1689 .vreg_list = NULL,
1690 .num_vregs = 0,
1691 .regs = ipq_pciephy_gen3_regs_layout,
1692
94a407cc 1693 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
30518b19 1694 .phy_status = PHYSTATUS,
94a407cc
DB		 1695};
1696
1697static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
f02543fa 1698 .lanes = 1,
94a407cc 1699
d8c9a1e9 1700 .tbls = {
2566ad8e
DB		 1701 .serdes = sdm845_qmp_pcie_serdes_tbl,
1702 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
1703 .tx = sdm845_qmp_pcie_tx_tbl,
1704 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
1705 .rx = sdm845_qmp_pcie_rx_tbl,
1706 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
1707 .pcs = sdm845_qmp_pcie_pcs_tbl,
1708 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
1709 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl,
1710 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
1711 },
94a407cc
DB		 1712 .clk_list = sdm845_pciephy_clk_l,
1713 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
1714 .reset_list = sdm845_pciephy_reset_l,
1715 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1716 .vreg_list = qmp_phy_vreg_l,
1717 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1718 .regs = sdm845_qmp_pciephy_regs_layout,
1719
94a407cc
DB		 1720 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1721 .phy_status = PHYSTATUS,
94a407cc
DB		 1722};
1723
1724static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
f02543fa 1725 .lanes = 1,
94a407cc 1726
d8c9a1e9 1727 .tbls = {
2566ad8e
DB		 1728 .serdes = sdm845_qhp_pcie_serdes_tbl,
1729 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
1730 .tx = sdm845_qhp_pcie_tx_tbl,
1731 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
1732 .rx = sdm845_qhp_pcie_rx_tbl,
1733 .rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
1734 .pcs = sdm845_qhp_pcie_pcs_tbl,
1735 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
1736 },
94a407cc
DB		 1737 .clk_list = sdm845_pciephy_clk_l,
1738 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
1739 .reset_list = sdm845_pciephy_reset_l,
1740 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1741 .vreg_list = qmp_phy_vreg_l,
1742 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1743 .regs = sdm845_qhp_pciephy_regs_layout,
1744
94a407cc
DB		 1745 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1746 .phy_status = PHYSTATUS,
94a407cc
DB		 1747};
1748
1749static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
f02543fa 1750 .lanes = 1,
94a407cc 1751
d8c9a1e9 1752 .tbls = {
2566ad8e
DB		 1753 .serdes = sm8250_qmp_pcie_serdes_tbl,
1754 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
1755 .tx = sm8250_qmp_pcie_tx_tbl,
1756 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
1757 .rx = sm8250_qmp_pcie_rx_tbl,
1758 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
1759 .pcs = sm8250_qmp_pcie_pcs_tbl,
1760 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
1761 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl,
1762 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
1763 },
d8c9a1e9 1764 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2566ad8e
DB		 1765 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl,
1766 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
1767 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl,
1768 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
1769 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl,
1770 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
1771 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
1772 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
1773 },
94a407cc
DB		 1774 .clk_list = sdm845_pciephy_clk_l,
1775 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
1776 .reset_list = sdm845_pciephy_reset_l,
1777 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1778 .vreg_list = qmp_phy_vreg_l,
1779 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1780 .regs = sm8250_pcie_regs_layout,
1781
94a407cc
DB		 1782 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1783 .phy_status = PHYSTATUS,
94a407cc
DB		 1784};
1785
1786static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
f02543fa 1787 .lanes = 2,
94a407cc 1788
d8c9a1e9 1789 .tbls = {
2566ad8e
DB		 1790 .serdes = sm8250_qmp_pcie_serdes_tbl,
1791 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
1792 .tx = sm8250_qmp_pcie_tx_tbl,
1793 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
1794 .rx = sm8250_qmp_pcie_rx_tbl,
1795 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
1796 .pcs = sm8250_qmp_pcie_pcs_tbl,
1797 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
1798 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl,
1799 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
1800 },
d8c9a1e9 1801 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2566ad8e
DB		 1802 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl,
1803 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
1804 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl,
1805 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
1806 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl,
1807 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
1808 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
1809 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
1810 },
94a407cc
DB		 1811 .clk_list = sdm845_pciephy_clk_l,
1812 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
1813 .reset_list = sdm845_pciephy_reset_l,
1814 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1815 .vreg_list = qmp_phy_vreg_l,
1816 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1817 .regs = sm8250_pcie_regs_layout,
1818
94a407cc
DB		 1819 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1820 .phy_status = PHYSTATUS,
94a407cc
DB		 1821};
1822
94a407cc 1823static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
f02543fa 1824 .lanes = 1,
94a407cc 1825
d8c9a1e9 1826 .tbls = {
2566ad8e
DB		 1827 .serdes = msm8998_pcie_serdes_tbl,
1828 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
1829 .tx = msm8998_pcie_tx_tbl,
1830 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
1831 .rx = msm8998_pcie_rx_tbl,
1832 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
1833 .pcs = msm8998_pcie_pcs_tbl,
1834 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
1835 },
94a407cc
DB		 1836 .clk_list = msm8996_phy_clk_l,
1837 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
1838 .reset_list = ipq8074_pciephy_reset_l,
1839 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1840 .vreg_list = qmp_phy_vreg_l,
1841 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1842 .regs = pciephy_regs_layout,
1843
94a407cc
DB		 1844 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1845 .phy_status = PHYSTATUS,
51bd3306
JH		 1846
1847 .skip_start_delay = true,
94a407cc
DB		 1848};
1849
94a407cc 1850static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
f02543fa 1851 .lanes = 1,
94a407cc 1852
d8c9a1e9 1853 .tbls = {
2566ad8e
DB		 1854 .serdes = sc8180x_qmp_pcie_serdes_tbl,
1855 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
1856 .tx = sc8180x_qmp_pcie_tx_tbl,
1857 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
1858 .rx = sc8180x_qmp_pcie_rx_tbl,
1859 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
1860 .pcs = sc8180x_qmp_pcie_pcs_tbl,
1861 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
1862 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl,
1863 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
1864 },
b35a5311
DB		 1865 .clk_list = sdm845_pciephy_clk_l,
1866 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
1867 .reset_list = sdm845_pciephy_reset_l,
1868 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
94a407cc
DB		 1869 .vreg_list = qmp_phy_vreg_l,
1870 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
b35a5311 1871 .regs = sm8250_pcie_regs_layout,
94a407cc 1872
b35a5311 1873 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4a9eac5a 1874 .phy_status = PHYSTATUS,
94a407cc
DB		 1875};
1876
d0a846ba
JH		 1877static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = {
1878 .lanes = 1,
1879
1880 .offsets = &qmp_pcie_offsets_v5,
1881
1882 .tbls = {
1883 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
1884 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
1885 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl,
1886 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl),
1887 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl,
1888 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl),
1889 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl,
1890 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl),
1891 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl,
1892 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl),
1893 },
1894
1895 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
1896 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl,
1897 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl),
1898 },
1899
1900 .clk_list = sc8280xp_pciephy_clk_l,
1901 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
1902 .reset_list = sdm845_pciephy_reset_l,
1903 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1904 .vreg_list = qmp_phy_vreg_l,
1905 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1906 .regs = sm8250_pcie_regs_layout,
1907
1908 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1909 .phy_status = PHYSTATUS,
1910};
1911
1912static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = {
1913 .lanes = 2,
1914
1915 .offsets = &qmp_pcie_offsets_v5,
1916
1917 .tbls = {
1918 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
1919 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
1920 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
1921 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
1922 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
1923 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
1924 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
1925 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
1926 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
1927 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
1928 },
1929
1930 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
1931 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
1932 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
1933 },
1934
1935 .clk_list = sc8280xp_pciephy_clk_l,
1936 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
1937 .reset_list = sdm845_pciephy_reset_l,
1938 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1939 .vreg_list = qmp_phy_vreg_l,
1940 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1941 .regs = sm8250_pcie_regs_layout,
1942
1943 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1944 .phy_status = PHYSTATUS,
1945};
1946
6c37a02b
JH		 1947static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {
1948 .lanes = 4,
1949
1950 .offsets = &qmp_pcie_offsets_v5,
1951
1952 .tbls = {
1953 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
1954 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
1955 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
1956 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
1957 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
1958 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
1959 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
1960 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
1961 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
1962 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
1963 },
1964
1965 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
1966 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
1967 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
1968 },
1969
1970 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl,
1971 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl),
1972
1973 .clk_list = sc8280xp_pciephy_clk_l,
1974 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
1975 .reset_list = sdm845_pciephy_reset_l,
1976 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
1977 .vreg_list = qmp_phy_vreg_l,
1978 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1979 .regs = sm8250_pcie_regs_layout,
1980
1981 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
1982 .phy_status = PHYSTATUS,
1983};
1984
94a407cc 1985static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
f02543fa 1986 .lanes = 2,
94a407cc 1987
d8c9a1e9 1988 .tbls = {
2566ad8e
DB		 1989 .serdes = sdx55_qmp_pcie_serdes_tbl,
1990 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
1991 .tx = sdx55_qmp_pcie_tx_tbl,
1992 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
1993 .rx = sdx55_qmp_pcie_rx_tbl,
1994 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
1995 .pcs = sdx55_qmp_pcie_pcs_tbl,
1996 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
1997 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl,
1998 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
1999 },
94a407cc
DB		 2000 .clk_list = sdm845_pciephy_clk_l,
2001 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
2002 .reset_list = sdm845_pciephy_reset_l,
2003 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2004 .vreg_list = qmp_phy_vreg_l,
2005 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2006 .regs = sm8250_pcie_regs_layout,
2007
94a407cc
DB		 2008 .pwrdn_ctrl = SW_PWRDN,
2009 .phy_status = PHYSTATUS_4_20,
94a407cc
DB		 2010};
2011
94a407cc 2012static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
f02543fa 2013 .lanes = 1,
94a407cc 2014
d8c9a1e9 2015 .tbls = {
2566ad8e
DB		 2016 .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl,
2017 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
2018 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl,
2019 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
2020 .rx = sm8450_qmp_gen3x1_pcie_rx_tbl,
2021 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
2022 .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl,
2023 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
2024 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
2025 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
2026 },
94a407cc
DB		 2027 .clk_list = sdm845_pciephy_clk_l,
2028 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
2029 .reset_list = sdm845_pciephy_reset_l,
2030 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2031 .vreg_list = qmp_phy_vreg_l,
2032 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2033 .regs = sm8250_pcie_regs_layout,
2034
94a407cc
DB		 2035 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2036 .phy_status = PHYSTATUS,
94a407cc
DB		 2037};
2038
2039static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
f02543fa 2040 .lanes = 2,
94a407cc 2041
d8c9a1e9 2042 .tbls = {
2566ad8e
DB		 2043 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl,
2044 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
2045 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl,
2046 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
2047 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl,
2048 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
2049 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl,
2050 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
2051 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
2052 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
2053 },
f5682f13 2054
d8c9a1e9 2055 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
f5682f13
DB		 2056 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl,
2057 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl),
2058 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl,
2059 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl),
2060 },
2061
d8c9a1e9 2062 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
f5682f13
DB		 2063 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl,
2064 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl),
2065 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
2066 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
2067 },
2068
94a407cc
DB		 2069 .clk_list = sdm845_pciephy_clk_l,
2070 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
2071 .reset_list = sdm845_pciephy_reset_l,
2072 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2073 .vreg_list = qmp_phy_vreg_l,
2074 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2075 .regs = sm8250_pcie_regs_layout,
2076
94a407cc
DB		 2077 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2078 .phy_status = PHYSTATUS_4_20,
94a407cc
DB		 2079};
2080
27878615 2081static void qmp_pcie_configure_lane(void __iomem *base,
94a407cc
DB		 2082 const struct qmp_phy_init_tbl tbl[],
2083 int num,
2084 u8 lane_mask)
2085{
2086 int i;
2087 const struct qmp_phy_init_tbl *t = tbl;
2088
2089 if (!t)
2090 return;
2091
2092 for (i = 0; i < num; i++, t++) {
2093 if (!(t->lane_mask & lane_mask))
2094 continue;
2095
f2175762 2096 writel(t->val, base + t->offset);
94a407cc
DB		 2097 }
2098}
2099
27878615 2100static void qmp_pcie_configure(void __iomem *base,
27878615
JH		 2101 const struct qmp_phy_init_tbl tbl[],
2102 int num)
94a407cc 2103{
f2175762 2104 qmp_pcie_configure_lane(base, tbl, num, 0xff);
94a407cc
DB		 2105}
2106
6c37a02b
JH		 2107static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
2108{
2109 const struct qmp_phy_cfg *cfg = qmp->cfg;
2110 const struct qmp_pcie_offsets *offs = cfg->offsets;
2111 void __iomem *tx3, *rx3, *tx4, *rx4;
2112
2113 tx3 = qmp->port_b + offs->tx;
2114 rx3 = qmp->port_b + offs->rx;
2115 tx4 = qmp->port_b + offs->tx2;
2116 rx4 = qmp->port_b + offs->rx2;
2117
2118 qmp_pcie_configure_lane(tx3, tbls->tx, tbls->tx_num, 1);
2119 qmp_pcie_configure_lane(rx3, tbls->rx, tbls->rx_num, 1);
2120
2121 qmp_pcie_configure_lane(tx4, tbls->tx, tbls->tx_num, 2);
2122 qmp_pcie_configure_lane(rx4, tbls->rx, tbls->rx_num, 2);
2123}
2124
ec7bc1b4 2125static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
2566ad8e 2126{
2fdedef3 2127 const struct qmp_phy_cfg *cfg = qmp->cfg;
ec7bc1b4 2128 void __iomem *serdes = qmp->serdes;
2fdedef3
JH		 2129 void __iomem *tx = qmp->tx;
2130 void __iomem *rx = qmp->rx;
f8b64114
JH		 2131 void __iomem *tx2 = qmp->tx2;
2132 void __iomem *rx2 = qmp->rx2;
ec7bc1b4
JH		 2133 void __iomem *pcs = qmp->pcs;
2134 void __iomem *pcs_misc = qmp->pcs_misc;
2566ad8e 2135
d8c9a1e9 2136 if (!tbls)
2566ad8e
DB		 2137 return;
2138
ec7bc1b4
JH		 2139 qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num);
2140
d8c9a1e9
JH		 2141 qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
2142 qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
f8b64114
JH		 2143
2144 if (cfg->lanes >= 2) {
d8c9a1e9
JH		 2145 qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2);
2146 qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2);
f8b64114 2147 }
2566ad8e 2148
d8c9a1e9
JH		 2149 qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num);
2150 qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
6c37a02b
JH		 2151
2152 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
2153 qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
2154 qmp_pcie_init_port_b(qmp, tbls);
2155 }
94a407cc
DB		 2156}
2157
91174e2c 2158static int qmp_pcie_init(struct phy *phy)
94a407cc 2159{
2fdedef3
JH		 2160 struct qmp_pcie *qmp = phy_get_drvdata(phy);
2161 const struct qmp_phy_cfg *cfg = qmp->cfg;
189ac6b8 2162 int ret;
94a407cc 2163
94a407cc
DB		 2164 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2165 if (ret) {
2166 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1239fd71 2167 return ret;
94a407cc
DB		 2168 }
2169
189ac6b8
DB		 2170 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2171 if (ret) {
2172 dev_err(qmp->dev, "reset assert failed\n");
2173 goto err_disable_regulators;
94a407cc
DB		 2174 }
2175
fffdeaf8
JH		 2176 usleep_range(200, 300);
2177
189ac6b8
DB		 2178 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2179 if (ret) {
2180 dev_err(qmp->dev, "reset deassert failed\n");
2181 goto err_disable_regulators;
94a407cc
DB		 2182 }
2183
2184 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2185 if (ret)
2186 goto err_assert_reset;
2187
94a407cc
DB		 2188 return 0;
2189
2190err_assert_reset:
189ac6b8 2191 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
94a407cc
DB		 2192err_disable_regulators:
2193 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
94a407cc
DB		 2194
2195 return ret;
2196}
2197
91174e2c 2198static int qmp_pcie_exit(struct phy *phy)
94a407cc 2199{
2fdedef3
JH		 2200 struct qmp_pcie *qmp = phy_get_drvdata(phy);
2201 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 2202
189ac6b8 2203 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
94a407cc
DB		 2204
2205 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2206
2207 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2208
94a407cc
DB		 2209 return 0;
2210}
2211
27878615 2212static int qmp_pcie_power_on(struct phy *phy)
94a407cc 2213{
2fdedef3
JH		 2214 struct qmp_pcie *qmp = phy_get_drvdata(phy);
2215 const struct qmp_phy_cfg *cfg = qmp->cfg;
d8c9a1e9 2216 const struct qmp_phy_cfg_tbls *mode_tbls;
2fdedef3 2217 void __iomem *pcs = qmp->pcs;
94a407cc 2218 void __iomem *status;
2577ba8c 2219 unsigned int mask, val;
94a407cc
DB		 2220 int ret;
2221
5b68d95c
JH		 2222 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2223 cfg->pwrdn_ctrl);
2224
2fdedef3 2225 if (qmp->mode == PHY_MODE_PCIE_RC)
d8c9a1e9 2226 mode_tbls = cfg->tbls_rc;
11bf53a3 2227 else
d8c9a1e9 2228 mode_tbls = cfg->tbls_ep;
11bf53a3 2229
ec7bc1b4
JH		 2230 qmp_pcie_init_registers(qmp, &cfg->tbls);
2231 qmp_pcie_init_registers(qmp, mode_tbls);
94a407cc 2232
9e420f1e
JH		 2233 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
2234 if (ret)
fd926994 2235 return ret;
94a407cc 2236
da07a06b 2237 /* Pull PHY out of reset state */
fd926994
DB		 2238 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2239
da07a06b 2240 /* start SerDes and Phy-Coding-Sublayer */
5806b87d 2241 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
94a407cc 2242
51bd3306
JH		 2243 if (!cfg->skip_start_delay)
2244 usleep_range(1000, 1200);
2245
da07a06b
DB		 2246 status = pcs + cfg->regs[QPHY_PCS_STATUS];
2247 mask = cfg->phy_status;
5cbeb75a 2248 ret = readl_poll_timeout(status, val, !(val & mask), 200,
da07a06b
DB		 2249 PHY_INIT_COMPLETE_TIMEOUT);
2250 if (ret) {
2251 dev_err(qmp->dev, "phy initialization timed-out\n");
2252 goto err_disable_pipe_clk;
94a407cc 2253 }
da07a06b 2254
94a407cc
DB		 2255 return 0;
2256
2257err_disable_pipe_clk:
9e420f1e 2258 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
94a407cc
DB		 2259
2260 return ret;
2261}
2262
27878615 2263static int qmp_pcie_power_off(struct phy *phy)
94a407cc 2264{
2fdedef3
JH		 2265 struct qmp_pcie *qmp = phy_get_drvdata(phy);
2266 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 2267
9e420f1e 2268 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
94a407cc 2269
da07a06b 2270 /* PHY reset */
2fdedef3 2271 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
94a407cc 2272
da07a06b 2273 /* stop SerDes and Phy-Coding-Sublayer */
2fdedef3 2274 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
5806b87d 2275 SERDES_START | PCS_START);
94a407cc 2276
da07a06b 2277 /* Put PHY into POWER DOWN state: active low */
2fdedef3 2278 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
6d5b1e20 2279 cfg->pwrdn_ctrl);
94a407cc
DB		 2280
2281 return 0;
2282}
2283
27878615 2284static int qmp_pcie_enable(struct phy *phy)
94a407cc
DB		 2285{
2286 int ret;
2287
27878615 2288 ret = qmp_pcie_init(phy);
94a407cc
DB		 2289 if (ret)
2290 return ret;
2291
27878615 2292 ret = qmp_pcie_power_on(phy);
94a407cc 2293 if (ret)
27878615 2294 qmp_pcie_exit(phy);
94a407cc
DB		 2295
2296 return ret;
2297}
2298
27878615 2299static int qmp_pcie_disable(struct phy *phy)
94a407cc
DB		 2300{
2301 int ret;
2302
27878615 2303 ret = qmp_pcie_power_off(phy);
94a407cc
DB		 2304 if (ret)
2305 return ret;
27878615
JH		 2306
2307 return qmp_pcie_exit(phy);
94a407cc
DB		 2308}
2309
11bf53a3
DB		 2310static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode)
2311{
2fdedef3 2312 struct qmp_pcie *qmp = phy_get_drvdata(phy);
11bf53a3
DB		 2313
2314 switch (submode) {
2315 case PHY_MODE_PCIE_RC:
2316 case PHY_MODE_PCIE_EP:
2fdedef3 2317 qmp->mode = submode;
11bf53a3
DB		 2318 break;
2319 default:
2320 dev_err(&phy->dev, "Unsupported submode %d\n", submode);
2321 return -EINVAL;
2322 }
2323
2324 return 0;
2325}
2326
63bf101a
JH		 2327static const struct phy_ops qmp_pcie_phy_ops = {
2328 .power_on = qmp_pcie_enable,
2329 .power_off = qmp_pcie_disable,
2330 .set_mode = qmp_pcie_set_mode,
2331 .owner = THIS_MODULE,
2332};
2333
52b99773 2334static int qmp_pcie_vreg_init(struct qmp_pcie *qmp)
94a407cc 2335{
52b99773
JH		 2336 const struct qmp_phy_cfg *cfg = qmp->cfg;
2337 struct device *dev = qmp->dev;
94a407cc
DB		 2338 int num = cfg->num_vregs;
2339 int i;
2340
2341 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2342 if (!qmp->vregs)
2343 return -ENOMEM;
2344
2345 for (i = 0; i < num; i++)
2346 qmp->vregs[i].supply = cfg->vreg_list[i];
2347
2348 return devm_regulator_bulk_get(dev, num, qmp->vregs);
2349}
2350
52b99773 2351static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
94a407cc 2352{
52b99773
JH		 2353 const struct qmp_phy_cfg *cfg = qmp->cfg;
2354 struct device *dev = qmp->dev;
94a407cc 2355 int i;
189ac6b8 2356 int ret;
94a407cc
DB		 2357
2358 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
2359 sizeof(*qmp->resets), GFP_KERNEL);
2360 if (!qmp->resets)
2361 return -ENOMEM;
2362
189ac6b8
DB		 2363 for (i = 0; i < cfg->num_resets; i++)
2364 qmp->resets[i].id = cfg->reset_list[i];
94a407cc 2365
189ac6b8
DB		 2366 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
2367 if (ret)
2368 return dev_err_probe(dev, ret, "failed to get resets\n");
94a407cc
DB		 2369
2370 return 0;
2371}
2372
52b99773 2373static int qmp_pcie_clk_init(struct qmp_pcie *qmp)
94a407cc 2374{
52b99773
JH		 2375 const struct qmp_phy_cfg *cfg = qmp->cfg;
2376 struct device *dev = qmp->dev;
94a407cc
DB		 2377 int num = cfg->num_clks;
2378 int i;
2379
2380 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2381 if (!qmp->clks)
2382 return -ENOMEM;
2383
2384 for (i = 0; i < num; i++)
2385 qmp->clks[i].id = cfg->clk_list[i];
2386
2387 return devm_clk_bulk_get(dev, num, qmp->clks);
2388}
2389
2390static void phy_clk_release_provider(void *res)
2391{
2392 of_clk_del_provider(res);
2393}
2394
2395/*
2396 * Register a fixed rate pipe clock.
2397 *
2398 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2399 * controls it. The <s>_pipe_clk coming out of the GCC is requested
2400 * by the PHY driver for its operations.
2401 * We register the <s>_pipe_clksrc here. The gcc driver takes care
2402 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2403 * Below picture shows this relationship.
2404 *
2405 * +---------------+
2406 * | PHY block |<<---------------------------------------+
2407 * | | |
2408 * | +-------+ | +-----+ |
2409 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2410 * clk | +-------+ | +-----+
2411 * +---------------+
2412 */
2fdedef3 2413static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)
94a407cc
DB		 2414{
2415 struct clk_fixed_rate *fixed;
2416 struct clk_init_data init = { };
2417 int ret;
2418
2419 ret = of_property_read_string(np, "clock-output-names", &init.name);
2420 if (ret) {
2421 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2422 return ret;
2423 }
2424
2425 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
2426 if (!fixed)
2427 return -ENOMEM;
2428
2429 init.ops = &clk_fixed_rate_ops;
2430
2ec9bc8d
RM		 2431 /*
2432 * Controllers using QMP PHY-s use 125MHz pipe clock interface
2433 * unless other frequency is specified in the PHY config.
2434 */
2fdedef3
JH		 2435 if (qmp->cfg->pipe_clock_rate)
2436 fixed->fixed_rate = qmp->cfg->pipe_clock_rate;
2ec9bc8d
RM		 2437 else
2438 fixed->fixed_rate = 125000000;
2439
94a407cc
DB		 2440 fixed->hw.init = &init;
2441
2442 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2443 if (ret)
2444 return ret;
2445
2446 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2447 if (ret)
2448 return ret;
2449
2450 /*
2451 * Roll a devm action because the clock provider is the child node, but
2452 * the child node is not actually a device.
2453 */
2454 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2455}
2456
7bc609e3 2457static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np)
94a407cc 2458{
7bc609e3 2459 struct platform_device *pdev = to_platform_device(qmp->dev);
52b99773
JH		 2460 const struct qmp_phy_cfg *cfg = qmp->cfg;
2461 struct device *dev = qmp->dev;
9e420f1e 2462 struct clk *clk;
94a407cc 2463
7bc609e3
JH		 2464 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2465 if (IS_ERR(qmp->serdes))
2466 return PTR_ERR(qmp->serdes);
94a407cc 2467
94a407cc 2468 /*
8d3bf724 2469 * Get memory resources for the PHY:
94a407cc
DB		 2470 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2471 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2472 * For single lane PHYs: pcs_misc (optional) -> 3.
2473 */
2fdedef3
JH		 2474 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2475 if (IS_ERR(qmp->tx))
2476 return PTR_ERR(qmp->tx);
94a407cc 2477
0a40891b 2478 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy"))
2fdedef3 2479 qmp->rx = qmp->tx;
0a40891b 2480 else
2fdedef3
JH		 2481 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2482 if (IS_ERR(qmp->rx))
2483 return PTR_ERR(qmp->rx);
94a407cc 2484
2fdedef3
JH		 2485 qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
2486 if (IS_ERR(qmp->pcs))
2487 return PTR_ERR(qmp->pcs);
94a407cc 2488
f02543fa 2489 if (cfg->lanes >= 2) {
2fdedef3
JH		 2490 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2491 if (IS_ERR(qmp->tx2))
2492 return PTR_ERR(qmp->tx2);
94a407cc 2493
2fdedef3
JH		 2494 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2495 if (IS_ERR(qmp->rx2))
2496 return PTR_ERR(qmp->rx2);
94a407cc 2497
2fdedef3 2498 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
94a407cc 2499 } else {
2fdedef3 2500 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
94a407cc
DB		 2501 }
2502
2fdedef3 2503 if (IS_ERR(qmp->pcs_misc) &&
af664324 2504 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
2fdedef3 2505 qmp->pcs_misc = qmp->pcs + 0x400;
af664324 2506
2fdedef3 2507 if (IS_ERR(qmp->pcs_misc)) {
d8c9a1e9
JH		 2508 if (cfg->tbls.pcs_misc ||
2509 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) ||
2510 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) {
2fdedef3
JH		 2511 return PTR_ERR(qmp->pcs_misc);
2512 }
ecd5507e 2513 }
94a407cc 2514
9e420f1e
JH		 2515 clk = devm_get_clk_from_child(dev, np, NULL);
2516 if (IS_ERR(clk)) {
2517 return dev_err_probe(dev, PTR_ERR(clk),
2fdedef3 2518 "failed to get pipe clock\n");
94a407cc
DB		 2519 }
2520
9e420f1e
JH		 2521 qmp->num_pipe_clks = 1;
2522 qmp->pipe_clks[0].id = "pipe";
2523 qmp->pipe_clks[0].clk = clk;
2524
94a407cc
DB		 2525 return 0;
2526}
2527
6c37a02b
JH		 2528static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp)
2529{
2530 struct regmap *tcsr;
2531 unsigned int args[2];
2532 int ret;
2533
2534 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node,
2535 "qcom,4ln-config-sel",
2536 ARRAY_SIZE(args), args);
2537 if (IS_ERR(tcsr)) {
2538 ret = PTR_ERR(tcsr);
2539 if (ret == -ENOENT)
2540 return 0;
2541
2542 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret);
2543 return ret;
2544 }
2545
2546 ret = regmap_test_bits(tcsr, args[0], BIT(args[1]));
2547 if (ret < 0) {
2548 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret);
2549 return ret;
2550 }
2551
2552 qmp->tcsr_4ln_config = ret;
2553
2554 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config);
2555
2556 return 0;
2557}
2558
d0a846ba
JH		 2559static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
2560{
2561 struct platform_device *pdev = to_platform_device(qmp->dev);
2562 const struct qmp_phy_cfg *cfg = qmp->cfg;
2563 const struct qmp_pcie_offsets *offs = cfg->offsets;
2564 struct device *dev = qmp->dev;
2565 void __iomem *base;
2566 int ret;
2567
2568 if (!offs)
2569 return -EINVAL;
2570
6c37a02b
JH		 2571 ret = qmp_pcie_get_4ln_config(qmp);
2572 if (ret)
2573 return ret;
2574
d0a846ba
JH		 2575 base = devm_platform_ioremap_resource(pdev, 0);
2576 if (IS_ERR(base))
2577 return PTR_ERR(base);
2578
2579 qmp->serdes = base + offs->serdes;
2580 qmp->pcs = base + offs->pcs;
2581 qmp->pcs_misc = base + offs->pcs_misc;
2582 qmp->tx = base + offs->tx;
2583 qmp->rx = base + offs->rx;
2584
2585 if (cfg->lanes >= 2) {
2586 qmp->tx2 = base + offs->tx2;
2587 qmp->rx2 = base + offs->rx2;
2588 }
2589
6c37a02b
JH		 2590 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
2591 qmp->port_b = devm_platform_ioremap_resource(pdev, 1);
2592 if (IS_ERR(qmp->port_b))
2593 return PTR_ERR(qmp->port_b);
2594 }
2595
d0a846ba
JH		 2596 qmp->num_pipe_clks = 2;
2597 qmp->pipe_clks[0].id = "pipe";
2598 qmp->pipe_clks[1].id = "pipediv2";
2599
2600 ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks);
2601 if (ret)
2602 return ret;
2603
2604 return 0;
2605}
2606
27878615 2607static int qmp_pcie_probe(struct platform_device *pdev)
94a407cc 2608{
94a407cc 2609 struct device *dev = &pdev->dev;
94a407cc 2610 struct phy_provider *phy_provider;
d0a846ba 2611 struct device_node *np;
2fdedef3 2612 struct qmp_pcie *qmp;
94a407cc
DB		 2613 int ret;
2614
2615 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2616 if (!qmp)
2617 return -ENOMEM;
2618
2619 qmp->dev = dev;
94a407cc 2620
52b99773
JH		 2621 qmp->cfg = of_device_get_match_data(dev);
2622 if (!qmp->cfg)
b35a5311 2623 return -EINVAL;
94a407cc 2624
52b99773
JH		 2625 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
2626 WARN_ON_ONCE(!qmp->cfg->phy_status);
73ad6a9d 2627
52b99773 2628 ret = qmp_pcie_clk_init(qmp);
94a407cc
DB		 2629 if (ret)
2630 return ret;
2631
52b99773 2632 ret = qmp_pcie_reset_init(qmp);
94a407cc
DB		 2633 if (ret)
2634 return ret;
2635
52b99773 2636 ret = qmp_pcie_vreg_init(qmp);
a548b6b4 2637 if (ret)
28d74fc3 2638 return ret;
94a407cc 2639
d0a846ba
JH		 2640 /* Check for legacy binding with child node. */
2641 np = of_get_next_available_child(dev->of_node, NULL);
2642 if (np) {
2643 ret = qmp_pcie_parse_dt_legacy(qmp, np);
2644 } else {
2645 np = of_node_get(dev->of_node);
2646 ret = qmp_pcie_parse_dt(qmp);
2647 }
393ed5d5
JH		 2648 if (ret)
2649 goto err_node_put;
94a407cc 2650
d0a846ba 2651 ret = phy_pipe_clk_register(qmp, np);
393ed5d5
JH		 2652 if (ret)
2653 goto err_node_put;
da07a06b 2654
7bc609e3
JH		 2655 qmp->mode = PHY_MODE_PCIE_RC;
2656
d0a846ba 2657 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops);
7bc609e3
JH		 2658 if (IS_ERR(qmp->phy)) {
2659 ret = PTR_ERR(qmp->phy);
2660 dev_err(dev, "failed to create PHY: %d\n", ret);
2661 goto err_node_put;
2662 }
2663
2664 phy_set_drvdata(qmp->phy, qmp);
2665
d0a846ba 2666 of_node_put(np);
94a407cc
DB		 2667
2668 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
94a407cc
DB		 2669
2670 return PTR_ERR_OR_ZERO(phy_provider);
2671
2672err_node_put:
d0a846ba 2673 of_node_put(np);
94a407cc
DB		 2674 return ret;
2675}
2676
cebc6ca7
JH		 2677static const struct of_device_id qmp_pcie_of_match_table[] = {
2678 {
2679 .compatible = "qcom,ipq6018-qmp-pcie-phy",
2680 .data = &ipq6018_pciephy_cfg,
2681 }, {
2682 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
2683 .data = &ipq8074_pciephy_gen3_cfg,
2684 }, {
2685 .compatible = "qcom,ipq8074-qmp-pcie-phy",
2686 .data = &ipq8074_pciephy_cfg,
2687 }, {
2688 .compatible = "qcom,msm8998-qmp-pcie-phy",
2689 .data = &msm8998_pciephy_cfg,
2690 }, {
2691 .compatible = "qcom,sc8180x-qmp-pcie-phy",
2692 .data = &sc8180x_pciephy_cfg,
d0a846ba
JH		 2693 }, {
2694 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
2695 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg,
2696 }, {
2697 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
2698 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg,
6c37a02b
JH		 2699 }, {
2700 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
2701 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg,
cebc6ca7
JH		 2702 }, {
2703 .compatible = "qcom,sdm845-qhp-pcie-phy",
2704 .data = &sdm845_qhp_pciephy_cfg,
2705 }, {
2706 .compatible = "qcom,sdm845-qmp-pcie-phy",
2707 .data = &sdm845_qmp_pciephy_cfg,
2708 }, {
2709 .compatible = "qcom,sdx55-qmp-pcie-phy",
2710 .data = &sdx55_qmp_pciephy_cfg,
2711 }, {
2712 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
2713 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
2714 }, {
2715 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
2716 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
2717 }, {
2718 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
2719 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
2720 }, {
2721 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
2722 .data = &sm8450_qmp_gen3x1_pciephy_cfg,
2723 }, {
2724 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
2725 .data = &sm8450_qmp_gen4x2_pciephy_cfg,
2726 },
2727 { },
2728};
2729MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table);
2730
27878615
JH		 2731static struct platform_driver qmp_pcie_driver = {
2732 .probe = qmp_pcie_probe,
94a407cc 2733 .driver = {
b35a5311 2734 .name = "qcom-qmp-pcie-phy",
27878615 2735 .of_match_table = qmp_pcie_of_match_table,
94a407cc
DB		 2736 },
2737};
2738
27878615 2739module_platform_driver(qmp_pcie_driver);
94a407cc
DB		 2740
2741MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
b35a5311 2742MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver");
94a407cc 2743MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)