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phy: qcom-qmp-combo: fix type-c switch registration
[linux-2.6-block.git] / drivers / phy / qualcomm / phy-qcom-qmp-combo.c
CommitLineData
94a407cc
DB		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
94a407cc
DB		 15#include <linux/of_address.h>
16#include <linux/phy/phy.h>
17#include <linux/platform_device.h>
18#include <linux/regulator/consumer.h>
19#include <linux/reset.h>
20#include <linux/slab.h>
815891ee 21#include <linux/usb/typec.h>
2851117f 22#include <linux/usb/typec_mux.h>
94a407cc 23
35921910 24#include <drm/bridge/aux-bridge.h>
1904c3f5 25
83a0bbe3 26#include <dt-bindings/phy/phy-qcom-qmp.h>
94a407cc
DB		 27
28#include "phy-qcom-qmp.h"
eb5793fb
DB		 29#include "phy-qcom-qmp-pcs-misc-v3.h"
30#include "phy-qcom-qmp-pcs-usb-v4.h"
31#include "phy-qcom-qmp-pcs-usb-v5.h"
39bbf82d 32#include "phy-qcom-qmp-pcs-usb-v6.h"
94a407cc
DB		 33
34/* QPHY_SW_RESET bit */
35#define SW_RESET BIT(0)
36/* QPHY_POWER_DOWN_CONTROL */
37#define SW_PWRDN BIT(0)
94a407cc
DB		 38/* QPHY_START_CONTROL bits */
39#define SERDES_START BIT(0)
40#define PCS_START BIT(1)
94a407cc
DB		 41/* QPHY_PCS_STATUS bit */
42#define PHYSTATUS BIT(6)
94a407cc
DB		 43
44/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
45/* DP PHY soft reset */
46#define SW_DPPHY_RESET BIT(0)
47/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
48#define SW_DPPHY_RESET_MUX BIT(1)
49/* USB3 PHY soft reset */
50#define SW_USB3PHY_RESET BIT(2)
51/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
52#define SW_USB3PHY_RESET_MUX BIT(3)
53
54/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
55#define USB3_MODE BIT(0) /* enables USB3 mode */
56#define DP_MODE BIT(1) /* enables DP mode */
57
58/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
59#define ARCVR_DTCT_EN BIT(0)
60#define ALFPS_DTCT_EN BIT(1)
61#define ARCVR_DTCT_EVENT_SEL BIT(4)
62
63/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
64#define IRQ_CLEAR BIT(0)
65
94a407cc
DB		 66/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
67#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
68
815891ee
BA		 69/* QPHY_V3_DP_COM_TYPEC_CTRL register bits */
70#define SW_PORTSELECT_VAL BIT(0)
71#define SW_PORTSELECT_MUX BIT(1)
72
94a407cc 73#define PHY_INIT_COMPLETE_TIMEOUT 10000
94a407cc 74
94a407cc
DB		 75struct qmp_phy_init_tbl {
76 unsigned int offset;
77 unsigned int val;
94a407cc
DB		 78 /*
79 * mask of lanes for which this register is written
80 * for cases when second lane needs different values
81 */
82 u8 lane_mask;
83};
84
85#define QMP_PHY_INIT_CFG(o, v) \
86 { \
87 .offset = o, \
88 .val = v, \
89 .lane_mask = 0xff, \
90 }
91
94a407cc
DB		 92#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
93 { \
94 .offset = o, \
95 .val = v, \
96 .lane_mask = l, \
97 }
98
99/* set of registers with offsets different per-PHY */
100enum qphy_reg_layout {
94a407cc 101 /* PCS registers */
94a407cc
DB		 102 QPHY_SW_RESET,
103 QPHY_START_CTRL,
94a407cc
DB		 104 QPHY_PCS_STATUS,
105 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
106 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
94a407cc 107 QPHY_PCS_POWER_DOWN_CONTROL,
8447fa7f
DB		 108
109 QPHY_COM_RESETSM_CNTRL,
110 QPHY_COM_C_READY_STATUS,
111 QPHY_COM_CMN_STATUS,
31a4ac68 112 QPHY_COM_BIAS_EN_CLKBUFLR_EN,
8447fa7f
DB		 113
114 QPHY_DP_PHY_STATUS,
115
186ad90a
DB		 116 QPHY_TX_TX_POL_INV,
117 QPHY_TX_TX_DRV_LVL,
118 QPHY_TX_TX_EMP_POST1_LVL,
cd1f3343
DB		 119 QPHY_TX_HIGHZ_DRVR_EN,
120 QPHY_TX_TRANSCEIVER_BIAS_EN,
186ad90a 121
94a407cc
DB		 122 /* Keep last to ensure regs_layout arrays are properly initialized */
123 QPHY_LAYOUT_SIZE
124};
125
94a407cc 126static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
aa14cff1
DB		 127 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
128 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
129 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
130 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
131 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
132 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
8447fa7f
DB		 133
134 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL,
135 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS,
136 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS,
31a4ac68 137 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN,
8447fa7f
DB		 138
139 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS,
186ad90a
DB		 140
141 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV,
142 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL,
143 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL,
cd1f3343
DB		 144 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN,
145 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN,
94a407cc
DB		 146};
147
8447fa7f 148static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
aa14cff1
DB		 149 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
150 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
151 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
152 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
fc646236
DB		 153
154 /* In PCS_USB */
aa14cff1
DB		 155 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
156 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
8447fa7f
DB		 157
158 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL,
159 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS,
160 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS,
31a4ac68 161 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN,
8447fa7f
DB		 162
163 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS,
186ad90a
DB		 164
165 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV,
166 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL,
167 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL,
cd1f3343
DB		 168 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN,
169 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN,
186ad90a
DB		 170};
171
172static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
173 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
174 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
175 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
176 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
177
178 /* In PCS_USB */
179 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
180 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
181
182 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL,
183 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS,
184 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS,
31a4ac68 185 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN,
186ad90a
DB		 186
187 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS,
188
189 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV,
190 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL,
191 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL,
cd1f3343
DB		 192 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN,
193 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN,
8447fa7f
DB		 194};
195
196static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
b5ec2824
DB		 197 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,
198 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,
199 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,
200 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
8447fa7f
DB		 201
202 /* In PCS_USB */
b5ec2824
DB		 203 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
204 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
8447fa7f
DB		 205
206 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL,
207 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS,
208 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS,
31a4ac68 209 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN,
8447fa7f
DB		 210
211 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
186ad90a
DB		 212
213 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV,
214 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL,
215 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL,
cd1f3343
DB		 216 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN,
217 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN,
94a407cc
DB		 218};
219
94a407cc
DB		 220static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
257};
258
259static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
260 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
261 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
262 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
263 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
264 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
265};
266
267static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
289};
290
291static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
299};
300
301static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
309};
310
311static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
319};
320
321static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
325 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
326 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
327 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
328 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
329};
330
331static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
332 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
333 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
334 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
335 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
336 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
337 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
338 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
339 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
340 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
341 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
342 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
343 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
344 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
345 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
346 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
347};
348
349static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
350 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
351 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
352 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
353 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
354 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
355 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
356 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
357 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
358 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
359};
360
361static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
362 /* FLL settings */
363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
364 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
368
369 /* Lock Det settings */
370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
374
375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
394
395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
399 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
404 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
406};
407
05bd1834
LW		 408static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
409 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
410 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
411 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
412 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
413 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
414 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
415 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
416 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
417 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
418 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
419};
420
421static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
422 /* FLL settings */
423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
428
429 /* Lock Det settings */
430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
434
435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
437 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
438 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
439 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
440 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
441 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
442 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
443 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
444 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
445 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
446 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
447 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
454
455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
467
468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
470};
471
94a407cc
DB		 472static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
485 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
486 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
487 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
488 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
489 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
490 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
491 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
492 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
493 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
494 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
495 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
496 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
497 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
513};
514
515static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
516 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
517 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
518 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
519 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
520 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
521};
522
523static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
540 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
541 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
542 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
560};
561
562static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
563 /* Lock Det settings */
564 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
565 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
566 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
567
568 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
569 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
570 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
571 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
572 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
573 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
574 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
575 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
fc646236
DB		 576};
577
578static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
94a407cc
DB		 579 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
580 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
581};
582
ee7ffc92
DB		 583static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
584 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
585 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
586 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
587 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
588 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
94a407cc 589 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
ee7ffc92
DB		 590 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
591 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
94a407cc
DB		 592};
593
ee7ffc92
DB		 594static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
94a407cc
DB		 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
94a407cc
DB		 605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
94a407cc
DB		 607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
ee7ffc92
DB		 610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
94a407cc
DB		 613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
615 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
616 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
ee7ffc92
DB		 617 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
618 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
621 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
622 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
623 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
628 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
631 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
632 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
94a407cc
DB		 633};
634
ee7ffc92
DB		 635static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
636 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
637 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
638 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
639 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
640 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
641 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
642 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
643 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
644 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
645 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
646 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
647 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
fc646236
DB		 648};
649
650static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
ee7ffc92
DB		 651 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
652 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
94a407cc
DB		 653};
654
ef14aff1
NA		 655static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
656 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
657 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
658 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
659 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
660 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
661 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
662 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
663 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
664 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
665 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
666};
667
668static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
677 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
678 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
679 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
680 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
681 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
682 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
683 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
684 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
685 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
686 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
687 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
688 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
689 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
690 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
691 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
692 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
693 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
694 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
695 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
696 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
697 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
698 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
699 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
700 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
701 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
702 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
703 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
704 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
705 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
706 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
707};
708
709static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
712 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
713 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
722 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
724};
725
726static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
727 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
729 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
730 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
731};
732
49742e9e
AV		 733static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = {
734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
738 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
739 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41),
743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75),
746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
750 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
752 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
753 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
754 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
755 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
756 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
757 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
758 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75),
765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
769 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
770 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
771 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
772 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
773 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
774 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
775 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
776 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
782};
783
784static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = {
785 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
786 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
787 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
788 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
789 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
790 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
791 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
792 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
793 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
794 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
795 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
796};
797
798static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = {
799 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
800 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
801 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
802 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
803 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
804 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
805 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
806 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
807 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
808 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
809 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
810 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
811 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
812 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
813 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
814 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
815 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
816 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
817 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
818 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
819 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
820 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
821 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
822 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
823 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
824 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
825 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
826 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
827 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
828 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
829 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
830 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
831 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
832 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
833
834 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1),
835 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1),
836 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1),
837 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1),
838 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1),
839
840 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2),
841 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2),
842 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2),
843 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2),
844 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2),
845};
846
847static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
579483ec
DB		 848 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
849 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
850 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
851 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
852 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
853 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99),
854 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
855 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
856 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
857 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
858 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
859 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
860 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
861 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
49742e9e
AV		 862};
863
864static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
579483ec
DB		 865 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
866 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
867 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
868 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
869 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
49742e9e
AV		 870};
871
ee7ffc92
DB		 872static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
883 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
884 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
885 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
94a407cc
DB		 893};
894
ee7ffc92
DB		 895static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
896 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
898 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
899 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
900 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
901 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
902 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
94a407cc
DB		 903};
904
ee7ffc92
DB		 905static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
906 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
907 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
908 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
909 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
910 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
911 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
912 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
94a407cc
DB		 913};
914
ee7ffc92
DB		 915static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
916 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
917 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
918 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
919 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
920 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
921 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
922 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
94a407cc
DB		 923};
924
ee7ffc92
DB		 925static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
926 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
927 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
928 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
929 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
930 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
931 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
932 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
94a407cc
DB		 933};
934
ee7ffc92
DB		 935static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
936 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
937 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
938 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
939 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
940 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
941 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
942 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
943 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
944 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
945 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
946 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
947 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
948 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
949 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
94a407cc
DB		 950};
951
a2e927b0
BA		 952static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = {
953 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
954 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
955 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
956 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
957 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
958 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
959 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
966 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
967 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
969 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
970 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
971 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
972 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
973 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
974 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
975 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
976};
977
ef14aff1
NA		 978static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = {
979 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40),
980 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
981 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b),
982 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f),
983 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03),
984 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f),
985 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
986 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00),
987 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
988 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
989 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04),
990};
991
a2e927b0
BA		 992static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {
993 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),
994 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),
995 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40),
996 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0),
997 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff),
998 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f),
999 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03),
1000 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf),
1001 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1002 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1003 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
1004 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),
1005};
1006
49742e9e
AV		 1007static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = {
1008 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
1009 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
1010 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
1011 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
1012 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
1013 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
1014 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1015 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1016 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1017 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1018 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
1019 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
1020 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1021 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1022 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
1023 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1024 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
1025 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
1026 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
1027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
1028};
1029
1030static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
1031 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),
1032 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1033 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b),
1034 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f),
1035 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03),
1036 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f),
1037 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1038 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00),
1039 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c),
1040 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1041 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),
1042};
1043
1044static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {
1045 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
1046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1048 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1049 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
1050 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
1051 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1052 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1053 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1054};
1055
1056static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = {
1057 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
1058 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1059 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1060 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1061 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
1062 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
1063 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1064 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1065 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1066};
1067
1068static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = {
1069 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1070 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
1071 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00),
1072 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
1073 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
1074 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
1075 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1076 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
1077 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
1078};
1079
1080static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = {
1081 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
1082 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1083 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1084 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1085 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
1086 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
1087 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1088 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1089 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1090};
1091
a2e927b0
BA		 1092static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd),
1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d),
1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd),
1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d),
1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02),
1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02),
1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04),
1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01),
1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04),
1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01),
1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1118 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5),
1119 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05),
1120 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5),
1122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
1123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1124 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4),
1125 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00),
1126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4),
1127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00),
1128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13),
1129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1130 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1131 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1132 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1133 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76),
1134 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff),
1135 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1136 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1137 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
1138 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01),
1139 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a),
1140};
1141
1142static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = {
1143 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05),
1144 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2),
1145 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10),
1146 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1147 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1148};
1149
1150static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = {
1151 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04),
1152 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1153 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00),
1154 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2),
1155 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2),
1156 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb),
1157 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21),
1158 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f),
1159 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80),
1160 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45),
1161 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00),
1162 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b),
1163 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63),
1164 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6),
1165 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23),
1166 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35),
1167 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30),
1168 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e),
1169 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00),
1170 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1171 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80),
1172 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b),
1173 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1174 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15),
1175 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1176 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1177 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00),
1178 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d),
1179 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00),
1180 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45),
1181 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09),
1182 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09),
1183 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05),
1184 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f),
1185};
1186
1187static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = {
1188 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1189 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1190 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1191 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1192 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1193 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1194 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1195 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1196 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a),
1197 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1198 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1199 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1200 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1201 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1202 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1203 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1204};
85936d4f 1205
d7b3579f
AV		 1206static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = {
1207 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1208 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1209 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1210 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2),
1211 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03),
1212 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2),
1213 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1214 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a),
1215 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
1216 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
1217 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1218 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1219 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1220 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1221 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
1222 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1223 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1224 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
1225 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
1226 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
1227 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
1228 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
1229 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
1230 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82),
1231 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
1232 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
1233 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55),
1234 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03),
1235 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
1236 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
1237 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03),
1238 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1239 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba),
1240 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00),
1241 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba),
1242 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00),
1243 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13),
1244 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1245 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1246 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1247 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1248 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76),
1249 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1250 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f),
1251 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1252 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1253 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
1254 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01),
1255 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a),
1256 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1257};
1258
1259static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = {
1260 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05),
1261 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50),
1262 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50),
1263 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1264 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1265};
1266
1267static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = {
1268 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04),
1269 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1270 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00),
1271 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3),
1272 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3),
1273 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8),
1274 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e),
1275 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36),
1276 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6),
1277 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64),
1278 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6),
1279 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee),
1280 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18),
1281 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a),
1282 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04),
1283 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36),
1284 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3),
1285 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1286 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80),
1287 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f),
1288 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08),
1289 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15),
1290 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0),
1291 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48),
1292 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1293 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1294 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00),
1295 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04),
1296 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88),
1297 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45),
1298 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d),
1299 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09),
1300 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05),
1301 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f),
1302 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14),
1303};
1304
1305static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = {
1306 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1307 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1308 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1309 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
1310 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
1311 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
1312 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
1313 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x55),
1314 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
1315 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0xd4),
1316 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x30),
1317 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
1318 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
1319 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
1320};
1321
1322static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
1323 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1324 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1325};
1326
85936d4f
KH		 1327/* list of regulators */
1328struct qmp_regulator_data {
1329 const char *name;
1330 unsigned int enable_load;
1331};
1332
38b6dbcc 1333static struct qmp_regulator_data qmp_phy_vreg_l[] = {
85936d4f
KH		 1334 { .name = "vdda-phy", .enable_load = 21800 },
1335 { .name = "vdda-pll", .enable_load = 36000 },
1336};
1337
712e5dff
BA		 1338static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
1339 { 0x00, 0x0c, 0x15, 0x1a },
1340 { 0x02, 0x0e, 0x16, 0xff },
1341 { 0x02, 0x11, 0xff, 0xff },
1342 { 0x04, 0xff, 0xff, 0xff }
1343};
1344
1345static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
1346 { 0x02, 0x12, 0x16, 0x1a },
1347 { 0x09, 0x19, 0x1f, 0xff },
1348 { 0x10, 0x1f, 0xff, 0xff },
1349 { 0x1f, 0xff, 0xff, 0xff }
1350};
1351
1352static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
1353 { 0x00, 0x0c, 0x14, 0x19 },
1354 { 0x00, 0x0b, 0x12, 0xff },
1355 { 0x00, 0x0b, 0xff, 0xff },
1356 { 0x04, 0xff, 0xff, 0xff }
1357};
1358
1359static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
1360 { 0x08, 0x0f, 0x16, 0x1f },
1361 { 0x11, 0x1e, 0x1f, 0xff },
1362 { 0x19, 0x1f, 0xff, 0xff },
1363 { 0x1f, 0xff, 0xff, 0xff }
1364};
1365
ef14aff1
NA		 1366static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = {
1367 { 0x00, 0x0c, 0x15, 0x1b },
1368 { 0x02, 0x0e, 0x16, 0xff },
1369 { 0x02, 0x11, 0xff, 0xff },
1370 { 0x04, 0xff, 0xff, 0xff }
1371};
1372
1373static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = {
1374 { 0x00, 0x0d, 0x14, 0x1a },
1375 { 0x00, 0x0e, 0x15, 0xff },
1376 { 0x00, 0x0d, 0xff, 0xff },
1377 { 0x03, 0xff, 0xff, 0xff }
1378};
1379
1380static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = {
1381 { 0x08, 0x0f, 0x16, 0x1f },
1382 { 0x11, 0x1e, 0x1f, 0xff },
1383 { 0x16, 0x1f, 0xff, 0xff },
1384 { 0x1f, 0xff, 0xff, 0xff }
1385};
1386
a2e927b0
BA		 1387static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {
1388 { 0x20, 0x2c, 0x35, 0x3b },
1389 { 0x22, 0x2e, 0x36, 0xff },
1390 { 0x22, 0x31, 0xff, 0xff },
1391 { 0x24, 0xff, 0xff, 0xff }
1392};
1393
1394static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = {
1395 { 0x22, 0x32, 0x36, 0x3a },
1396 { 0x29, 0x39, 0x3f, 0xff },
1397 { 0x30, 0x3f, 0xff, 0xff },
1398 { 0x3f, 0xff, 0xff, 0xff }
1399};
1400
1401static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = {
1402 { 0x20, 0x2d, 0x34, 0x3a },
1403 { 0x20, 0x2e, 0x35, 0xff },
1404 { 0x20, 0x2e, 0xff, 0xff },
1405 { 0x24, 0xff, 0xff, 0xff }
1406};
1407
1408static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = {
1409 { 0x28, 0x2f, 0x36, 0x3f },
1410 { 0x31, 0x3e, 0x3f, 0xff },
1411 { 0x36, 0x3f, 0xff, 0xff },
1412 { 0x3f, 0xff, 0xff, 0xff }
1413};
1414
49742e9e
AV		 1415static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = {
1416 { 0x20, 0x2d, 0x34, 0x3a },
1417 { 0x20, 0x2e, 0x35, 0xff },
1418 { 0x20, 0x2e, 0xff, 0xff },
1419 { 0x22, 0xff, 0xff, 0xff }
1420};
1421
dd115365 1422struct qmp_combo;
94a407cc 1423
83a0bbe3
JH		 1424struct qmp_combo_offsets {
1425 u16 com;
1426 u16 txa;
1427 u16 rxa;
1428 u16 txb;
1429 u16 rxb;
1430 u16 usb3_serdes;
1431 u16 usb3_pcs_misc;
1432 u16 usb3_pcs;
1433 u16 usb3_pcs_usb;
1434 u16 dp_serdes;
05bd1834
LW		 1435 u16 dp_txa;
1436 u16 dp_txb;
83a0bbe3
JH		 1437 u16 dp_dp_phy;
1438};
1439
94a407cc 1440struct qmp_phy_cfg {
83a0bbe3
JH		 1441 const struct qmp_combo_offsets *offsets;
1442
94a407cc
DB		 1443 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1444 const struct qmp_phy_init_tbl *serdes_tbl;
1445 int serdes_tbl_num;
94a407cc
DB		 1446 const struct qmp_phy_init_tbl *tx_tbl;
1447 int tx_tbl_num;
94a407cc
DB		 1448 const struct qmp_phy_init_tbl *rx_tbl;
1449 int rx_tbl_num;
94a407cc
DB		 1450 const struct qmp_phy_init_tbl *pcs_tbl;
1451 int pcs_tbl_num;
fc646236
DB		 1452 const struct qmp_phy_init_tbl *pcs_usb_tbl;
1453 int pcs_usb_tbl_num;
94a407cc 1454
488f116d
JH		 1455 const struct qmp_phy_init_tbl *dp_serdes_tbl;
1456 int dp_serdes_tbl_num;
1457 const struct qmp_phy_init_tbl *dp_tx_tbl;
1458 int dp_tx_tbl_num;
1459
94a407cc
DB		 1460 /* Init sequence for DP PHY block link rates */
1461 const struct qmp_phy_init_tbl *serdes_tbl_rbr;
1462 int serdes_tbl_rbr_num;
1463 const struct qmp_phy_init_tbl *serdes_tbl_hbr;
1464 int serdes_tbl_hbr_num;
1465 const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
1466 int serdes_tbl_hbr2_num;
1467 const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
1468 int serdes_tbl_hbr3_num;
1469
712e5dff
BA		 1470 /* DP PHY swing and pre_emphasis tables */
1471 const u8 (*swing_hbr_rbr)[4][4];
1472 const u8 (*swing_hbr3_hbr2)[4][4];
1473 const u8 (*pre_emphasis_hbr_rbr)[4][4];
1474 const u8 (*pre_emphasis_hbr3_hbr2)[4][4];
1475
94a407cc 1476 /* DP PHY callbacks */
dd115365
JH		 1477 int (*configure_dp_phy)(struct qmp_combo *qmp);
1478 void (*configure_dp_tx)(struct qmp_combo *qmp);
1479 int (*calibrate_dp_phy)(struct qmp_combo *qmp);
1480 void (*dp_aux_init)(struct qmp_combo *qmp);
94a407cc 1481
94a407cc
DB		 1482 /* resets to be requested */
1483 const char * const *reset_list;
1484 int num_resets;
1485 /* regulators to be requested */
85936d4f 1486 const struct qmp_regulator_data *vreg_list;
94a407cc
DB		 1487 int num_vregs;
1488
1489 /* array of registers with different offsets */
1490 const unsigned int *regs;
1491
94a407cc
DB		 1492 /* true, if PHY needs delay after POWER_DOWN */
1493 bool has_pwrdn_delay;
94a407cc 1494
fc646236
DB		 1495 /* Offset from PCS to PCS_USB region */
1496 unsigned int pcs_usb_offset;
1497
94a407cc
DB		 1498};
1499
dd115365
JH		 1500struct qmp_combo {
1501 struct device *dev;
1502
94a407cc 1503 const struct qmp_phy_cfg *cfg;
dd115365 1504
9e5b59ea 1505 void __iomem *com;
dd115365 1506
94a407cc
DB		 1507 void __iomem *serdes;
1508 void __iomem *tx;
1509 void __iomem *rx;
1510 void __iomem *pcs;
1511 void __iomem *tx2;
1512 void __iomem *rx2;
1513 void __iomem *pcs_misc;
fc646236 1514 void __iomem *pcs_usb;
4197a2a2
JH		 1515
1516 void __iomem *dp_serdes;
1517 void __iomem *dp_tx;
1518 void __iomem *dp_tx2;
133836a7 1519 void __iomem *dp_dp_phy;
4197a2a2 1520
94a407cc 1521 struct clk *pipe_clk;
94a407cc 1522 struct clk_bulk_data *clks;
28e265bf 1523 int num_clks;
1de24861 1524 struct reset_control_bulk_data *resets;
94a407cc
DB		 1525 struct regulator_bulk_data *vregs;
1526
94a407cc
DB		 1527 struct mutex phy_mutex;
1528 int init_count;
dd115365
JH		 1529
1530 struct phy *usb_phy;
1531 enum phy_mode mode;
2851117f 1532 unsigned int usb_init_count;
dd115365
JH		 1533
1534 struct phy *dp_phy;
1535 unsigned int dp_aux_cfg;
1536 struct phy_configure_opts_dp dp_opts;
2851117f 1537 unsigned int dp_init_count;
ee81f2eb 1538
55b1c39b 1539 struct clk_fixed_rate pipe_clk_fixed;
ee81f2eb
JH		 1540 struct clk_hw dp_link_hw;
1541 struct clk_hw dp_pixel_hw;
815891ee 1542
2851117f 1543 struct typec_switch_dev *sw;
815891ee 1544 enum typec_orientation orientation;
94a407cc
DB		 1545};
1546
526103b7
JH		 1547static void qmp_v3_dp_aux_init(struct qmp_combo *qmp);
1548static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp);
1549static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp);
1550static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp);
94a407cc 1551
526103b7
JH		 1552static void qmp_v4_dp_aux_init(struct qmp_combo *qmp);
1553static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp);
1554static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp);
1555static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp);
94a407cc
DB		 1556
1557static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1558{
1559 u32 reg;
1560
1561 reg = readl(base + offset);
1562 reg |= val;
1563 writel(reg, base + offset);
1564
1565 /* ensure that above write is through */
1566 readl(base + offset);
1567}
1568
1569static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1570{
1571 u32 reg;
1572
1573 reg = readl(base + offset);
1574 reg &= ~val;
1575 writel(reg, base + offset);
1576
1577 /* ensure that above write is through */
1578 readl(base + offset);
1579}
1580
1581/* list of clocks required by phy */
28e265bf 1582static const char * const qmp_combo_phy_clk_l[] = {
94a407cc
DB		 1583 "aux", "cfg_ahb", "ref", "com_aux",
1584};
1585
94a407cc 1586/* list of resets */
94a407cc
DB		 1587static const char * const msm8996_usb3phy_reset_l[] = {
1588 "phy", "common",
1589};
1590
1591static const char * const sc7180_usb3phy_reset_l[] = {
1592 "phy",
1593};
1594
05bd1834
LW		 1595static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
1596 .com = 0x0000,
1597 .txa = 0x1200,
1598 .rxa = 0x1400,
1599 .txb = 0x1600,
1600 .rxb = 0x1800,
1601 .usb3_serdes = 0x1000,
1602 .usb3_pcs_misc = 0x1a00,
1603 .usb3_pcs = 0x1c00,
4546334f 1604 .usb3_pcs_usb = 0x1f00,
05bd1834
LW		 1605 .dp_serdes = 0x2000,
1606 .dp_txa = 0x2200,
1607 .dp_txb = 0x2600,
1608 .dp_dp_phy = 0x2a00,
1609};
1610
83a0bbe3
JH		 1611static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
1612 .com = 0x0000,
1613 .txa = 0x0400,
1614 .rxa = 0x0600,
1615 .txb = 0x0a00,
1616 .rxb = 0x0c00,
1617 .usb3_serdes = 0x1000,
1618 .usb3_pcs_misc = 0x1200,
1619 .usb3_pcs = 0x1400,
1620 .usb3_pcs_usb = 0x1700,
1621 .dp_serdes = 0x2000,
1622 .dp_dp_phy = 0x2200,
1623};
1624
9e62877e 1625static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
a542ae82
DB		 1626 .offsets = &qmp_combo_offsets_v3,
1627
94a407cc
DB		 1628 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1629 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1630 .tx_tbl = qmp_v3_usb3_tx_tbl,
1631 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1632 .rx_tbl = qmp_v3_usb3_rx_tbl,
1633 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1634 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1635 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
94a407cc 1636
488f116d
JH		 1637 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
1638 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1639 .dp_tx_tbl = qmp_v3_dp_tx_tbl,
1640 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
94a407cc
DB		 1641
1642 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
1643 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1644 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
1645 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1646 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
1647 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1648 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
1649 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1650
712e5dff
BA		 1651 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1652 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1653 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1654 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1655
526103b7
JH		 1656 .dp_aux_init = qmp_v3_dp_aux_init,
1657 .configure_dp_tx = qmp_v3_configure_dp_tx,
1658 .configure_dp_phy = qmp_v3_configure_dp_phy,
1659 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
94a407cc 1660
9e62877e
JH		 1661 .reset_list = sc7180_usb3phy_reset_l,
1662 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
1663 .vreg_list = qmp_phy_vreg_l,
1664 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1665 .regs = qmp_v3_usb3phy_regs_layout,
94a407cc 1666
9e62877e
JH		 1667 .has_pwrdn_delay = true,
1668};
d88497fb 1669
9e62877e 1670static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = {
a542ae82
DB		 1671 .offsets = &qmp_combo_offsets_v3,
1672
d88497fb
DB		 1673 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1674 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1675 .tx_tbl = qmp_v3_usb3_tx_tbl,
1676 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1677 .rx_tbl = qmp_v3_usb3_rx_tbl,
1678 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1679 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1680 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
d88497fb 1681
9e62877e
JH		 1682 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
1683 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1684 .dp_tx_tbl = qmp_v3_dp_tx_tbl,
1685 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
e965ab82
JH		 1686
1687 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
1688 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1689 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
1690 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1691 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
1692 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1693 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
1694 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1695
1696 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1697 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1698 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1699 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1700
526103b7
JH		 1701 .dp_aux_init = qmp_v3_dp_aux_init,
1702 .configure_dp_tx = qmp_v3_configure_dp_tx,
1703 .configure_dp_phy = qmp_v3_configure_dp_phy,
1704 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
e965ab82 1705
9e62877e
JH		 1706 .reset_list = msm8996_usb3phy_reset_l,
1707 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1708 .vreg_list = qmp_phy_vreg_l,
1709 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1710 .regs = qmp_v3_usb3phy_regs_layout,
d88497fb 1711
9e62877e
JH		 1712 .has_pwrdn_delay = true,
1713};
94a407cc 1714
9e62877e 1715static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = {
a542ae82
DB		 1716 .offsets = &qmp_combo_offsets_v3,
1717
94a407cc
DB		 1718 .serdes_tbl = sm8150_usb3_serdes_tbl,
1719 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1720 .tx_tbl = sm8150_usb3_tx_tbl,
1721 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
1722 .rx_tbl = sm8150_usb3_rx_tbl,
1723 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
1724 .pcs_tbl = sm8150_usb3_pcs_tbl,
1725 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
fc646236
DB		 1726 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
1727 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
94a407cc 1728
488f116d
JH		 1729 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
1730 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1731 .dp_tx_tbl = qmp_v4_dp_tx_tbl,
1732 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
94a407cc
DB		 1733
1734 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
1735 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1736 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
1737 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1738 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
1739 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1740 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
1741 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1742
712e5dff
BA		 1743 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1744 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1745 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1746 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1747
526103b7
JH		 1748 .dp_aux_init = qmp_v4_dp_aux_init,
1749 .configure_dp_tx = qmp_v4_configure_dp_tx,
1750 .configure_dp_phy = qmp_v4_configure_dp_phy,
1751 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
a2e927b0 1752
a2e927b0
BA		 1753 .reset_list = msm8996_usb3phy_reset_l,
1754 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1755 .vreg_list = qmp_phy_vreg_l,
1756 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
8447fa7f 1757 .regs = qmp_v45_usb3phy_regs_layout,
f5d6b5d6 1758 .pcs_usb_offset = 0x300,
9e62877e
JH		 1759
1760 .has_pwrdn_delay = true,
a2e927b0
BA		 1761};
1762
9e62877e 1763static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = {
83a0bbe3
JH		 1764 .offsets = &qmp_combo_offsets_v5,
1765
9e62877e
JH		 1766 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl,
1767 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl),
1768 .tx_tbl = sc8280xp_usb43dp_tx_tbl,
1769 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl),
1770 .rx_tbl = sc8280xp_usb43dp_rx_tbl,
1771 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl),
1772 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl,
1773 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl),
a2e927b0 1774
488f116d
JH		 1775 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl,
1776 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl),
1777 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl,
1778 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl),
a2e927b0
BA		 1779
1780 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
1781 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1782 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
1783 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1784 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
1785 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1786 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
1787 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1788
1789 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
1790 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr,
1791 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1792 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1793
526103b7
JH		 1794 .dp_aux_init = qmp_v4_dp_aux_init,
1795 .configure_dp_tx = qmp_v4_configure_dp_tx,
9e6a0403 1796 .configure_dp_phy = qmp_v4_configure_dp_phy,
526103b7 1797 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
a2e927b0 1798
9e62877e
JH		 1799 .reset_list = msm8996_usb3phy_reset_l,
1800 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1801 .vreg_list = qmp_phy_vreg_l,
1802 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
186ad90a 1803 .regs = qmp_v5_5nm_usb3phy_regs_layout,
a2e927b0
BA		 1804};
1805
d7b3579f
AV		 1806static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = {
1807 .offsets = &qmp_combo_offsets_v5,
1808
1809 .serdes_tbl = x1e80100_usb43dp_serdes_tbl,
1810 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl),
1811 .tx_tbl = x1e80100_usb43dp_tx_tbl,
1812 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl),
1813 .rx_tbl = x1e80100_usb43dp_rx_tbl,
1814 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl),
1815 .pcs_tbl = x1e80100_usb43dp_pcs_tbl,
1816 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl),
1817 .pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl,
1818 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl),
1819
1820 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
1821 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
1822 .dp_tx_tbl = qmp_v6_dp_tx_tbl,
1823 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
1824
1825 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
1826 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
1827 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
1828 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
1829 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
1830 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
1831 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
1832 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
1833
1834 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
1835 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr,
1836 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1837 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1838
1839 .dp_aux_init = qmp_v4_dp_aux_init,
1840 .configure_dp_tx = qmp_v4_configure_dp_tx,
1841 .configure_dp_phy = qmp_v4_configure_dp_phy,
1842 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1843
1844 .reset_list = msm8996_usb3phy_reset_l,
1845 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1846 .vreg_list = qmp_phy_vreg_l,
1847 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1848 .regs = qmp_v45_usb3phy_regs_layout,
1849};
1850
05bd1834
LW		 1851static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
1852 .offsets = &qmp_combo_offsets_v3,
1853
1854 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1855 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1856 .tx_tbl = qmp_v3_usb3_tx_tbl,
1857 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1858 .rx_tbl = sm6350_usb3_rx_tbl,
1859 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl),
1860 .pcs_tbl = sm6350_usb3_pcs_tbl,
1861 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl),
1862
1863 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
1864 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1865 .dp_tx_tbl = qmp_v3_dp_tx_tbl,
1866 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1867
1868 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
1869 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1870 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
1871 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1872 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
1873 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1874 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
1875 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1876
1877 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1878 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1879 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1880 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1881
1882 .dp_aux_init = qmp_v3_dp_aux_init,
1883 .configure_dp_tx = qmp_v3_configure_dp_tx,
1884 .configure_dp_phy = qmp_v3_configure_dp_phy,
1885 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
1886
05bd1834
LW		 1887 .reset_list = msm8996_usb3phy_reset_l,
1888 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1889 .vreg_list = qmp_phy_vreg_l,
1890 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1891 .regs = qmp_v3_usb3phy_regs_layout,
1892};
1893
9e62877e 1894static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
a542ae82
DB		 1895 .offsets = &qmp_combo_offsets_v3,
1896
94a407cc
DB		 1897 .serdes_tbl = sm8150_usb3_serdes_tbl,
1898 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1899 .tx_tbl = sm8250_usb3_tx_tbl,
1900 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
1901 .rx_tbl = sm8250_usb3_rx_tbl,
1902 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
1903 .pcs_tbl = sm8250_usb3_pcs_tbl,
1904 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
fc646236
DB		 1905 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
1906 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
94a407cc 1907
488f116d
JH		 1908 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
1909 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1910 .dp_tx_tbl = qmp_v4_dp_tx_tbl,
1911 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
94a407cc
DB		 1912
1913 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
1914 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1915 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
1916 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1917 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
1918 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1919 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
1920 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1921
712e5dff
BA		 1922 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1923 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1924 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1925 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1926
526103b7
JH		 1927 .dp_aux_init = qmp_v4_dp_aux_init,
1928 .configure_dp_tx = qmp_v4_configure_dp_tx,
1929 .configure_dp_phy = qmp_v4_configure_dp_phy,
1930 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
94a407cc 1931
9e62877e
JH		 1932 .reset_list = msm8996_usb3phy_reset_l,
1933 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1934 .vreg_list = qmp_phy_vreg_l,
1935 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
8447fa7f 1936 .regs = qmp_v45_usb3phy_regs_layout,
9e62877e
JH		 1937 .pcs_usb_offset = 0x300,
1938
1939 .has_pwrdn_delay = true,
94a407cc
DB		 1940};
1941
ef14aff1
NA		 1942static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
1943 .offsets = &qmp_combo_offsets_v3,
1944
1945 .serdes_tbl = sm8150_usb3_serdes_tbl,
1946 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1947 .tx_tbl = sm8350_usb3_tx_tbl,
1948 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
1949 .rx_tbl = sm8350_usb3_rx_tbl,
1950 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
1951 .pcs_tbl = sm8350_usb3_pcs_tbl,
1952 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
1953 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl,
1954 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
1955
1956 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
1957 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1958 .dp_tx_tbl = qmp_v5_dp_tx_tbl,
1959 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl),
1960
1961 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
1962 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1963 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
1964 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1965 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
1966 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1967 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
1968 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1969
1970 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr,
1971 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr,
1972 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1973 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2,
1974
1975 .dp_aux_init = qmp_v4_dp_aux_init,
1976 .configure_dp_tx = qmp_v4_configure_dp_tx,
1977 .configure_dp_phy = qmp_v4_configure_dp_phy,
1978 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1979
ef14aff1
NA		 1980 .reset_list = msm8996_usb3phy_reset_l,
1981 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1982 .vreg_list = qmp_phy_vreg_l,
1983 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
8447fa7f 1984 .regs = qmp_v45_usb3phy_regs_layout,
ef14aff1
NA		 1985
1986 .has_pwrdn_delay = true,
1987};
1988
49742e9e 1989static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
eb016875 1990 .offsets = &qmp_combo_offsets_v3,
49742e9e
AV		 1991
1992 .serdes_tbl = sm8550_usb3_serdes_tbl,
1993 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
1994 .tx_tbl = sm8550_usb3_tx_tbl,
1995 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl),
1996 .rx_tbl = sm8550_usb3_rx_tbl,
1997 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl),
1998 .pcs_tbl = sm8550_usb3_pcs_tbl,
1999 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
2000 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl,
2001 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
2002
2003 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
2004 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
2005 .dp_tx_tbl = qmp_v6_dp_tx_tbl,
2006 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
2007
2008 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
2009 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
2010 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
2011 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
2012 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
2013 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
2014 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
2015 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
2016
2017 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
2018 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
2019 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2020 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2021
31a4ac68 2022 .dp_aux_init = qmp_v4_dp_aux_init,
49742e9e 2023 .configure_dp_tx = qmp_v4_configure_dp_tx,
9e6a0403 2024 .configure_dp_phy = qmp_v4_configure_dp_phy,
49742e9e
AV		 2025 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2026
8447fa7f 2027 .regs = qmp_v6_usb3phy_regs_layout,
49742e9e
AV		 2028 .reset_list = msm8996_usb3phy_reset_l,
2029 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2030 .vreg_list = qmp_phy_vreg_l,
2031 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2032};
2033
e5cedefa 2034static void qmp_combo_configure_lane(void __iomem *base,
94a407cc
DB		 2035 const struct qmp_phy_init_tbl tbl[],
2036 int num,
2037 u8 lane_mask)
2038{
2039 int i;
2040 const struct qmp_phy_init_tbl *t = tbl;
2041
2042 if (!t)
2043 return;
2044
2045 for (i = 0; i < num; i++, t++) {
2046 if (!(t->lane_mask & lane_mask))
2047 continue;
2048
ccf6f83b 2049 writel(t->val, base + t->offset);
94a407cc
DB		 2050 }
2051}
2052
e5cedefa 2053static void qmp_combo_configure(void __iomem *base,
94a407cc
DB		 2054 const struct qmp_phy_init_tbl tbl[],
2055 int num)
2056{
ccf6f83b 2057 qmp_combo_configure_lane(base, tbl, num, 0xff);
94a407cc
DB		 2058}
2059
dd115365 2060static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
94a407cc 2061{
dd115365
JH		 2062 const struct qmp_phy_cfg *cfg = qmp->cfg;
2063 void __iomem *serdes = qmp->dp_serdes;
2064 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
94a407cc 2065
488f116d 2066 qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num);
94a407cc 2067
dae95d7f
JH		 2068 switch (dp_opts->link_rate) {
2069 case 1620:
2070 qmp_combo_configure(serdes, cfg->serdes_tbl_rbr,
2071 cfg->serdes_tbl_rbr_num);
2072 break;
2073 case 2700:
2074 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr,
2075 cfg->serdes_tbl_hbr_num);
2076 break;
2077 case 5400:
2078 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2,
2079 cfg->serdes_tbl_hbr2_num);
2080 break;
2081 case 8100:
2082 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3,
2083 cfg->serdes_tbl_hbr3_num);
2084 break;
2085 default:
2086 /* Other link rates aren't supported */
2087 return -EINVAL;
94a407cc
DB		 2088 }
2089
94a407cc
DB		 2090 return 0;
2091}
2092
526103b7 2093static void qmp_v3_dp_aux_init(struct qmp_combo *qmp)
94a407cc 2094{
31a4ac68
DB		 2095 const struct qmp_phy_cfg *cfg = qmp->cfg;
2096
94a407cc
DB		 2097 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2098 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
133836a7 2099 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
94a407cc
DB		 2100
2101 /* Turn on BIAS current for PHY/PLL */
2102 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
2103 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
31a4ac68 2104 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
94a407cc 2105
133836a7 2106 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
94a407cc
DB		 2107
2108 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2109 DP_PHY_PD_CTL_LANE_0_1_PWRDN |
2110 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
2111 DP_PHY_PD_CTL_DP_CLAMP_EN,
133836a7 2112 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
94a407cc
DB		 2113
2114 writel(QSERDES_V3_COM_BIAS_EN |
2115 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
2116 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
2117 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
31a4ac68 2118 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
dd115365 2119
133836a7
JH		 2120 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2121 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2122 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2123 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2124 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2125 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2126 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2127 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2128 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2129 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
dd115365 2130 qmp->dp_aux_cfg = 0;
94a407cc
DB		 2131
2132 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2133 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2134 PHY_AUX_REQ_ERR_MASK,
133836a7 2135 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
94a407cc
DB		 2136}
2137
186ad90a 2138static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp)
94a407cc 2139{
dd115365
JH		 2140 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2141 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc
DB		 2142 unsigned int v_level = 0, p_level = 0;
2143 u8 voltage_swing_cfg, pre_emphasis_cfg;
2144 int i;
2145
2146 for (i = 0; i < dp_opts->lanes; i++) {
2147 v_level = max(v_level, dp_opts->voltage[i]);
2148 p_level = max(p_level, dp_opts->pre[i]);
2149 }
2150
2151 if (dp_opts->link_rate <= 2700) {
712e5dff
BA		 2152 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level];
2153 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level];
94a407cc 2154 } else {
712e5dff
BA		 2155 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level];
2156 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level];
94a407cc
DB		 2157 }
2158
2159 /* TODO: Move check to config check */
2160 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
2161 return -EINVAL;
2162
2163 /* Enable MUX to use Cursor values from these registers */
2164 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
2165 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
2166
186ad90a
DB		 2167 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2168 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2169 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2170 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
94a407cc
DB		 2171
2172 return 0;
2173}
2174
526103b7 2175static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp)
94a407cc 2176{
dd115365 2177 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
94a407cc
DB		 2178 u32 bias_en, drvr_en;
2179
186ad90a 2180 if (qmp_combo_configure_dp_swing(qmp) < 0)
94a407cc
DB		 2181 return;
2182
2183 if (dp_opts->lanes == 1) {
2184 bias_en = 0x3e;
2185 drvr_en = 0x13;
2186 } else {
2187 bias_en = 0x3f;
2188 drvr_en = 0x10;
2189 }
2190
dd115365
JH		 2191 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2192 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2193 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2194 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
94a407cc
DB		 2195}
2196
dd115365 2197static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
94a407cc 2198{
815891ee
BA		 2199 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2200 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
94a407cc 2201 u32 val;
94a407cc
DB		 2202
2203 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2204 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
2205
815891ee
BA		 2206 if (dp_opts->lanes == 4 || reverse)
2207 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
2208 if (dp_opts->lanes == 4 || !reverse)
2209 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
2210
133836a7 2211 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
94a407cc 2212
815891ee
BA		 2213 if (reverse)
2214 writel(0x4c, qmp->pcs + QSERDES_DP_PHY_MODE);
2215 else
2216 writel(0x5c, qmp->pcs + QSERDES_DP_PHY_MODE);
94a407cc
DB		 2217
2218 return reverse;
2219}
2220
ec17373a 2221static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp)
94a407cc 2222{
dd115365 2223 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
ec17373a 2224 u32 phy_vco_div;
94a407cc
DB		 2225 unsigned long pixel_freq;
2226
94a407cc
DB		 2227 switch (dp_opts->link_rate) {
2228 case 1620:
2229 phy_vco_div = 0x1;
2230 pixel_freq = 1620000000UL / 2;
2231 break;
2232 case 2700:
2233 phy_vco_div = 0x1;
2234 pixel_freq = 2700000000UL / 2;
2235 break;
2236 case 5400:
2237 phy_vco_div = 0x2;
2238 pixel_freq = 5400000000UL / 4;
2239 break;
2240 case 8100:
2241 phy_vco_div = 0x0;
2242 pixel_freq = 8100000000UL / 6;
2243 break;
2244 default:
2245 /* Other link rates aren't supported */
2246 return -EINVAL;
2247 }
ec17373a 2248 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV);
94a407cc 2249
ee81f2eb
JH		 2250 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
2251 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
94a407cc 2252
ec17373a
DB		 2253 return 0;
2254}
2255
2256static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp)
2257{
2258 const struct qmp_phy_cfg *cfg = qmp->cfg;
2259 u32 status;
2260 int ret;
2261
2262 qmp_combo_configure_dp_mode(qmp);
2263
2264 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
2265 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
2266
2267 ret = qmp_combo_configure_dp_clocks(qmp);
2268 if (ret)
2269 return ret;
2270
133836a7
JH		 2271 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2272 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2273 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2274 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2275 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
94a407cc 2276
8447fa7f 2277 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
94a407cc 2278
8447fa7f 2279 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS],
94a407cc
DB		 2280 status,
2281 ((status & BIT(0)) > 0),
2282 500,
2283 10000))
2284 return -ETIMEDOUT;
2285
133836a7 2286 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
94a407cc 2287
8447fa7f 2288 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
94a407cc
DB		 2289 status,
2290 ((status & BIT(1)) > 0),
2291 500,
2292 10000))
2293 return -ETIMEDOUT;
2294
133836a7 2295 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
94a407cc 2296 udelay(2000);
133836a7 2297 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
94a407cc 2298
8447fa7f 2299 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
94a407cc
DB		 2300 status,
2301 ((status & BIT(1)) > 0),
2302 500,
2303 10000);
2304}
2305
2306/*
2307 * We need to calibrate the aux setting here as many times
2308 * as the caller tries
2309 */
526103b7 2310static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp)
94a407cc
DB		 2311{
2312 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
2313 u8 val;
2314
dd115365
JH		 2315 qmp->dp_aux_cfg++;
2316 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2317 val = cfg1_settings[qmp->dp_aux_cfg];
94a407cc 2318
133836a7 2319 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
94a407cc
DB		 2320
2321 return 0;
2322}
2323
526103b7 2324static void qmp_v4_dp_aux_init(struct qmp_combo *qmp)
94a407cc 2325{
31a4ac68 2326 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 2327
49742e9e
AV		 2328 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2329 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2330 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2331
2332 /* Turn on BIAS current for PHY/PLL */
31a4ac68 2333 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
49742e9e
AV		 2334
2335 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2336 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2337 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2338 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2339 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2340 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2341 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2342 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2343 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2344 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2345 qmp->dp_aux_cfg = 0;
2346
2347 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2348 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2349 PHY_AUX_REQ_ERR_MASK,
2350 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
2351}
2352
526103b7 2353static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
94a407cc 2354{
186ad90a
DB		 2355 const struct qmp_phy_cfg *cfg = qmp->cfg;
2356
94a407cc 2357 /* Program default values before writing proper values */
186ad90a
DB		 2358 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2359 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
94a407cc 2360
186ad90a
DB		 2361 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2362 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
94a407cc 2363
186ad90a 2364 qmp_combo_configure_dp_swing(qmp);
94a407cc
DB		 2365}
2366
8447fa7f 2367static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp)
94a407cc 2368{
8447fa7f 2369 const struct qmp_phy_cfg *cfg = qmp->cfg;
ec17373a
DB		 2370 u32 status;
2371 int ret;
94a407cc 2372
133836a7 2373 writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1);
94a407cc 2374
dd115365 2375 qmp_combo_configure_dp_mode(qmp);
94a407cc 2376
133836a7
JH		 2377 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2378 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
94a407cc 2379
133836a7
JH		 2380 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
2381 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
94a407cc 2382
ec17373a
DB		 2383 ret = qmp_combo_configure_dp_clocks(qmp);
2384 if (ret)
2385 return ret;
94a407cc 2386
133836a7
JH		 2387 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2388 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2389 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2390 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
94a407cc 2391
8447fa7f 2392 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
94a407cc 2393
8447fa7f 2394 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS],
94a407cc
DB		 2395 status,
2396 ((status & BIT(0)) > 0),
2397 500,
2398 10000))
2399 return -ETIMEDOUT;
2400
8447fa7f 2401 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS],
94a407cc
DB		 2402 status,
2403 ((status & BIT(0)) > 0),
2404 500,
2405 10000))
2406 return -ETIMEDOUT;
2407
8447fa7f 2408 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS],
94a407cc
DB		 2409 status,
2410 ((status & BIT(1)) > 0),
2411 500,
2412 10000))
2413 return -ETIMEDOUT;
2414
133836a7 2415 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
94a407cc 2416
8447fa7f 2417 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
94a407cc
DB		 2418 status,
2419 ((status & BIT(0)) > 0),
2420 500,
2421 10000))
2422 return -ETIMEDOUT;
2423
8447fa7f 2424 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
94a407cc
DB		 2425 status,
2426 ((status & BIT(1)) > 0),
2427 500,
2428 10000))
2429 return -ETIMEDOUT;
2430
a2e927b0
BA		 2431 return 0;
2432}
2433
526103b7 2434static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp)
a2e927b0 2435{
8447fa7f 2436 const struct qmp_phy_cfg *cfg = qmp->cfg;
815891ee 2437 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
dd115365 2438 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
a2e927b0 2439 u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
a2e927b0
BA		 2440 u32 status;
2441 int ret;
2442
8447fa7f 2443 ret = qmp_v456_configure_dp_phy(qmp);
a2e927b0
BA		 2444 if (ret < 0)
2445 return ret;
2446
94a407cc
DB		 2447 /*
2448 * At least for 7nm DP PHY this has to be done after enabling link
2449 * clock.
2450 */
2451
2452 if (dp_opts->lanes == 1) {
2453 bias0_en = reverse ? 0x3e : 0x15;
2454 bias1_en = reverse ? 0x15 : 0x3e;
2455 drvr0_en = reverse ? 0x13 : 0x10;
2456 drvr1_en = reverse ? 0x10 : 0x13;
2457 } else if (dp_opts->lanes == 2) {
2458 bias0_en = reverse ? 0x3f : 0x15;
2459 bias1_en = reverse ? 0x15 : 0x3f;
2460 drvr0_en = 0x10;
2461 drvr1_en = 0x10;
2462 } else {
2463 bias0_en = 0x3f;
2464 bias1_en = 0x3f;
2465 drvr0_en = 0x10;
2466 drvr1_en = 0x10;
2467 }
2468
cd1f3343
DB		 2469 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
2470 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
2471 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
2472 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
94a407cc 2473
133836a7 2474 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
94a407cc 2475 udelay(2000);
133836a7 2476 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
94a407cc 2477
8447fa7f 2478 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
94a407cc
DB		 2479 status,
2480 ((status & BIT(1)) > 0),
2481 500,
2482 10000))
2483 return -ETIMEDOUT;
2484
186ad90a
DB		 2485 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
2486 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
94a407cc 2487
186ad90a
DB		 2488 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2489 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
94a407cc 2490
186ad90a
DB		 2491 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2492 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2493
2494 return 0;
94a407cc
DB		 2495
2496 return 0;
2497}
2498
2499/*
2500 * We need to calibrate the aux setting here as many times
2501 * as the caller tries
2502 */
526103b7 2503static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp)
94a407cc
DB		 2504{
2505 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
2506 u8 val;
2507
dd115365
JH		 2508 qmp->dp_aux_cfg++;
2509 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2510 val = cfg1_settings[qmp->dp_aux_cfg];
94a407cc 2511
133836a7 2512 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
94a407cc
DB		 2513
2514 return 0;
2515}
2516
186266f6 2517static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts)
94a407cc
DB		 2518{
2519 const struct phy_configure_opts_dp *dp_opts = &opts->dp;
dd115365
JH		 2520 struct qmp_combo *qmp = phy_get_drvdata(phy);
2521 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 2522
77cbca3a
BA		 2523 mutex_lock(&qmp->phy_mutex);
2524
dd115365
JH		 2525 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts));
2526 if (qmp->dp_opts.set_voltages) {
2527 cfg->configure_dp_tx(qmp);
2528 qmp->dp_opts.set_voltages = 0;
94a407cc
DB		 2529 }
2530
77cbca3a
BA		 2531 mutex_unlock(&qmp->phy_mutex);
2532
94a407cc
DB		 2533 return 0;
2534}
2535
186266f6 2536static int qmp_combo_dp_calibrate(struct phy *phy)
94a407cc 2537{
dd115365
JH		 2538 struct qmp_combo *qmp = phy_get_drvdata(phy);
2539 const struct qmp_phy_cfg *cfg = qmp->cfg;
77cbca3a
BA		 2540 int ret = 0;
2541
2542 mutex_lock(&qmp->phy_mutex);
94a407cc
DB		 2543
2544 if (cfg->calibrate_dp_phy)
77cbca3a 2545 ret = cfg->calibrate_dp_phy(qmp);
94a407cc 2546
77cbca3a
BA		 2547 mutex_unlock(&qmp->phy_mutex);
2548
2549 return ret;
94a407cc
DB		 2550}
2551
2851117f 2552static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
94a407cc 2553{
dd115365 2554 const struct qmp_phy_cfg *cfg = qmp->cfg;
9e5b59ea 2555 void __iomem *com = qmp->com;
1de24861 2556 int ret;
815891ee 2557 u32 val;
94a407cc 2558
2851117f 2559 if (!force && qmp->init_count++)
94a407cc 2560 return 0;
94a407cc 2561
94a407cc
DB		 2562 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2563 if (ret) {
2564 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
9bf03a0c 2565 goto err_decrement_count;
94a407cc
DB		 2566 }
2567
1de24861
DB		 2568 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2569 if (ret) {
2570 dev_err(qmp->dev, "reset assert failed\n");
2571 goto err_disable_regulators;
94a407cc
DB		 2572 }
2573
1de24861
DB		 2574 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2575 if (ret) {
2576 dev_err(qmp->dev, "reset deassert failed\n");
2577 goto err_disable_regulators;
94a407cc
DB		 2578 }
2579
28e265bf 2580 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
94a407cc
DB		 2581 if (ret)
2582 goto err_assert_reset;
2583
9e5b59ea 2584 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN);
94a407cc 2585
9d943961 2586 /* override hardware control for reset of qmp phy */
9e5b59ea 2587 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
9d943961
JH		 2588 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2589 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
94a407cc 2590
815891ee
BA		 2591 /* Use software based port select and switch on typec orientation */
2592 val = SW_PORTSELECT_MUX;
2593 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
2594 val |= SW_PORTSELECT_VAL;
2595 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL);
2596 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
94a407cc 2597
9d943961 2598 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
9e5b59ea 2599 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
9d943961
JH		 2600 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2601 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2602
9e5b59ea
JH		 2603 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
2604 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
94a407cc 2605
dd115365 2606 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
7a7d86d1 2607 SW_PWRDN);
94a407cc 2608
94a407cc
DB		 2609 return 0;
2610
2611err_assert_reset:
1de24861 2612 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
94a407cc
DB		 2613err_disable_regulators:
2614 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
9bf03a0c
JH		 2615err_decrement_count:
2616 qmp->init_count--;
94a407cc
DB		 2617
2618 return ret;
2619}
2620
2851117f 2621static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force)
94a407cc 2622{
dd115365 2623 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 2624
2851117f 2625 if (!force && --qmp->init_count)
94a407cc 2626 return 0;
94a407cc 2627
1de24861 2628 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
94a407cc 2629
28e265bf 2630 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
94a407cc
DB		 2631
2632 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2633
94a407cc
DB		 2634 return 0;
2635}
2636
8c75d9ea 2637static int qmp_combo_dp_init(struct phy *phy)
94a407cc 2638{
dd115365
JH		 2639 struct qmp_combo *qmp = phy_get_drvdata(phy);
2640 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 2641 int ret;
94a407cc 2642
02545aa3
BA		 2643 mutex_lock(&qmp->phy_mutex);
2644
2851117f 2645 ret = qmp_combo_com_init(qmp, false);
94a407cc 2646 if (ret)
02545aa3 2647 goto out_unlock;
94a407cc 2648
dd115365 2649 cfg->dp_aux_init(qmp);
8c75d9ea 2650
2851117f
BA		 2651 qmp->dp_init_count++;
2652
02545aa3
BA		 2653out_unlock:
2654 mutex_unlock(&qmp->phy_mutex);
2655 return ret;
8c75d9ea
JH		 2656}
2657
2658static int qmp_combo_dp_exit(struct phy *phy)
2659{
dd115365 2660 struct qmp_combo *qmp = phy_get_drvdata(phy);
8c75d9ea 2661
02545aa3
BA		 2662 mutex_lock(&qmp->phy_mutex);
2663
2851117f
BA		 2664 qmp_combo_com_exit(qmp, false);
2665
2666 qmp->dp_init_count--;
94a407cc 2667
02545aa3
BA		 2668 mutex_unlock(&qmp->phy_mutex);
2669
94a407cc
DB		 2670 return 0;
2671}
2672
3ade3ede
JH		 2673static int qmp_combo_dp_power_on(struct phy *phy)
2674{
dd115365
JH		 2675 struct qmp_combo *qmp = phy_get_drvdata(phy);
2676 const struct qmp_phy_cfg *cfg = qmp->cfg;
2677 void __iomem *tx = qmp->dp_tx;
2678 void __iomem *tx2 = qmp->dp_tx2;
3ade3ede 2679
77cbca3a
BA		 2680 mutex_lock(&qmp->phy_mutex);
2681
dd115365 2682 qmp_combo_dp_serdes_init(qmp);
3ade3ede 2683
488f116d 2684 qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1);
ba0af7b3 2685 qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2);
3ade3ede
JH		 2686
2687 /* Configure special DP tx tunings */
dd115365 2688 cfg->configure_dp_tx(qmp);
3ade3ede
JH		 2689
2690 /* Configure link rate, swing, etc. */
dd115365 2691 cfg->configure_dp_phy(qmp);
3ade3ede 2692
77cbca3a
BA		 2693 mutex_unlock(&qmp->phy_mutex);
2694
3ade3ede
JH		 2695 return 0;
2696}
2697
2698static int qmp_combo_dp_power_off(struct phy *phy)
2699{
dd115365 2700 struct qmp_combo *qmp = phy_get_drvdata(phy);
3ade3ede 2701
77cbca3a
BA		 2702 mutex_lock(&qmp->phy_mutex);
2703
3ade3ede 2704 /* Assert DP PHY power down */
133836a7 2705 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
3ade3ede 2706
77cbca3a
BA		 2707 mutex_unlock(&qmp->phy_mutex);
2708
3ade3ede
JH		 2709 return 0;
2710}
2711
2712static int qmp_combo_usb_power_on(struct phy *phy)
94a407cc 2713{
dd115365
JH		 2714 struct qmp_combo *qmp = phy_get_drvdata(phy);
2715 const struct qmp_phy_cfg *cfg = qmp->cfg;
2716 void __iomem *serdes = qmp->serdes;
2717 void __iomem *tx = qmp->tx;
2718 void __iomem *rx = qmp->rx;
2719 void __iomem *tx2 = qmp->tx2;
2720 void __iomem *rx2 = qmp->rx2;
2721 void __iomem *pcs = qmp->pcs;
76d20290 2722 void __iomem *pcs_usb = qmp->pcs_usb;
94a407cc 2723 void __iomem *status;
f7075f49 2724 unsigned int val;
94a407cc
DB		 2725 int ret;
2726
dae95d7f 2727 qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
94a407cc 2728
dd115365 2729 ret = clk_prepare_enable(qmp->pipe_clk);
94a407cc
DB		 2730 if (ret) {
2731 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
6066bac1 2732 return ret;
94a407cc
DB		 2733 }
2734
2735 /* Tx, Rx, and PCS configurations */
ccf6f83b 2736 qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
ba0af7b3 2737 qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
94a407cc 2738
ccf6f83b 2739 qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
ba0af7b3 2740 qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
94a407cc 2741
3ade3ede 2742 qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
94a407cc 2743
76d20290
KD		 2744 if (pcs_usb)
2745 qmp_combo_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
2746
94a407cc 2747 if (cfg->has_pwrdn_delay)
acfee73b 2748 usleep_range(10, 20);
94a407cc 2749
3ade3ede
JH		 2750 /* Pull PHY out of reset state */
2751 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2752
2753 /* start SerDes and Phy-Coding-Sublayer */
2754 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
2755
2756 status = pcs + cfg->regs[QPHY_PCS_STATUS];
2757 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
2758 PHY_INIT_COMPLETE_TIMEOUT);
2759 if (ret) {
2760 dev_err(qmp->dev, "phy initialization timed-out\n");
2761 goto err_disable_pipe_clk;
94a407cc 2762 }
3ade3ede 2763
94a407cc
DB		 2764 return 0;
2765
2766err_disable_pipe_clk:
dd115365 2767 clk_disable_unprepare(qmp->pipe_clk);
94a407cc
DB		 2768
2769 return ret;
2770}
2771
3ade3ede 2772static int qmp_combo_usb_power_off(struct phy *phy)
94a407cc 2773{
dd115365
JH		 2774 struct qmp_combo *qmp = phy_get_drvdata(phy);
2775 const struct qmp_phy_cfg *cfg = qmp->cfg;
94a407cc 2776
dd115365 2777 clk_disable_unprepare(qmp->pipe_clk);
94a407cc 2778
3ade3ede 2779 /* PHY reset */
dd115365 2780 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
94a407cc 2781
3ade3ede 2782 /* stop SerDes and Phy-Coding-Sublayer */
dd115365 2783 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
3ade3ede 2784 SERDES_START | PCS_START);
94a407cc 2785
3ade3ede 2786 /* Put PHY into POWER DOWN state: active low */
dd115365 2787 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3ade3ede 2788 SW_PWRDN);
94a407cc
DB		 2789
2790 return 0;
2791}
2792
ae1cdc70 2793static int qmp_combo_usb_init(struct phy *phy)
94a407cc 2794{
dd115365 2795 struct qmp_combo *qmp = phy_get_drvdata(phy);
94a407cc
DB		 2796 int ret;
2797
02545aa3 2798 mutex_lock(&qmp->phy_mutex);
2851117f 2799 ret = qmp_combo_com_init(qmp, false);
94a407cc 2800 if (ret)
02545aa3 2801 goto out_unlock;
94a407cc 2802
3ade3ede 2803 ret = qmp_combo_usb_power_on(phy);
02545aa3 2804 if (ret) {
2851117f 2805 qmp_combo_com_exit(qmp, false);
02545aa3
BA		 2806 goto out_unlock;
2807 }
94a407cc 2808
2851117f
BA		 2809 qmp->usb_init_count++;
2810
02545aa3
BA		 2811out_unlock:
2812 mutex_unlock(&qmp->phy_mutex);
94a407cc
DB		 2813 return ret;
2814}
2815
ae1cdc70 2816static int qmp_combo_usb_exit(struct phy *phy)
94a407cc 2817{
dd115365 2818 struct qmp_combo *qmp = phy_get_drvdata(phy);
94a407cc
DB		 2819 int ret;
2820
02545aa3 2821 mutex_lock(&qmp->phy_mutex);
3ade3ede 2822 ret = qmp_combo_usb_power_off(phy);
94a407cc 2823 if (ret)
02545aa3 2824 goto out_unlock;
8c75d9ea 2825
2851117f 2826 ret = qmp_combo_com_exit(qmp, false);
02545aa3
BA		 2827 if (ret)
2828 goto out_unlock;
2829
2851117f
BA		 2830 qmp->usb_init_count--;
2831
02545aa3
BA		 2832out_unlock:
2833 mutex_unlock(&qmp->phy_mutex);
2834 return ret;
94a407cc
DB		 2835}
2836
ae1cdc70 2837static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
94a407cc 2838{
dd115365 2839 struct qmp_combo *qmp = phy_get_drvdata(phy);
94a407cc 2840
dd115365 2841 qmp->mode = mode;
94a407cc
DB		 2842
2843 return 0;
2844}
2845
d6c81688 2846static const struct phy_ops qmp_combo_usb_phy_ops = {
ae1cdc70
JH		 2847 .init = qmp_combo_usb_init,
2848 .exit = qmp_combo_usb_exit,
2849 .set_mode = qmp_combo_usb_set_mode,
d6c81688
JH		 2850 .owner = THIS_MODULE,
2851};
2852
2853static const struct phy_ops qmp_combo_dp_phy_ops = {
8c75d9ea 2854 .init = qmp_combo_dp_init,
186266f6 2855 .configure = qmp_combo_dp_configure,
3ade3ede 2856 .power_on = qmp_combo_dp_power_on,
186266f6 2857 .calibrate = qmp_combo_dp_calibrate,
3ade3ede 2858 .power_off = qmp_combo_dp_power_off,
8c75d9ea 2859 .exit = qmp_combo_dp_exit,
d6c81688
JH		 2860 .owner = THIS_MODULE,
2861};
2862
dd115365 2863static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp)
94a407cc 2864{
dd115365
JH		 2865 const struct qmp_phy_cfg *cfg = qmp->cfg;
2866 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2867 void __iomem *pcs_misc = qmp->pcs_misc;
94a407cc
DB		 2868 u32 intr_mask;
2869
dd115365
JH		 2870 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2871 qmp->mode == PHY_MODE_USB_DEVICE_SS)
94a407cc
DB		 2872 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2873 else
2874 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2875
2876 /* Clear any pending interrupts status */
fc646236 2877 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 2878 /* Writing 1 followed by 0 clears the interrupt */
fc646236 2879 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 2880
fc646236 2881 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
94a407cc
DB		 2882 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2883
2884 /* Enable required PHY autonomous mode interrupts */
fc646236 2885 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
94a407cc
DB		 2886
2887 /* Enable i/o clamp_n for autonomous mode */
2888 if (pcs_misc)
2889 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2890}
2891
dd115365 2892static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp)
94a407cc 2893{
dd115365
JH		 2894 const struct qmp_phy_cfg *cfg = qmp->cfg;
2895 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2896 void __iomem *pcs_misc = qmp->pcs_misc;
94a407cc
DB		 2897
2898 /* Disable i/o clamp_n on resume for normal mode */
2899 if (pcs_misc)
2900 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2901
fc646236 2902 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
94a407cc
DB		 2903 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2904
fc646236 2905 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc 2906 /* Writing 1 followed by 0 clears the interrupt */
fc646236 2907 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
94a407cc
DB		 2908}
2909
e5cedefa 2910static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev)
94a407cc 2911{
dd115365 2912 struct qmp_combo *qmp = dev_get_drvdata(dev);
94a407cc 2913
dd115365 2914 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
94a407cc 2915
94a407cc
DB		 2916 if (!qmp->init_count) {
2917 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2918 return 0;
2919 }
2920
dd115365 2921 qmp_combo_enable_autonomous_mode(qmp);
94a407cc 2922
dd115365 2923 clk_disable_unprepare(qmp->pipe_clk);
28e265bf 2924 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
94a407cc
DB		 2925
2926 return 0;
2927}
2928
e5cedefa 2929static int __maybe_unused qmp_combo_runtime_resume(struct device *dev)
94a407cc 2930{
dd115365 2931 struct qmp_combo *qmp = dev_get_drvdata(dev);
94a407cc
DB		 2932 int ret = 0;
2933
dd115365 2934 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
94a407cc 2935
94a407cc
DB		 2936 if (!qmp->init_count) {
2937 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2938 return 0;
2939 }
2940
28e265bf 2941 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
94a407cc
DB		 2942 if (ret)
2943 return ret;
2944
dd115365 2945 ret = clk_prepare_enable(qmp->pipe_clk);
94a407cc
DB		 2946 if (ret) {
2947 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
28e265bf 2948 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
94a407cc
DB		 2949 return ret;
2950 }
2951
dd115365 2952 qmp_combo_disable_autonomous_mode(qmp);
94a407cc
DB		 2953
2954 return 0;
2955}
2956
987a505f
JH		 2957static const struct dev_pm_ops qmp_combo_pm_ops = {
2958 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend,
2959 qmp_combo_runtime_resume, NULL)
2960};
2961
44aff8e3 2962static int qmp_combo_vreg_init(struct qmp_combo *qmp)
94a407cc 2963{
44aff8e3
JH		 2964 const struct qmp_phy_cfg *cfg = qmp->cfg;
2965 struct device *dev = qmp->dev;
94a407cc 2966 int num = cfg->num_vregs;
85936d4f 2967 int ret, i;
94a407cc
DB		 2968
2969 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2970 if (!qmp->vregs)
2971 return -ENOMEM;
2972
2973 for (i = 0; i < num; i++)
85936d4f 2974 qmp->vregs[i].supply = cfg->vreg_list[i].name;
94a407cc 2975
85936d4f
KH		 2976 ret = devm_regulator_bulk_get(dev, num, qmp->vregs);
2977 if (ret) {
2978 dev_err(dev, "failed at devm_regulator_bulk_get\n");
2979 return ret;
2980 }
2981
2982 for (i = 0; i < num; i++) {
2983 ret = regulator_set_load(qmp->vregs[i].consumer,
2984 cfg->vreg_list[i].enable_load);
2985 if (ret) {
2986 dev_err(dev, "failed to set load at %s\n",
2987 qmp->vregs[i].supply);
2988 return ret;
2989 }
2990 }
2991
2992 return 0;
94a407cc
DB		 2993}
2994
44aff8e3 2995static int qmp_combo_reset_init(struct qmp_combo *qmp)
94a407cc 2996{
44aff8e3
JH		 2997 const struct qmp_phy_cfg *cfg = qmp->cfg;
2998 struct device *dev = qmp->dev;
94a407cc 2999 int i;
1de24861 3000 int ret;
94a407cc
DB		 3001
3002 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
3003 sizeof(*qmp->resets), GFP_KERNEL);
3004 if (!qmp->resets)
3005 return -ENOMEM;
3006
1de24861
DB		 3007 for (i = 0; i < cfg->num_resets; i++)
3008 qmp->resets[i].id = cfg->reset_list[i];
94a407cc 3009
1de24861
DB		 3010 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
3011 if (ret)
3012 return dev_err_probe(dev, ret, "failed to get resets\n");
94a407cc
DB		 3013
3014 return 0;
3015}
3016
44aff8e3 3017static int qmp_combo_clk_init(struct qmp_combo *qmp)
94a407cc 3018{
44aff8e3 3019 struct device *dev = qmp->dev;
28e265bf 3020 int num = ARRAY_SIZE(qmp_combo_phy_clk_l);
94a407cc
DB		 3021 int i;
3022
3023 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
3024 if (!qmp->clks)
3025 return -ENOMEM;
3026
3027 for (i = 0; i < num; i++)
28e265bf 3028 qmp->clks[i].id = qmp_combo_phy_clk_l[i];
94a407cc 3029
28e265bf
DB		 3030 qmp->num_clks = num;
3031
3032 return devm_clk_bulk_get_optional(dev, num, qmp->clks);
94a407cc
DB		 3033}
3034
3035static void phy_clk_release_provider(void *res)
3036{
3037 of_clk_del_provider(res);
3038}
3039
3040/*
3041 * Register a fixed rate pipe clock.
3042 *
3043 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
3044 * controls it. The <s>_pipe_clk coming out of the GCC is requested
3045 * by the PHY driver for its operations.
3046 * We register the <s>_pipe_clksrc here. The gcc driver takes care
3047 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
3048 * Below picture shows this relationship.
3049 *
3050 * +---------------+
3051 * | PHY block |<<---------------------------------------+
3052 * | | |
3053 * | +-------+ | +-----+ |
3054 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
3055 * clk | +-------+ | +-----+
3056 * +---------------+
3057 */
dd115365 3058static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np)
94a407cc 3059{
55b1c39b 3060 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
94a407cc 3061 struct clk_init_data init = { };
0dd521d5 3062 char name[64];
94a407cc 3063
0dd521d5
JH		 3064 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev));
3065 init.name = name;
94a407cc
DB		 3066 init.ops = &clk_fixed_rate_ops;
3067
3068 /* controllers using QMP phys use 125MHz pipe clock interface */
3069 fixed->fixed_rate = 125000000;
3070 fixed->hw.init = &init;
3071
ce51f7a7 3072 return devm_clk_hw_register(qmp->dev, &fixed->hw);
94a407cc
DB		 3073}
3074
3075/*
3076 * Display Port PLL driver block diagram for branch clocks
3077 *
3078 * +------------------------------+
3079 * | DP_VCO_CLK |
3080 * | |
3081 * | +-------------------+ |
3082 * | | (DP PLL/VCO) | |
3083 * | +---------+---------+ |
3084 * | v |
3085 * | +----------+-----------+ |
3086 * | | hsclk_divsel_clk_src | |
3087 * | +----------+-----------+ |
3088 * +------------------------------+
3089 * |
3090 * +---------<---------v------------>----------+
3091 * | |
3092 * +--------v----------------+ |
3093 * | dp_phy_pll_link_clk | |
3094 * | link_clk | |
3095 * +--------+----------------+ |
3096 * | |
3097 * | |
3098 * v v
3099 * Input to DISPCC block |
3100 * for link clk, crypto clk |
3101 * and interface clock |
3102 * |
3103 * |
3104 * +--------<------------+-----------------+---<---+
3105 * | | |
3106 * +----v---------+ +--------v-----+ +--------v------+
3107 * | vco_divided | | vco_divided | | vco_divided |
3108 * | _clk_src | | _clk_src | | _clk_src |
3109 * | | | | | |
3110 * |divsel_six | | divsel_two | | divsel_four |
3111 * +-------+------+ +-----+--------+ +--------+------+
3112 * | | |
3113 * v---->----------v-------------<------v
3114 * |
3115 * +----------+-----------------+
3116 * | dp_phy_pll_vco_div_clk |
3117 * +---------+------------------+
3118 * |
3119 * v
3120 * Input to DISPCC block
3121 * for DP pixel clock
3122 *
3123 */
b71bf1eb 3124static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
94a407cc
DB		 3125{
3126 switch (req->rate) {
3127 case 1620000000UL / 2:
3128 case 2700000000UL / 2:
3129 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
3130 return 0;
3131 default:
3132 return -EINVAL;
3133 }
3134}
3135
b71bf1eb 3136static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
94a407cc 3137{
dd115365 3138 const struct qmp_combo *qmp;
94a407cc
DB		 3139 const struct phy_configure_opts_dp *dp_opts;
3140
ee81f2eb 3141 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw);
dd115365 3142 dp_opts = &qmp->dp_opts;
94a407cc
DB		 3143
3144 switch (dp_opts->link_rate) {
3145 case 1620:
3146 return 1620000000UL / 2;
3147 case 2700:
3148 return 2700000000UL / 2;
3149 case 5400:
3150 return 5400000000UL / 4;
3151 case 8100:
3152 return 8100000000UL / 6;
3153 default:
3154 return 0;
3155 }
3156}
3157
b71bf1eb
JH		 3158static const struct clk_ops qmp_dp_pixel_clk_ops = {
3159 .determine_rate = qmp_dp_pixel_clk_determine_rate,
3160 .recalc_rate = qmp_dp_pixel_clk_recalc_rate,
94a407cc
DB		 3161};
3162
b71bf1eb 3163static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
94a407cc
DB		 3164{
3165 switch (req->rate) {
3166 case 162000000:
3167 case 270000000:
3168 case 540000000:
3169 case 810000000:
3170 return 0;
3171 default:
3172 return -EINVAL;
3173 }
3174}
3175
b71bf1eb 3176static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
94a407cc 3177{
dd115365 3178 const struct qmp_combo *qmp;
94a407cc
DB		 3179 const struct phy_configure_opts_dp *dp_opts;
3180
ee81f2eb 3181 qmp = container_of(hw, struct qmp_combo, dp_link_hw);
dd115365 3182 dp_opts = &qmp->dp_opts;
94a407cc
DB		 3183
3184 switch (dp_opts->link_rate) {
3185 case 1620:
3186 case 2700:
3187 case 5400:
3188 case 8100:
3189 return dp_opts->link_rate * 100000;
3190 default:
3191 return 0;
3192 }
3193}
3194
b71bf1eb
JH		 3195static const struct clk_ops qmp_dp_link_clk_ops = {
3196 .determine_rate = qmp_dp_link_clk_determine_rate,
3197 .recalc_rate = qmp_dp_link_clk_recalc_rate,
94a407cc
DB		 3198};
3199
b71bf1eb 3200static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
94a407cc 3201{
ee81f2eb 3202 struct qmp_combo *qmp = data;
94a407cc
DB		 3203 unsigned int idx = clkspec->args[0];
3204
3205 if (idx >= 2) {
3206 pr_err("%s: invalid index %u\n", __func__, idx);
3207 return ERR_PTR(-EINVAL);
3208 }
3209
3210 if (idx == 0)
ee81f2eb 3211 return &qmp->dp_link_hw;
94a407cc 3212
ee81f2eb 3213 return &qmp->dp_pixel_hw;
94a407cc
DB		 3214}
3215
dd115365 3216static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np)
94a407cc
DB		 3217{
3218 struct clk_init_data init = { };
94a407cc
DB		 3219 char name[64];
3220 int ret;
3221
94a407cc 3222 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
b71bf1eb 3223 init.ops = &qmp_dp_link_clk_ops;
94a407cc 3224 init.name = name;
ee81f2eb
JH		 3225 qmp->dp_link_hw.init = &init;
3226 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw);
94a407cc
DB		 3227 if (ret)
3228 return ret;
3229
3230 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
b71bf1eb 3231 init.ops = &qmp_dp_pixel_clk_ops;
94a407cc 3232 init.name = name;
ee81f2eb
JH		 3233 qmp->dp_pixel_hw.init = &init;
3234 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw);
94a407cc
DB		 3235 if (ret)
3236 return ret;
3237
ce51f7a7 3238 return 0;
94a407cc
DB		 3239}
3240
83a0bbe3
JH		 3241static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data)
3242{
3243 struct qmp_combo *qmp = data;
3244
3245 switch (clkspec->args[0]) {
3246 case QMP_USB43DP_USB3_PIPE_CLK:
3247 return &qmp->pipe_clk_fixed.hw;
3248 case QMP_USB43DP_DP_LINK_CLK:
3249 return &qmp->dp_link_hw;
3250 case QMP_USB43DP_DP_VCO_DIV_CLK:
3251 return &qmp->dp_pixel_hw;
3252 }
3253
3254 return ERR_PTR(-EINVAL);
3255}
3256
74401c85
JH		 3257static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np,
3258 struct device_node *dp_np)
3259{
3260 int ret;
3261
3262 ret = phy_pipe_clk_register(qmp, usb_np);
3263 if (ret)
3264 return ret;
3265
3266 ret = phy_dp_clks_register(qmp, dp_np);
3267 if (ret)
3268 return ret;
3269
83a0bbe3
JH		 3270 /*
3271 * Register a single provider for bindings without child nodes.
3272 */
3273 if (usb_np == qmp->dev->of_node)
3274 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp);
3275
3276 /*
3277 * Register multiple providers for legacy bindings with child nodes.
3278 */
ce51f7a7
JH		 3279 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get,
3280 &qmp->pipe_clk_fixed.hw);
3281 if (ret)
3282 return ret;
3283
3284 /*
3285 * Roll a devm action because the clock provider is the child node, but
3286 * the child node is not actually a device.
3287 */
3288 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np);
3289 if (ret)
3290 return ret;
3291
b71bf1eb 3292 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp);
ce51f7a7
JH		 3293 if (ret)
3294 return ret;
3295
3296 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np);
74401c85
JH		 3297}
3298
2851117f
BA		 3299#if IS_ENABLED(CONFIG_TYPEC)
3300static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw,
3301 enum typec_orientation orientation)
3302{
3303 struct qmp_combo *qmp = typec_switch_get_drvdata(sw);
3304 const struct qmp_phy_cfg *cfg = qmp->cfg;
3305
3306 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE)
3307 return 0;
3308
3309 mutex_lock(&qmp->phy_mutex);
3310 qmp->orientation = orientation;
3311
3312 if (qmp->init_count) {
3313 if (qmp->usb_init_count)
3314 qmp_combo_usb_power_off(qmp->usb_phy);
3315 qmp_combo_com_exit(qmp, true);
3316
3317 qmp_combo_com_init(qmp, true);
3318 if (qmp->usb_init_count)
3319 qmp_combo_usb_power_on(qmp->usb_phy);
3320 if (qmp->dp_init_count)
3321 cfg->dp_aux_init(qmp);
3322 }
3323 mutex_unlock(&qmp->phy_mutex);
3324
3325 return 0;
3326}
3327
3328static void qmp_combo_typec_unregister(void *data)
3329{
3330 struct qmp_combo *qmp = data;
3331
3332 typec_switch_unregister(qmp->sw);
3333}
3334
3335static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
3336{
3337 struct typec_switch_desc sw_desc = {};
3338 struct device *dev = qmp->dev;
3339
3340 sw_desc.drvdata = qmp;
3341 sw_desc.fwnode = dev->fwnode;
3342 sw_desc.set = qmp_combo_typec_switch_set;
3343 qmp->sw = typec_switch_register(dev, &sw_desc);
3344 if (IS_ERR(qmp->sw)) {
3345 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw);
3346 return PTR_ERR(qmp->sw);
3347 }
3348
3349 return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp);
3350}
3351#else
3352static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
3353{
3354 return 0;
3355}
3356#endif
3357
b3982f21 3358static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np)
94a407cc 3359{
44aff8e3 3360 struct device *dev = qmp->dev;
94a407cc 3361
94a407cc 3362 /*
c7fbe5bd 3363 * Get memory resources from the DP child node:
ba0af7b3
JH		 3364 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3365 * tx2 -> 3; rx2 -> 4
c7fbe5bd 3366 *
133836a7
JH		 3367 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP
3368 * implementation.
c7fbe5bd 3369 */
dd115365
JH		 3370 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL);
3371 if (IS_ERR(qmp->dp_tx))
3372 return PTR_ERR(qmp->dp_tx);
c7fbe5bd 3373
133836a7
JH		 3374 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL);
3375 if (IS_ERR(qmp->dp_dp_phy))
3376 return PTR_ERR(qmp->dp_dp_phy);
c7fbe5bd 3377
dd115365
JH		 3378 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL);
3379 if (IS_ERR(qmp->dp_tx2))
3380 return PTR_ERR(qmp->dp_tx2);
c7fbe5bd 3381
c7fbe5bd
JH		 3382 return 0;
3383}
3384
b3982f21 3385static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np)
c7fbe5bd 3386{
44aff8e3
JH		 3387 const struct qmp_phy_cfg *cfg = qmp->cfg;
3388 struct device *dev = qmp->dev;
c7fbe5bd 3389
c7fbe5bd
JH		 3390 /*
3391 * Get memory resources from the USB child node:
ba0af7b3
JH		 3392 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3393 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5
94a407cc 3394 */
dd115365
JH		 3395 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
3396 if (IS_ERR(qmp->tx))
3397 return PTR_ERR(qmp->tx);
94a407cc 3398
dd115365
JH		 3399 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
3400 if (IS_ERR(qmp->rx))
3401 return PTR_ERR(qmp->rx);
94a407cc 3402
dd115365
JH		 3403 qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
3404 if (IS_ERR(qmp->pcs))
3405 return PTR_ERR(qmp->pcs);
94a407cc 3406
fc646236 3407 if (cfg->pcs_usb_offset)
dd115365 3408 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
fc646236 3409
dd115365
JH		 3410 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
3411 if (IS_ERR(qmp->tx2))
3412 return PTR_ERR(qmp->tx2);
94a407cc 3413
dd115365
JH		 3414 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
3415 if (IS_ERR(qmp->rx2))
3416 return PTR_ERR(qmp->rx2);
94a407cc 3417
dd115365
JH		 3418 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
3419 if (IS_ERR(qmp->pcs_misc)) {
94a407cc 3420 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
dd115365 3421 qmp->pcs_misc = NULL;
2de8a325 3422 }
94a407cc 3423
dd115365
JH		 3424 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
3425 if (IS_ERR(qmp->pipe_clk)) {
3426 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3427 "failed to get pipe clock\n");
94a407cc
DB		 3428 }
3429
b3982f21
JH		 3430 return 0;
3431}
3432
3433static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np,
3434 struct device_node *dp_np)
3435{
3436 struct platform_device *pdev = to_platform_device(qmp->dev);
3437 int ret;
3438
3439 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
3440 if (IS_ERR(qmp->serdes))
3441 return PTR_ERR(qmp->serdes);
3442
9e5b59ea
JH		 3443 qmp->com = devm_platform_ioremap_resource(pdev, 1);
3444 if (IS_ERR(qmp->com))
3445 return PTR_ERR(qmp->com);
b3982f21
JH		 3446
3447 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2);
3448 if (IS_ERR(qmp->dp_serdes))
3449 return PTR_ERR(qmp->dp_serdes);
3450
3451 ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np);
3452 if (ret)
94a407cc 3453 return ret;
94a407cc 3454
b3982f21
JH		 3455 ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np);
3456 if (ret)
3457 return ret;
94a407cc 3458
b83eb8ba
DB		 3459 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
3460 if (ret < 0)
3461 return ret;
3462
3463 qmp->num_clks = ret;
3464
94a407cc
DB		 3465 return 0;
3466}
3467
83a0bbe3
JH		 3468static int qmp_combo_parse_dt(struct qmp_combo *qmp)
3469{
3470 struct platform_device *pdev = to_platform_device(qmp->dev);
3471 const struct qmp_phy_cfg *cfg = qmp->cfg;
3472 const struct qmp_combo_offsets *offs = cfg->offsets;
3473 struct device *dev = qmp->dev;
3474 void __iomem *base;
28e265bf 3475 int ret;
83a0bbe3
JH		 3476
3477 if (!offs)
3478 return -EINVAL;
3479
3480 base = devm_platform_ioremap_resource(pdev, 0);
3481 if (IS_ERR(base))
3482 return PTR_ERR(base);
3483
3484 qmp->com = base + offs->com;
3485 qmp->tx = base + offs->txa;
3486 qmp->rx = base + offs->rxa;
3487 qmp->tx2 = base + offs->txb;
3488 qmp->rx2 = base + offs->rxb;
3489
3490 qmp->serdes = base + offs->usb3_serdes;
3491 qmp->pcs_misc = base + offs->usb3_pcs_misc;
3492 qmp->pcs = base + offs->usb3_pcs;
3493 qmp->pcs_usb = base + offs->usb3_pcs_usb;
3494
3495 qmp->dp_serdes = base + offs->dp_serdes;
05bd1834
LW		 3496 if (offs->dp_txa) {
3497 qmp->dp_tx = base + offs->dp_txa;
3498 qmp->dp_tx2 = base + offs->dp_txb;
3499 } else {
3500 qmp->dp_tx = base + offs->txa;
3501 qmp->dp_tx2 = base + offs->txb;
3502 }
83a0bbe3
JH		 3503 qmp->dp_dp_phy = base + offs->dp_dp_phy;
3504
28e265bf
DB		 3505 ret = qmp_combo_clk_init(qmp);
3506 if (ret)
3507 return ret;
3508
83a0bbe3
JH		 3509 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe");
3510 if (IS_ERR(qmp->pipe_clk)) {
3511 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3512 "failed to get usb3_pipe clock\n");
3513 }
3514
3515 return 0;
3516}
3517
3518static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args)
3519{
3520 struct qmp_combo *qmp = dev_get_drvdata(dev);
3521
3522 if (args->args_count == 0)
3523 return ERR_PTR(-EINVAL);
3524
3525 switch (args->args[0]) {
3526 case QMP_USB43DP_USB3_PHY:
3527 return qmp->usb_phy;
3528 case QMP_USB43DP_DP_PHY:
3529 return qmp->dp_phy;
3530 }
3531
3532 return ERR_PTR(-EINVAL);
3533}
3534
e5cedefa 3535static int qmp_combo_probe(struct platform_device *pdev)
94a407cc 3536{
dd115365 3537 struct qmp_combo *qmp;
94a407cc 3538 struct device *dev = &pdev->dev;
6c7c449a 3539 struct device_node *dp_np, *usb_np;
94a407cc 3540 struct phy_provider *phy_provider;
94a407cc
DB		 3541 int ret;
3542
3543 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
3544 if (!qmp)
3545 return -ENOMEM;
3546
3547 qmp->dev = dev;
94a407cc 3548
815891ee
BA		 3549 qmp->orientation = TYPEC_ORIENTATION_NORMAL;
3550
44aff8e3
JH		 3551 qmp->cfg = of_device_get_match_data(dev);
3552 if (!qmp->cfg)
ee7ffc92 3553 return -EINVAL;
94a407cc 3554
94a407cc
DB		 3555 mutex_init(&qmp->phy_mutex);
3556
44aff8e3 3557 ret = qmp_combo_reset_init(qmp);
94a407cc
DB		 3558 if (ret)
3559 return ret;
3560
44aff8e3 3561 ret = qmp_combo_vreg_init(qmp);
4c0255e7 3562 if (ret)
28d74fc3 3563 return ret;
94a407cc 3564
83a0bbe3 3565 /* Check for legacy binding with child nodes. */
6c7c449a 3566 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy");
83a0bbe3
JH		 3567 if (usb_np) {
3568 dp_np = of_get_child_by_name(dev->of_node, "dp-phy");
3569 if (!dp_np) {
3570 of_node_put(usb_np);
3571 return -EINVAL;
3572 }
6c7c449a 3573
83a0bbe3
JH		 3574 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np);
3575 } else {
3576 usb_np = of_node_get(dev->of_node);
3577 dp_np = of_node_get(dev->of_node);
94a407cc 3578
83a0bbe3
JH		 3579 ret = qmp_combo_parse_dt(qmp);
3580 }
b3982f21
JH		 3581 if (ret)
3582 goto err_node_put;
3583
47b412c1
JH		 3584 ret = qmp_combo_typec_switch_register(qmp);
3585 if (ret)
3586 goto err_node_put;
3587
d2d7b8e8
JH		 3588 ret = drm_aux_bridge_register(dev);
3589 if (ret)
3590 goto err_node_put;
3591
94a407cc 3592 pm_runtime_set_active(dev);
4382d518
JH		 3593 ret = devm_pm_runtime_enable(dev);
3594 if (ret)
6c7c449a 3595 goto err_node_put;
94a407cc
DB		 3596 /*
3597 * Prevent runtime pm from being ON by default. Users can enable
3598 * it using power/control in sysfs.
3599 */
3600 pm_runtime_forbid(dev);
3601
74401c85 3602 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np);
6c7c449a
JH		 3603 if (ret)
3604 goto err_node_put;
94a407cc 3605
b3982f21
JH		 3606 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops);
3607 if (IS_ERR(qmp->usb_phy)) {
3608 ret = PTR_ERR(qmp->usb_phy);
3609 dev_err(dev, "failed to create USB PHY: %d\n", ret);
6c7c449a 3610 goto err_node_put;
b3982f21 3611 }
6c7c449a 3612
b3982f21
JH		 3613 phy_set_drvdata(qmp->usb_phy, qmp);
3614
3615 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops);
3616 if (IS_ERR(qmp->dp_phy)) {
3617 ret = PTR_ERR(qmp->dp_phy);
3618 dev_err(dev, "failed to create DP PHY: %d\n", ret);
6c7c449a 3619 goto err_node_put;
b3982f21
JH		 3620 }
3621
3622 phy_set_drvdata(qmp->dp_phy, qmp);
7a7d86d1 3623
83a0bbe3
JH		 3624 dev_set_drvdata(dev, qmp);
3625
3626 if (usb_np == dev->of_node)
3627 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate);
3628 else
3629 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
94a407cc 3630
6c7c449a
JH		 3631 of_node_put(usb_np);
3632 of_node_put(dp_np);
3633
94a407cc
DB		 3634 return PTR_ERR_OR_ZERO(phy_provider);
3635
3636err_node_put:
6c7c449a
JH		 3637 of_node_put(usb_np);
3638 of_node_put(dp_np);
94a407cc
DB		 3639 return ret;
3640}
3641
5c5f9fbc
JH		 3642static const struct of_device_id qmp_combo_of_match_table[] = {
3643 {
3644 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
3645 .data = &sc7180_usb3dpphy_cfg,
3646 },
486392f4
DB		 3647 {
3648 .compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3649 .data = &sm8250_usb3dpphy_cfg,
3650 },
5c5f9fbc
JH		 3651 {
3652 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
3653 .data = &sc8180x_usb3dpphy_cfg,
3654 },
3655 {
3656 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy",
ad4db91d 3657 .data = &sc8280xp_usb43dpphy_cfg,
5c5f9fbc
JH		 3658 },
3659 {
3660 .compatible = "qcom,sdm845-qmp-usb3-dp-phy",
3661 .data = &sdm845_usb3dpphy_cfg,
3662 },
05bd1834
LW		 3663 {
3664 .compatible = "qcom,sm6350-qmp-usb3-dp-phy",
3665 .data = &sm6350_usb3dpphy_cfg,
3666 },
757a788c
DB		 3667 {
3668 .compatible = "qcom,sm8150-qmp-usb3-dp-phy",
3669 .data = &sc8180x_usb3dpphy_cfg,
3670 },
5c5f9fbc
JH		 3671 {
3672 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
3673 .data = &sm8250_usb3dpphy_cfg,
3674 },
ef14aff1
NA		 3675 {
3676 .compatible = "qcom,sm8350-qmp-usb3-dp-phy",
3677 .data = &sm8350_usb3dpphy_cfg,
3678 },
3679 {
3680 .compatible = "qcom,sm8450-qmp-usb3-dp-phy",
3681 .data = &sm8350_usb3dpphy_cfg,
3682 },
49742e9e
AV		 3683 {
3684 .compatible = "qcom,sm8550-qmp-usb3-dp-phy",
3685 .data = &sm8550_usb3dpphy_cfg,
3686 },
80c1afe8
NA		 3687 {
3688 .compatible = "qcom,sm8650-qmp-usb3-dp-phy",
3689 .data = &sm8550_usb3dpphy_cfg,
3690 },
d7b3579f
AV		 3691 {
3692 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy",
3693 .data = &x1e80100_usb3dpphy_cfg,
3694 },
5c5f9fbc
JH		 3695 { }
3696};
3697MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table);
3698
e5cedefa
JH		 3699static struct platform_driver qmp_combo_driver = {
3700 .probe = qmp_combo_probe,
94a407cc 3701 .driver = {
ee7ffc92 3702 .name = "qcom-qmp-combo-phy",
e5cedefa
JH		 3703 .pm = &qmp_combo_pm_ops,
3704 .of_match_table = qmp_combo_of_match_table,
94a407cc
DB		 3705 },
3706};
3707
e5cedefa 3708module_platform_driver(qmp_combo_driver);
94a407cc
DB		 3709
3710MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
ee7ffc92 3711MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver");
94a407cc 3712MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)