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1ccea77e | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
88e670fe LH |
2 | /* |
3 | * AppliedMicro X-Gene Multi-purpose PHY driver | |
4 | * | |
5 | * Copyright (c) 2014, Applied Micro Circuits Corporation | |
6 | * Author: Loc Ho <lho@apm.com> | |
7 | * Tuan Phan <tphan@apm.com> | |
8 | * Suman Tripathi <stripathi@apm.com> | |
9 | * | |
88e670fe LH |
10 | * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes. |
11 | * The first PLL clock macro is used for internal reference clock. The second | |
12 | * PLL clock macro is used to generate the clock for the PHY. This driver | |
13 | * configures the first PLL CMU, the second PLL CMU, and programs the PHY to | |
14 | * operate according to the mode of operation. The first PLL CMU is only | |
15 | * required if internal clock is enabled. | |
16 | * | |
17 | * Logical Layer Out Of HW module units: | |
18 | * | |
19 | * ----------------- | |
20 | * | Internal | |------| | |
21 | * | Ref PLL CMU |----| | ------------- --------- | |
22 | * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes| | |
23 | * | | | | --------- | |
24 | * External Clock ------| | ------------- | |
25 | * |------| | |
26 | * | |
27 | * The Ref PLL CMU CSR (Configuration System Registers) is accessed | |
28 | * indirectly from the SDS offset at 0x2000. It is only required for | |
29 | * internal reference clock. | |
30 | * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000. | |
31 | * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400. | |
32 | * | |
33 | * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP | |
34 | * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP, | |
35 | * it is located outside the PHY IP. This is the case for the PHY located | |
36 | * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required | |
37 | * to located the SDS/Ref PLL CMU module and its clock for that IP enabled. | |
38 | * | |
39 | * Currently, this driver only supports Gen3 SATA mode with external clock. | |
40 | */ | |
41 | #include <linux/module.h> | |
42 | #include <linux/platform_device.h> | |
43 | #include <linux/io.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/phy/phy.h> | |
46 | #include <linux/clk.h> | |
47 | ||
48 | /* Max 2 lanes per a PHY unit */ | |
49 | #define MAX_LANE 2 | |
50 | ||
51 | /* Register offset inside the PHY */ | |
52 | #define SERDES_PLL_INDIRECT_OFFSET 0x0000 | |
53 | #define SERDES_PLL_REF_INDIRECT_OFFSET 0x2000 | |
54 | #define SERDES_INDIRECT_OFFSET 0x0400 | |
55 | #define SERDES_LANE_STRIDE 0x0200 | |
56 | ||
57 | /* Some default Serdes parameters */ | |
58 | #define DEFAULT_SATA_TXBOOST_GAIN { 0x1e, 0x1e, 0x1e } | |
59 | #define DEFAULT_SATA_TXEYEDIRECTION { 0x0, 0x0, 0x0 } | |
60 | #define DEFAULT_SATA_TXEYETUNING { 0xa, 0xa, 0xa } | |
61 | #define DEFAULT_SATA_SPD_SEL { 0x1, 0x3, 0x7 } | |
62 | #define DEFAULT_SATA_TXAMP { 0x8, 0x8, 0x8 } | |
63 | #define DEFAULT_SATA_TXCN1 { 0x2, 0x2, 0x2 } | |
64 | #define DEFAULT_SATA_TXCN2 { 0x0, 0x0, 0x0 } | |
65 | #define DEFAULT_SATA_TXCP1 { 0xa, 0xa, 0xa } | |
66 | ||
67 | #define SATA_SPD_SEL_GEN3 0x7 | |
68 | #define SATA_SPD_SEL_GEN2 0x3 | |
69 | #define SATA_SPD_SEL_GEN1 0x1 | |
70 | ||
71 | #define SSC_DISABLE 0 | |
72 | #define SSC_ENABLE 1 | |
73 | ||
74 | #define FBDIV_VAL_50M 0x77 | |
75 | #define REFDIV_VAL_50M 0x1 | |
76 | #define FBDIV_VAL_100M 0x3B | |
77 | #define REFDIV_VAL_100M 0x0 | |
78 | ||
79 | /* SATA Clock/Reset CSR */ | |
80 | #define SATACLKENREG 0x00000000 | |
81 | #define SATA0_CORE_CLKEN 0x00000002 | |
82 | #define SATA1_CORE_CLKEN 0x00000004 | |
83 | #define SATASRESETREG 0x00000004 | |
84 | #define SATA_MEM_RESET_MASK 0x00000020 | |
85 | #define SATA_MEM_RESET_RD(src) (((src) & 0x00000020) >> 5) | |
86 | #define SATA_SDS_RESET_MASK 0x00000004 | |
87 | #define SATA_CSR_RESET_MASK 0x00000001 | |
88 | #define SATA_CORE_RESET_MASK 0x00000002 | |
89 | #define SATA_PMCLK_RESET_MASK 0x00000010 | |
90 | #define SATA_PCLK_RESET_MASK 0x00000008 | |
91 | ||
92 | /* SDS CSR used for PHY Indirect access */ | |
93 | #define SATA_ENET_SDS_PCS_CTL0 0x00000000 | |
94 | #define REGSPEC_CFG_I_TX_WORDMODE0_SET(dst, src) \ | |
95 | (((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000)) | |
96 | #define REGSPEC_CFG_I_RX_WORDMODE0_SET(dst, src) \ | |
97 | (((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000)) | |
98 | #define SATA_ENET_SDS_CTL0 0x0000000c | |
99 | #define REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(dst, src) \ | |
100 | (((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff)) | |
101 | #define SATA_ENET_SDS_CTL1 0x00000010 | |
102 | #define CFG_I_SPD_SEL_CDR_OVR1_SET(dst, src) \ | |
103 | (((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f)) | |
104 | #define SATA_ENET_SDS_RST_CTL 0x00000024 | |
105 | #define SATA_ENET_SDS_IND_CMD_REG 0x0000003c | |
106 | #define CFG_IND_WR_CMD_MASK 0x00000001 | |
107 | #define CFG_IND_RD_CMD_MASK 0x00000002 | |
108 | #define CFG_IND_CMD_DONE_MASK 0x00000004 | |
109 | #define CFG_IND_ADDR_SET(dst, src) \ | |
110 | (((dst) & ~0x003ffff0) | (((u32) (src) << 4) & 0x003ffff0)) | |
111 | #define SATA_ENET_SDS_IND_RDATA_REG 0x00000040 | |
112 | #define SATA_ENET_SDS_IND_WDATA_REG 0x00000044 | |
113 | #define SATA_ENET_CLK_MACRO_REG 0x0000004c | |
114 | #define I_RESET_B_SET(dst, src) \ | |
115 | (((dst) & ~0x00000001) | (((u32) (src)) & 0x00000001)) | |
116 | #define I_PLL_FBDIV_SET(dst, src) \ | |
117 | (((dst) & ~0x001ff000) | (((u32) (src) << 12) & 0x001ff000)) | |
118 | #define I_CUSTOMEROV_SET(dst, src) \ | |
119 | (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80)) | |
120 | #define O_PLL_LOCK_RD(src) (((src) & 0x40000000) >> 30) | |
121 | #define O_PLL_READY_RD(src) (((src) & 0x80000000) >> 31) | |
122 | ||
123 | /* PLL Clock Macro Unit (CMU) CSR accessing from SDS indirectly */ | |
124 | #define CMU_REG0 0x00000 | |
125 | #define CMU_REG0_PLL_REF_SEL_MASK 0x00002000 | |
126 | #define CMU_REG0_PLL_REF_SEL_SET(dst, src) \ | |
127 | (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000)) | |
128 | #define CMU_REG0_PDOWN_MASK 0x00004000 | |
129 | #define CMU_REG0_CAL_COUNT_RESOL_SET(dst, src) \ | |
130 | (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0)) | |
131 | #define CMU_REG1 0x00002 | |
132 | #define CMU_REG1_PLL_CP_SET(dst, src) \ | |
133 | (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00)) | |
134 | #define CMU_REG1_PLL_MANUALCAL_SET(dst, src) \ | |
135 | (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) | |
136 | #define CMU_REG1_PLL_CP_SEL_SET(dst, src) \ | |
137 | (((dst) & ~0x000003e0) | (((u32) (src) << 5) & 0x000003e0)) | |
138 | #define CMU_REG1_REFCLK_CMOS_SEL_MASK 0x00000001 | |
139 | #define CMU_REG1_REFCLK_CMOS_SEL_SET(dst, src) \ | |
140 | (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001)) | |
141 | #define CMU_REG2 0x00004 | |
142 | #define CMU_REG2_PLL_REFDIV_SET(dst, src) \ | |
143 | (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000)) | |
144 | #define CMU_REG2_PLL_LFRES_SET(dst, src) \ | |
145 | (((dst) & ~0x0000001e) | (((u32) (src) << 1) & 0x0000001e)) | |
146 | #define CMU_REG2_PLL_FBDIV_SET(dst, src) \ | |
147 | (((dst) & ~0x00003fe0) | (((u32) (src) << 5) & 0x00003fe0)) | |
148 | #define CMU_REG3 0x00006 | |
149 | #define CMU_REG3_VCOVARSEL_SET(dst, src) \ | |
150 | (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f)) | |
151 | #define CMU_REG3_VCO_MOMSEL_INIT_SET(dst, src) \ | |
152 | (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0)) | |
153 | #define CMU_REG3_VCO_MANMOMSEL_SET(dst, src) \ | |
154 | (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00)) | |
155 | #define CMU_REG4 0x00008 | |
156 | #define CMU_REG5 0x0000a | |
157 | #define CMU_REG5_PLL_LFSMCAP_SET(dst, src) \ | |
158 | (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000)) | |
159 | #define CMU_REG5_PLL_LOCK_RESOLUTION_SET(dst, src) \ | |
160 | (((dst) & ~0x0000000e) | (((u32) (src) << 1) & 0x0000000e)) | |
161 | #define CMU_REG5_PLL_LFCAP_SET(dst, src) \ | |
162 | (((dst) & ~0x00003000) | (((u32) (src) << 12) & 0x00003000)) | |
163 | #define CMU_REG5_PLL_RESETB_MASK 0x00000001 | |
164 | #define CMU_REG6 0x0000c | |
165 | #define CMU_REG6_PLL_VREGTRIM_SET(dst, src) \ | |
166 | (((dst) & ~0x00000600) | (((u32) (src) << 9) & 0x00000600)) | |
167 | #define CMU_REG6_MAN_PVT_CAL_SET(dst, src) \ | |
168 | (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004)) | |
169 | #define CMU_REG7 0x0000e | |
170 | #define CMU_REG7_PLL_CALIB_DONE_RD(src) ((0x00004000 & (u32) (src)) >> 14) | |
171 | #define CMU_REG7_VCO_CAL_FAIL_RD(src) ((0x00000c00 & (u32) (src)) >> 10) | |
172 | #define CMU_REG8 0x00010 | |
173 | #define CMU_REG9 0x00012 | |
174 | #define CMU_REG9_WORD_LEN_8BIT 0x000 | |
175 | #define CMU_REG9_WORD_LEN_10BIT 0x001 | |
176 | #define CMU_REG9_WORD_LEN_16BIT 0x002 | |
177 | #define CMU_REG9_WORD_LEN_20BIT 0x003 | |
178 | #define CMU_REG9_WORD_LEN_32BIT 0x004 | |
179 | #define CMU_REG9_WORD_LEN_40BIT 0x005 | |
180 | #define CMU_REG9_WORD_LEN_64BIT 0x006 | |
181 | #define CMU_REG9_WORD_LEN_66BIT 0x007 | |
182 | #define CMU_REG9_TX_WORD_MODE_CH1_SET(dst, src) \ | |
183 | (((dst) & ~0x00000380) | (((u32) (src) << 7) & 0x00000380)) | |
184 | #define CMU_REG9_TX_WORD_MODE_CH0_SET(dst, src) \ | |
185 | (((dst) & ~0x00000070) | (((u32) (src) << 4) & 0x00000070)) | |
186 | #define CMU_REG9_PLL_POST_DIVBY2_SET(dst, src) \ | |
187 | (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) | |
188 | #define CMU_REG9_VBG_BYPASSB_SET(dst, src) \ | |
189 | (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004)) | |
190 | #define CMU_REG9_IGEN_BYPASS_SET(dst, src) \ | |
191 | (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) | |
192 | #define CMU_REG10 0x00014 | |
193 | #define CMU_REG10_VREG_REFSEL_SET(dst, src) \ | |
194 | (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001)) | |
195 | #define CMU_REG11 0x00016 | |
196 | #define CMU_REG12 0x00018 | |
197 | #define CMU_REG12_STATE_DELAY9_SET(dst, src) \ | |
198 | (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0)) | |
199 | #define CMU_REG13 0x0001a | |
200 | #define CMU_REG14 0x0001c | |
201 | #define CMU_REG15 0x0001e | |
202 | #define CMU_REG16 0x00020 | |
203 | #define CMU_REG16_PVT_DN_MAN_ENA_MASK 0x00000001 | |
204 | #define CMU_REG16_PVT_UP_MAN_ENA_MASK 0x00000002 | |
205 | #define CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(dst, src) \ | |
206 | (((dst) & ~0x0000001c) | (((u32) (src) << 2) & 0x0000001c)) | |
207 | #define CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(dst, src) \ | |
208 | (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040)) | |
209 | #define CMU_REG16_BYPASS_PLL_LOCK_SET(dst, src) \ | |
210 | (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020)) | |
211 | #define CMU_REG17 0x00022 | |
212 | #define CMU_REG17_PVT_CODE_R2A_SET(dst, src) \ | |
213 | (((dst) & ~0x00007f00) | (((u32) (src) << 8) & 0x00007f00)) | |
214 | #define CMU_REG17_RESERVED_7_SET(dst, src) \ | |
215 | (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0)) | |
216 | #define CMU_REG17_PVT_TERM_MAN_ENA_MASK 0x00008000 | |
217 | #define CMU_REG18 0x00024 | |
218 | #define CMU_REG19 0x00026 | |
219 | #define CMU_REG20 0x00028 | |
220 | #define CMU_REG21 0x0002a | |
221 | #define CMU_REG22 0x0002c | |
222 | #define CMU_REG23 0x0002e | |
223 | #define CMU_REG24 0x00030 | |
224 | #define CMU_REG25 0x00032 | |
225 | #define CMU_REG26 0x00034 | |
226 | #define CMU_REG26_FORCE_PLL_LOCK_SET(dst, src) \ | |
227 | (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001)) | |
228 | #define CMU_REG27 0x00036 | |
229 | #define CMU_REG28 0x00038 | |
230 | #define CMU_REG29 0x0003a | |
231 | #define CMU_REG30 0x0003c | |
232 | #define CMU_REG30_LOCK_COUNT_SET(dst, src) \ | |
233 | (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006)) | |
234 | #define CMU_REG30_PCIE_MODE_SET(dst, src) \ | |
235 | (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) | |
236 | #define CMU_REG31 0x0003e | |
237 | #define CMU_REG32 0x00040 | |
238 | #define CMU_REG32_FORCE_VCOCAL_START_MASK 0x00004000 | |
239 | #define CMU_REG32_PVT_CAL_WAIT_SEL_SET(dst, src) \ | |
240 | (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006)) | |
241 | #define CMU_REG32_IREF_ADJ_SET(dst, src) \ | |
242 | (((dst) & ~0x00000180) | (((u32) (src) << 7) & 0x00000180)) | |
243 | #define CMU_REG33 0x00042 | |
244 | #define CMU_REG34 0x00044 | |
245 | #define CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(dst, src) \ | |
246 | (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f)) | |
247 | #define CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(dst, src) \ | |
248 | (((dst) & ~0x00000f00) | (((u32) (src) << 8) & 0x00000f00)) | |
249 | #define CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(dst, src) \ | |
250 | (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0)) | |
251 | #define CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(dst, src) \ | |
252 | (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000)) | |
253 | #define CMU_REG35 0x00046 | |
254 | #define CMU_REG35_PLL_SSC_MOD_SET(dst, src) \ | |
255 | (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00)) | |
256 | #define CMU_REG36 0x00048 | |
257 | #define CMU_REG36_PLL_SSC_EN_SET(dst, src) \ | |
258 | (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010)) | |
259 | #define CMU_REG36_PLL_SSC_VSTEP_SET(dst, src) \ | |
260 | (((dst) & ~0x0000ffc0) | (((u32) (src) << 6) & 0x0000ffc0)) | |
261 | #define CMU_REG36_PLL_SSC_DSMSEL_SET(dst, src) \ | |
262 | (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020)) | |
263 | #define CMU_REG37 0x0004a | |
264 | #define CMU_REG38 0x0004c | |
265 | #define CMU_REG39 0x0004e | |
266 | ||
267 | /* PHY lane CSR accessing from SDS indirectly */ | |
268 | #define RXTX_REG0 0x000 | |
269 | #define RXTX_REG0_CTLE_EQ_HR_SET(dst, src) \ | |
270 | (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) | |
271 | #define RXTX_REG0_CTLE_EQ_QR_SET(dst, src) \ | |
272 | (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0)) | |
273 | #define RXTX_REG0_CTLE_EQ_FR_SET(dst, src) \ | |
274 | (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e)) | |
275 | #define RXTX_REG1 0x002 | |
276 | #define RXTX_REG1_RXACVCM_SET(dst, src) \ | |
277 | (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000)) | |
278 | #define RXTX_REG1_CTLE_EQ_SET(dst, src) \ | |
279 | (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80)) | |
280 | #define RXTX_REG1_RXVREG1_SET(dst, src) \ | |
281 | (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060)) | |
282 | #define RXTX_REG1_RXIREF_ADJ_SET(dst, src) \ | |
283 | (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006)) | |
284 | #define RXTX_REG2 0x004 | |
285 | #define RXTX_REG2_VTT_ENA_SET(dst, src) \ | |
286 | (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100)) | |
287 | #define RXTX_REG2_TX_FIFO_ENA_SET(dst, src) \ | |
288 | (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020)) | |
289 | #define RXTX_REG2_VTT_SEL_SET(dst, src) \ | |
290 | (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0)) | |
291 | #define RXTX_REG4 0x008 | |
292 | #define RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK 0x00000040 | |
293 | #define RXTX_REG4_TX_DATA_RATE_SET(dst, src) \ | |
294 | (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000)) | |
295 | #define RXTX_REG4_TX_WORD_MODE_SET(dst, src) \ | |
296 | (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800)) | |
297 | #define RXTX_REG5 0x00a | |
298 | #define RXTX_REG5_TX_CN1_SET(dst, src) \ | |
299 | (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) | |
300 | #define RXTX_REG5_TX_CP1_SET(dst, src) \ | |
301 | (((dst) & ~0x000007e0) | (((u32) (src) << 5) & 0x000007e0)) | |
302 | #define RXTX_REG5_TX_CN2_SET(dst, src) \ | |
303 | (((dst) & ~0x0000001f) | (((u32) (src) << 0) & 0x0000001f)) | |
304 | #define RXTX_REG6 0x00c | |
305 | #define RXTX_REG6_TXAMP_CNTL_SET(dst, src) \ | |
306 | (((dst) & ~0x00000780) | (((u32) (src) << 7) & 0x00000780)) | |
307 | #define RXTX_REG6_TXAMP_ENA_SET(dst, src) \ | |
308 | (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040)) | |
309 | #define RXTX_REG6_RX_BIST_ERRCNT_RD_SET(dst, src) \ | |
310 | (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001)) | |
311 | #define RXTX_REG6_TX_IDLE_SET(dst, src) \ | |
312 | (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) | |
313 | #define RXTX_REG6_RX_BIST_RESYNC_SET(dst, src) \ | |
314 | (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) | |
315 | #define RXTX_REG7 0x00e | |
316 | #define RXTX_REG7_RESETB_RXD_MASK 0x00000100 | |
317 | #define RXTX_REG7_RESETB_RXA_MASK 0x00000080 | |
318 | #define RXTX_REG7_BIST_ENA_RX_SET(dst, src) \ | |
319 | (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040)) | |
320 | #define RXTX_REG7_RX_WORD_MODE_SET(dst, src) \ | |
321 | (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800)) | |
322 | #define RXTX_REG8 0x010 | |
323 | #define RXTX_REG8_CDR_LOOP_ENA_SET(dst, src) \ | |
324 | (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000)) | |
325 | #define RXTX_REG8_CDR_BYPASS_RXLOS_SET(dst, src) \ | |
326 | (((dst) & ~0x00000800) | (((u32) (src) << 11) & 0x00000800)) | |
327 | #define RXTX_REG8_SSC_ENABLE_SET(dst, src) \ | |
328 | (((dst) & ~0x00000200) | (((u32) (src) << 9) & 0x00000200)) | |
329 | #define RXTX_REG8_SD_VREF_SET(dst, src) \ | |
330 | (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0)) | |
331 | #define RXTX_REG8_SD_DISABLE_SET(dst, src) \ | |
332 | (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100)) | |
333 | #define RXTX_REG7 0x00e | |
334 | #define RXTX_REG7_RESETB_RXD_SET(dst, src) \ | |
335 | (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100)) | |
336 | #define RXTX_REG7_RESETB_RXA_SET(dst, src) \ | |
337 | (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080)) | |
338 | #define RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK 0x00004000 | |
339 | #define RXTX_REG7_LOOP_BACK_ENA_CTLE_SET(dst, src) \ | |
340 | (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000)) | |
341 | #define RXTX_REG11 0x016 | |
342 | #define RXTX_REG11_PHASE_ADJUST_LIMIT_SET(dst, src) \ | |
343 | (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) | |
344 | #define RXTX_REG12 0x018 | |
345 | #define RXTX_REG12_LATCH_OFF_ENA_SET(dst, src) \ | |
346 | (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000)) | |
347 | #define RXTX_REG12_SUMOS_ENABLE_SET(dst, src) \ | |
348 | (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004)) | |
349 | #define RXTX_REG12_RX_DET_TERM_ENABLE_MASK 0x00000002 | |
350 | #define RXTX_REG12_RX_DET_TERM_ENABLE_SET(dst, src) \ | |
351 | (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) | |
352 | #define RXTX_REG13 0x01a | |
353 | #define RXTX_REG14 0x01c | |
354 | #define RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(dst, src) \ | |
355 | (((dst) & ~0x0000003f) | (((u32) (src) << 0) & 0x0000003f)) | |
356 | #define RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(dst, src) \ | |
357 | (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040)) | |
358 | #define RXTX_REG26 0x034 | |
359 | #define RXTX_REG26_PERIOD_ERROR_LATCH_SET(dst, src) \ | |
360 | (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800)) | |
361 | #define RXTX_REG26_BLWC_ENA_SET(dst, src) \ | |
362 | (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) | |
363 | #define RXTX_REG21 0x02a | |
364 | #define RXTX_REG21_DO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) | |
365 | #define RXTX_REG21_XO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) | |
366 | #define RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(src) ((0x0000000f & (u32)(src))) | |
367 | #define RXTX_REG22 0x02c | |
368 | #define RXTX_REG22_SO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) | |
369 | #define RXTX_REG22_EO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) | |
370 | #define RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(src) ((0x0000000f & (u32)(src))) | |
371 | #define RXTX_REG23 0x02e | |
372 | #define RXTX_REG23_DE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) | |
373 | #define RXTX_REG23_XE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) | |
374 | #define RXTX_REG24 0x030 | |
375 | #define RXTX_REG24_EE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) | |
376 | #define RXTX_REG24_SE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) | |
377 | #define RXTX_REG27 0x036 | |
378 | #define RXTX_REG28 0x038 | |
379 | #define RXTX_REG31 0x03e | |
380 | #define RXTX_REG38 0x04c | |
381 | #define RXTX_REG38_CUSTOMER_PINMODE_INV_SET(dst, src) \ | |
382 | (((dst) & 0x0000fffe) | (((u32) (src) << 1) & 0x0000fffe)) | |
383 | #define RXTX_REG39 0x04e | |
384 | #define RXTX_REG40 0x050 | |
385 | #define RXTX_REG41 0x052 | |
386 | #define RXTX_REG42 0x054 | |
387 | #define RXTX_REG43 0x056 | |
388 | #define RXTX_REG44 0x058 | |
389 | #define RXTX_REG45 0x05a | |
390 | #define RXTX_REG46 0x05c | |
391 | #define RXTX_REG47 0x05e | |
392 | #define RXTX_REG48 0x060 | |
393 | #define RXTX_REG49 0x062 | |
394 | #define RXTX_REG50 0x064 | |
395 | #define RXTX_REG51 0x066 | |
396 | #define RXTX_REG52 0x068 | |
397 | #define RXTX_REG53 0x06a | |
398 | #define RXTX_REG54 0x06c | |
399 | #define RXTX_REG55 0x06e | |
400 | #define RXTX_REG61 0x07a | |
401 | #define RXTX_REG61_ISCAN_INBERT_SET(dst, src) \ | |
402 | (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010)) | |
403 | #define RXTX_REG61_LOADFREQ_SHIFT_SET(dst, src) \ | |
404 | (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) | |
405 | #define RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(dst, src) \ | |
406 | (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0)) | |
407 | #define RXTX_REG61_SPD_SEL_CDR_SET(dst, src) \ | |
408 | (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00)) | |
409 | #define RXTX_REG62 0x07c | |
410 | #define RXTX_REG62_PERIOD_H1_QLATCH_SET(dst, src) \ | |
411 | (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800)) | |
412 | #define RXTX_REG81 0x0a2 | |
413 | #define RXTX_REG89_MU_TH7_SET(dst, src) \ | |
414 | (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) | |
415 | #define RXTX_REG89_MU_TH8_SET(dst, src) \ | |
416 | (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0)) | |
417 | #define RXTX_REG89_MU_TH9_SET(dst, src) \ | |
418 | (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e)) | |
419 | #define RXTX_REG96 0x0c0 | |
420 | #define RXTX_REG96_MU_FREQ1_SET(dst, src) \ | |
421 | (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) | |
422 | #define RXTX_REG96_MU_FREQ2_SET(dst, src) \ | |
423 | (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0)) | |
424 | #define RXTX_REG96_MU_FREQ3_SET(dst, src) \ | |
425 | (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e)) | |
426 | #define RXTX_REG99 0x0c6 | |
427 | #define RXTX_REG99_MU_PHASE1_SET(dst, src) \ | |
428 | (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800)) | |
429 | #define RXTX_REG99_MU_PHASE2_SET(dst, src) \ | |
430 | (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0)) | |
431 | #define RXTX_REG99_MU_PHASE3_SET(dst, src) \ | |
432 | (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e)) | |
433 | #define RXTX_REG102 0x0cc | |
434 | #define RXTX_REG102_FREQLOOP_LIMIT_SET(dst, src) \ | |
435 | (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060)) | |
436 | #define RXTX_REG114 0x0e4 | |
437 | #define RXTX_REG121 0x0f2 | |
438 | #define RXTX_REG121_SUMOS_CAL_CODE_RD(src) ((0x0000003e & (u32)(src)) >> 0x1) | |
439 | #define RXTX_REG125 0x0fa | |
440 | #define RXTX_REG125_PQ_REG_SET(dst, src) \ | |
441 | (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00)) | |
442 | #define RXTX_REG125_SIGN_PQ_SET(dst, src) \ | |
443 | (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100)) | |
444 | #define RXTX_REG125_SIGN_PQ_2C_SET(dst, src) \ | |
445 | (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080)) | |
446 | #define RXTX_REG125_PHZ_MANUALCODE_SET(dst, src) \ | |
447 | (((dst) & ~0x0000007c) | (((u32) (src) << 2) & 0x0000007c)) | |
448 | #define RXTX_REG125_PHZ_MANUAL_SET(dst, src) \ | |
449 | (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) | |
450 | #define RXTX_REG127 0x0fe | |
451 | #define RXTX_REG127_FORCE_SUM_CAL_START_MASK 0x00000002 | |
452 | #define RXTX_REG127_FORCE_LAT_CAL_START_MASK 0x00000004 | |
453 | #define RXTX_REG127_FORCE_SUM_CAL_START_SET(dst, src) \ | |
454 | (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) | |
455 | #define RXTX_REG127_FORCE_LAT_CAL_START_SET(dst, src) \ | |
456 | (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004)) | |
457 | #define RXTX_REG127_LATCH_MAN_CAL_ENA_SET(dst, src) \ | |
458 | (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008)) | |
459 | #define RXTX_REG127_DO_LATCH_MANCAL_SET(dst, src) \ | |
460 | (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00)) | |
461 | #define RXTX_REG127_XO_LATCH_MANCAL_SET(dst, src) \ | |
462 | (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0)) | |
463 | #define RXTX_REG128 0x100 | |
464 | #define RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(dst, src) \ | |
465 | (((dst) & ~0x0000000c) | (((u32) (src) << 2) & 0x0000000c)) | |
466 | #define RXTX_REG128_EO_LATCH_MANCAL_SET(dst, src) \ | |
467 | (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00)) | |
468 | #define RXTX_REG128_SO_LATCH_MANCAL_SET(dst, src) \ | |
469 | (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0)) | |
470 | #define RXTX_REG129 0x102 | |
471 | #define RXTX_REG129_DE_LATCH_MANCAL_SET(dst, src) \ | |
472 | (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00)) | |
473 | #define RXTX_REG129_XE_LATCH_MANCAL_SET(dst, src) \ | |
474 | (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0)) | |
475 | #define RXTX_REG130 0x104 | |
476 | #define RXTX_REG130_EE_LATCH_MANCAL_SET(dst, src) \ | |
477 | (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00)) | |
478 | #define RXTX_REG130_SE_LATCH_MANCAL_SET(dst, src) \ | |
479 | (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0)) | |
480 | #define RXTX_REG145 0x122 | |
481 | #define RXTX_REG145_TX_IDLE_SATA_SET(dst, src) \ | |
482 | (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001)) | |
483 | #define RXTX_REG145_RXES_ENA_SET(dst, src) \ | |
484 | (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002)) | |
485 | #define RXTX_REG145_RXDFE_CONFIG_SET(dst, src) \ | |
486 | (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000)) | |
487 | #define RXTX_REG145_RXVWES_LATENA_SET(dst, src) \ | |
488 | (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004)) | |
489 | #define RXTX_REG147 0x126 | |
490 | #define RXTX_REG148 0x128 | |
491 | ||
492 | /* Clock macro type */ | |
493 | enum cmu_type_t { | |
494 | REF_CMU = 0, /* Clock macro is the internal reference clock */ | |
495 | PHY_CMU = 1, /* Clock macro is the PLL for the Serdes */ | |
496 | }; | |
497 | ||
498 | enum mux_type_t { | |
499 | MUX_SELECT_ATA = 0, /* Switch the MUX to ATA */ | |
500 | MUX_SELECT_SGMMII = 0, /* Switch the MUX to SGMII */ | |
501 | }; | |
502 | ||
503 | enum clk_type_t { | |
504 | CLK_EXT_DIFF = 0, /* External differential */ | |
505 | CLK_INT_DIFF = 1, /* Internal differential */ | |
506 | CLK_INT_SING = 2, /* Internal single ended */ | |
507 | }; | |
508 | ||
65048f4d | 509 | enum xgene_phy_mode { |
88e670fe LH |
510 | MODE_SATA = 0, /* List them for simple reference */ |
511 | MODE_SGMII = 1, | |
512 | MODE_PCIE = 2, | |
513 | MODE_USB = 3, | |
514 | MODE_XFI = 4, | |
515 | MODE_MAX | |
516 | }; | |
517 | ||
518 | struct xgene_sata_override_param { | |
519 | u32 speed[MAX_LANE]; /* Index for override parameter per lane */ | |
520 | u32 txspeed[3]; /* Tx speed */ | |
521 | u32 txboostgain[MAX_LANE*3]; /* Tx freq boost and gain control */ | |
522 | u32 txeyetuning[MAX_LANE*3]; /* Tx eye tuning */ | |
523 | u32 txeyedirection[MAX_LANE*3]; /* Tx eye tuning direction */ | |
524 | u32 txamplitude[MAX_LANE*3]; /* Tx amplitude control */ | |
525 | u32 txprecursor_cn1[MAX_LANE*3]; /* Tx emphasis taps 1st pre-cursor */ | |
526 | u32 txprecursor_cn2[MAX_LANE*3]; /* Tx emphasis taps 2nd pre-cursor */ | |
527 | u32 txpostcursor_cp1[MAX_LANE*3]; /* Tx emphasis taps post-cursor */ | |
528 | }; | |
529 | ||
530 | struct xgene_phy_ctx { | |
531 | struct device *dev; | |
532 | struct phy *phy; | |
65048f4d | 533 | enum xgene_phy_mode mode; /* Mode of operation */ |
88e670fe LH |
534 | enum clk_type_t clk_type; /* Input clock selection */ |
535 | void __iomem *sds_base; /* PHY CSR base addr */ | |
536 | struct clk *clk; /* Optional clock */ | |
537 | ||
538 | /* Override Serdes parameters */ | |
539 | struct xgene_sata_override_param sata_param; | |
540 | }; | |
541 | ||
542 | /* | |
543 | * For chip earlier than A3 version, enable this flag. | |
544 | * To enable, pass boot argument phy_xgene.preA3Chip=1 | |
545 | */ | |
546 | static int preA3Chip; | |
547 | MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)"); | |
548 | module_param_named(preA3Chip, preA3Chip, int, 0444); | |
549 | ||
550 | static void sds_wr(void __iomem *csr_base, u32 indirect_cmd_reg, | |
551 | u32 indirect_data_reg, u32 addr, u32 data) | |
552 | { | |
553 | unsigned long deadline = jiffies + HZ; | |
554 | u32 val; | |
555 | u32 cmd; | |
556 | ||
557 | cmd = CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK; | |
558 | cmd = CFG_IND_ADDR_SET(cmd, addr); | |
559 | writel(data, csr_base + indirect_data_reg); | |
560 | readl(csr_base + indirect_data_reg); /* Force a barrier */ | |
561 | writel(cmd, csr_base + indirect_cmd_reg); | |
562 | readl(csr_base + indirect_cmd_reg); /* Force a barrier */ | |
563 | do { | |
564 | val = readl(csr_base + indirect_cmd_reg); | |
565 | } while (!(val & CFG_IND_CMD_DONE_MASK) && | |
566 | time_before(jiffies, deadline)); | |
567 | if (!(val & CFG_IND_CMD_DONE_MASK)) | |
568 | pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n", | |
569 | csr_base + indirect_cmd_reg, addr, data); | |
570 | } | |
571 | ||
572 | static void sds_rd(void __iomem *csr_base, u32 indirect_cmd_reg, | |
573 | u32 indirect_data_reg, u32 addr, u32 *data) | |
574 | { | |
575 | unsigned long deadline = jiffies + HZ; | |
576 | u32 val; | |
577 | u32 cmd; | |
578 | ||
579 | cmd = CFG_IND_RD_CMD_MASK | CFG_IND_CMD_DONE_MASK; | |
580 | cmd = CFG_IND_ADDR_SET(cmd, addr); | |
581 | writel(cmd, csr_base + indirect_cmd_reg); | |
582 | readl(csr_base + indirect_cmd_reg); /* Force a barrier */ | |
583 | do { | |
584 | val = readl(csr_base + indirect_cmd_reg); | |
585 | } while (!(val & CFG_IND_CMD_DONE_MASK) && | |
586 | time_before(jiffies, deadline)); | |
587 | *data = readl(csr_base + indirect_data_reg); | |
588 | if (!(val & CFG_IND_CMD_DONE_MASK)) | |
589 | pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n", | |
590 | csr_base + indirect_cmd_reg, addr, *data); | |
591 | } | |
592 | ||
593 | static void cmu_wr(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, | |
594 | u32 reg, u32 data) | |
595 | { | |
596 | void __iomem *sds_base = ctx->sds_base; | |
597 | u32 val; | |
598 | ||
599 | if (cmu_type == REF_CMU) | |
600 | reg += SERDES_PLL_REF_INDIRECT_OFFSET; | |
601 | else | |
602 | reg += SERDES_PLL_INDIRECT_OFFSET; | |
603 | sds_wr(sds_base, SATA_ENET_SDS_IND_CMD_REG, | |
604 | SATA_ENET_SDS_IND_WDATA_REG, reg, data); | |
605 | sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG, | |
606 | SATA_ENET_SDS_IND_RDATA_REG, reg, &val); | |
607 | pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); | |
608 | } | |
609 | ||
610 | static void cmu_rd(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, | |
611 | u32 reg, u32 *data) | |
612 | { | |
613 | void __iomem *sds_base = ctx->sds_base; | |
614 | ||
615 | if (cmu_type == REF_CMU) | |
616 | reg += SERDES_PLL_REF_INDIRECT_OFFSET; | |
617 | else | |
618 | reg += SERDES_PLL_INDIRECT_OFFSET; | |
619 | sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG, | |
620 | SATA_ENET_SDS_IND_RDATA_REG, reg, data); | |
621 | pr_debug("CMU RD addr 0x%X value 0x%08X\n", reg, *data); | |
622 | } | |
623 | ||
624 | static void cmu_toggle1to0(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, | |
625 | u32 reg, u32 bits) | |
626 | { | |
627 | u32 val; | |
628 | ||
629 | cmu_rd(ctx, cmu_type, reg, &val); | |
630 | val |= bits; | |
631 | cmu_wr(ctx, cmu_type, reg, val); | |
632 | cmu_rd(ctx, cmu_type, reg, &val); | |
633 | val &= ~bits; | |
634 | cmu_wr(ctx, cmu_type, reg, val); | |
635 | } | |
636 | ||
637 | static void cmu_clrbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, | |
638 | u32 reg, u32 bits) | |
639 | { | |
640 | u32 val; | |
641 | ||
642 | cmu_rd(ctx, cmu_type, reg, &val); | |
643 | val &= ~bits; | |
644 | cmu_wr(ctx, cmu_type, reg, val); | |
645 | } | |
646 | ||
647 | static void cmu_setbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type, | |
648 | u32 reg, u32 bits) | |
649 | { | |
650 | u32 val; | |
651 | ||
652 | cmu_rd(ctx, cmu_type, reg, &val); | |
653 | val |= bits; | |
654 | cmu_wr(ctx, cmu_type, reg, val); | |
655 | } | |
656 | ||
657 | static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) | |
658 | { | |
659 | void __iomem *sds_base = ctx->sds_base; | |
660 | u32 val; | |
661 | ||
662 | reg += SERDES_INDIRECT_OFFSET; | |
663 | reg += lane * SERDES_LANE_STRIDE; | |
664 | sds_wr(sds_base, SATA_ENET_SDS_IND_CMD_REG, | |
665 | SATA_ENET_SDS_IND_WDATA_REG, reg, data); | |
666 | sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG, | |
667 | SATA_ENET_SDS_IND_RDATA_REG, reg, &val); | |
668 | pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, | |
669 | val); | |
670 | } | |
671 | ||
672 | static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) | |
673 | { | |
674 | void __iomem *sds_base = ctx->sds_base; | |
675 | ||
676 | reg += SERDES_INDIRECT_OFFSET; | |
677 | reg += lane * SERDES_LANE_STRIDE; | |
678 | sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG, | |
679 | SATA_ENET_SDS_IND_RDATA_REG, reg, data); | |
680 | pr_debug("SERDES RD addr 0x%X value 0x%08X\n", reg, *data); | |
681 | } | |
682 | ||
683 | static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, | |
684 | u32 bits) | |
685 | { | |
686 | u32 val; | |
687 | ||
688 | serdes_rd(ctx, lane, reg, &val); | |
689 | val &= ~bits; | |
690 | serdes_wr(ctx, lane, reg, val); | |
691 | } | |
692 | ||
693 | static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, | |
694 | u32 bits) | |
695 | { | |
696 | u32 val; | |
697 | ||
698 | serdes_rd(ctx, lane, reg, &val); | |
699 | val |= bits; | |
700 | serdes_wr(ctx, lane, reg, val); | |
701 | } | |
702 | ||
703 | static void xgene_phy_cfg_cmu_clk_type(struct xgene_phy_ctx *ctx, | |
704 | enum cmu_type_t cmu_type, | |
705 | enum clk_type_t clk_type) | |
706 | { | |
707 | u32 val; | |
708 | ||
709 | /* Set the reset sequence delay for TX ready assertion */ | |
710 | cmu_rd(ctx, cmu_type, CMU_REG12, &val); | |
711 | val = CMU_REG12_STATE_DELAY9_SET(val, 0x1); | |
712 | cmu_wr(ctx, cmu_type, CMU_REG12, val); | |
713 | /* Set the programmable stage delays between various enable stages */ | |
714 | cmu_wr(ctx, cmu_type, CMU_REG13, 0x0222); | |
715 | cmu_wr(ctx, cmu_type, CMU_REG14, 0x2225); | |
716 | ||
717 | /* Configure clock type */ | |
718 | if (clk_type == CLK_EXT_DIFF) { | |
719 | /* Select external clock mux */ | |
720 | cmu_rd(ctx, cmu_type, CMU_REG0, &val); | |
721 | val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0); | |
722 | cmu_wr(ctx, cmu_type, CMU_REG0, val); | |
723 | /* Select CMOS as reference clock */ | |
724 | cmu_rd(ctx, cmu_type, CMU_REG1, &val); | |
725 | val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); | |
726 | cmu_wr(ctx, cmu_type, CMU_REG1, val); | |
727 | dev_dbg(ctx->dev, "Set external reference clock\n"); | |
728 | } else if (clk_type == CLK_INT_DIFF) { | |
729 | /* Select internal clock mux */ | |
730 | cmu_rd(ctx, cmu_type, CMU_REG0, &val); | |
731 | val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1); | |
732 | cmu_wr(ctx, cmu_type, CMU_REG0, val); | |
733 | /* Select CMOS as reference clock */ | |
734 | cmu_rd(ctx, cmu_type, CMU_REG1, &val); | |
735 | val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); | |
736 | cmu_wr(ctx, cmu_type, CMU_REG1, val); | |
737 | dev_dbg(ctx->dev, "Set internal reference clock\n"); | |
738 | } else if (clk_type == CLK_INT_SING) { | |
739 | /* | |
740 | * NOTE: This clock type is NOT support for controller | |
741 | * whose internal clock shared in the PCIe controller | |
742 | * | |
743 | * Select internal clock mux | |
744 | */ | |
745 | cmu_rd(ctx, cmu_type, CMU_REG1, &val); | |
746 | val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1); | |
747 | cmu_wr(ctx, cmu_type, CMU_REG1, val); | |
748 | /* Select CML as reference clock */ | |
749 | cmu_rd(ctx, cmu_type, CMU_REG1, &val); | |
750 | val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0); | |
751 | cmu_wr(ctx, cmu_type, CMU_REG1, val); | |
752 | dev_dbg(ctx->dev, | |
753 | "Set internal single ended reference clock\n"); | |
754 | } | |
755 | } | |
756 | ||
757 | static void xgene_phy_sata_cfg_cmu_core(struct xgene_phy_ctx *ctx, | |
758 | enum cmu_type_t cmu_type, | |
759 | enum clk_type_t clk_type) | |
760 | { | |
761 | u32 val; | |
762 | int ref_100MHz; | |
763 | ||
764 | if (cmu_type == REF_CMU) { | |
765 | /* Set VCO calibration voltage threshold */ | |
766 | cmu_rd(ctx, cmu_type, CMU_REG34, &val); | |
767 | val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7); | |
768 | val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc); | |
769 | val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3); | |
770 | val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8); | |
771 | cmu_wr(ctx, cmu_type, CMU_REG34, val); | |
772 | } | |
773 | ||
774 | /* Set the VCO calibration counter */ | |
775 | cmu_rd(ctx, cmu_type, CMU_REG0, &val); | |
776 | if (cmu_type == REF_CMU || preA3Chip) | |
777 | val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4); | |
778 | else | |
779 | val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7); | |
780 | cmu_wr(ctx, cmu_type, CMU_REG0, val); | |
781 | ||
782 | /* Configure PLL for calibration */ | |
783 | cmu_rd(ctx, cmu_type, CMU_REG1, &val); | |
784 | val = CMU_REG1_PLL_CP_SET(val, 0x1); | |
785 | if (cmu_type == REF_CMU || preA3Chip) | |
786 | val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5); | |
787 | else | |
788 | val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3); | |
789 | if (cmu_type == REF_CMU) | |
790 | val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); | |
791 | else | |
792 | val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1); | |
793 | cmu_wr(ctx, cmu_type, CMU_REG1, val); | |
794 | ||
795 | if (cmu_type != REF_CMU) | |
796 | cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); | |
797 | ||
798 | /* Configure the PLL for either 100MHz or 50MHz */ | |
799 | cmu_rd(ctx, cmu_type, CMU_REG2, &val); | |
800 | if (cmu_type == REF_CMU) { | |
801 | val = CMU_REG2_PLL_LFRES_SET(val, 0xa); | |
802 | ref_100MHz = 1; | |
803 | } else { | |
804 | val = CMU_REG2_PLL_LFRES_SET(val, 0x3); | |
805 | if (clk_type == CLK_EXT_DIFF) | |
806 | ref_100MHz = 0; | |
807 | else | |
808 | ref_100MHz = 1; | |
809 | } | |
810 | if (ref_100MHz) { | |
811 | val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_100M); | |
812 | val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_100M); | |
813 | } else { | |
814 | val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_50M); | |
815 | val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_50M); | |
816 | } | |
817 | cmu_wr(ctx, cmu_type, CMU_REG2, val); | |
818 | ||
819 | /* Configure the VCO */ | |
820 | cmu_rd(ctx, cmu_type, CMU_REG3, &val); | |
821 | if (cmu_type == REF_CMU) { | |
822 | val = CMU_REG3_VCOVARSEL_SET(val, 0x3); | |
823 | val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10); | |
824 | } else { | |
825 | val = CMU_REG3_VCOVARSEL_SET(val, 0xF); | |
826 | if (preA3Chip) | |
827 | val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15); | |
828 | else | |
829 | val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a); | |
830 | val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15); | |
831 | } | |
832 | cmu_wr(ctx, cmu_type, CMU_REG3, val); | |
833 | ||
834 | /* Disable force PLL lock */ | |
835 | cmu_rd(ctx, cmu_type, CMU_REG26, &val); | |
836 | val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0); | |
837 | cmu_wr(ctx, cmu_type, CMU_REG26, val); | |
838 | ||
839 | /* Setup PLL loop filter */ | |
840 | cmu_rd(ctx, cmu_type, CMU_REG5, &val); | |
841 | val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3); | |
842 | val = CMU_REG5_PLL_LFCAP_SET(val, 0x3); | |
843 | if (cmu_type == REF_CMU || !preA3Chip) | |
844 | val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7); | |
845 | else | |
846 | val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4); | |
847 | cmu_wr(ctx, cmu_type, CMU_REG5, val); | |
848 | ||
849 | /* Enable or disable manual calibration */ | |
850 | cmu_rd(ctx, cmu_type, CMU_REG6, &val); | |
851 | val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2); | |
852 | val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0); | |
853 | cmu_wr(ctx, cmu_type, CMU_REG6, val); | |
854 | ||
855 | /* Configure lane for 20-bits */ | |
856 | if (cmu_type == PHY_CMU) { | |
857 | cmu_rd(ctx, cmu_type, CMU_REG9, &val); | |
858 | val = CMU_REG9_TX_WORD_MODE_CH1_SET(val, | |
859 | CMU_REG9_WORD_LEN_20BIT); | |
860 | val = CMU_REG9_TX_WORD_MODE_CH0_SET(val, | |
861 | CMU_REG9_WORD_LEN_20BIT); | |
862 | val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1); | |
863 | if (!preA3Chip) { | |
864 | val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0); | |
865 | val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0); | |
866 | } | |
867 | cmu_wr(ctx, cmu_type, CMU_REG9, val); | |
868 | ||
869 | if (!preA3Chip) { | |
870 | cmu_rd(ctx, cmu_type, CMU_REG10, &val); | |
871 | val = CMU_REG10_VREG_REFSEL_SET(val, 0x1); | |
872 | cmu_wr(ctx, cmu_type, CMU_REG10, val); | |
873 | } | |
874 | } | |
875 | ||
876 | cmu_rd(ctx, cmu_type, CMU_REG16, &val); | |
877 | val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1); | |
878 | val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1); | |
879 | if (cmu_type == REF_CMU || preA3Chip) | |
880 | val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4); | |
881 | else | |
882 | val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); | |
883 | cmu_wr(ctx, cmu_type, CMU_REG16, val); | |
884 | ||
885 | /* Configure for SATA */ | |
886 | cmu_rd(ctx, cmu_type, CMU_REG30, &val); | |
887 | val = CMU_REG30_PCIE_MODE_SET(val, 0x0); | |
888 | val = CMU_REG30_LOCK_COUNT_SET(val, 0x3); | |
889 | cmu_wr(ctx, cmu_type, CMU_REG30, val); | |
890 | ||
891 | /* Disable state machine bypass */ | |
892 | cmu_wr(ctx, cmu_type, CMU_REG31, 0xF); | |
893 | ||
894 | cmu_rd(ctx, cmu_type, CMU_REG32, &val); | |
895 | val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3); | |
896 | if (cmu_type == REF_CMU || preA3Chip) | |
897 | val = CMU_REG32_IREF_ADJ_SET(val, 0x3); | |
898 | else | |
899 | val = CMU_REG32_IREF_ADJ_SET(val, 0x1); | |
900 | cmu_wr(ctx, cmu_type, CMU_REG32, val); | |
901 | ||
902 | /* Set VCO calibration threshold */ | |
903 | if (cmu_type != REF_CMU && preA3Chip) | |
904 | cmu_wr(ctx, cmu_type, CMU_REG34, 0x8d27); | |
905 | else | |
906 | cmu_wr(ctx, cmu_type, CMU_REG34, 0x873c); | |
907 | ||
908 | /* Set CTLE Override and override waiting from state machine */ | |
909 | cmu_wr(ctx, cmu_type, CMU_REG37, 0xF00F); | |
910 | } | |
911 | ||
912 | static void xgene_phy_ssc_enable(struct xgene_phy_ctx *ctx, | |
913 | enum cmu_type_t cmu_type) | |
914 | { | |
915 | u32 val; | |
916 | ||
917 | /* Set SSC modulation value */ | |
918 | cmu_rd(ctx, cmu_type, CMU_REG35, &val); | |
919 | val = CMU_REG35_PLL_SSC_MOD_SET(val, 98); | |
920 | cmu_wr(ctx, cmu_type, CMU_REG35, val); | |
921 | ||
922 | /* Enable SSC, set vertical step and DSM value */ | |
923 | cmu_rd(ctx, cmu_type, CMU_REG36, &val); | |
924 | val = CMU_REG36_PLL_SSC_VSTEP_SET(val, 30); | |
925 | val = CMU_REG36_PLL_SSC_EN_SET(val, 1); | |
926 | val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1); | |
927 | cmu_wr(ctx, cmu_type, CMU_REG36, val); | |
928 | ||
929 | /* Reset the PLL */ | |
930 | cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); | |
931 | cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); | |
932 | ||
933 | /* Force VCO calibration to restart */ | |
934 | cmu_toggle1to0(ctx, cmu_type, CMU_REG32, | |
935 | CMU_REG32_FORCE_VCOCAL_START_MASK); | |
936 | } | |
937 | ||
938 | static void xgene_phy_sata_cfg_lanes(struct xgene_phy_ctx *ctx) | |
939 | { | |
940 | u32 val; | |
941 | u32 reg; | |
942 | int i; | |
943 | int lane; | |
944 | ||
945 | for (lane = 0; lane < MAX_LANE; lane++) { | |
946 | serdes_wr(ctx, lane, RXTX_REG147, 0x6); | |
947 | ||
948 | /* Set boost control for quarter, half, and full rate */ | |
949 | serdes_rd(ctx, lane, RXTX_REG0, &val); | |
950 | val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10); | |
951 | val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10); | |
952 | val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10); | |
953 | serdes_wr(ctx, lane, RXTX_REG0, val); | |
954 | ||
955 | /* Set boost control value */ | |
956 | serdes_rd(ctx, lane, RXTX_REG1, &val); | |
957 | val = RXTX_REG1_RXACVCM_SET(val, 0x7); | |
958 | val = RXTX_REG1_CTLE_EQ_SET(val, | |
959 | ctx->sata_param.txboostgain[lane * 3 + | |
960 | ctx->sata_param.speed[lane]]); | |
961 | serdes_wr(ctx, lane, RXTX_REG1, val); | |
962 | ||
963 | /* Latch VTT value based on the termination to ground and | |
964 | enable TX FIFO */ | |
965 | serdes_rd(ctx, lane, RXTX_REG2, &val); | |
966 | val = RXTX_REG2_VTT_ENA_SET(val, 0x1); | |
967 | val = RXTX_REG2_VTT_SEL_SET(val, 0x1); | |
968 | val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1); | |
969 | serdes_wr(ctx, lane, RXTX_REG2, val); | |
970 | ||
971 | /* Configure Tx for 20-bits */ | |
972 | serdes_rd(ctx, lane, RXTX_REG4, &val); | |
973 | val = RXTX_REG4_TX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); | |
974 | serdes_wr(ctx, lane, RXTX_REG4, val); | |
975 | ||
976 | if (!preA3Chip) { | |
977 | serdes_rd(ctx, lane, RXTX_REG1, &val); | |
978 | val = RXTX_REG1_RXVREG1_SET(val, 0x2); | |
979 | val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2); | |
980 | serdes_wr(ctx, lane, RXTX_REG1, val); | |
981 | } | |
982 | ||
983 | /* Set pre-emphasis first 1 and 2, and post-emphasis values */ | |
984 | serdes_rd(ctx, lane, RXTX_REG5, &val); | |
985 | val = RXTX_REG5_TX_CN1_SET(val, | |
986 | ctx->sata_param.txprecursor_cn1[lane * 3 + | |
987 | ctx->sata_param.speed[lane]]); | |
988 | val = RXTX_REG5_TX_CP1_SET(val, | |
989 | ctx->sata_param.txpostcursor_cp1[lane * 3 + | |
990 | ctx->sata_param.speed[lane]]); | |
991 | val = RXTX_REG5_TX_CN2_SET(val, | |
992 | ctx->sata_param.txprecursor_cn2[lane * 3 + | |
993 | ctx->sata_param.speed[lane]]); | |
994 | serdes_wr(ctx, lane, RXTX_REG5, val); | |
995 | ||
996 | /* Set TX amplitude value */ | |
997 | serdes_rd(ctx, lane, RXTX_REG6, &val); | |
998 | val = RXTX_REG6_TXAMP_CNTL_SET(val, | |
999 | ctx->sata_param.txamplitude[lane * 3 + | |
1000 | ctx->sata_param.speed[lane]]); | |
1001 | val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1); | |
1002 | val = RXTX_REG6_TX_IDLE_SET(val, 0x0); | |
1003 | val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0); | |
1004 | val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0); | |
1005 | serdes_wr(ctx, lane, RXTX_REG6, val); | |
1006 | ||
1007 | /* Configure Rx for 20-bits */ | |
1008 | serdes_rd(ctx, lane, RXTX_REG7, &val); | |
1009 | val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0); | |
1010 | val = RXTX_REG7_RX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT); | |
1011 | serdes_wr(ctx, lane, RXTX_REG7, val); | |
1012 | ||
1013 | /* Set CDR and LOS values and enable Rx SSC */ | |
1014 | serdes_rd(ctx, lane, RXTX_REG8, &val); | |
1015 | val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1); | |
1016 | val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0); | |
1017 | val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1); | |
1018 | val = RXTX_REG8_SD_DISABLE_SET(val, 0x0); | |
1019 | val = RXTX_REG8_SD_VREF_SET(val, 0x4); | |
1020 | serdes_wr(ctx, lane, RXTX_REG8, val); | |
1021 | ||
1022 | /* Set phase adjust upper/lower limits */ | |
1023 | serdes_rd(ctx, lane, RXTX_REG11, &val); | |
1024 | val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0); | |
1025 | serdes_wr(ctx, lane, RXTX_REG11, val); | |
1026 | ||
1027 | /* Enable Latch Off; disable SUMOS and Tx termination */ | |
1028 | serdes_rd(ctx, lane, RXTX_REG12, &val); | |
1029 | val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1); | |
1030 | val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0); | |
1031 | val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0); | |
1032 | serdes_wr(ctx, lane, RXTX_REG12, val); | |
1033 | ||
1034 | /* Set period error latch to 512T and enable BWL */ | |
1035 | serdes_rd(ctx, lane, RXTX_REG26, &val); | |
1036 | val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0); | |
1037 | val = RXTX_REG26_BLWC_ENA_SET(val, 0x1); | |
1038 | serdes_wr(ctx, lane, RXTX_REG26, val); | |
1039 | ||
1040 | serdes_wr(ctx, lane, RXTX_REG28, 0x0); | |
1041 | ||
1042 | /* Set DFE loop preset value */ | |
1043 | serdes_wr(ctx, lane, RXTX_REG31, 0x0); | |
1044 | ||
1045 | /* Set Eye Monitor counter width to 12-bit */ | |
1046 | serdes_rd(ctx, lane, RXTX_REG61, &val); | |
1047 | val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1); | |
1048 | val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0); | |
1049 | val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0); | |
1050 | serdes_wr(ctx, lane, RXTX_REG61, val); | |
1051 | ||
1052 | serdes_rd(ctx, lane, RXTX_REG62, &val); | |
1053 | val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0); | |
1054 | serdes_wr(ctx, lane, RXTX_REG62, val); | |
1055 | ||
1056 | /* Set BW select tap X for DFE loop */ | |
1057 | for (i = 0; i < 9; i++) { | |
1058 | reg = RXTX_REG81 + i * 2; | |
1059 | serdes_rd(ctx, lane, reg, &val); | |
1060 | val = RXTX_REG89_MU_TH7_SET(val, 0xe); | |
1061 | val = RXTX_REG89_MU_TH8_SET(val, 0xe); | |
1062 | val = RXTX_REG89_MU_TH9_SET(val, 0xe); | |
1063 | serdes_wr(ctx, lane, reg, val); | |
1064 | } | |
1065 | ||
1066 | /* Set BW select tap X for frequency adjust loop */ | |
1067 | for (i = 0; i < 3; i++) { | |
1068 | reg = RXTX_REG96 + i * 2; | |
1069 | serdes_rd(ctx, lane, reg, &val); | |
1070 | val = RXTX_REG96_MU_FREQ1_SET(val, 0x10); | |
1071 | val = RXTX_REG96_MU_FREQ2_SET(val, 0x10); | |
1072 | val = RXTX_REG96_MU_FREQ3_SET(val, 0x10); | |
1073 | serdes_wr(ctx, lane, reg, val); | |
1074 | } | |
1075 | ||
1076 | /* Set BW select tap X for phase adjust loop */ | |
1077 | for (i = 0; i < 3; i++) { | |
1078 | reg = RXTX_REG99 + i * 2; | |
1079 | serdes_rd(ctx, lane, reg, &val); | |
1080 | val = RXTX_REG99_MU_PHASE1_SET(val, 0x7); | |
1081 | val = RXTX_REG99_MU_PHASE2_SET(val, 0x7); | |
1082 | val = RXTX_REG99_MU_PHASE3_SET(val, 0x7); | |
1083 | serdes_wr(ctx, lane, reg, val); | |
1084 | } | |
1085 | ||
1086 | serdes_rd(ctx, lane, RXTX_REG102, &val); | |
1087 | val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0); | |
1088 | serdes_wr(ctx, lane, RXTX_REG102, val); | |
1089 | ||
1090 | serdes_wr(ctx, lane, RXTX_REG114, 0xffe0); | |
1091 | ||
1092 | serdes_rd(ctx, lane, RXTX_REG125, &val); | |
1093 | val = RXTX_REG125_SIGN_PQ_SET(val, | |
1094 | ctx->sata_param.txeyedirection[lane * 3 + | |
1095 | ctx->sata_param.speed[lane]]); | |
1096 | val = RXTX_REG125_PQ_REG_SET(val, | |
1097 | ctx->sata_param.txeyetuning[lane * 3 + | |
1098 | ctx->sata_param.speed[lane]]); | |
1099 | val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1); | |
1100 | serdes_wr(ctx, lane, RXTX_REG125, val); | |
1101 | ||
1102 | serdes_rd(ctx, lane, RXTX_REG127, &val); | |
1103 | val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0); | |
1104 | serdes_wr(ctx, lane, RXTX_REG127, val); | |
1105 | ||
1106 | serdes_rd(ctx, lane, RXTX_REG128, &val); | |
1107 | val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3); | |
1108 | serdes_wr(ctx, lane, RXTX_REG128, val); | |
1109 | ||
1110 | serdes_rd(ctx, lane, RXTX_REG145, &val); | |
1111 | val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3); | |
1112 | val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0); | |
1113 | if (preA3Chip) { | |
1114 | val = RXTX_REG145_RXES_ENA_SET(val, 0x1); | |
1115 | val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1); | |
1116 | } else { | |
1117 | val = RXTX_REG145_RXES_ENA_SET(val, 0x0); | |
1118 | val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0); | |
1119 | } | |
1120 | serdes_wr(ctx, lane, RXTX_REG145, val); | |
1121 | ||
1122 | /* | |
1123 | * Set Rx LOS filter clock rate, sample rate, and threshold | |
1124 | * windows | |
1125 | */ | |
1126 | for (i = 0; i < 4; i++) { | |
1127 | reg = RXTX_REG148 + i * 2; | |
1128 | serdes_wr(ctx, lane, reg, 0xFFFF); | |
1129 | } | |
1130 | } | |
1131 | } | |
1132 | ||
1133 | static int xgene_phy_cal_rdy_chk(struct xgene_phy_ctx *ctx, | |
1134 | enum cmu_type_t cmu_type, | |
1135 | enum clk_type_t clk_type) | |
1136 | { | |
1137 | void __iomem *csr_serdes = ctx->sds_base; | |
1138 | int loop; | |
1139 | u32 val; | |
1140 | ||
1141 | /* Release PHY main reset */ | |
1142 | writel(0xdf, csr_serdes + SATA_ENET_SDS_RST_CTL); | |
1143 | readl(csr_serdes + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ | |
1144 | ||
1145 | if (cmu_type != REF_CMU) { | |
1146 | cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK); | |
1147 | /* | |
1148 | * As per PHY design spec, the PLL reset requires a minimum | |
1149 | * of 800us. | |
1150 | */ | |
1151 | usleep_range(800, 1000); | |
1152 | ||
1153 | cmu_rd(ctx, cmu_type, CMU_REG1, &val); | |
1154 | val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0); | |
1155 | cmu_wr(ctx, cmu_type, CMU_REG1, val); | |
1156 | /* | |
1157 | * As per PHY design spec, the PLL auto calibration requires | |
1158 | * a minimum of 800us. | |
1159 | */ | |
1160 | usleep_range(800, 1000); | |
1161 | ||
1162 | cmu_toggle1to0(ctx, cmu_type, CMU_REG32, | |
1163 | CMU_REG32_FORCE_VCOCAL_START_MASK); | |
1164 | /* | |
1165 | * As per PHY design spec, the PLL requires a minimum of | |
1166 | * 800us to settle. | |
1167 | */ | |
1168 | usleep_range(800, 1000); | |
1169 | } | |
1170 | ||
1171 | if (!preA3Chip) | |
1172 | goto skip_manual_cal; | |
1173 | ||
1174 | /* | |
1175 | * Configure the termination resister calibration | |
1176 | * The serial receive pins, RXP/RXN, have TERMination resistor | |
1177 | * that is required to be calibrated. | |
1178 | */ | |
1179 | cmu_rd(ctx, cmu_type, CMU_REG17, &val); | |
1180 | val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12); | |
1181 | val = CMU_REG17_RESERVED_7_SET(val, 0x0); | |
1182 | cmu_wr(ctx, cmu_type, CMU_REG17, val); | |
1183 | cmu_toggle1to0(ctx, cmu_type, CMU_REG17, | |
1184 | CMU_REG17_PVT_TERM_MAN_ENA_MASK); | |
1185 | /* | |
1186 | * The serial transmit pins, TXP/TXN, have Pull-UP and Pull-DOWN | |
1187 | * resistors that are required to the calibrated. | |
1188 | * Configure the pull DOWN calibration | |
1189 | */ | |
1190 | cmu_rd(ctx, cmu_type, CMU_REG17, &val); | |
1191 | val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29); | |
1192 | val = CMU_REG17_RESERVED_7_SET(val, 0x0); | |
1193 | cmu_wr(ctx, cmu_type, CMU_REG17, val); | |
1194 | cmu_toggle1to0(ctx, cmu_type, CMU_REG16, | |
1195 | CMU_REG16_PVT_DN_MAN_ENA_MASK); | |
1196 | /* Configure the pull UP calibration */ | |
1197 | cmu_rd(ctx, cmu_type, CMU_REG17, &val); | |
1198 | val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28); | |
1199 | val = CMU_REG17_RESERVED_7_SET(val, 0x0); | |
1200 | cmu_wr(ctx, cmu_type, CMU_REG17, val); | |
1201 | cmu_toggle1to0(ctx, cmu_type, CMU_REG16, | |
1202 | CMU_REG16_PVT_UP_MAN_ENA_MASK); | |
1203 | ||
1204 | skip_manual_cal: | |
1205 | /* Poll the PLL calibration completion status for at least 1 ms */ | |
1206 | loop = 100; | |
1207 | do { | |
1208 | cmu_rd(ctx, cmu_type, CMU_REG7, &val); | |
1209 | if (CMU_REG7_PLL_CALIB_DONE_RD(val)) | |
1210 | break; | |
1211 | /* | |
1212 | * As per PHY design spec, PLL calibration status requires | |
1213 | * a minimum of 10us to be updated. | |
1214 | */ | |
1215 | usleep_range(10, 100); | |
1216 | } while (--loop > 0); | |
1217 | ||
1218 | cmu_rd(ctx, cmu_type, CMU_REG7, &val); | |
1219 | dev_dbg(ctx->dev, "PLL calibration %s\n", | |
1220 | CMU_REG7_PLL_CALIB_DONE_RD(val) ? "done" : "failed"); | |
1221 | if (CMU_REG7_VCO_CAL_FAIL_RD(val)) { | |
1222 | dev_err(ctx->dev, | |
1223 | "PLL calibration failed due to VCO failure\n"); | |
1224 | return -1; | |
1225 | } | |
1226 | dev_dbg(ctx->dev, "PLL calibration successful\n"); | |
1227 | ||
1228 | cmu_rd(ctx, cmu_type, CMU_REG15, &val); | |
1229 | dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); | |
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | static void xgene_phy_pdwn_force_vco(struct xgene_phy_ctx *ctx, | |
1234 | enum cmu_type_t cmu_type, | |
1235 | enum clk_type_t clk_type) | |
1236 | { | |
1237 | u32 val; | |
1238 | ||
1239 | dev_dbg(ctx->dev, "Reset VCO and re-start again\n"); | |
1240 | if (cmu_type == PHY_CMU) { | |
1241 | cmu_rd(ctx, cmu_type, CMU_REG16, &val); | |
1242 | val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7); | |
1243 | cmu_wr(ctx, cmu_type, CMU_REG16, val); | |
1244 | } | |
1245 | ||
1246 | cmu_toggle1to0(ctx, cmu_type, CMU_REG0, CMU_REG0_PDOWN_MASK); | |
1247 | cmu_toggle1to0(ctx, cmu_type, CMU_REG32, | |
1248 | CMU_REG32_FORCE_VCOCAL_START_MASK); | |
1249 | } | |
1250 | ||
1251 | static int xgene_phy_hw_init_sata(struct xgene_phy_ctx *ctx, | |
1252 | enum clk_type_t clk_type, int ssc_enable) | |
1253 | { | |
1254 | void __iomem *sds_base = ctx->sds_base; | |
1255 | u32 val; | |
1256 | int i; | |
1257 | ||
1258 | /* Configure the PHY for operation */ | |
1259 | dev_dbg(ctx->dev, "Reset PHY\n"); | |
1260 | /* Place PHY into reset */ | |
1261 | writel(0x0, sds_base + SATA_ENET_SDS_RST_CTL); | |
1262 | val = readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ | |
1263 | /* Release PHY lane from reset (active high) */ | |
1264 | writel(0x20, sds_base + SATA_ENET_SDS_RST_CTL); | |
1265 | readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ | |
1266 | /* Release all PHY module out of reset except PHY main reset */ | |
1267 | writel(0xde, sds_base + SATA_ENET_SDS_RST_CTL); | |
1268 | readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */ | |
1269 | ||
1270 | /* Set the operation speed */ | |
1271 | val = readl(sds_base + SATA_ENET_SDS_CTL1); | |
1272 | val = CFG_I_SPD_SEL_CDR_OVR1_SET(val, | |
1273 | ctx->sata_param.txspeed[ctx->sata_param.speed[0]]); | |
1274 | writel(val, sds_base + SATA_ENET_SDS_CTL1); | |
1275 | ||
1276 | dev_dbg(ctx->dev, "Set the customer pin mode to SATA\n"); | |
1277 | val = readl(sds_base + SATA_ENET_SDS_CTL0); | |
1278 | val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421); | |
1279 | writel(val, sds_base + SATA_ENET_SDS_CTL0); | |
1280 | ||
1281 | /* Configure the clock macro unit (CMU) clock type */ | |
1282 | xgene_phy_cfg_cmu_clk_type(ctx, PHY_CMU, clk_type); | |
1283 | ||
1284 | /* Configure the clock macro */ | |
1285 | xgene_phy_sata_cfg_cmu_core(ctx, PHY_CMU, clk_type); | |
1286 | ||
1287 | /* Enable SSC if enabled */ | |
1288 | if (ssc_enable) | |
1289 | xgene_phy_ssc_enable(ctx, PHY_CMU); | |
1290 | ||
1291 | /* Configure PHY lanes */ | |
1292 | xgene_phy_sata_cfg_lanes(ctx); | |
1293 | ||
1294 | /* Set Rx/Tx 20-bit */ | |
1295 | val = readl(sds_base + SATA_ENET_SDS_PCS_CTL0); | |
1296 | val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3); | |
1297 | val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3); | |
1298 | writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0); | |
1299 | ||
1300 | /* Start PLL calibration and try for three times */ | |
1301 | i = 10; | |
1302 | do { | |
1303 | if (!xgene_phy_cal_rdy_chk(ctx, PHY_CMU, clk_type)) | |
1304 | break; | |
1305 | /* If failed, toggle the VCO power signal and start again */ | |
1306 | xgene_phy_pdwn_force_vco(ctx, PHY_CMU, clk_type); | |
1307 | } while (--i > 0); | |
1308 | /* Even on failure, allow to continue any way */ | |
1309 | if (i <= 0) | |
1310 | dev_err(ctx->dev, "PLL calibration failed\n"); | |
1311 | ||
1312 | return 0; | |
1313 | } | |
1314 | ||
1315 | static int xgene_phy_hw_initialize(struct xgene_phy_ctx *ctx, | |
1316 | enum clk_type_t clk_type, | |
1317 | int ssc_enable) | |
1318 | { | |
1319 | int rc; | |
1320 | ||
1321 | dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type); | |
1322 | ||
1323 | if (ctx->mode == MODE_SATA) { | |
1324 | rc = xgene_phy_hw_init_sata(ctx, clk_type, ssc_enable); | |
1325 | if (rc) | |
1326 | return rc; | |
1327 | } else { | |
1328 | dev_err(ctx->dev, "Un-supported customer pin mode %d\n", | |
1329 | ctx->mode); | |
1330 | return -ENODEV; | |
1331 | } | |
1332 | ||
1333 | return 0; | |
1334 | } | |
1335 | ||
1336 | /* | |
1337 | * Receiver Offset Calibration: | |
1338 | * | |
1339 | * Calibrate the receiver signal path offset in two steps - summar and | |
1340 | * latch calibrations | |
1341 | */ | |
1342 | static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane) | |
1343 | { | |
1344 | int i; | |
fbf6a7a4 | 1345 | static const struct { |
88e670fe LH |
1346 | u32 reg; |
1347 | u32 val; | |
1348 | } serdes_reg[] = { | |
1349 | {RXTX_REG38, 0x0}, | |
1350 | {RXTX_REG39, 0xff00}, | |
1351 | {RXTX_REG40, 0xffff}, | |
1352 | {RXTX_REG41, 0xffff}, | |
1353 | {RXTX_REG42, 0xffff}, | |
1354 | {RXTX_REG43, 0xffff}, | |
1355 | {RXTX_REG44, 0xffff}, | |
1356 | {RXTX_REG45, 0xffff}, | |
1357 | {RXTX_REG46, 0xffff}, | |
1358 | {RXTX_REG47, 0xfffc}, | |
1359 | {RXTX_REG48, 0x0}, | |
1360 | {RXTX_REG49, 0x0}, | |
1361 | {RXTX_REG50, 0x0}, | |
1362 | {RXTX_REG51, 0x0}, | |
1363 | {RXTX_REG52, 0x0}, | |
1364 | {RXTX_REG53, 0x0}, | |
1365 | {RXTX_REG54, 0x0}, | |
1366 | {RXTX_REG55, 0x0}, | |
1367 | }; | |
1368 | ||
1369 | /* Start SUMMER calibration */ | |
1370 | serdes_setbits(ctx, lane, RXTX_REG127, | |
1371 | RXTX_REG127_FORCE_SUM_CAL_START_MASK); | |
1372 | /* | |
1373 | * As per PHY design spec, the Summer calibration requires a minimum | |
1374 | * of 100us to complete. | |
1375 | */ | |
1376 | usleep_range(100, 500); | |
1377 | serdes_clrbits(ctx, lane, RXTX_REG127, | |
1378 | RXTX_REG127_FORCE_SUM_CAL_START_MASK); | |
1379 | /* | |
1380 | * As per PHY design spec, the auto calibration requires a minimum | |
1381 | * of 100us to complete. | |
1382 | */ | |
1383 | usleep_range(100, 500); | |
1384 | ||
1385 | /* Start latch calibration */ | |
1386 | serdes_setbits(ctx, lane, RXTX_REG127, | |
1387 | RXTX_REG127_FORCE_LAT_CAL_START_MASK); | |
1388 | /* | |
1389 | * As per PHY design spec, the latch calibration requires a minimum | |
1390 | * of 100us to complete. | |
1391 | */ | |
1392 | usleep_range(100, 500); | |
1393 | serdes_clrbits(ctx, lane, RXTX_REG127, | |
1394 | RXTX_REG127_FORCE_LAT_CAL_START_MASK); | |
1395 | ||
1396 | /* Configure the PHY lane for calibration */ | |
1397 | serdes_wr(ctx, lane, RXTX_REG28, 0x7); | |
1398 | serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); | |
1399 | serdes_clrbits(ctx, lane, RXTX_REG4, | |
1400 | RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK); | |
1401 | serdes_clrbits(ctx, lane, RXTX_REG7, | |
1402 | RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK); | |
1403 | for (i = 0; i < ARRAY_SIZE(serdes_reg); i++) | |
1404 | serdes_wr(ctx, lane, serdes_reg[i].reg, | |
1405 | serdes_reg[i].val); | |
1406 | } | |
1407 | ||
1408 | static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane) | |
1409 | { | |
1410 | /* Reset digital Rx */ | |
1411 | serdes_clrbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); | |
1412 | /* As per PHY design spec, the reset requires a minimum of 100us. */ | |
1413 | usleep_range(100, 150); | |
1414 | serdes_setbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); | |
1415 | } | |
1416 | ||
1417 | static int xgene_phy_get_avg(int accum, int samples) | |
1418 | { | |
1419 | return (accum + (samples / 2)) / samples; | |
1420 | } | |
1421 | ||
1422 | static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane) | |
1423 | { | |
1424 | int max_loop = 10; | |
1425 | int avg_loop = 0; | |
1426 | int lat_do = 0, lat_xo = 0, lat_eo = 0, lat_so = 0; | |
1427 | int lat_de = 0, lat_xe = 0, lat_ee = 0, lat_se = 0; | |
1428 | int sum_cal = 0; | |
1429 | int lat_do_itr, lat_xo_itr, lat_eo_itr, lat_so_itr; | |
1430 | int lat_de_itr, lat_xe_itr, lat_ee_itr, lat_se_itr; | |
1431 | int sum_cal_itr; | |
1432 | int fail_even; | |
1433 | int fail_odd; | |
1434 | u32 val; | |
1435 | ||
1436 | dev_dbg(ctx->dev, "Generating avg calibration value for lane %d\n", | |
1437 | lane); | |
1438 | ||
1439 | /* Enable RX Hi-Z termination */ | |
1440 | serdes_setbits(ctx, lane, RXTX_REG12, | |
1441 | RXTX_REG12_RX_DET_TERM_ENABLE_MASK); | |
1442 | /* Turn off DFE */ | |
1443 | serdes_wr(ctx, lane, RXTX_REG28, 0x0000); | |
1444 | /* DFE Presets to zero */ | |
1445 | serdes_wr(ctx, lane, RXTX_REG31, 0x0000); | |
1446 | ||
1447 | /* | |
1448 | * Receiver Offset Calibration: | |
1449 | * Calibrate the receiver signal path offset in two steps - summar | |
1450 | * and latch calibration. | |
1451 | * Runs the "Receiver Offset Calibration multiple times to determine | |
1452 | * the average value to use. | |
1453 | */ | |
1454 | while (avg_loop < max_loop) { | |
1455 | /* Start the calibration */ | |
1456 | xgene_phy_force_lat_summer_cal(ctx, lane); | |
1457 | ||
1458 | serdes_rd(ctx, lane, RXTX_REG21, &val); | |
1459 | lat_do_itr = RXTX_REG21_DO_LATCH_CALOUT_RD(val); | |
1460 | lat_xo_itr = RXTX_REG21_XO_LATCH_CALOUT_RD(val); | |
1461 | fail_odd = RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(val); | |
1462 | ||
1463 | serdes_rd(ctx, lane, RXTX_REG22, &val); | |
1464 | lat_eo_itr = RXTX_REG22_EO_LATCH_CALOUT_RD(val); | |
1465 | lat_so_itr = RXTX_REG22_SO_LATCH_CALOUT_RD(val); | |
1466 | fail_even = RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(val); | |
1467 | ||
1468 | serdes_rd(ctx, lane, RXTX_REG23, &val); | |
1469 | lat_de_itr = RXTX_REG23_DE_LATCH_CALOUT_RD(val); | |
1470 | lat_xe_itr = RXTX_REG23_XE_LATCH_CALOUT_RD(val); | |
1471 | ||
1472 | serdes_rd(ctx, lane, RXTX_REG24, &val); | |
1473 | lat_ee_itr = RXTX_REG24_EE_LATCH_CALOUT_RD(val); | |
1474 | lat_se_itr = RXTX_REG24_SE_LATCH_CALOUT_RD(val); | |
1475 | ||
1476 | serdes_rd(ctx, lane, RXTX_REG121, &val); | |
1477 | sum_cal_itr = RXTX_REG121_SUMOS_CAL_CODE_RD(val); | |
1478 | ||
1479 | /* Check for failure. If passed, sum them for averaging */ | |
1480 | if ((fail_even == 0 || fail_even == 1) && | |
1481 | (fail_odd == 0 || fail_odd == 1)) { | |
1482 | lat_do += lat_do_itr; | |
1483 | lat_xo += lat_xo_itr; | |
1484 | lat_eo += lat_eo_itr; | |
1485 | lat_so += lat_so_itr; | |
1486 | lat_de += lat_de_itr; | |
1487 | lat_xe += lat_xe_itr; | |
1488 | lat_ee += lat_ee_itr; | |
1489 | lat_se += lat_se_itr; | |
1490 | sum_cal += sum_cal_itr; | |
1491 | ||
1492 | dev_dbg(ctx->dev, "Iteration %d:\n", avg_loop); | |
1493 | dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", | |
1494 | lat_do_itr, lat_xo_itr, lat_eo_itr, | |
1495 | lat_so_itr); | |
1496 | dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", | |
1497 | lat_de_itr, lat_xe_itr, lat_ee_itr, | |
1498 | lat_se_itr); | |
1499 | dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr); | |
1500 | ++avg_loop; | |
1501 | } else { | |
1502 | dev_err(ctx->dev, | |
1503 | "Receiver calibration failed at %d loop\n", | |
1504 | avg_loop); | |
1505 | } | |
1506 | xgene_phy_reset_rxd(ctx, lane); | |
1507 | } | |
1508 | ||
1509 | /* Update latch manual calibration with average value */ | |
1510 | serdes_rd(ctx, lane, RXTX_REG127, &val); | |
1511 | val = RXTX_REG127_DO_LATCH_MANCAL_SET(val, | |
1512 | xgene_phy_get_avg(lat_do, max_loop)); | |
1513 | val = RXTX_REG127_XO_LATCH_MANCAL_SET(val, | |
1514 | xgene_phy_get_avg(lat_xo, max_loop)); | |
1515 | serdes_wr(ctx, lane, RXTX_REG127, val); | |
1516 | ||
1517 | serdes_rd(ctx, lane, RXTX_REG128, &val); | |
1518 | val = RXTX_REG128_EO_LATCH_MANCAL_SET(val, | |
1519 | xgene_phy_get_avg(lat_eo, max_loop)); | |
1520 | val = RXTX_REG128_SO_LATCH_MANCAL_SET(val, | |
1521 | xgene_phy_get_avg(lat_so, max_loop)); | |
1522 | serdes_wr(ctx, lane, RXTX_REG128, val); | |
1523 | ||
1524 | serdes_rd(ctx, lane, RXTX_REG129, &val); | |
1525 | val = RXTX_REG129_DE_LATCH_MANCAL_SET(val, | |
1526 | xgene_phy_get_avg(lat_de, max_loop)); | |
1527 | val = RXTX_REG129_XE_LATCH_MANCAL_SET(val, | |
1528 | xgene_phy_get_avg(lat_xe, max_loop)); | |
1529 | serdes_wr(ctx, lane, RXTX_REG129, val); | |
1530 | ||
1531 | serdes_rd(ctx, lane, RXTX_REG130, &val); | |
1532 | val = RXTX_REG130_EE_LATCH_MANCAL_SET(val, | |
1533 | xgene_phy_get_avg(lat_ee, max_loop)); | |
1534 | val = RXTX_REG130_SE_LATCH_MANCAL_SET(val, | |
1535 | xgene_phy_get_avg(lat_se, max_loop)); | |
1536 | serdes_wr(ctx, lane, RXTX_REG130, val); | |
1537 | ||
1538 | /* Update SUMMER calibration with average value */ | |
1539 | serdes_rd(ctx, lane, RXTX_REG14, &val); | |
1540 | val = RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(val, | |
1541 | xgene_phy_get_avg(sum_cal, max_loop)); | |
1542 | serdes_wr(ctx, lane, RXTX_REG14, val); | |
1543 | ||
1544 | dev_dbg(ctx->dev, "Average Value:\n"); | |
1545 | dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", | |
1546 | xgene_phy_get_avg(lat_do, max_loop), | |
1547 | xgene_phy_get_avg(lat_xo, max_loop), | |
1548 | xgene_phy_get_avg(lat_eo, max_loop), | |
1549 | xgene_phy_get_avg(lat_so, max_loop)); | |
1550 | dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", | |
1551 | xgene_phy_get_avg(lat_de, max_loop), | |
1552 | xgene_phy_get_avg(lat_xe, max_loop), | |
1553 | xgene_phy_get_avg(lat_ee, max_loop), | |
1554 | xgene_phy_get_avg(lat_se, max_loop)); | |
1555 | dev_dbg(ctx->dev, "SUM 0x%x\n", | |
1556 | xgene_phy_get_avg(sum_cal, max_loop)); | |
1557 | ||
1558 | serdes_rd(ctx, lane, RXTX_REG14, &val); | |
1559 | val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1); | |
1560 | serdes_wr(ctx, lane, RXTX_REG14, val); | |
1561 | dev_dbg(ctx->dev, "Enable Manual Summer calibration\n"); | |
1562 | ||
1563 | serdes_rd(ctx, lane, RXTX_REG127, &val); | |
1564 | val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1); | |
1565 | dev_dbg(ctx->dev, "Enable Manual Latch calibration\n"); | |
1566 | serdes_wr(ctx, lane, RXTX_REG127, val); | |
1567 | ||
1568 | /* Disable RX Hi-Z termination */ | |
1569 | serdes_rd(ctx, lane, RXTX_REG12, &val); | |
1570 | val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0); | |
1571 | serdes_wr(ctx, lane, RXTX_REG12, val); | |
1572 | /* Turn on DFE */ | |
1573 | serdes_wr(ctx, lane, RXTX_REG28, 0x0007); | |
1574 | /* Set DFE preset */ | |
1575 | serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); | |
1576 | } | |
1577 | ||
1578 | static int xgene_phy_hw_init(struct phy *phy) | |
1579 | { | |
1580 | struct xgene_phy_ctx *ctx = phy_get_drvdata(phy); | |
1581 | int rc; | |
1582 | int i; | |
1583 | ||
1584 | rc = xgene_phy_hw_initialize(ctx, CLK_EXT_DIFF, SSC_DISABLE); | |
1585 | if (rc) { | |
1586 | dev_err(ctx->dev, "PHY initialize failed %d\n", rc); | |
1587 | return rc; | |
1588 | } | |
1589 | ||
1590 | /* Setup clock properly after PHY configuration */ | |
1591 | if (!IS_ERR(ctx->clk)) { | |
1592 | /* HW requires an toggle of the clock */ | |
1593 | clk_prepare_enable(ctx->clk); | |
1594 | clk_disable_unprepare(ctx->clk); | |
1595 | clk_prepare_enable(ctx->clk); | |
1596 | } | |
1597 | ||
1598 | /* Compute average value */ | |
1599 | for (i = 0; i < MAX_LANE; i++) | |
1600 | xgene_phy_gen_avg_val(ctx, i); | |
1601 | ||
1602 | dev_dbg(ctx->dev, "PHY initialized\n"); | |
1603 | return 0; | |
1604 | } | |
1605 | ||
1606 | static const struct phy_ops xgene_phy_ops = { | |
1607 | .init = xgene_phy_hw_init, | |
1608 | .owner = THIS_MODULE, | |
1609 | }; | |
1610 | ||
1611 | static struct phy *xgene_phy_xlate(struct device *dev, | |
1612 | struct of_phandle_args *args) | |
1613 | { | |
1614 | struct xgene_phy_ctx *ctx = dev_get_drvdata(dev); | |
1615 | ||
1616 | if (args->args_count <= 0) | |
1617 | return ERR_PTR(-EINVAL); | |
f0c47c74 | 1618 | if (args->args[0] >= MODE_MAX) |
88e670fe LH |
1619 | return ERR_PTR(-EINVAL); |
1620 | ||
1621 | ctx->mode = args->args[0]; | |
1622 | return ctx->phy; | |
1623 | } | |
1624 | ||
1625 | static void xgene_phy_get_param(struct platform_device *pdev, | |
1626 | const char *name, u32 *buffer, | |
1627 | int count, u32 *default_val, | |
1628 | u32 conv_factor) | |
1629 | { | |
1630 | int i; | |
1631 | ||
1632 | if (!of_property_read_u32_array(pdev->dev.of_node, name, buffer, | |
1633 | count)) { | |
1634 | for (i = 0; i < count; i++) | |
1635 | buffer[i] /= conv_factor; | |
1636 | return; | |
1637 | } | |
1638 | /* Does not exist, load default */ | |
1639 | for (i = 0; i < count; i++) | |
1640 | buffer[i] = default_val[i % 3]; | |
1641 | } | |
1642 | ||
1643 | static int xgene_phy_probe(struct platform_device *pdev) | |
1644 | { | |
1645 | struct phy_provider *phy_provider; | |
1646 | struct xgene_phy_ctx *ctx; | |
88e670fe LH |
1647 | u32 default_spd[] = DEFAULT_SATA_SPD_SEL; |
1648 | u32 default_txboost_gain[] = DEFAULT_SATA_TXBOOST_GAIN; | |
1649 | u32 default_txeye_direction[] = DEFAULT_SATA_TXEYEDIRECTION; | |
1650 | u32 default_txeye_tuning[] = DEFAULT_SATA_TXEYETUNING; | |
1651 | u32 default_txamp[] = DEFAULT_SATA_TXAMP; | |
1652 | u32 default_txcn1[] = DEFAULT_SATA_TXCN1; | |
1653 | u32 default_txcn2[] = DEFAULT_SATA_TXCN2; | |
1654 | u32 default_txcp1[] = DEFAULT_SATA_TXCP1; | |
1655 | int i; | |
1656 | ||
1657 | ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); | |
1658 | if (!ctx) | |
1659 | return -ENOMEM; | |
1660 | ||
1661 | ctx->dev = &pdev->dev; | |
1662 | ||
5d797059 | 1663 | ctx->sds_base = devm_platform_ioremap_resource(pdev, 0); |
8fd0ea39 AL |
1664 | if (IS_ERR(ctx->sds_base)) |
1665 | return PTR_ERR(ctx->sds_base); | |
88e670fe LH |
1666 | |
1667 | /* Retrieve optional clock */ | |
1668 | ctx->clk = clk_get(&pdev->dev, NULL); | |
1669 | ||
1670 | /* Load override paramaters */ | |
1671 | xgene_phy_get_param(pdev, "apm,tx-eye-tuning", | |
1672 | ctx->sata_param.txeyetuning, 6, default_txeye_tuning, 1); | |
1673 | xgene_phy_get_param(pdev, "apm,tx-eye-direction", | |
1674 | ctx->sata_param.txeyedirection, 6, default_txeye_direction, 1); | |
1675 | xgene_phy_get_param(pdev, "apm,tx-boost-gain", | |
1676 | ctx->sata_param.txboostgain, 6, default_txboost_gain, 1); | |
1677 | xgene_phy_get_param(pdev, "apm,tx-amplitude", | |
1678 | ctx->sata_param.txamplitude, 6, default_txamp, 13300); | |
1679 | xgene_phy_get_param(pdev, "apm,tx-pre-cursor1", | |
1680 | ctx->sata_param.txprecursor_cn1, 6, default_txcn1, 18200); | |
1681 | xgene_phy_get_param(pdev, "apm,tx-pre-cursor2", | |
1682 | ctx->sata_param.txprecursor_cn2, 6, default_txcn2, 18200); | |
1683 | xgene_phy_get_param(pdev, "apm,tx-post-cursor", | |
1684 | ctx->sata_param.txpostcursor_cp1, 6, default_txcp1, 18200); | |
1685 | xgene_phy_get_param(pdev, "apm,tx-speed", | |
1686 | ctx->sata_param.txspeed, 3, default_spd, 1); | |
1687 | for (i = 0; i < MAX_LANE; i++) | |
1688 | ctx->sata_param.speed[i] = 2; /* Default to Gen3 */ | |
1689 | ||
88e670fe LH |
1690 | platform_set_drvdata(pdev, ctx); |
1691 | ||
dbc98635 | 1692 | ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops); |
88e670fe LH |
1693 | if (IS_ERR(ctx->phy)) { |
1694 | dev_dbg(&pdev->dev, "Failed to create PHY\n"); | |
8fd0ea39 | 1695 | return PTR_ERR(ctx->phy); |
88e670fe LH |
1696 | } |
1697 | phy_set_drvdata(ctx->phy, ctx); | |
1698 | ||
8fd0ea39 AL |
1699 | phy_provider = devm_of_phy_provider_register(ctx->dev, xgene_phy_xlate); |
1700 | return PTR_ERR_OR_ZERO(phy_provider); | |
88e670fe LH |
1701 | } |
1702 | ||
1703 | static const struct of_device_id xgene_phy_of_match[] = { | |
1704 | {.compatible = "apm,xgene-phy",}, | |
1705 | {}, | |
1706 | }; | |
1707 | MODULE_DEVICE_TABLE(of, xgene_phy_of_match); | |
1708 | ||
1709 | static struct platform_driver xgene_phy_driver = { | |
1710 | .probe = xgene_phy_probe, | |
1711 | .driver = { | |
1712 | .name = "xgene-phy", | |
88e670fe LH |
1713 | .of_match_table = xgene_phy_of_match, |
1714 | }, | |
1715 | }; | |
1716 | module_platform_driver(xgene_phy_driver); | |
1717 | ||
1718 | MODULE_DESCRIPTION("APM X-Gene Multi-Purpose PHY driver"); | |
1719 | MODULE_AUTHOR("Loc Ho <lho@apm.com>"); | |
1720 | MODULE_LICENSE("GPL v2"); | |
1721 | MODULE_VERSION("0.1"); |