[linux-2.6-block.git] / drivers / phy / phy-rcar-gen3-usb2.c

/*
 * Renesas R-Car Gen3 for USB2.0 PHY driver
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 *
 * This is based on the phy-rcar-gen2 driver:
 * Copyright (C) 2014 Renesas Solutions Corp.
 * Copyright (C) 2014 Cogent Embedded, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>

/******* USB2.0 Host registers (original offset is +0x200) *******/
#define USB2_INT_ENABLE		0x000
#define USB2_USBCTR		0x00c
#define USB2_SPD_RSM_TIMSET	0x10c
#define USB2_OC_TIMSET		0x110
#define USB2_COMMCTRL		0x600
#define USB2_OBINTSTA		0x604
#define USB2_OBINTEN		0x608
#define USB2_VBCTRL		0x60c
#define USB2_LINECTRL1		0x610
#define USB2_ADPCTRL		0x630

/* INT_ENABLE */
#define USB2_INT_ENABLE_UCOM_INTEN	BIT(3)
#define USB2_INT_ENABLE_USBH_INTB_EN	BIT(2)
#define USB2_INT_ENABLE_USBH_INTA_EN	BIT(1)
#define USB2_INT_ENABLE_INIT		(USB2_INT_ENABLE_UCOM_INTEN | \
					 USB2_INT_ENABLE_USBH_INTB_EN | \
					 USB2_INT_ENABLE_USBH_INTA_EN)

/* USBCTR */
#define USB2_USBCTR_DIRPD	BIT(2)
#define USB2_USBCTR_PLL_RST	BIT(1)

/* SPD_RSM_TIMSET */
#define USB2_SPD_RSM_TIMSET_INIT	0x014e029b

/* OC_TIMSET */
#define USB2_OC_TIMSET_INIT		0x000209ab

/* COMMCTRL */
#define USB2_COMMCTRL_OTG_PERI		BIT(31)	/* 1 = Peripheral mode */

/* OBINTSTA and OBINTEN */
#define USB2_OBINT_SESSVLDCHG		BIT(12)
#define USB2_OBINT_IDDIGCHG		BIT(11)
#define USB2_OBINT_BITS			(USB2_OBINT_SESSVLDCHG | \
					 USB2_OBINT_IDDIGCHG)

/* VBCTRL */
#define USB2_VBCTRL_DRVVBUSSEL		BIT(8)

/* LINECTRL1 */
#define USB2_LINECTRL1_DPRPD_EN		BIT(19)
#define USB2_LINECTRL1_DP_RPD		BIT(18)
#define USB2_LINECTRL1_DMRPD_EN		BIT(17)
#define USB2_LINECTRL1_DM_RPD		BIT(16)

/* ADPCTRL */
#define USB2_ADPCTRL_OTGSESSVLD		BIT(20)
#define USB2_ADPCTRL_IDDIG		BIT(19)
#define USB2_ADPCTRL_IDPULLUP		BIT(5)	/* 1 = ID sampling is enabled */
#define USB2_ADPCTRL_DRVVBUS		BIT(4)

/******* HSUSB registers (original offset is +0x100) *******/
#define HSUSB_LPSTS			0x02
#define HSUSB_UGCTRL2			0x84

/* Low Power Status register (LPSTS) */
#define HSUSB_LPSTS_SUSPM		0x4000

/* USB General control register 2 (UGCTRL2) */
#define HSUSB_UGCTRL2_MASK		0x00000031 /* bit[31:6] should be 0 */
#define HSUSB_UGCTRL2_USB0SEL		0x00000030
#define HSUSB_UGCTRL2_USB0SEL_HOST	0x00000010
#define HSUSB_UGCTRL2_USB0SEL_HS_USB	0x00000020
#define HSUSB_UGCTRL2_USB0SEL_OTG	0x00000030

struct rcar_gen3_data {
	void __iomem *base;
	struct clk *clk;
};

struct rcar_gen3_chan {
	struct rcar_gen3_data usb2;
	struct rcar_gen3_data hsusb;
	struct phy *phy;
};

static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
{
	void __iomem *usb2_base = ch->usb2.base;
	u32 val = readl(usb2_base + USB2_COMMCTRL);

	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, host);
	if (host)
		val &= ~USB2_COMMCTRL_OTG_PERI;
	else
		val |= USB2_COMMCTRL_OTG_PERI;
	writel(val, usb2_base + USB2_COMMCTRL);
}

static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
{
	void __iomem *usb2_base = ch->usb2.base;
	u32 val = readl(usb2_base + USB2_LINECTRL1);

	dev_vdbg(&ch->phy->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm);
	val &= ~(USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
	if (dp)
		val |= USB2_LINECTRL1_DP_RPD;
	if (dm)
		val |= USB2_LINECTRL1_DM_RPD;
	writel(val, usb2_base + USB2_LINECTRL1);
}

static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
{
	void __iomem *usb2_base = ch->usb2.base;
	u32 val = readl(usb2_base + USB2_ADPCTRL);

	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, vbus);
	if (vbus)
		val |= USB2_ADPCTRL_DRVVBUS;
	else
		val &= ~USB2_ADPCTRL_DRVVBUS;
	writel(val, usb2_base + USB2_ADPCTRL);
}

static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch)
{
	rcar_gen3_set_linectrl(ch, 1, 1);
	rcar_gen3_set_host_mode(ch, 1);
	rcar_gen3_enable_vbus_ctrl(ch, 1);
}

static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch)
{
	rcar_gen3_set_linectrl(ch, 0, 1);
	rcar_gen3_set_host_mode(ch, 0);
	rcar_gen3_enable_vbus_ctrl(ch, 0);
}

static bool rcar_gen3_check_vbus(struct rcar_gen3_chan *ch)
{
	return !!(readl(ch->usb2.base + USB2_ADPCTRL) &
		  USB2_ADPCTRL_OTGSESSVLD);
}

static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
{
	return !!(readl(ch->usb2.base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
}

static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
{
	bool is_host = true;

	/* B-device? */
	if (rcar_gen3_check_id(ch) && rcar_gen3_check_vbus(ch))
		is_host = false;

	if (is_host)
		rcar_gen3_init_for_host(ch);
	else
		rcar_gen3_init_for_peri(ch);
}

static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
{
	void __iomem *usb2_base = ch->usb2.base;
	u32 val;

	val = readl(usb2_base + USB2_VBCTRL);
	writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
	writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
	val = readl(usb2_base + USB2_OBINTEN);
	writel(val | USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
	val = readl(usb2_base + USB2_ADPCTRL);
	writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
	val = readl(usb2_base + USB2_LINECTRL1);
	rcar_gen3_set_linectrl(ch, 0, 0);
	writel(val | USB2_LINECTRL1_DPRPD_EN | USB2_LINECTRL1_DMRPD_EN,
	       usb2_base + USB2_LINECTRL1);

	rcar_gen3_device_recognition(ch);
}

static int rcar_gen3_phy_usb2_init(struct phy *p)
{
	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	void __iomem *usb2_base = channel->usb2.base;
	void __iomem *hsusb_base = channel->hsusb.base;
	u32 val;

	/* Initialize USB2 part */
	writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
	writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
	writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);

	/* Initialize HSUSB part */
	if (hsusb_base) {
		val = readl(hsusb_base + HSUSB_UGCTRL2);
		val = (val & ~HSUSB_UGCTRL2_USB0SEL) |
		      HSUSB_UGCTRL2_USB0SEL_OTG;
		writel(val & HSUSB_UGCTRL2_MASK, hsusb_base + HSUSB_UGCTRL2);

		/* Initialize otg part */
		rcar_gen3_init_otg(channel);
	}

	return 0;
}

static int rcar_gen3_phy_usb2_exit(struct phy *p)
{
	struct rcar_gen3_chan *channel = phy_get_drvdata(p);

	writel(0, channel->usb2.base + USB2_INT_ENABLE);

	return 0;
}

static int rcar_gen3_phy_usb2_power_on(struct phy *p)
{
	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	void __iomem *usb2_base = channel->usb2.base;
	void __iomem *hsusb_base = channel->hsusb.base;
	u32 val;

	val = readl(usb2_base + USB2_USBCTR);
	val |= USB2_USBCTR_PLL_RST;
	writel(val, usb2_base + USB2_USBCTR);
	val &= ~USB2_USBCTR_PLL_RST;
	writel(val, usb2_base + USB2_USBCTR);

	/*
	 * TODO: To reduce power consuming, this driver should set the SUSPM
	 *	after the PHY detects ID pin as peripheral.
	 */
	if (hsusb_base) {
		/* Power on HSUSB PHY */
		val = readw(hsusb_base + HSUSB_LPSTS);
		val |= HSUSB_LPSTS_SUSPM;
		writew(val, hsusb_base + HSUSB_LPSTS);
	}

	return 0;
}

static int rcar_gen3_phy_usb2_power_off(struct phy *p)
{
	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	void __iomem *hsusb_base = channel->hsusb.base;
	u32 val;

	if (hsusb_base) {
		/* Power off HSUSB PHY */
		val = readw(hsusb_base + HSUSB_LPSTS);
		val &= ~HSUSB_LPSTS_SUSPM;
		writew(val, hsusb_base + HSUSB_LPSTS);
	}

	return 0;
}

static struct phy_ops rcar_gen3_phy_usb2_ops = {
	.init		= rcar_gen3_phy_usb2_init,
	.exit		= rcar_gen3_phy_usb2_exit,
	.power_on	= rcar_gen3_phy_usb2_power_on,
	.power_off	= rcar_gen3_phy_usb2_power_off,
	.owner		= THIS_MODULE,
};

static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
{
	struct rcar_gen3_chan *ch = _ch;
	void __iomem *usb2_base = ch->usb2.base;
	u32 status = readl(usb2_base + USB2_OBINTSTA);
	irqreturn_t ret = IRQ_NONE;

	if (status & USB2_OBINT_BITS) {
		dev_vdbg(&ch->phy->dev, "%s: %08x\n", __func__, status);
		writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
		rcar_gen3_device_recognition(ch);
		ret = IRQ_HANDLED;
	}

	return ret;
}

static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
	{ .compatible = "renesas,usb2-phy-r8a7795" },
	{ }
};
MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);

static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct rcar_gen3_chan *channel;
	struct phy_provider *provider;
	struct resource *res;

	if (!dev->of_node) {
		dev_err(dev, "This driver needs device tree\n");
		return -EINVAL;
	}

	channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
	if (!channel)
		return -ENOMEM;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usb2_host");
	channel->usb2.base = devm_ioremap_resource(dev, res);
	if (IS_ERR(channel->usb2.base))
		return PTR_ERR(channel->usb2.base);

	/* "hsusb" memory resource is optional */
	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsusb");

	/* To avoid error message by devm_ioremap_resource() */
	if (res) {
		int irq;

		channel->hsusb.base = devm_ioremap_resource(dev, res);
		if (IS_ERR(channel->hsusb.base))
			channel->hsusb.base = NULL;
		/* call request_irq for OTG */
		irq = platform_get_irq(pdev, 0);
		if (irq >= 0)
			irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
					       IRQF_SHARED, dev_name(dev),
					       channel);
		if (irq < 0)
			dev_err(dev, "No irq handler (%d)\n", irq);
	}

	/* devm_phy_create() will call pm_runtime_enable(dev); */
	channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops);
	if (IS_ERR(channel->phy)) {
		dev_err(dev, "Failed to create USB2 PHY\n");
		return PTR_ERR(channel->phy);
	}

	phy_set_drvdata(channel->phy, channel);

	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	if (IS_ERR(provider))
		dev_err(dev, "Failed to register PHY provider\n");

	return PTR_ERR_OR_ZERO(provider);
}

static struct platform_driver rcar_gen3_phy_usb2_driver = {
	.driver = {
		.name		= "phy_rcar_gen3_usb2",
		.of_match_table	= rcar_gen3_phy_usb2_match_table,
	},
	.probe	= rcar_gen3_phy_usb2_probe,
};
module_platform_driver(rcar_gen3_phy_usb2_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
Commit	Line	Data
f3b5a8d9 YS	1	/*
	2	* Renesas R-Car Gen3 for USB2.0 PHY driver
	3	*
	4	* Copyright (C) 2015 Renesas Electronics Corporation
	5	*
	6	* This is based on the phy-rcar-gen2 driver:
	7	* Copyright (C) 2014 Renesas Solutions Corp.
	8	* Copyright (C) 2014 Cogent Embedded, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
9f391c57	15	#include <linux/interrupt.h>
f3b5a8d9 YS	16	#include <linux/io.h>
	17	#include <linux/module.h>
	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/phy/phy.h>
	21	#include <linux/platform_device.h>
	22
	23	/***** USB2.0 Host registers (original offset is +0x200) *****/
	24	#define USB2_INT_ENABLE 0x000
	25	#define USB2_USBCTR 0x00c
	26	#define USB2_SPD_RSM_TIMSET 0x10c
	27	#define USB2_OC_TIMSET 0x110
1114e2d3	28	#define USB2_COMMCTRL 0x600
9f391c57 YS	29	#define USB2_OBINTSTA 0x604
9f391c57 YS	30	#define USB2_OBINTEN 0x608
1114e2d3 YS	31	#define USB2_VBCTRL 0x60c
	32	#define USB2_LINECTRL1 0x610
	33	#define USB2_ADPCTRL 0x630
f3b5a8d9 YS	34
f3b5a8d9 YS	35	/* INT_ENABLE */
9f391c57	36	#define USB2_INT_ENABLE_UCOM_INTEN BIT(3)
f3b5a8d9 YS	37	#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2)
f3b5a8d9 YS	38	#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1)
9f391c57 YS	39	#define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_UCOM_INTEN \| \
9f391c57 YS	40	USB2_INT_ENABLE_USBH_INTB_EN \| \
f3b5a8d9 YS	41	USB2_INT_ENABLE_USBH_INTA_EN)
	42
	43	/* USBCTR */
	44	#define USB2_USBCTR_DIRPD BIT(2)
	45	#define USB2_USBCTR_PLL_RST BIT(1)
	46
	47	/* SPD_RSM_TIMSET */
	48	#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
	49
	50	/* OC_TIMSET */
	51	#define USB2_OC_TIMSET_INIT 0x000209ab
	52
1114e2d3 YS	53	/* COMMCTRL */
	54	#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
	55
9f391c57 YS	56	/* OBINTSTA and OBINTEN */
	57	#define USB2_OBINT_SESSVLDCHG BIT(12)
	58	#define USB2_OBINT_IDDIGCHG BIT(11)
	59	#define USB2_OBINT_BITS (USB2_OBINT_SESSVLDCHG \| \
	60	USB2_OBINT_IDDIGCHG)
	61
1114e2d3 YS	62	/* VBCTRL */
	63	#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
	64
	65	/* LINECTRL1 */
	66	#define USB2_LINECTRL1_DPRPD_EN BIT(19)
	67	#define USB2_LINECTRL1_DP_RPD BIT(18)
	68	#define USB2_LINECTRL1_DMRPD_EN BIT(17)
	69	#define USB2_LINECTRL1_DM_RPD BIT(16)
	70
	71	/* ADPCTRL */
	72	#define USB2_ADPCTRL_OTGSESSVLD BIT(20)
	73	#define USB2_ADPCTRL_IDDIG BIT(19)
	74	#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
	75	#define USB2_ADPCTRL_DRVVBUS BIT(4)
	76
f3b5a8d9 YS	77	/***** HSUSB registers (original offset is +0x100) *****/
	78	#define HSUSB_LPSTS 0x02
	79	#define HSUSB_UGCTRL2 0x84
	80
	81	/* Low Power Status register (LPSTS) */
	82	#define HSUSB_LPSTS_SUSPM 0x4000
	83
	84	/* USB General control register 2 (UGCTRL2) */
	85	#define HSUSB_UGCTRL2_MASK 0x00000031 /* bit[31:6] should be 0 */
	86	#define HSUSB_UGCTRL2_USB0SEL 0x00000030
	87	#define HSUSB_UGCTRL2_USB0SEL_HOST 0x00000010
	88	#define HSUSB_UGCTRL2_USB0SEL_HS_USB 0x00000020
	89	#define HSUSB_UGCTRL2_USB0SEL_OTG 0x00000030
	90
	91	struct rcar_gen3_data {
	92	void __iomem *base;
	93	struct clk *clk;
	94	};
	95
	96	struct rcar_gen3_chan {
	97	struct rcar_gen3_data usb2;
	98	struct rcar_gen3_data hsusb;
	99	struct phy *phy;
	100	};
	101
1114e2d3 YS	102	static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
	103	{
	104	void __iomem *usb2_base = ch->usb2.base;
	105	u32 val = readl(usb2_base + USB2_COMMCTRL);
	106
	107	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, host);
	108	if (host)
	109	val &= ~USB2_COMMCTRL_OTG_PERI;
	110	else
	111	val \|= USB2_COMMCTRL_OTG_PERI;
	112	writel(val, usb2_base + USB2_COMMCTRL);
	113	}
	114
	115	static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
	116	{
	117	void __iomem *usb2_base = ch->usb2.base;
	118	u32 val = readl(usb2_base + USB2_LINECTRL1);
	119
	120	dev_vdbg(&ch->phy->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm);
	121	val &= ~(USB2_LINECTRL1_DP_RPD \| USB2_LINECTRL1_DM_RPD);
	122	if (dp)
	123	val \|= USB2_LINECTRL1_DP_RPD;
	124	if (dm)
	125	val \|= USB2_LINECTRL1_DM_RPD;
	126	writel(val, usb2_base + USB2_LINECTRL1);
	127	}
	128
	129	static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
	130	{
	131	void __iomem *usb2_base = ch->usb2.base;
	132	u32 val = readl(usb2_base + USB2_ADPCTRL);
	133
	134	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, vbus);
	135	if (vbus)
	136	val \|= USB2_ADPCTRL_DRVVBUS;
	137	else
	138	val &= ~USB2_ADPCTRL_DRVVBUS;
	139	writel(val, usb2_base + USB2_ADPCTRL);
	140	}
	141
	142	static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch)
	143	{
	144	rcar_gen3_set_linectrl(ch, 1, 1);
	145	rcar_gen3_set_host_mode(ch, 1);
	146	rcar_gen3_enable_vbus_ctrl(ch, 1);
	147	}
	148
	149	static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch)
	150	{
	151	rcar_gen3_set_linectrl(ch, 0, 1);
	152	rcar_gen3_set_host_mode(ch, 0);
	153	rcar_gen3_enable_vbus_ctrl(ch, 0);
	154	}
	155
	156	static bool rcar_gen3_check_vbus(struct rcar_gen3_chan *ch)
	157	{
	158	return !!(readl(ch->usb2.base + USB2_ADPCTRL) &
	159	USB2_ADPCTRL_OTGSESSVLD);
	160	}
	161
	162	static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
	163	{
	164	return !!(readl(ch->usb2.base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
	165	}
166
167	static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
168	{
169	bool is_host = true;
170
171	/* B-device? */
172	if (rcar_gen3_check_id(ch) && rcar_gen3_check_vbus(ch))
173	is_host = false;
174
175	if (is_host)
176	rcar_gen3_init_for_host(ch);
177	else
178	rcar_gen3_init_for_peri(ch);
179	}
180
181	static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
182	{
183	void __iomem *usb2_base = ch->usb2.base;
184	u32 val;
185
186	val = readl(usb2_base + USB2_VBCTRL);
187	writel(val \| USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
9f391c57 YS	188	writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
	189	val = readl(usb2_base + USB2_OBINTEN);
	190	writel(val \| USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
1114e2d3 YS	191	val = readl(usb2_base + USB2_ADPCTRL);
	192	writel(val \| USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
	193	val = readl(usb2_base + USB2_LINECTRL1);
	194	rcar_gen3_set_linectrl(ch, 0, 0);
	195	writel(val \| USB2_LINECTRL1_DPRPD_EN \| USB2_LINECTRL1_DMRPD_EN,
	196	usb2_base + USB2_LINECTRL1);
	197
	198	rcar_gen3_device_recognition(ch);
	199	}
	200
f3b5a8d9 YS	201	static int rcar_gen3_phy_usb2_init(struct phy *p)
	202	{
	203	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	204	void __iomem *usb2_base = channel->usb2.base;
	205	void __iomem *hsusb_base = channel->hsusb.base;
	206	u32 val;
	207
	208	/* Initialize USB2 part */
	209	writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
	210	writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
	211	writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
	212
	213	/* Initialize HSUSB part */
	214	if (hsusb_base) {
f3b5a8d9 YS	215	val = readl(hsusb_base + HSUSB_UGCTRL2);
f3b5a8d9 YS	216	val = (val & ~HSUSB_UGCTRL2_USB0SEL) \|
1114e2d3	217	HSUSB_UGCTRL2_USB0SEL_OTG;
f3b5a8d9	218	writel(val & HSUSB_UGCTRL2_MASK, hsusb_base + HSUSB_UGCTRL2);
1114e2d3 YS	219
	220	/* Initialize otg part */
	221	rcar_gen3_init_otg(channel);
f3b5a8d9 YS	222	}
	223
	224	return 0;
	225	}
	226
	227	static int rcar_gen3_phy_usb2_exit(struct phy *p)
	228	{
	229	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	230
	231	writel(0, channel->usb2.base + USB2_INT_ENABLE);
	232
	233	return 0;
	234	}
	235
	236	static int rcar_gen3_phy_usb2_power_on(struct phy *p)
	237	{
	238	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	239	void __iomem *usb2_base = channel->usb2.base;
	240	void __iomem *hsusb_base = channel->hsusb.base;
	241	u32 val;
	242
	243	val = readl(usb2_base + USB2_USBCTR);
	244	val \|= USB2_USBCTR_PLL_RST;
	245	writel(val, usb2_base + USB2_USBCTR);
	246	val &= ~USB2_USBCTR_PLL_RST;
	247	writel(val, usb2_base + USB2_USBCTR);
	248
	249	/*
	250	* TODO: To reduce power consuming, this driver should set the SUSPM
	251	* after the PHY detects ID pin as peripheral.
	252	*/
	253	if (hsusb_base) {
	254	/* Power on HSUSB PHY */
	255	val = readw(hsusb_base + HSUSB_LPSTS);
	256	val \|= HSUSB_LPSTS_SUSPM;
	257	writew(val, hsusb_base + HSUSB_LPSTS);
	258	}
	259
	260	return 0;
	261	}
	262
	263	static int rcar_gen3_phy_usb2_power_off(struct phy *p)
	264	{
	265	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	266	void __iomem *hsusb_base = channel->hsusb.base;
	267	u32 val;
	268
	269	if (hsusb_base) {
	270	/* Power off HSUSB PHY */
	271	val = readw(hsusb_base + HSUSB_LPSTS);
	272	val &= ~HSUSB_LPSTS_SUSPM;
	273	writew(val, hsusb_base + HSUSB_LPSTS);
	274	}
	275
	276	return 0;
	277	}
	278
	279	static struct phy_ops rcar_gen3_phy_usb2_ops = {
	280	.init = rcar_gen3_phy_usb2_init,
	281	.exit = rcar_gen3_phy_usb2_exit,
	282	.power_on = rcar_gen3_phy_usb2_power_on,
	283	.power_off = rcar_gen3_phy_usb2_power_off,
	284	.owner = THIS_MODULE,
	285	};
286
9f391c57 YS	287	static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
	288	{
	289	struct rcar_gen3_chan *ch = _ch;
	290	void __iomem *usb2_base = ch->usb2.base;
	291	u32 status = readl(usb2_base + USB2_OBINTSTA);
	292	irqreturn_t ret = IRQ_NONE;
	293
	294	if (status & USB2_OBINT_BITS) {
	295	dev_vdbg(&ch->phy->dev, "%s: %08x\n", __func__, status);
	296	writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
	297	rcar_gen3_device_recognition(ch);
	298	ret = IRQ_HANDLED;
	299	}
	300
	301	return ret;
	302	}
	303
f3b5a8d9 YS	304	static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
	305	{ .compatible = "renesas,usb2-phy-r8a7795" },
	306	{ }
	307	};
	308	MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);
	309
	310	static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
	311	{
	312	struct device *dev = &pdev->dev;
	313	struct rcar_gen3_chan *channel;
	314	struct phy_provider *provider;
	315	struct resource *res;
	316
	317	if (!dev->of_node) {
	318	dev_err(dev, "This driver needs device tree\n");
	319	return -EINVAL;
	320	}
	321
	322	channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
	323	if (!channel)
	324	return -ENOMEM;
	325
	326	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usb2_host");
	327	channel->usb2.base = devm_ioremap_resource(dev, res);
	328	if (IS_ERR(channel->usb2.base))
	329	return PTR_ERR(channel->usb2.base);
	330
	331	/* "hsusb" memory resource is optional */
	332	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsusb");
	333
	334	/* To avoid error message by devm_ioremap_resource() */
	335	if (res) {
9f391c57 YS	336	int irq;
9f391c57 YS	337
f3b5a8d9 YS	338	channel->hsusb.base = devm_ioremap_resource(dev, res);
	339	if (IS_ERR(channel->hsusb.base))
	340	channel->hsusb.base = NULL;
9f391c57 YS	341	/* call request_irq for OTG */
	342	irq = platform_get_irq(pdev, 0);
	343	if (irq >= 0)
	344	irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
	345	IRQF_SHARED, dev_name(dev),
	346	channel);
	347	if (irq < 0)
	348	dev_err(dev, "No irq handler (%d)\n", irq);
f3b5a8d9 YS	349	}
	350
	351	/* devm_phy_create() will call pm_runtime_enable(dev); */
	352	channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops);
	353	if (IS_ERR(channel->phy)) {
	354	dev_err(dev, "Failed to create USB2 PHY\n");
	355	return PTR_ERR(channel->phy);
	356	}
	357
	358	phy_set_drvdata(channel->phy, channel);
	359
	360	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	361	if (IS_ERR(provider))
	362	dev_err(dev, "Failed to register PHY provider\n");
	363
	364	return PTR_ERR_OR_ZERO(provider);
	365	}
	366
	367	static struct platform_driver rcar_gen3_phy_usb2_driver = {
	368	.driver = {
	369	.name = "phy_rcar_gen3_usb2",
	370	.of_match_table = rcar_gen3_phy_usb2_match_table,
	371	},
	372	.probe = rcar_gen3_phy_usb2_probe,
	373	};
	374	module_platform_driver(rcar_gen3_phy_usb2_driver);
	375
	376	MODULE_LICENSE("GPL v2");
	377	MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
	378	MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");