[linux-2.6-block.git] / drivers / phy / phy-miphy365x.c

/*
 * Copyright (C) 2014 STMicroelectronics – All Rights Reserved
 *
 * STMicroelectronics PHY driver MiPHY365 (for SoC STiH416).
 *
 * Authors: Alexandre Torgue <alexandre.torgue@st.com>
 *          Lee Jones <lee.jones@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2, as
 * published by the Free Software Foundation.
 *
 */

#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/clk.h>
#include <linux/phy/phy.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include <dt-bindings/phy/phy.h>

#define HFC_TIMEOUT		100

#define SYSCFG_SELECT_SATA_MASK	BIT(1)
#define SYSCFG_SELECT_SATA_POS	1

/* MiPHY365x register definitions */
#define RESET_REG		0x00
#define RST_PLL			BIT(1)
#define RST_PLL_CAL		BIT(2)
#define RST_RX			BIT(4)
#define RST_MACRO		BIT(7)

#define STATUS_REG		0x01
#define IDLL_RDY		BIT(0)
#define PLL_RDY			BIT(1)
#define DES_BIT_LOCK		BIT(2)
#define DES_SYMBOL_LOCK		BIT(3)

#define CTRL_REG		0x02
#define TERM_EN			BIT(0)
#define PCI_EN			BIT(2)
#define DES_BIT_LOCK_EN		BIT(3)
#define TX_POL			BIT(5)

#define INT_CTRL_REG		0x03

#define BOUNDARY1_REG		0x10
#define SPDSEL_SEL		BIT(0)

#define BOUNDARY3_REG		0x12
#define TX_SPDSEL_GEN1_VAL	0
#define TX_SPDSEL_GEN2_VAL	0x01
#define TX_SPDSEL_GEN3_VAL	0x02
#define RX_SPDSEL_GEN1_VAL	0
#define RX_SPDSEL_GEN2_VAL	(0x01 << 3)
#define RX_SPDSEL_GEN3_VAL	(0x02 << 3)

#define PCIE_REG		0x16

#define BUF_SEL_REG		0x20
#define CONF_GEN_SEL_GEN3	0x02
#define CONF_GEN_SEL_GEN2	0x01
#define PD_VDDTFILTER		BIT(4)

#define TXBUF1_REG		0x21
#define SWING_VAL		0x04
#define SWING_VAL_GEN1		0x03
#define PREEMPH_VAL		(0x3 << 5)

#define TXBUF2_REG		0x22
#define TXSLEW_VAL		0x2
#define TXSLEW_VAL_GEN1		0x4

#define RXBUF_OFFSET_CTRL_REG	0x23

#define RXBUF_REG		0x25
#define SDTHRES_VAL		0x01
#define EQ_ON3			(0x03 << 4)
#define EQ_ON1			(0x01 << 4)

#define COMP_CTRL1_REG		0x40
#define START_COMSR		BIT(0)
#define START_COMZC		BIT(1)
#define COMSR_DONE		BIT(2)
#define COMZC_DONE		BIT(3)
#define COMP_AUTO_LOAD		BIT(4)

#define COMP_CTRL2_REG		0x41
#define COMP_2MHZ_RAT_GEN1	0x1e
#define COMP_2MHZ_RAT		0xf

#define COMP_CTRL3_REG		0x42
#define COMSR_COMP_REF		0x33

#define COMP_IDLL_REG		0x47
#define COMZC_IDLL		0x2a

#define PLL_CTRL1_REG		0x50
#define PLL_START_CAL		BIT(0)
#define BUF_EN			BIT(2)
#define SYNCHRO_TX		BIT(3)
#define SSC_EN			BIT(6)
#define CONFIG_PLL		BIT(7)

#define PLL_CTRL2_REG		0x51
#define BYPASS_PLL_CAL		BIT(1)

#define PLL_RAT_REG		0x52

#define PLL_SSC_STEP_MSB_REG	0x56
#define PLL_SSC_STEP_MSB_VAL	0x03

#define PLL_SSC_STEP_LSB_REG	0x57
#define PLL_SSC_STEP_LSB_VAL	0x63

#define PLL_SSC_PER_MSB_REG	0x58
#define PLL_SSC_PER_MSB_VAL	0

#define PLL_SSC_PER_LSB_REG	0x59
#define PLL_SSC_PER_LSB_VAL	0xf1

#define IDLL_TEST_REG		0x72
#define START_CLK_HF		BIT(6)

#define DES_BITLOCK_REG		0x86
#define BIT_LOCK_LEVEL		0x01
#define BIT_LOCK_CNT_512	(0x03 << 5)

struct miphy365x_phy {
	struct phy *phy;
	void __iomem *base;
	bool pcie_tx_pol_inv;
	bool sata_tx_pol_inv;
	u32 sata_gen;
	u32 ctrlreg;
	u8 type;
};

struct miphy365x_dev {
	struct device *dev;
	struct regmap *regmap;
	struct mutex miphy_mutex;
	struct miphy365x_phy **phys;
	int nphys;
};

/*
 * These values are represented in Device tree. They are considered to be ABI
 * and although they can be extended any existing values must not change.
 */
enum miphy_sata_gen {
	SATA_GEN1 = 1,
	SATA_GEN2,
	SATA_GEN3
};

static u8 rx_tx_spd[] = {
	0, /* GEN0 doesn't exist. */
	TX_SPDSEL_GEN1_VAL | RX_SPDSEL_GEN1_VAL,
	TX_SPDSEL_GEN2_VAL | RX_SPDSEL_GEN2_VAL,
	TX_SPDSEL_GEN3_VAL | RX_SPDSEL_GEN3_VAL
};

/*
 * This function selects the system configuration,
 * either two SATA, one SATA and one PCIe, or two PCIe lanes.
 */
static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
			      struct miphy365x_dev *miphy_dev)
{
	bool sata = (miphy_phy->type == PHY_TYPE_SATA);

	return regmap_update_bits(miphy_dev->regmap,
				  miphy_phy->ctrlreg,
				  SYSCFG_SELECT_SATA_MASK,
				  sata << SYSCFG_SELECT_SATA_POS);
}

static int miphy365x_init_pcie_port(struct miphy365x_phy *miphy_phy,
				    struct miphy365x_dev *miphy_dev)
{
	u8 val;

	if (miphy_phy->pcie_tx_pol_inv) {
		/* Invert Tx polarity and clear pci_txdetect_pol bit */
		val = TERM_EN | PCI_EN | DES_BIT_LOCK_EN | TX_POL;
		writeb_relaxed(val, miphy_phy->base + CTRL_REG);
		writeb_relaxed(0x00, miphy_phy->base + PCIE_REG);
	}

	return 0;
}

static inline int miphy365x_hfc_not_rdy(struct miphy365x_phy *miphy_phy,
					struct miphy365x_dev *miphy_dev)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(HFC_TIMEOUT);
	u8 mask = IDLL_RDY | PLL_RDY;
	u8 regval;

	do {
		regval = readb_relaxed(miphy_phy->base + STATUS_REG);
		if (!(regval & mask))
			return 0;

		usleep_range(2000, 2500);
	} while (time_before(jiffies, timeout));

	dev_err(miphy_dev->dev, "HFC ready timeout!\n");
	return -EBUSY;
}

static inline int miphy365x_rdy(struct miphy365x_phy *miphy_phy,
				struct miphy365x_dev *miphy_dev)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(HFC_TIMEOUT);
	u8 mask = IDLL_RDY | PLL_RDY;
	u8 regval;

	do {
		regval = readb_relaxed(miphy_phy->base + STATUS_REG);
		if ((regval & mask) == mask)
			return 0;

		usleep_range(2000, 2500);
	} while (time_before(jiffies, timeout));

	dev_err(miphy_dev->dev, "PHY not ready timeout!\n");
	return -EBUSY;
}

static inline void miphy365x_set_comp(struct miphy365x_phy *miphy_phy,
				      struct miphy365x_dev *miphy_dev)
{
	u8 val, mask;

	if (miphy_phy->sata_gen == SATA_GEN1)
		writeb_relaxed(COMP_2MHZ_RAT_GEN1,
			       miphy_phy->base + COMP_CTRL2_REG);
	else
		writeb_relaxed(COMP_2MHZ_RAT,
			       miphy_phy->base + COMP_CTRL2_REG);

	if (miphy_phy->sata_gen != SATA_GEN3) {
		writeb_relaxed(COMSR_COMP_REF,
			       miphy_phy->base + COMP_CTRL3_REG);
		/*
		 * Force VCO current to value defined by address 0x5A
		 * and disable PCIe100Mref bit
		 * Enable auto load compensation for pll_i_bias
		 */
		writeb_relaxed(BYPASS_PLL_CAL, miphy_phy->base + PLL_CTRL2_REG);
		writeb_relaxed(COMZC_IDLL, miphy_phy->base + COMP_IDLL_REG);
	}

	/*
	 * Force restart compensation and enable auto load
	 * for Comzc_Tx, Comzc_Rx and Comsr on macro
	 */
	val = START_COMSR | START_COMZC | COMP_AUTO_LOAD;
	writeb_relaxed(val, miphy_phy->base + COMP_CTRL1_REG);

	mask = COMSR_DONE | COMZC_DONE;
	while ((readb_relaxed(miphy_phy->base + COMP_CTRL1_REG) & mask)	!= mask)
		cpu_relax();
}

static inline void miphy365x_set_ssc(struct miphy365x_phy *miphy_phy,
				     struct miphy365x_dev *miphy_dev)
{
	u8 val;

	/*
	 * SSC Settings. SSC will be enabled through Link
	 * SSC Ampl. = 0.4%
	 * SSC Freq = 31KHz
	 */
	writeb_relaxed(PLL_SSC_STEP_MSB_VAL,
		       miphy_phy->base + PLL_SSC_STEP_MSB_REG);
	writeb_relaxed(PLL_SSC_STEP_LSB_VAL,
		       miphy_phy->base + PLL_SSC_STEP_LSB_REG);
	writeb_relaxed(PLL_SSC_PER_MSB_VAL,
		       miphy_phy->base + PLL_SSC_PER_MSB_REG);
	writeb_relaxed(PLL_SSC_PER_LSB_VAL,
		       miphy_phy->base + PLL_SSC_PER_LSB_REG);

	/* SSC Settings complete */
	if (miphy_phy->sata_gen == SATA_GEN1) {
		val = PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
		writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
	} else {
		val = SSC_EN | PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
		writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
	}
}

static int miphy365x_init_sata_port(struct miphy365x_phy *miphy_phy,
				    struct miphy365x_dev *miphy_dev)
{
	int ret;
	u8 val;

	/*
	 * Force PHY macro reset, PLL calibration reset, PLL reset
	 * and assert Deserializer Reset
	 */
	val = RST_PLL | RST_PLL_CAL | RST_RX | RST_MACRO;
	writeb_relaxed(val, miphy_phy->base + RESET_REG);

	if (miphy_phy->sata_tx_pol_inv)
		writeb_relaxed(TX_POL, miphy_phy->base + CTRL_REG);

	/*
	 * Force macro1 to use rx_lspd, tx_lspd
	 * Force Rx_Clock on first I-DLL phase
	 * Force Des in HP mode on macro, rx_lspd, tx_lspd for Gen2/3
	 */
	writeb_relaxed(SPDSEL_SEL, miphy_phy->base + BOUNDARY1_REG);
	writeb_relaxed(START_CLK_HF, miphy_phy->base + IDLL_TEST_REG);
	val = rx_tx_spd[miphy_phy->sata_gen];
	writeb_relaxed(val, miphy_phy->base + BOUNDARY3_REG);

	/* Wait for HFC_READY = 0 */
	ret = miphy365x_hfc_not_rdy(miphy_phy, miphy_dev);
	if (ret)
		return ret;

	/* Compensation Recalibration */
	miphy365x_set_comp(miphy_phy, miphy_dev);

	switch (miphy_phy->sata_gen) {
	case SATA_GEN3:
		/*
		 * TX Swing target 550-600mv peak to peak diff
		 * Tx Slew target 90-110ps rising/falling time
		 * Rx Eq ON3, Sigdet threshold SDTH1
		 */
		val = PD_VDDTFILTER | CONF_GEN_SEL_GEN3;
		writeb_relaxed(val, miphy_phy->base + BUF_SEL_REG);
		val = SWING_VAL | PREEMPH_VAL;
		writeb_relaxed(val, miphy_phy->base + TXBUF1_REG);
		writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
		writeb_relaxed(0x00, miphy_phy->base + RXBUF_OFFSET_CTRL_REG);
		val = SDTHRES_VAL | EQ_ON3;
		writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
		break;
	case SATA_GEN2:
		/*
		 * conf gen sel=0x1 to program Gen2 banked registers
		 * VDDT filter ON
		 * Tx Swing target 550-600mV peak-to-peak diff
		 * Tx Slew target 90-110 ps rising/falling time
		 * RX Equalization ON1, Sigdet threshold SDTH1
		 */
		writeb_relaxed(CONF_GEN_SEL_GEN2,
			       miphy_phy->base + BUF_SEL_REG);
		writeb_relaxed(SWING_VAL, miphy_phy->base + TXBUF1_REG);
		writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
		val = SDTHRES_VAL | EQ_ON1;
		writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
		break;
	case SATA_GEN1:
		/*
		 * conf gen sel = 00b to program Gen1 banked registers
		 * VDDT filter ON
		 * Tx Swing target 500-550mV peak-to-peak diff
		 * Tx Slew target120-140 ps rising/falling time
		 */
		writeb_relaxed(PD_VDDTFILTER, miphy_phy->base + BUF_SEL_REG);
		writeb_relaxed(SWING_VAL_GEN1, miphy_phy->base + TXBUF1_REG);
		writeb_relaxed(TXSLEW_VAL_GEN1,	miphy_phy->base + TXBUF2_REG);
		break;
	default:
		break;
	}

	/* Force Macro1 in partial mode & release pll cal reset */
	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
	usleep_range(100, 150);

	miphy365x_set_ssc(miphy_phy, miphy_dev);

	/* Wait for phy_ready */
	ret = miphy365x_rdy(miphy_phy, miphy_dev);
	if (ret)
		return ret;

	/*
	 * Enable macro1 to use rx_lspd & tx_lspd
	 * Release Rx_Clock on first I-DLL phase on macro1
	 * Assert deserializer reset
	 * des_bit_lock_en is set
	 * bit lock detection strength
	 * Deassert deserializer reset
	 */
	writeb_relaxed(0x00, miphy_phy->base + BOUNDARY1_REG);
	writeb_relaxed(0x00, miphy_phy->base + IDLL_TEST_REG);
	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
	val = miphy_phy->sata_tx_pol_inv ?
		(TX_POL | DES_BIT_LOCK_EN) : DES_BIT_LOCK_EN;
	writeb_relaxed(val, miphy_phy->base + CTRL_REG);

	val = BIT_LOCK_CNT_512 | BIT_LOCK_LEVEL;
	writeb_relaxed(val, miphy_phy->base + DES_BITLOCK_REG);
	writeb_relaxed(0x00, miphy_phy->base + RESET_REG);

	return 0;
}

static int miphy365x_init(struct phy *phy)
{
	struct miphy365x_phy *miphy_phy = phy_get_drvdata(phy);
	struct miphy365x_dev *miphy_dev = dev_get_drvdata(phy->dev.parent);
	int ret = 0;

	mutex_lock(&miphy_dev->miphy_mutex);

	ret = miphy365x_set_path(miphy_phy, miphy_dev);
	if (ret) {
		mutex_unlock(&miphy_dev->miphy_mutex);
		return ret;
	}

	/* Initialise Miphy for PCIe or SATA */
	if (miphy_phy->type == PHY_TYPE_PCIE)
		ret = miphy365x_init_pcie_port(miphy_phy, miphy_dev);
	else
		ret = miphy365x_init_sata_port(miphy_phy, miphy_dev);

	mutex_unlock(&miphy_dev->miphy_mutex);

	return ret;
}

static int miphy365x_get_addr(struct device *dev,
		struct miphy365x_phy *miphy_phy, int index)
{
	struct device_node *phynode = miphy_phy->phy->dev.of_node;
	const char *name;
	int type = miphy_phy->type;
	int ret;

	ret = of_property_read_string_index(phynode, "reg-names", index, &name);
	if (ret) {
		dev_err(dev, "no reg-names property not found\n");
		return ret;
	}

	if (!((!strncmp(name, "sata", 4) && type == PHY_TYPE_SATA) ||
	      (!strncmp(name, "pcie", 4) && type == PHY_TYPE_PCIE)))
		return 0;

	miphy_phy->base = of_iomap(phynode, index);
	if (!miphy_phy->base) {
		dev_err(dev, "Failed to map %s\n", phynode->full_name);
		return -EINVAL;
	}

	return 0;
}

static struct phy *miphy365x_xlate(struct device *dev,
				   struct of_phandle_args *args)
{
	struct miphy365x_dev *miphy_dev = dev_get_drvdata(dev);
	struct miphy365x_phy *miphy_phy = NULL;
	struct device_node *phynode = args->np;
	int ret, index;

	if (args->args_count != 1) {
		dev_err(dev, "Invalid number of cells in 'phy' property\n");
		return ERR_PTR(-EINVAL);
	}

	for (index = 0; index < miphy_dev->nphys; index++)
		if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {
			miphy_phy = miphy_dev->phys[index];
			break;
		}

	if (!miphy_phy) {
		dev_err(dev, "Failed to find appropriate phy\n");
		return ERR_PTR(-EINVAL);
	}

	miphy_phy->type = args->args[0];

	if (!(miphy_phy->type == PHY_TYPE_SATA ||
	      miphy_phy->type == PHY_TYPE_PCIE)) {
		dev_err(dev, "Unsupported device type: %d\n", miphy_phy->type);
		return ERR_PTR(-EINVAL);
	}

	/* Each port handles SATA and PCIE - third entry is always sysconf. */
	for (index = 0; index < 3; index++) {
		ret = miphy365x_get_addr(dev, miphy_phy, index);
		if (ret < 0)
			return ERR_PTR(ret);
	}

	return miphy_phy->phy;
}

static const struct phy_ops miphy365x_ops = {
	.init		= miphy365x_init,
	.owner		= THIS_MODULE,
};

static int miphy365x_of_probe(struct device_node *phynode,
			      struct miphy365x_phy *miphy_phy)
{
	of_property_read_u32(phynode, "st,sata-gen", &miphy_phy->sata_gen);
	if (!miphy_phy->sata_gen)
		miphy_phy->sata_gen = SATA_GEN1;

	miphy_phy->pcie_tx_pol_inv =
		of_property_read_bool(phynode, "st,pcie-tx-pol-inv");

	miphy_phy->sata_tx_pol_inv =
		of_property_read_bool(phynode, "st,sata-tx-pol-inv");

	return 0;
}

static int miphy365x_probe(struct platform_device *pdev)
{
	struct device_node *child, *np = pdev->dev.of_node;
	struct miphy365x_dev *miphy_dev;
	struct phy_provider *provider;
	struct phy *phy;
	int ret, port = 0;

	miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
	if (!miphy_dev)
		return -ENOMEM;

	miphy_dev->nphys = of_get_child_count(np);
	miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys,
				       sizeof(*miphy_dev->phys), GFP_KERNEL);
	if (!miphy_dev->phys)
		return -ENOMEM;

	miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
	if (IS_ERR(miphy_dev->regmap)) {
		dev_err(miphy_dev->dev, "No syscfg phandle specified\n");
		return PTR_ERR(miphy_dev->regmap);
	}

	miphy_dev->dev = &pdev->dev;

	dev_set_drvdata(&pdev->dev, miphy_dev);

	mutex_init(&miphy_dev->miphy_mutex);

	for_each_child_of_node(np, child) {
		struct miphy365x_phy *miphy_phy;

		miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
					 GFP_KERNEL);
		if (!miphy_phy) {
			ret = -ENOMEM;
			goto put_child;
		}

		miphy_dev->phys[port] = miphy_phy;

		phy = devm_phy_create(&pdev->dev, child, &miphy365x_ops);
		if (IS_ERR(phy)) {
			dev_err(&pdev->dev, "failed to create PHY\n");
			ret = PTR_ERR(phy);
			goto put_child;
		}

		miphy_dev->phys[port]->phy = phy;

		ret = miphy365x_of_probe(child, miphy_phy);
		if (ret)
			goto put_child;

		phy_set_drvdata(phy, miphy_dev->phys[port]);

		port++;
		/* sysconfig offsets are indexed from 1 */
		ret = of_property_read_u32_index(np, "st,syscfg", port,
					&miphy_phy->ctrlreg);
		if (ret) {
			dev_err(&pdev->dev, "No sysconfig offset found\n");
			goto put_child;
		}
	}

	provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
	return PTR_ERR_OR_ZERO(provider);
put_child:
	of_node_put(child);
	return ret;
}

static const struct of_device_id miphy365x_of_match[] = {
	{ .compatible = "st,miphy365x-phy", },
	{ },
};
MODULE_DEVICE_TABLE(of, miphy365x_of_match);

static struct platform_driver miphy365x_driver = {
	.probe	= miphy365x_probe,
	.driver = {
		.name	= "miphy365x-phy",
		.of_match_table	= miphy365x_of_match,
	}
};
module_platform_driver(miphy365x_driver);

MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
MODULE_DESCRIPTION("STMicroelectronics miphy365x driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
6e877fed LJ	1	/*
	2	* Copyright (C) 2014 STMicroelectronics – All Rights Reserved
	3	*
	4	* STMicroelectronics PHY driver MiPHY365 (for SoC STiH416).
	5	*
	6	* Authors: Alexandre Torgue <alexandre.torgue@st.com>
	7	* Lee Jones <lee.jones@linaro.org>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2, as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/platform_device.h>
	16	#include <linux/io.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_platform.h>
7ebdb52e	21	#include <linux/of_address.h>
6e877fed LJ	22	#include <linux/clk.h>
	23	#include <linux/phy/phy.h>
	24	#include <linux/delay.h>
	25	#include <linux/mfd/syscon.h>
	26	#include <linux/regmap.h>
	27
fbea230e	28	#include <dt-bindings/phy/phy.h>
6e877fed LJ	29
	30	#define HFC_TIMEOUT 100
	31
7ebdb52e LJ	32	#define SYSCFG_SELECT_SATA_MASK BIT(1)
7ebdb52e LJ	33	#define SYSCFG_SELECT_SATA_POS 1
6e877fed LJ	34
	35	/* MiPHY365x register definitions */
	36	#define RESET_REG 0x00
	37	#define RST_PLL BIT(1)
	38	#define RST_PLL_CAL BIT(2)
	39	#define RST_RX BIT(4)
	40	#define RST_MACRO BIT(7)
	41
	42	#define STATUS_REG 0x01
	43	#define IDLL_RDY BIT(0)
	44	#define PLL_RDY BIT(1)
	45	#define DES_BIT_LOCK BIT(2)
	46	#define DES_SYMBOL_LOCK BIT(3)
	47
	48	#define CTRL_REG 0x02
	49	#define TERM_EN BIT(0)
	50	#define PCI_EN BIT(2)
	51	#define DES_BIT_LOCK_EN BIT(3)
	52	#define TX_POL BIT(5)
	53
	54	#define INT_CTRL_REG 0x03
	55
	56	#define BOUNDARY1_REG 0x10
	57	#define SPDSEL_SEL BIT(0)
	58
	59	#define BOUNDARY3_REG 0x12
	60	#define TX_SPDSEL_GEN1_VAL 0
	61	#define TX_SPDSEL_GEN2_VAL 0x01
	62	#define TX_SPDSEL_GEN3_VAL 0x02
	63	#define RX_SPDSEL_GEN1_VAL 0
	64	#define RX_SPDSEL_GEN2_VAL (0x01 << 3)
	65	#define RX_SPDSEL_GEN3_VAL (0x02 << 3)
	66
	67	#define PCIE_REG 0x16
	68
	69	#define BUF_SEL_REG 0x20
	70	#define CONF_GEN_SEL_GEN3 0x02
	71	#define CONF_GEN_SEL_GEN2 0x01
	72	#define PD_VDDTFILTER BIT(4)
	73
	74	#define TXBUF1_REG 0x21
	75	#define SWING_VAL 0x04
	76	#define SWING_VAL_GEN1 0x03
	77	#define PREEMPH_VAL (0x3 << 5)
	78
	79	#define TXBUF2_REG 0x22
	80	#define TXSLEW_VAL 0x2
	81	#define TXSLEW_VAL_GEN1 0x4
	82
	83	#define RXBUF_OFFSET_CTRL_REG 0x23
	84
	85	#define RXBUF_REG 0x25
	86	#define SDTHRES_VAL 0x01
	87	#define EQ_ON3 (0x03 << 4)
	88	#define EQ_ON1 (0x01 << 4)
	89
	90	#define COMP_CTRL1_REG 0x40
	91	#define START_COMSR BIT(0)
	92	#define START_COMZC BIT(1)
	93	#define COMSR_DONE BIT(2)
	94	#define COMZC_DONE BIT(3)
	95	#define COMP_AUTO_LOAD BIT(4)
	96
	97	#define COMP_CTRL2_REG 0x41
98	#define COMP_2MHZ_RAT_GEN1 0x1e
99	#define COMP_2MHZ_RAT 0xf
100
101	#define COMP_CTRL3_REG 0x42
102	#define COMSR_COMP_REF 0x33
103
104	#define COMP_IDLL_REG 0x47
105	#define COMZC_IDLL 0x2a
106
107	#define PLL_CTRL1_REG 0x50
108	#define PLL_START_CAL BIT(0)
109	#define BUF_EN BIT(2)
110	#define SYNCHRO_TX BIT(3)
111	#define SSC_EN BIT(6)
112	#define CONFIG_PLL BIT(7)
113
114	#define PLL_CTRL2_REG 0x51
115	#define BYPASS_PLL_CAL BIT(1)
116
117	#define PLL_RAT_REG 0x52
118
119	#define PLL_SSC_STEP_MSB_REG 0x56
120	#define PLL_SSC_STEP_MSB_VAL 0x03
121
122	#define PLL_SSC_STEP_LSB_REG 0x57
123	#define PLL_SSC_STEP_LSB_VAL 0x63
124
125	#define PLL_SSC_PER_MSB_REG 0x58
126	#define PLL_SSC_PER_MSB_VAL 0
127
128	#define PLL_SSC_PER_LSB_REG 0x59
129	#define PLL_SSC_PER_LSB_VAL 0xf1
130
131	#define IDLL_TEST_REG 0x72
132	#define START_CLK_HF BIT(6)
133
134	#define DES_BITLOCK_REG 0x86
135	#define BIT_LOCK_LEVEL 0x01
136	#define BIT_LOCK_CNT_512 (0x03 << 5)
137
6e877fed LJ	138	struct miphy365x_phy {
	139	struct phy *phy;
	140	void __iomem *base;
7ebdb52e LJ	141	bool pcie_tx_pol_inv;
	142	bool sata_tx_pol_inv;
	143	u32 sata_gen;
63139885	144	u32 ctrlreg;
6e877fed	145	u8 type;
6e877fed LJ	146	};
	147
	148	struct miphy365x_dev {
	149	struct device *dev;
	150	struct regmap *regmap;
	151	struct mutex miphy_mutex;
7ebdb52e	152	struct miphy365x_phy **phys;
5bd568f5	153	int nphys;
6e877fed LJ	154	};
	155
	156	/*
	157	* These values are represented in Device tree. They are considered to be ABI
	158	* and although they can be extended any existing values must not change.
	159	*/
	160	enum miphy_sata_gen {
	161	SATA_GEN1 = 1,
	162	SATA_GEN2,
	163	SATA_GEN3
	164	};
	165
	166	static u8 rx_tx_spd[] = {
a6cc1b94	167	0, /* GEN0 doesn't exist. */
6e877fed LJ	168	TX_SPDSEL_GEN1_VAL \| RX_SPDSEL_GEN1_VAL,
	169	TX_SPDSEL_GEN2_VAL \| RX_SPDSEL_GEN2_VAL,
	170	TX_SPDSEL_GEN3_VAL \| RX_SPDSEL_GEN3_VAL
	171	};
	172
	173	/*
	174	* This function selects the system configuration,
	175	* either two SATA, one SATA and one PCIe, or two PCIe lanes.
	176	*/
	177	static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
	178	struct miphy365x_dev *miphy_dev)
	179	{
fbea230e	180	bool sata = (miphy_phy->type == PHY_TYPE_SATA);
6e877fed	181
7ebdb52e	182	return regmap_update_bits(miphy_dev->regmap,
63139885	183	miphy_phy->ctrlreg,
7ebdb52e LJ	184	SYSCFG_SELECT_SATA_MASK,
7ebdb52e LJ	185	sata << SYSCFG_SELECT_SATA_POS);
6e877fed LJ	186	}
	187
	188	static int miphy365x_init_pcie_port(struct miphy365x_phy *miphy_phy,
	189	struct miphy365x_dev *miphy_dev)
	190	{
	191	u8 val;
	192
	193	if (miphy_phy->pcie_tx_pol_inv) {
	194	/* Invert Tx polarity and clear pci_txdetect_pol bit */
	195	val = TERM_EN \| PCI_EN \| DES_BIT_LOCK_EN \| TX_POL;
	196	writeb_relaxed(val, miphy_phy->base + CTRL_REG);
	197	writeb_relaxed(0x00, miphy_phy->base + PCIE_REG);
	198	}
	199
	200	return 0;
	201	}
	202
	203	static inline int miphy365x_hfc_not_rdy(struct miphy365x_phy *miphy_phy,
	204	struct miphy365x_dev *miphy_dev)
	205	{
	206	unsigned long timeout = jiffies + msecs_to_jiffies(HFC_TIMEOUT);
	207	u8 mask = IDLL_RDY \| PLL_RDY;
	208	u8 regval;
	209
	210	do {
	211	regval = readb_relaxed(miphy_phy->base + STATUS_REG);
	212	if (!(regval & mask))
	213	return 0;
	214
	215	usleep_range(2000, 2500);
	216	} while (time_before(jiffies, timeout));
	217
	218	dev_err(miphy_dev->dev, "HFC ready timeout!\n");
	219	return -EBUSY;
	220	}
	221
	222	static inline int miphy365x_rdy(struct miphy365x_phy *miphy_phy,
	223	struct miphy365x_dev *miphy_dev)
	224	{
	225	unsigned long timeout = jiffies + msecs_to_jiffies(HFC_TIMEOUT);
	226	u8 mask = IDLL_RDY \| PLL_RDY;
	227	u8 regval;
	228
	229	do {
	230	regval = readb_relaxed(miphy_phy->base + STATUS_REG);
	231	if ((regval & mask) == mask)
	232	return 0;
	233
	234	usleep_range(2000, 2500);
	235	} while (time_before(jiffies, timeout));
	236
	237	dev_err(miphy_dev->dev, "PHY not ready timeout!\n");
	238	return -EBUSY;
	239	}
	240
	241	static inline void miphy365x_set_comp(struct miphy365x_phy *miphy_phy,
	242	struct miphy365x_dev *miphy_dev)
	243	{
	244	u8 val, mask;
	245
7ebdb52e	246	if (miphy_phy->sata_gen == SATA_GEN1)
6e877fed LJ	247	writeb_relaxed(COMP_2MHZ_RAT_GEN1,
	248	miphy_phy->base + COMP_CTRL2_REG);
	249	else
	250	writeb_relaxed(COMP_2MHZ_RAT,
	251	miphy_phy->base + COMP_CTRL2_REG);
	252
7ebdb52e	253	if (miphy_phy->sata_gen != SATA_GEN3) {
6e877fed LJ	254	writeb_relaxed(COMSR_COMP_REF,
	255	miphy_phy->base + COMP_CTRL3_REG);
	256	/*
	257	* Force VCO current to value defined by address 0x5A
	258	* and disable PCIe100Mref bit
	259	* Enable auto load compensation for pll_i_bias
	260	*/
	261	writeb_relaxed(BYPASS_PLL_CAL, miphy_phy->base + PLL_CTRL2_REG);
	262	writeb_relaxed(COMZC_IDLL, miphy_phy->base + COMP_IDLL_REG);
	263	}
	264
	265	/*
	266	* Force restart compensation and enable auto load
	267	* for Comzc_Tx, Comzc_Rx and Comsr on macro
	268	*/
	269	val = START_COMSR \| START_COMZC \| COMP_AUTO_LOAD;
	270	writeb_relaxed(val, miphy_phy->base + COMP_CTRL1_REG);
	271
	272	mask = COMSR_DONE \| COMZC_DONE;
	273	while ((readb_relaxed(miphy_phy->base + COMP_CTRL1_REG) & mask) != mask)
	274	cpu_relax();
	275	}
	276
	277	static inline void miphy365x_set_ssc(struct miphy365x_phy *miphy_phy,
	278	struct miphy365x_dev *miphy_dev)
	279	{
	280	u8 val;
	281
	282	/*
	283	* SSC Settings. SSC will be enabled through Link
	284	* SSC Ampl. = 0.4%
	285	* SSC Freq = 31KHz
	286	*/
	287	writeb_relaxed(PLL_SSC_STEP_MSB_VAL,
	288	miphy_phy->base + PLL_SSC_STEP_MSB_REG);
	289	writeb_relaxed(PLL_SSC_STEP_LSB_VAL,
	290	miphy_phy->base + PLL_SSC_STEP_LSB_REG);
	291	writeb_relaxed(PLL_SSC_PER_MSB_VAL,
	292	miphy_phy->base + PLL_SSC_PER_MSB_REG);
	293	writeb_relaxed(PLL_SSC_PER_LSB_VAL,
	294	miphy_phy->base + PLL_SSC_PER_LSB_REG);
	295
	296	/* SSC Settings complete */
7ebdb52e	297	if (miphy_phy->sata_gen == SATA_GEN1) {
6e877fed LJ	298	val = PLL_START_CAL \| BUF_EN \| SYNCHRO_TX \| CONFIG_PLL;
	299	writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
	300	} else {
	301	val = SSC_EN \| PLL_START_CAL \| BUF_EN \| SYNCHRO_TX \| CONFIG_PLL;
	302	writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
	303	}
	304	}
	305
	306	static int miphy365x_init_sata_port(struct miphy365x_phy *miphy_phy,
	307	struct miphy365x_dev *miphy_dev)
	308	{
	309	int ret;
	310	u8 val;
	311
	312	/*
	313	* Force PHY macro reset, PLL calibration reset, PLL reset
	314	* and assert Deserializer Reset
	315	*/
	316	val = RST_PLL \| RST_PLL_CAL \| RST_RX \| RST_MACRO;
	317	writeb_relaxed(val, miphy_phy->base + RESET_REG);
	318
7ebdb52e	319	if (miphy_phy->sata_tx_pol_inv)
6e877fed LJ	320	writeb_relaxed(TX_POL, miphy_phy->base + CTRL_REG);
	321
	322	/*
	323	* Force macro1 to use rx_lspd, tx_lspd
	324	* Force Rx_Clock on first I-DLL phase
	325	* Force Des in HP mode on macro, rx_lspd, tx_lspd for Gen2/3
	326	*/
	327	writeb_relaxed(SPDSEL_SEL, miphy_phy->base + BOUNDARY1_REG);
	328	writeb_relaxed(START_CLK_HF, miphy_phy->base + IDLL_TEST_REG);
7ebdb52e	329	val = rx_tx_spd[miphy_phy->sata_gen];
6e877fed LJ	330	writeb_relaxed(val, miphy_phy->base + BOUNDARY3_REG);
	331
	332	/* Wait for HFC_READY = 0 */
	333	ret = miphy365x_hfc_not_rdy(miphy_phy, miphy_dev);
	334	if (ret)
	335	return ret;
	336
	337	/* Compensation Recalibration */
	338	miphy365x_set_comp(miphy_phy, miphy_dev);
	339
7ebdb52e	340	switch (miphy_phy->sata_gen) {
6e877fed LJ	341	case SATA_GEN3:
	342	/*
	343	* TX Swing target 550-600mv peak to peak diff
	344	* Tx Slew target 90-110ps rising/falling time
	345	* Rx Eq ON3, Sigdet threshold SDTH1
	346	*/
	347	val = PD_VDDTFILTER \| CONF_GEN_SEL_GEN3;
	348	writeb_relaxed(val, miphy_phy->base + BUF_SEL_REG);
	349	val = SWING_VAL \| PREEMPH_VAL;
	350	writeb_relaxed(val, miphy_phy->base + TXBUF1_REG);
	351	writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
	352	writeb_relaxed(0x00, miphy_phy->base + RXBUF_OFFSET_CTRL_REG);
	353	val = SDTHRES_VAL \| EQ_ON3;
	354	writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
	355	break;
	356	case SATA_GEN2:
	357	/*
	358	* conf gen sel=0x1 to program Gen2 banked registers
	359	* VDDT filter ON
	360	* Tx Swing target 550-600mV peak-to-peak diff
	361	* Tx Slew target 90-110 ps rising/falling time
	362	* RX Equalization ON1, Sigdet threshold SDTH1
	363	*/
	364	writeb_relaxed(CONF_GEN_SEL_GEN2,
	365	miphy_phy->base + BUF_SEL_REG);
	366	writeb_relaxed(SWING_VAL, miphy_phy->base + TXBUF1_REG);
	367	writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
	368	val = SDTHRES_VAL \| EQ_ON1;
	369	writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
	370	break;
	371	case SATA_GEN1:
	372	/*
	373	* conf gen sel = 00b to program Gen1 banked registers
	374	* VDDT filter ON
	375	* Tx Swing target 500-550mV peak-to-peak diff
	376	* Tx Slew target120-140 ps rising/falling time
	377	*/
	378	writeb_relaxed(PD_VDDTFILTER, miphy_phy->base + BUF_SEL_REG);
	379	writeb_relaxed(SWING_VAL_GEN1, miphy_phy->base + TXBUF1_REG);
	380	writeb_relaxed(TXSLEW_VAL_GEN1, miphy_phy->base + TXBUF2_REG);
	381	break;
	382	default:
	383	break;
	384	}
	385
	386	/* Force Macro1 in partial mode & release pll cal reset */
	387	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
	388	usleep_range(100, 150);
	389
	390	miphy365x_set_ssc(miphy_phy, miphy_dev);
	391
	392	/* Wait for phy_ready */
	393	ret = miphy365x_rdy(miphy_phy, miphy_dev);
	394	if (ret)
	395	return ret;
	396
	397	/*
	398	* Enable macro1 to use rx_lspd & tx_lspd
	399	* Release Rx_Clock on first I-DLL phase on macro1
	400	* Assert deserializer reset
	401	* des_bit_lock_en is set
	402	* bit lock detection strength
	403	* Deassert deserializer reset
	404	*/
405	writeb_relaxed(0x00, miphy_phy->base + BOUNDARY1_REG);
406	writeb_relaxed(0x00, miphy_phy->base + IDLL_TEST_REG);
407	writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
7ebdb52e	408	val = miphy_phy->sata_tx_pol_inv ?
6e877fed LJ	409	(TX_POL \| DES_BIT_LOCK_EN) : DES_BIT_LOCK_EN;
	410	writeb_relaxed(val, miphy_phy->base + CTRL_REG);
	411
	412	val = BIT_LOCK_CNT_512 \| BIT_LOCK_LEVEL;
	413	writeb_relaxed(val, miphy_phy->base + DES_BITLOCK_REG);
	414	writeb_relaxed(0x00, miphy_phy->base + RESET_REG);
	415
	416	return 0;
	417	}
	418
	419	static int miphy365x_init(struct phy *phy)
	420	{
	421	struct miphy365x_phy *miphy_phy = phy_get_drvdata(phy);
	422	struct miphy365x_dev *miphy_dev = dev_get_drvdata(phy->dev.parent);
	423	int ret = 0;
	424
	425	mutex_lock(&miphy_dev->miphy_mutex);
	426
	427	ret = miphy365x_set_path(miphy_phy, miphy_dev);
	428	if (ret) {
	429	mutex_unlock(&miphy_dev->miphy_mutex);
	430	return ret;
	431	}
	432
	433	/* Initialise Miphy for PCIe or SATA */
fbea230e	434	if (miphy_phy->type == PHY_TYPE_PCIE)
6e877fed LJ	435	ret = miphy365x_init_pcie_port(miphy_phy, miphy_dev);
	436	else
	437	ret = miphy365x_init_sata_port(miphy_phy, miphy_dev);
	438
	439	mutex_unlock(&miphy_dev->miphy_mutex);
	440
	441	return ret;
	442	}
	443
5bea4968 FB	444	static int miphy365x_get_addr(struct device *dev,
5bea4968 FB	445	struct miphy365x_phy *miphy_phy, int index)
7ebdb52e LJ	446	{
	447	struct device_node *phynode = miphy_phy->phy->dev.of_node;
	448	const char *name;
7ebdb52e LJ	449	int type = miphy_phy->type;
	450	int ret;
	451
	452	ret = of_property_read_string_index(phynode, "reg-names", index, &name);
	453	if (ret) {
	454	dev_err(dev, "no reg-names property not found\n");
	455	return ret;
	456	}
	457
fbea230e PG	458	if (!((!strncmp(name, "sata", 4) && type == PHY_TYPE_SATA) \|\|
fbea230e PG	459	(!strncmp(name, "pcie", 4) && type == PHY_TYPE_PCIE)))
7ebdb52e LJ	460	return 0;
	461
	462	miphy_phy->base = of_iomap(phynode, index);
	463	if (!miphy_phy->base) {
	464	dev_err(dev, "Failed to map %s\n", phynode->full_name);
	465	return -EINVAL;
	466	}
	467
	468	return 0;
	469	}
	470
6e877fed LJ	471	static struct phy miphy365x_xlate(struct device dev,
	472	struct of_phandle_args *args)
	473	{
7ebdb52e LJ	474	struct miphy365x_dev *miphy_dev = dev_get_drvdata(dev);
	475	struct miphy365x_phy *miphy_phy = NULL;
	476	struct device_node *phynode = args->np;
	477	int ret, index;
	478
7ebdb52e	479	if (args->args_count != 1) {
6e877fed LJ	480	dev_err(dev, "Invalid number of cells in 'phy' property\n");
	481	return ERR_PTR(-EINVAL);
	482	}
	483
5bd568f5	484	for (index = 0; index < miphy_dev->nphys; index++)
7ebdb52e LJ	485	if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {
	486	miphy_phy = miphy_dev->phys[index];
	487	break;
	488	}
	489
	490	if (!miphy_phy) {
	491	dev_err(dev, "Failed to find appropriate phy\n");
6e877fed LJ	492	return ERR_PTR(-EINVAL);
	493	}
	494
7ebdb52e	495	miphy_phy->type = args->args[0];
6e877fed	496
fbea230e PG	497	if (!(miphy_phy->type == PHY_TYPE_SATA \|\|
fbea230e PG	498	miphy_phy->type == PHY_TYPE_PCIE)) {
7ebdb52e	499	dev_err(dev, "Unsupported device type: %d\n", miphy_phy->type);
6e877fed LJ	500	return ERR_PTR(-EINVAL);
	501	}
	502
7ebdb52e LJ	503	/* Each port handles SATA and PCIE - third entry is always sysconf. */
	504	for (index = 0; index < 3; index++) {
	505	ret = miphy365x_get_addr(dev, miphy_phy, index);
	506	if (ret < 0)
	507	return ERR_PTR(ret);
	508	}
6e877fed	509
7ebdb52e	510	return miphy_phy->phy;
6e877fed LJ	511	}
6e877fed LJ	512
4a9e5ca1	513	static const struct phy_ops miphy365x_ops = {
6e877fed LJ	514	.init = miphy365x_init,
	515	.owner = THIS_MODULE,
	516	};
	517
7ebdb52e LJ	518	static int miphy365x_of_probe(struct device_node *phynode,
7ebdb52e LJ	519	struct miphy365x_phy *miphy_phy)
6e877fed	520	{
7ebdb52e LJ	521	of_property_read_u32(phynode, "st,sata-gen", &miphy_phy->sata_gen);
	522	if (!miphy_phy->sata_gen)
	523	miphy_phy->sata_gen = SATA_GEN1;
6e877fed	524
7ebdb52e LJ	525	miphy_phy->pcie_tx_pol_inv =
7ebdb52e LJ	526	of_property_read_bool(phynode, "st,pcie-tx-pol-inv");
6e877fed	527
7ebdb52e LJ	528	miphy_phy->sata_tx_pol_inv =
7ebdb52e LJ	529	of_property_read_bool(phynode, "st,sata-tx-pol-inv");
6e877fed LJ	530
	531	return 0;
	532	}
	533
	534	static int miphy365x_probe(struct platform_device *pdev)
	535	{
7ebdb52e LJ	536	struct device_node child, np = pdev->dev.of_node;
7ebdb52e LJ	537	struct miphy365x_dev *miphy_dev;
6e877fed	538	struct phy_provider *provider;
7ebdb52e	539	struct phy *phy;
5bd568f5	540	int ret, port = 0;
6e877fed	541
7ebdb52e LJ	542	miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
7ebdb52e LJ	543	if (!miphy_dev)
6e877fed LJ	544	return -ENOMEM;
6e877fed LJ	545
5bd568f5	546	miphy_dev->nphys = of_get_child_count(np);
d8d52948 AL	547	miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys,
d8d52948 AL	548	sizeof(*miphy_dev->phys), GFP_KERNEL);
7ebdb52e LJ	549	if (!miphy_dev->phys)
	550	return -ENOMEM;
	551
	552	miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
	553	if (IS_ERR(miphy_dev->regmap)) {
	554	dev_err(miphy_dev->dev, "No syscfg phandle specified\n");
	555	return PTR_ERR(miphy_dev->regmap);
	556	}
	557
	558	miphy_dev->dev = &pdev->dev;
	559
	560	dev_set_drvdata(&pdev->dev, miphy_dev);
6e877fed	561
7ebdb52e	562	mutex_init(&miphy_dev->miphy_mutex);
6e877fed	563
7ebdb52e LJ	564	for_each_child_of_node(np, child) {
7ebdb52e LJ	565	struct miphy365x_phy *miphy_phy;
6e877fed	566
7ebdb52e LJ	567	miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
7ebdb52e LJ	568	GFP_KERNEL);
39c2b964 JL	569	if (!miphy_phy) {
	570	ret = -ENOMEM;
	571	goto put_child;
	572	}
6e877fed	573
7ebdb52e	574	miphy_dev->phys[port] = miphy_phy;
6e877fed	575
dbc98635	576	phy = devm_phy_create(&pdev->dev, child, &miphy365x_ops);
6e877fed	577	if (IS_ERR(phy)) {
7ebdb52e	578	dev_err(&pdev->dev, "failed to create PHY\n");
39c2b964 JL	579	ret = PTR_ERR(phy);
39c2b964 JL	580	goto put_child;
6e877fed LJ	581	}
6e877fed LJ	582
7ebdb52e	583	miphy_dev->phys[port]->phy = phy;
6e877fed	584
7ebdb52e	585	ret = miphy365x_of_probe(child, miphy_phy);
6e877fed	586	if (ret)
39c2b964	587	goto put_child;
6e877fed	588
7ebdb52e	589	phy_set_drvdata(phy, miphy_dev->phys[port]);
63139885	590
7ebdb52e	591	port++;
63139885 PG	592	/* sysconfig offsets are indexed from 1 */
	593	ret = of_property_read_u32_index(np, "st,syscfg", port,
	594	&miphy_phy->ctrlreg);
	595	if (ret) {
	596	dev_err(&pdev->dev, "No sysconfig offset found\n");
39c2b964	597	goto put_child;
63139885	598	}
6e877fed LJ	599	}
6e877fed LJ	600
7ebdb52e	601	provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
c1fc0050	602	return PTR_ERR_OR_ZERO(provider);
39c2b964 JL	603	put_child:
	604	of_node_put(child);
	605	return ret;
6e877fed LJ	606	}
	607
	608	static const struct of_device_id miphy365x_of_match[] = {
	609	{ .compatible = "st,miphy365x-phy", },
	610	{ },
	611	};
	612	MODULE_DEVICE_TABLE(of, miphy365x_of_match);
	613
	614	static struct platform_driver miphy365x_driver = {
	615	.probe = miphy365x_probe,
	616	.driver = {
	617	.name = "miphy365x-phy",
6e877fed LJ	618	.of_match_table = miphy365x_of_match,
	619	}
	620	};
	621	module_platform_driver(miphy365x_driver);
	622
	623	MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
	624	MODULE_DESCRIPTION("STMicroelectronics miphy365x driver");
	625	MODULE_LICENSE("GPL v2");