[linux-2.6-block.git] / drivers / phy / phy-exynos-mipi-video.c

/*
 * Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
 *
 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon/exynos4-pmu.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/spinlock.h>
#include <linux/mfd/syscon.h>

/* MIPI_PHYn_CONTROL reg. offset (for base address from ioremap): n = 0..1 */
#define EXYNOS_MIPI_PHY_CONTROL(n)	((n) * 4)

enum exynos_mipi_phy_id {
	EXYNOS_MIPI_PHY_ID_CSIS0,
	EXYNOS_MIPI_PHY_ID_DSIM0,
	EXYNOS_MIPI_PHY_ID_CSIS1,
	EXYNOS_MIPI_PHY_ID_DSIM1,
	EXYNOS_MIPI_PHYS_NUM
};

#define is_mipi_dsim_phy_id(id) \
	((id) == EXYNOS_MIPI_PHY_ID_DSIM0 || (id) == EXYNOS_MIPI_PHY_ID_DSIM1)

struct exynos_mipi_video_phy {
	struct video_phy_desc {
		struct phy *phy;
		unsigned int index;
	} phys[EXYNOS_MIPI_PHYS_NUM];
	spinlock_t slock;
	void __iomem *regs;
	struct mutex mutex;
	struct regmap *regmap;
};

static int __set_phy_state(struct exynos_mipi_video_phy *state,
			enum exynos_mipi_phy_id id, unsigned int on)
{
	const unsigned int offset = EXYNOS4_MIPI_PHY_CONTROL(id / 2);
	void __iomem *addr;
	u32 val, reset;

	if (is_mipi_dsim_phy_id(id))
		reset = EXYNOS4_MIPI_PHY_MRESETN;
	else
		reset = EXYNOS4_MIPI_PHY_SRESETN;

	if (state->regmap) {
		mutex_lock(&state->mutex);
		regmap_read(state->regmap, offset, &val);
		if (on)
			val |= reset;
		else
			val &= ~reset;
		regmap_write(state->regmap, offset, val);
		if (on)
			val |= EXYNOS4_MIPI_PHY_ENABLE;
		else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK))
			val &= ~EXYNOS4_MIPI_PHY_ENABLE;
		regmap_write(state->regmap, offset, val);
		mutex_unlock(&state->mutex);
	} else {
		addr = state->regs + EXYNOS_MIPI_PHY_CONTROL(id / 2);

		spin_lock(&state->slock);
		val = readl(addr);
		if (on)
			val |= reset;
		else
			val &= ~reset;
		writel(val, addr);
		/* Clear ENABLE bit only if MRESETN, SRESETN bits are not set */
		if (on)
			val |= EXYNOS4_MIPI_PHY_ENABLE;
		else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK))
			val &= ~EXYNOS4_MIPI_PHY_ENABLE;

		writel(val, addr);
		spin_unlock(&state->slock);
	}

	return 0;
}

#define to_mipi_video_phy(desc) \
	container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index]);

static int exynos_mipi_video_phy_power_on(struct phy *phy)
{
	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);

	return __set_phy_state(state, phy_desc->index, 1);
}

static int exynos_mipi_video_phy_power_off(struct phy *phy)
{
	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);

	return __set_phy_state(state, phy_desc->index, 0);
}

static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
					struct of_phandle_args *args)
{
	struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);

	if (WARN_ON(args->args[0] >= EXYNOS_MIPI_PHYS_NUM))
		return ERR_PTR(-ENODEV);

	return state->phys[args->args[0]].phy;
}

static struct phy_ops exynos_mipi_video_phy_ops = {
	.power_on	= exynos_mipi_video_phy_power_on,
	.power_off	= exynos_mipi_video_phy_power_off,
	.owner		= THIS_MODULE,
};

static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
{
	struct exynos_mipi_video_phy *state;
	struct device *dev = &pdev->dev;
	struct phy_provider *phy_provider;
	unsigned int i;

	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
	if (!state)
		return -ENOMEM;

	state->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
	if (IS_ERR(state->regmap)) {
		struct resource *res;

		dev_info(dev, "regmap lookup failed: %ld\n",
			 PTR_ERR(state->regmap));

		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		state->regs = devm_ioremap_resource(dev, res);
		if (IS_ERR(state->regs))
			return PTR_ERR(state->regs);
	}

	dev_set_drvdata(dev, state);
	spin_lock_init(&state->slock);
	mutex_init(&state->mutex);

	for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) {
		struct phy *phy = devm_phy_create(dev, NULL,
						  &exynos_mipi_video_phy_ops);
		if (IS_ERR(phy)) {
			dev_err(dev, "failed to create PHY %d\n", i);
			return PTR_ERR(phy);
		}

		state->phys[i].phy = phy;
		state->phys[i].index = i;
		phy_set_drvdata(phy, &state->phys[i]);
	}

	phy_provider = devm_of_phy_provider_register(dev,
					exynos_mipi_video_phy_xlate);

	return PTR_ERR_OR_ZERO(phy_provider);
}

static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
	{ .compatible = "samsung,s5pv210-mipi-video-phy" },
	{ },
};
MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);

static struct platform_driver exynos_mipi_video_phy_driver = {
	.probe	= exynos_mipi_video_phy_probe,
	.driver = {
		.of_match_table	= exynos_mipi_video_phy_of_match,
		.name  = "exynos-mipi-video-phy",
	}
};
module_platform_driver(exynos_mipi_video_phy_driver);

MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver");
MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
069d2e26 SN	1	/*
	2	* Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
	3	*
	4	* Copyright (C) 2013 Samsung Electronics Co., Ltd.
	5	* Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
22fda307	12	#include <linux/err.h>
069d2e26 SN	13	#include <linux/io.h>
069d2e26 SN	14	#include <linux/kernel.h>
e4b3d380	15	#include <linux/mfd/syscon/exynos4-pmu.h>
069d2e26 SN	16	#include <linux/module.h>
	17	#include <linux/of.h>
	18	#include <linux/of_address.h>
	19	#include <linux/phy/phy.h>
	20	#include <linux/platform_device.h>
e4b3d380	21	#include <linux/regmap.h>
069d2e26	22	#include <linux/spinlock.h>
e4b3d380	23	#include <linux/mfd/syscon.h>
069d2e26	24
e4b3d380	25	/* MIPI_PHYn_CONTROL reg. offset (for base address from ioremap): n = 0..1 */
069d2e26	26	#define EXYNOS_MIPI_PHY_CONTROL(n) ((n) * 4)
069d2e26 SN	27
	28	enum exynos_mipi_phy_id {
	29	EXYNOS_MIPI_PHY_ID_CSIS0,
	30	EXYNOS_MIPI_PHY_ID_DSIM0,
	31	EXYNOS_MIPI_PHY_ID_CSIS1,
	32	EXYNOS_MIPI_PHY_ID_DSIM1,
	33	EXYNOS_MIPI_PHYS_NUM
	34	};
	35
	36	#define is_mipi_dsim_phy_id(id) \
	37	((id) == EXYNOS_MIPI_PHY_ID_DSIM0 \|\| (id) == EXYNOS_MIPI_PHY_ID_DSIM1)
	38
	39	struct exynos_mipi_video_phy {
069d2e26 SN	40	struct video_phy_desc {
	41	struct phy *phy;
	42	unsigned int index;
	43	} phys[EXYNOS_MIPI_PHYS_NUM];
e4b3d380	44	spinlock_t slock;
069d2e26	45	void __iomem *regs;
e4b3d380 SN	46	struct mutex mutex;
e4b3d380 SN	47	struct regmap *regmap;
069d2e26 SN	48	};
	49
	50	static int __set_phy_state(struct exynos_mipi_video_phy *state,
	51	enum exynos_mipi_phy_id id, unsigned int on)
	52	{
e4b3d380	53	const unsigned int offset = EXYNOS4_MIPI_PHY_CONTROL(id / 2);
069d2e26	54	void __iomem *addr;
e4b3d380	55	u32 val, reset;
069d2e26 SN	56
069d2e26 SN	57	if (is_mipi_dsim_phy_id(id))
e4b3d380	58	reset = EXYNOS4_MIPI_PHY_MRESETN;
069d2e26	59	else
e4b3d380 SN	60	reset = EXYNOS4_MIPI_PHY_SRESETN;
	61
	62	if (state->regmap) {
	63	mutex_lock(&state->mutex);
	64	regmap_read(state->regmap, offset, &val);
	65	if (on)
	66	val \|= reset;
	67	else
	68	val &= ~reset;
	69	regmap_write(state->regmap, offset, val);
	70	if (on)
	71	val \|= EXYNOS4_MIPI_PHY_ENABLE;
	72	else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK))
	73	val &= ~EXYNOS4_MIPI_PHY_ENABLE;
	74	regmap_write(state->regmap, offset, val);
	75	mutex_unlock(&state->mutex);
	76	} else {
	77	addr = state->regs + EXYNOS_MIPI_PHY_CONTROL(id / 2);
	78
	79	spin_lock(&state->slock);
	80	val = readl(addr);
	81	if (on)
	82	val \|= reset;
	83	else
	84	val &= ~reset;
	85	writel(val, addr);
	86	/* Clear ENABLE bit only if MRESETN, SRESETN bits are not set */
	87	if (on)
	88	val \|= EXYNOS4_MIPI_PHY_ENABLE;
	89	else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK))
	90	val &= ~EXYNOS4_MIPI_PHY_ENABLE;
	91
	92	writel(val, addr);
	93	spin_unlock(&state->slock);
	94	}
069d2e26	95
069d2e26 SN	96	return 0;
	97	}
	98
	99	#define to_mipi_video_phy(desc) \
	100	container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index]);
	101
	102	static int exynos_mipi_video_phy_power_on(struct phy *phy)
	103	{
	104	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
	105	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
	106
	107	return __set_phy_state(state, phy_desc->index, 1);
	108	}
	109
	110	static int exynos_mipi_video_phy_power_off(struct phy *phy)
	111	{
	112	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
	113	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
	114
e3967e7b	115	return __set_phy_state(state, phy_desc->index, 0);
069d2e26 SN	116	}
	117
	118	static struct phy exynos_mipi_video_phy_xlate(struct device dev,
	119	struct of_phandle_args *args)
	120	{
	121	struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
	122
98c3b322	123	if (WARN_ON(args->args[0] >= EXYNOS_MIPI_PHYS_NUM))
069d2e26 SN	124	return ERR_PTR(-ENODEV);
	125
	126	return state->phys[args->args[0]].phy;
	127	}
	128
	129	static struct phy_ops exynos_mipi_video_phy_ops = {
	130	.power_on = exynos_mipi_video_phy_power_on,
	131	.power_off = exynos_mipi_video_phy_power_off,
	132	.owner = THIS_MODULE,
	133	};
	134
	135	static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
	136	{
	137	struct exynos_mipi_video_phy *state;
	138	struct device *dev = &pdev->dev;
069d2e26 SN	139	struct phy_provider *phy_provider;
	140	unsigned int i;
	141
	142	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
	143	if (!state)
	144	return -ENOMEM;
	145
e4b3d380 SN	146	state->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
	147	if (IS_ERR(state->regmap)) {
	148	struct resource *res;
	149
	150	dev_info(dev, "regmap lookup failed: %ld\n",
	151	PTR_ERR(state->regmap));
069d2e26	152
e4b3d380 SN	153	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	154	state->regs = devm_ioremap_resource(dev, res);
	155	if (IS_ERR(state->regs))
	156	return PTR_ERR(state->regs);
	157	}
069d2e26 SN	158
	159	dev_set_drvdata(dev, state);
	160	spin_lock_init(&state->slock);
e4b3d380	161	mutex_init(&state->mutex);
069d2e26	162
069d2e26	163	for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) {
f0ed8176	164	struct phy *phy = devm_phy_create(dev, NULL,
dbc98635	165	&exynos_mipi_video_phy_ops);
069d2e26 SN	166	if (IS_ERR(phy)) {
	167	dev_err(dev, "failed to create PHY %d\n", i);
	168	return PTR_ERR(phy);
	169	}
	170
	171	state->phys[i].phy = phy;
	172	state->phys[i].index = i;
	173	phy_set_drvdata(phy, &state->phys[i]);
	174	}
	175
64fe1891 KVA	176	phy_provider = devm_of_phy_provider_register(dev,
64fe1891 KVA	177	exynos_mipi_video_phy_xlate);
64fe1891	178
22fda307	179	return PTR_ERR_OR_ZERO(phy_provider);
069d2e26 SN	180	}
	181
	182	static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
	183	{ .compatible = "samsung,s5pv210-mipi-video-phy" },
	184	{ },
	185	};
	186	MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
	187
	188	static struct platform_driver exynos_mipi_video_phy_driver = {
	189	.probe = exynos_mipi_video_phy_probe,
	190	.driver = {
	191	.of_match_table = exynos_mipi_video_phy_of_match,
	192	.name = "exynos-mipi-video-phy",
069d2e26 SN	193	}
	194	};
	195	module_platform_driver(exynos_mipi_video_phy_driver);
	196
	197	MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver");
	198	MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
	199	MODULE_LICENSE("GPL v2");