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perf: Use device_show_string() helper for sysfs attributes
[linux-block.git] / drivers / perf / xgene_pmu.c
CommitLineData
1ccea77e 1// SPDX-License-Identifier: GPL-2.0-or-later
832c927d
TN		 2/*
3 * APM X-Gene SoC PMU (Performance Monitor Unit)
4 *
5 * Copyright (c) 2016, Applied Micro Circuits Corporation
6 * Author: Hoan Tran <hotran@apm.com>
7 * Tai Nguyen <ttnguyen@apm.com>
832c927d
TN		 8 */
9
10#include <linux/acpi.h>
11#include <linux/clk.h>
cbb72a3c 12#include <linux/cpuhotplug.h>
832c927d
TN		 13#include <linux/cpumask.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/mfd/syscon.h>
c0bfc549 17#include <linux/module.h>
832c927d 18#include <linux/of_address.h>
832c927d
TN		 19#include <linux/perf_event.h>
20#include <linux/platform_device.h>
1f33cdef 21#include <linux/property.h>
832c927d
TN		 22#include <linux/regmap.h>
23#include <linux/slab.h>
24
25#define CSW_CSWCR 0x0000
26#define CSW_CSWCR_DUALMCB_MASK BIT(0)
c0f7f7ac
HT		 27#define CSW_CSWCR_MCB0_ROUTING(x) (((x) & 0x0C) >> 2)
28#define CSW_CSWCR_MCB1_ROUTING(x) (((x) & 0x30) >> 4)
832c927d
TN		 29#define MCBADDRMR 0x0000
30#define MCBADDRMR_DUALMCU_MODE_MASK BIT(2)
31
32#define PCPPMU_INTSTATUS_REG 0x000
33#define PCPPMU_INTMASK_REG 0x004
34#define PCPPMU_INTMASK 0x0000000F
35#define PCPPMU_INTENMASK 0xFFFFFFFF
36#define PCPPMU_INTCLRMASK 0xFFFFFFF0
37#define PCPPMU_INT_MCU BIT(0)
38#define PCPPMU_INT_MCB BIT(1)
39#define PCPPMU_INT_L3C BIT(2)
40#define PCPPMU_INT_IOB BIT(3)
41
c0f7f7ac
HT		 42#define PCPPMU_V3_INTMASK 0x00FF33FF
43#define PCPPMU_V3_INTENMASK 0xFFFFFFFF
44#define PCPPMU_V3_INTCLRMASK 0xFF00CC00
45#define PCPPMU_V3_INT_MCU 0x000000FF
46#define PCPPMU_V3_INT_MCB 0x00000300
47#define PCPPMU_V3_INT_L3C 0x00FF0000
48#define PCPPMU_V3_INT_IOB 0x00003000
49
832c927d 50#define PMU_MAX_COUNTERS 4
c0f7f7ac
HT		 51#define PMU_CNT_MAX_PERIOD 0xFFFFFFFFULL
52#define PMU_V3_CNT_MAX_PERIOD 0xFFFFFFFFFFFFFFFFULL
832c927d
TN		 53#define PMU_OVERFLOW_MASK 0xF
54#define PMU_PMCR_E BIT(0)
55#define PMU_PMCR_P BIT(1)
56
57#define PMU_PMEVCNTR0 0x000
58#define PMU_PMEVCNTR1 0x004
59#define PMU_PMEVCNTR2 0x008
60#define PMU_PMEVCNTR3 0x00C
61#define PMU_PMEVTYPER0 0x400
62#define PMU_PMEVTYPER1 0x404
63#define PMU_PMEVTYPER2 0x408
64#define PMU_PMEVTYPER3 0x40C
65#define PMU_PMAMR0 0xA00
66#define PMU_PMAMR1 0xA04
67#define PMU_PMCNTENSET 0xC00
68#define PMU_PMCNTENCLR 0xC20
69#define PMU_PMINTENSET 0xC40
70#define PMU_PMINTENCLR 0xC60
71#define PMU_PMOVSR 0xC80
72#define PMU_PMCR 0xE04
73
c0f7f7ac
HT		 74/* PMU registers for V3 */
75#define PMU_PMOVSCLR 0xC80
76#define PMU_PMOVSSET 0xCC0
77
832c927d
TN		 78#define to_pmu_dev(p) container_of(p, struct xgene_pmu_dev, pmu)
79#define GET_CNTR(ev) (ev->hw.idx)
80#define GET_EVENTID(ev) (ev->hw.config & 0xFFULL)
81#define GET_AGENTID(ev) (ev->hw.config_base & 0xFFFFFFFFUL)
82#define GET_AGENT1ID(ev) ((ev->hw.config_base >> 32) & 0xFFFFFFFFUL)
83
84struct hw_pmu_info {
85 u32 type;
86 u32 enable_mask;
87 void __iomem *csr;
88};
89
90struct xgene_pmu_dev {
91 struct hw_pmu_info *inf;
92 struct xgene_pmu *parent;
93 struct pmu pmu;
94 u8 max_counters;
95 DECLARE_BITMAP(cntr_assign_mask, PMU_MAX_COUNTERS);
96 u64 max_period;
97 const struct attribute_group **attr_groups;
98 struct perf_event *pmu_counter_event[PMU_MAX_COUNTERS];
99};
100
e35e0a04
HT		 101struct xgene_pmu_ops {
102 void (*mask_int)(struct xgene_pmu *pmu);
103 void (*unmask_int)(struct xgene_pmu *pmu);
104 u64 (*read_counter)(struct xgene_pmu_dev *pmu, int idx);
105 void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val);
106 void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val);
107 void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val);
108 void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val);
109 void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
110 void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
111 void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
112 void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
113 void (*reset_counters)(struct xgene_pmu_dev *pmu_dev);
114 void (*start_counters)(struct xgene_pmu_dev *pmu_dev);
115 void (*stop_counters)(struct xgene_pmu_dev *pmu_dev);
116};
117
832c927d
TN		 118struct xgene_pmu {
119 struct device *dev;
cbb72a3c 120 struct hlist_node node;
832c927d
TN		 121 int version;
122 void __iomem *pcppmu_csr;
123 u32 mcb_active_mask;
124 u32 mc_active_mask;
c0f7f7ac 125 u32 l3c_active_mask;
832c927d 126 cpumask_t cpu;
cbb72a3c 127 int irq;
832c927d 128 raw_spinlock_t lock;
e35e0a04 129 const struct xgene_pmu_ops *ops;
832c927d
TN		 130 struct list_head l3cpmus;
131 struct list_head iobpmus;
132 struct list_head mcbpmus;
133 struct list_head mcpmus;
134};
135
136struct xgene_pmu_dev_ctx {
137 char *name;
138 struct list_head next;
139 struct xgene_pmu_dev *pmu_dev;
140 struct hw_pmu_info inf;
141};
142
143struct xgene_pmu_data {
144 int id;
145 u32 data;
146};
147
148enum xgene_pmu_version {
149 PCP_PMU_V1 = 1,
150 PCP_PMU_V2,
c0f7f7ac 151 PCP_PMU_V3,
832c927d
TN		 152};
153
154enum xgene_pmu_dev_type {
155 PMU_TYPE_L3C = 0,
156 PMU_TYPE_IOB,
c0f7f7ac 157 PMU_TYPE_IOB_SLOW,
832c927d
TN		 158 PMU_TYPE_MCB,
159 PMU_TYPE_MC,
160};
161
162/*
163 * sysfs format attributes
164 */
832c927d
TN		 165#define XGENE_PMU_FORMAT_ATTR(_name, _config) \
166 (&((struct dev_ext_attribute[]) { \
b91b73a4 167 { .attr = __ATTR(_name, S_IRUGO, device_show_string, NULL), \
832c927d
TN		 168 .var = (void *) _config, } \
169 })[0].attr.attr)
170
171static struct attribute *l3c_pmu_format_attrs[] = {
172 XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-7"),
173 XGENE_PMU_FORMAT_ATTR(l3c_agentid, "config1:0-9"),
174 NULL,
175};
176
177static struct attribute *iob_pmu_format_attrs[] = {
178 XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-7"),
179 XGENE_PMU_FORMAT_ATTR(iob_agentid, "config1:0-63"),
180 NULL,
181};
182
183static struct attribute *mcb_pmu_format_attrs[] = {
184 XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-5"),
185 XGENE_PMU_FORMAT_ATTR(mcb_agentid, "config1:0-9"),
186 NULL,
187};
188
189static struct attribute *mc_pmu_format_attrs[] = {
190 XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-28"),
191 NULL,
192};
193
194static const struct attribute_group l3c_pmu_format_attr_group = {
195 .name = "format",
196 .attrs = l3c_pmu_format_attrs,
197};
198
199static const struct attribute_group iob_pmu_format_attr_group = {
200 .name = "format",
201 .attrs = iob_pmu_format_attrs,
202};
203
204static const struct attribute_group mcb_pmu_format_attr_group = {
205 .name = "format",
206 .attrs = mcb_pmu_format_attrs,
207};
208
209static const struct attribute_group mc_pmu_format_attr_group = {
210 .name = "format",
211 .attrs = mc_pmu_format_attrs,
212};
213
c0f7f7ac
HT		 214static struct attribute *l3c_pmu_v3_format_attrs[] = {
215 XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-39"),
216 NULL,
217};
218
219static struct attribute *iob_pmu_v3_format_attrs[] = {
220 XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-47"),
221 NULL,
222};
223
224static struct attribute *iob_slow_pmu_v3_format_attrs[] = {
225 XGENE_PMU_FORMAT_ATTR(iob_slow_eventid, "config:0-16"),
226 NULL,
227};
228
229static struct attribute *mcb_pmu_v3_format_attrs[] = {
230 XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-35"),
231 NULL,
232};
233
234static struct attribute *mc_pmu_v3_format_attrs[] = {
235 XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-44"),
236 NULL,
237};
238
239static const struct attribute_group l3c_pmu_v3_format_attr_group = {
240 .name = "format",
241 .attrs = l3c_pmu_v3_format_attrs,
242};
243
244static const struct attribute_group iob_pmu_v3_format_attr_group = {
245 .name = "format",
246 .attrs = iob_pmu_v3_format_attrs,
247};
248
249static const struct attribute_group iob_slow_pmu_v3_format_attr_group = {
250 .name = "format",
251 .attrs = iob_slow_pmu_v3_format_attrs,
252};
253
254static const struct attribute_group mcb_pmu_v3_format_attr_group = {
255 .name = "format",
256 .attrs = mcb_pmu_v3_format_attrs,
257};
258
259static const struct attribute_group mc_pmu_v3_format_attr_group = {
260 .name = "format",
261 .attrs = mc_pmu_v3_format_attrs,
262};
263
832c927d
TN		 264/*
265 * sysfs event attributes
266 */
267static ssize_t xgene_pmu_event_show(struct device *dev,
268 struct device_attribute *attr, char *buf)
269{
b323dfe0
QL		 270 struct perf_pmu_events_attr *pmu_attr =
271 container_of(attr, struct perf_pmu_events_attr, attr);
832c927d 272
b323dfe0 273 return sysfs_emit(buf, "config=0x%llx\n", pmu_attr->id);
832c927d
TN		 274}
275
276#define XGENE_PMU_EVENT_ATTR(_name, _config) \
b323dfe0 277 PMU_EVENT_ATTR_ID(_name, xgene_pmu_event_show, _config)
832c927d
TN		 278
279static struct attribute *l3c_pmu_events_attrs[] = {
280 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
281 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
282 XGENE_PMU_EVENT_ATTR(read-hit, 0x02),
283 XGENE_PMU_EVENT_ATTR(read-miss, 0x03),
284 XGENE_PMU_EVENT_ATTR(write-need-replacement, 0x06),
285 XGENE_PMU_EVENT_ATTR(write-not-need-replacement, 0x07),
286 XGENE_PMU_EVENT_ATTR(tq-full, 0x08),
287 XGENE_PMU_EVENT_ATTR(ackq-full, 0x09),
288 XGENE_PMU_EVENT_ATTR(wdb-full, 0x0a),
289 XGENE_PMU_EVENT_ATTR(bank-fifo-full, 0x0b),
290 XGENE_PMU_EVENT_ATTR(odb-full, 0x0c),
291 XGENE_PMU_EVENT_ATTR(wbq-full, 0x0d),
292 XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue, 0x0e),
293 XGENE_PMU_EVENT_ATTR(bank-fifo-issue, 0x0f),
294 NULL,
295};
296
297static struct attribute *iob_pmu_events_attrs[] = {
298 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
299 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
300 XGENE_PMU_EVENT_ATTR(axi0-read, 0x02),
301 XGENE_PMU_EVENT_ATTR(axi0-read-partial, 0x03),
302 XGENE_PMU_EVENT_ATTR(axi1-read, 0x04),
303 XGENE_PMU_EVENT_ATTR(axi1-read-partial, 0x05),
304 XGENE_PMU_EVENT_ATTR(csw-read-block, 0x06),
305 XGENE_PMU_EVENT_ATTR(csw-read-partial, 0x07),
306 XGENE_PMU_EVENT_ATTR(axi0-write, 0x10),
307 XGENE_PMU_EVENT_ATTR(axi0-write-partial, 0x11),
308 XGENE_PMU_EVENT_ATTR(axi1-write, 0x13),
309 XGENE_PMU_EVENT_ATTR(axi1-write-partial, 0x14),
310 XGENE_PMU_EVENT_ATTR(csw-inbound-dirty, 0x16),
311 NULL,
312};
313
314static struct attribute *mcb_pmu_events_attrs[] = {
315 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
316 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
317 XGENE_PMU_EVENT_ATTR(csw-read, 0x02),
318 XGENE_PMU_EVENT_ATTR(csw-write-request, 0x03),
319 XGENE_PMU_EVENT_ATTR(mcb-csw-stall, 0x04),
320 XGENE_PMU_EVENT_ATTR(cancel-read-gack, 0x05),
321 NULL,
322};
323
324static struct attribute *mc_pmu_events_attrs[] = {
325 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
326 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
327 XGENE_PMU_EVENT_ATTR(act-cmd-sent, 0x02),
328 XGENE_PMU_EVENT_ATTR(pre-cmd-sent, 0x03),
329 XGENE_PMU_EVENT_ATTR(rd-cmd-sent, 0x04),
330 XGENE_PMU_EVENT_ATTR(rda-cmd-sent, 0x05),
331 XGENE_PMU_EVENT_ATTR(wr-cmd-sent, 0x06),
332 XGENE_PMU_EVENT_ATTR(wra-cmd-sent, 0x07),
333 XGENE_PMU_EVENT_ATTR(pde-cmd-sent, 0x08),
334 XGENE_PMU_EVENT_ATTR(sre-cmd-sent, 0x09),
335 XGENE_PMU_EVENT_ATTR(prea-cmd-sent, 0x0a),
336 XGENE_PMU_EVENT_ATTR(ref-cmd-sent, 0x0b),
337 XGENE_PMU_EVENT_ATTR(rd-rda-cmd-sent, 0x0c),
338 XGENE_PMU_EVENT_ATTR(wr-wra-cmd-sent, 0x0d),
339 XGENE_PMU_EVENT_ATTR(in-rd-collision, 0x0e),
340 XGENE_PMU_EVENT_ATTR(in-wr-collision, 0x0f),
341 XGENE_PMU_EVENT_ATTR(collision-queue-not-empty, 0x10),
342 XGENE_PMU_EVENT_ATTR(collision-queue-full, 0x11),
343 XGENE_PMU_EVENT_ATTR(mcu-request, 0x12),
344 XGENE_PMU_EVENT_ATTR(mcu-rd-request, 0x13),
345 XGENE_PMU_EVENT_ATTR(mcu-hp-rd-request, 0x14),
346 XGENE_PMU_EVENT_ATTR(mcu-wr-request, 0x15),
347 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-all, 0x16),
348 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-cancel, 0x17),
349 XGENE_PMU_EVENT_ATTR(mcu-rd-response, 0x18),
350 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-all, 0x19),
351 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-cancel, 0x1a),
352 XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-all, 0x1b),
353 XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-cancel, 0x1c),
354 NULL,
355};
356
357static const struct attribute_group l3c_pmu_events_attr_group = {
358 .name = "events",
359 .attrs = l3c_pmu_events_attrs,
360};
361
362static const struct attribute_group iob_pmu_events_attr_group = {
363 .name = "events",
364 .attrs = iob_pmu_events_attrs,
365};
366
367static const struct attribute_group mcb_pmu_events_attr_group = {
368 .name = "events",
369 .attrs = mcb_pmu_events_attrs,
370};
371
372static const struct attribute_group mc_pmu_events_attr_group = {
373 .name = "events",
374 .attrs = mc_pmu_events_attrs,
375};
376
c0f7f7ac
HT		 377static struct attribute *l3c_pmu_v3_events_attrs[] = {
378 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
379 XGENE_PMU_EVENT_ATTR(read-hit, 0x01),
380 XGENE_PMU_EVENT_ATTR(read-miss, 0x02),
381 XGENE_PMU_EVENT_ATTR(index-flush-eviction, 0x03),
382 XGENE_PMU_EVENT_ATTR(write-caused-replacement, 0x04),
383 XGENE_PMU_EVENT_ATTR(write-not-caused-replacement, 0x05),
384 XGENE_PMU_EVENT_ATTR(clean-eviction, 0x06),
385 XGENE_PMU_EVENT_ATTR(dirty-eviction, 0x07),
386 XGENE_PMU_EVENT_ATTR(read, 0x08),
387 XGENE_PMU_EVENT_ATTR(write, 0x09),
388 XGENE_PMU_EVENT_ATTR(request, 0x0a),
389 XGENE_PMU_EVENT_ATTR(tq-bank-conflict-issue-stall, 0x0b),
390 XGENE_PMU_EVENT_ATTR(tq-full, 0x0c),
391 XGENE_PMU_EVENT_ATTR(ackq-full, 0x0d),
392 XGENE_PMU_EVENT_ATTR(wdb-full, 0x0e),
393 XGENE_PMU_EVENT_ATTR(odb-full, 0x10),
394 XGENE_PMU_EVENT_ATTR(wbq-full, 0x11),
395 XGENE_PMU_EVENT_ATTR(input-req-async-fifo-stall, 0x12),
396 XGENE_PMU_EVENT_ATTR(output-req-async-fifo-stall, 0x13),
397 XGENE_PMU_EVENT_ATTR(output-data-async-fifo-stall, 0x14),
398 XGENE_PMU_EVENT_ATTR(total-insertion, 0x15),
399 XGENE_PMU_EVENT_ATTR(sip-insertions-r-set, 0x16),
400 XGENE_PMU_EVENT_ATTR(sip-insertions-r-clear, 0x17),
401 XGENE_PMU_EVENT_ATTR(dip-insertions-r-set, 0x18),
402 XGENE_PMU_EVENT_ATTR(dip-insertions-r-clear, 0x19),
403 XGENE_PMU_EVENT_ATTR(dip-insertions-force-r-set, 0x1a),
404 XGENE_PMU_EVENT_ATTR(egression, 0x1b),
405 XGENE_PMU_EVENT_ATTR(replacement, 0x1c),
406 XGENE_PMU_EVENT_ATTR(old-replacement, 0x1d),
407 XGENE_PMU_EVENT_ATTR(young-replacement, 0x1e),
408 XGENE_PMU_EVENT_ATTR(r-set-replacement, 0x1f),
409 XGENE_PMU_EVENT_ATTR(r-clear-replacement, 0x20),
410 XGENE_PMU_EVENT_ATTR(old-r-replacement, 0x21),
411 XGENE_PMU_EVENT_ATTR(old-nr-replacement, 0x22),
412 XGENE_PMU_EVENT_ATTR(young-r-replacement, 0x23),
413 XGENE_PMU_EVENT_ATTR(young-nr-replacement, 0x24),
414 XGENE_PMU_EVENT_ATTR(bloomfilter-clearing, 0x25),
415 XGENE_PMU_EVENT_ATTR(generation-flip, 0x26),
416 XGENE_PMU_EVENT_ATTR(vcc-droop-detected, 0x27),
417 NULL,
418};
419
420static struct attribute *iob_fast_pmu_v3_events_attrs[] = {
421 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
422 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-all, 0x01),
423 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-rd, 0x02),
424 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-wr, 0x03),
425 XGENE_PMU_EVENT_ATTR(pa-all-cp-req, 0x04),
426 XGENE_PMU_EVENT_ATTR(pa-cp-blk-req, 0x05),
427 XGENE_PMU_EVENT_ATTR(pa-cp-ptl-req, 0x06),
428 XGENE_PMU_EVENT_ATTR(pa-cp-rd-req, 0x07),
429 XGENE_PMU_EVENT_ATTR(pa-cp-wr-req, 0x08),
430 XGENE_PMU_EVENT_ATTR(ba-all-req, 0x09),
431 XGENE_PMU_EVENT_ATTR(ba-rd-req, 0x0a),
432 XGENE_PMU_EVENT_ATTR(ba-wr-req, 0x0b),
433 XGENE_PMU_EVENT_ATTR(pa-rd-shared-req-issued, 0x10),
434 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-req-issued, 0x11),
435 XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-stashable, 0x12),
436 XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-nonstashable, 0x13),
437 XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-stashable, 0x14),
438 XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-nonstashable, 0x15),
439 XGENE_PMU_EVENT_ATTR(pa-ptl-wr-req, 0x16),
440 XGENE_PMU_EVENT_ATTR(pa-ptl-rd-req, 0x17),
441 XGENE_PMU_EVENT_ATTR(pa-wr-back-clean-data, 0x18),
442 XGENE_PMU_EVENT_ATTR(pa-wr-back-cancelled-on-SS, 0x1b),
443 XGENE_PMU_EVENT_ATTR(pa-barrier-occurrence, 0x1c),
444 XGENE_PMU_EVENT_ATTR(pa-barrier-cycles, 0x1d),
445 XGENE_PMU_EVENT_ATTR(pa-total-cp-snoops, 0x20),
446 XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop, 0x21),
447 XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop-hit, 0x22),
448 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop, 0x23),
449 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop-hit, 0x24),
450 XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop, 0x25),
451 XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop-hit, 0x26),
452 XGENE_PMU_EVENT_ATTR(pa-req-buffer-full, 0x28),
453 XGENE_PMU_EVENT_ATTR(cswlf-outbound-req-fifo-full, 0x29),
454 XGENE_PMU_EVENT_ATTR(cswlf-inbound-snoop-fifo-backpressure, 0x2a),
455 XGENE_PMU_EVENT_ATTR(cswlf-outbound-lack-fifo-full, 0x2b),
456 XGENE_PMU_EVENT_ATTR(cswlf-inbound-gack-fifo-backpressure, 0x2c),
457 XGENE_PMU_EVENT_ATTR(cswlf-outbound-data-fifo-full, 0x2d),
458 XGENE_PMU_EVENT_ATTR(cswlf-inbound-data-fifo-backpressure, 0x2e),
459 XGENE_PMU_EVENT_ATTR(cswlf-inbound-req-backpressure, 0x2f),
460 NULL,
461};
462
463static struct attribute *iob_slow_pmu_v3_events_attrs[] = {
464 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
465 XGENE_PMU_EVENT_ATTR(pa-axi0-rd-req, 0x01),
466 XGENE_PMU_EVENT_ATTR(pa-axi0-wr-req, 0x02),
467 XGENE_PMU_EVENT_ATTR(pa-axi1-rd-req, 0x03),
468 XGENE_PMU_EVENT_ATTR(pa-axi1-wr-req, 0x04),
469 XGENE_PMU_EVENT_ATTR(ba-all-axi-req, 0x07),
470 XGENE_PMU_EVENT_ATTR(ba-axi-rd-req, 0x08),
471 XGENE_PMU_EVENT_ATTR(ba-axi-wr-req, 0x09),
472 XGENE_PMU_EVENT_ATTR(ba-free-list-empty, 0x10),
473 NULL,
474};
475
476static struct attribute *mcb_pmu_v3_events_attrs[] = {
477 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
478 XGENE_PMU_EVENT_ATTR(req-receive, 0x01),
479 XGENE_PMU_EVENT_ATTR(rd-req-recv, 0x02),
480 XGENE_PMU_EVENT_ATTR(rd-req-recv-2, 0x03),
481 XGENE_PMU_EVENT_ATTR(wr-req-recv, 0x04),
482 XGENE_PMU_EVENT_ATTR(wr-req-recv-2, 0x05),
483 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu, 0x06),
484 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu-2, 0x07),
485 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu, 0x08),
486 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu-2, 0x09),
487 XGENE_PMU_EVENT_ATTR(glbl-ack-recv-for-rd-sent-to-spec-mcu, 0x0a),
488 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-for-rd-sent-to-spec-mcu, 0x0b),
489 XGENE_PMU_EVENT_ATTR(glbl-ack-nogo-recv-for-rd-sent-to-spec-mcu, 0x0c),
490 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req, 0x0d),
491 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req-2, 0x0e),
492 XGENE_PMU_EVENT_ATTR(wr-req-sent-to-mcu, 0x0f),
493 XGENE_PMU_EVENT_ATTR(gack-recv, 0x10),
494 XGENE_PMU_EVENT_ATTR(rd-gack-recv, 0x11),
495 XGENE_PMU_EVENT_ATTR(wr-gack-recv, 0x12),
496 XGENE_PMU_EVENT_ATTR(cancel-rd-gack, 0x13),
497 XGENE_PMU_EVENT_ATTR(cancel-wr-gack, 0x14),
498 XGENE_PMU_EVENT_ATTR(mcb-csw-req-stall, 0x15),
499 XGENE_PMU_EVENT_ATTR(mcu-req-intf-blocked, 0x16),
500 XGENE_PMU_EVENT_ATTR(mcb-mcu-rd-intf-stall, 0x17),
501 XGENE_PMU_EVENT_ATTR(csw-rd-intf-blocked, 0x18),
502 XGENE_PMU_EVENT_ATTR(csw-local-ack-intf-blocked, 0x19),
503 XGENE_PMU_EVENT_ATTR(mcu-req-table-full, 0x1a),
504 XGENE_PMU_EVENT_ATTR(mcu-stat-table-full, 0x1b),
505 XGENE_PMU_EVENT_ATTR(mcu-wr-table-full, 0x1c),
506 XGENE_PMU_EVENT_ATTR(mcu-rdreceipt-resp, 0x1d),
507 XGENE_PMU_EVENT_ATTR(mcu-wrcomplete-resp, 0x1e),
508 XGENE_PMU_EVENT_ATTR(mcu-retryack-resp, 0x1f),
509 XGENE_PMU_EVENT_ATTR(mcu-pcrdgrant-resp, 0x20),
510 XGENE_PMU_EVENT_ATTR(mcu-req-from-lastload, 0x21),
511 XGENE_PMU_EVENT_ATTR(mcu-req-from-bypass, 0x22),
512 XGENE_PMU_EVENT_ATTR(volt-droop-detect, 0x23),
513 NULL,
514};
515
516static struct attribute *mc_pmu_v3_events_attrs[] = {
517 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
518 XGENE_PMU_EVENT_ATTR(act-sent, 0x01),
519 XGENE_PMU_EVENT_ATTR(pre-sent, 0x02),
520 XGENE_PMU_EVENT_ATTR(rd-sent, 0x03),
521 XGENE_PMU_EVENT_ATTR(rda-sent, 0x04),
522 XGENE_PMU_EVENT_ATTR(wr-sent, 0x05),
523 XGENE_PMU_EVENT_ATTR(wra-sent, 0x06),
524 XGENE_PMU_EVENT_ATTR(pd-entry-vld, 0x07),
525 XGENE_PMU_EVENT_ATTR(sref-entry-vld, 0x08),
526 XGENE_PMU_EVENT_ATTR(prea-sent, 0x09),
527 XGENE_PMU_EVENT_ATTR(ref-sent, 0x0a),
528 XGENE_PMU_EVENT_ATTR(rd-rda-sent, 0x0b),
529 XGENE_PMU_EVENT_ATTR(wr-wra-sent, 0x0c),
530 XGENE_PMU_EVENT_ATTR(raw-hazard, 0x0d),
531 XGENE_PMU_EVENT_ATTR(war-hazard, 0x0e),
532 XGENE_PMU_EVENT_ATTR(waw-hazard, 0x0f),
533 XGENE_PMU_EVENT_ATTR(rar-hazard, 0x10),
534 XGENE_PMU_EVENT_ATTR(raw-war-waw-hazard, 0x11),
535 XGENE_PMU_EVENT_ATTR(hprd-lprd-wr-req-vld, 0x12),
536 XGENE_PMU_EVENT_ATTR(lprd-req-vld, 0x13),
537 XGENE_PMU_EVENT_ATTR(hprd-req-vld, 0x14),
538 XGENE_PMU_EVENT_ATTR(hprd-lprd-req-vld, 0x15),
539 XGENE_PMU_EVENT_ATTR(wr-req-vld, 0x16),
540 XGENE_PMU_EVENT_ATTR(partial-wr-req-vld, 0x17),
541 XGENE_PMU_EVENT_ATTR(rd-retry, 0x18),
542 XGENE_PMU_EVENT_ATTR(wr-retry, 0x19),
543 XGENE_PMU_EVENT_ATTR(retry-gnt, 0x1a),
544 XGENE_PMU_EVENT_ATTR(rank-change, 0x1b),
545 XGENE_PMU_EVENT_ATTR(dir-change, 0x1c),
546 XGENE_PMU_EVENT_ATTR(rank-dir-change, 0x1d),
547 XGENE_PMU_EVENT_ATTR(rank-active, 0x1e),
548 XGENE_PMU_EVENT_ATTR(rank-idle, 0x1f),
549 XGENE_PMU_EVENT_ATTR(rank-pd, 0x20),
550 XGENE_PMU_EVENT_ATTR(rank-sref, 0x21),
551 XGENE_PMU_EVENT_ATTR(queue-fill-gt-thresh, 0x22),
552 XGENE_PMU_EVENT_ATTR(queue-rds-gt-thresh, 0x23),
553 XGENE_PMU_EVENT_ATTR(queue-wrs-gt-thresh, 0x24),
554 XGENE_PMU_EVENT_ATTR(phy-updt-complt, 0x25),
555 XGENE_PMU_EVENT_ATTR(tz-fail, 0x26),
556 XGENE_PMU_EVENT_ATTR(dram-errc, 0x27),
557 XGENE_PMU_EVENT_ATTR(dram-errd, 0x28),
558 XGENE_PMU_EVENT_ATTR(rd-enq, 0x29),
559 XGENE_PMU_EVENT_ATTR(wr-enq, 0x2a),
560 XGENE_PMU_EVENT_ATTR(tmac-limit-reached, 0x2b),
561 XGENE_PMU_EVENT_ATTR(tmaw-tracker-full, 0x2c),
562 NULL,
563};
564
565static const struct attribute_group l3c_pmu_v3_events_attr_group = {
566 .name = "events",
567 .attrs = l3c_pmu_v3_events_attrs,
568};
569
570static const struct attribute_group iob_fast_pmu_v3_events_attr_group = {
571 .name = "events",
572 .attrs = iob_fast_pmu_v3_events_attrs,
573};
574
575static const struct attribute_group iob_slow_pmu_v3_events_attr_group = {
576 .name = "events",
577 .attrs = iob_slow_pmu_v3_events_attrs,
578};
579
580static const struct attribute_group mcb_pmu_v3_events_attr_group = {
581 .name = "events",
582 .attrs = mcb_pmu_v3_events_attrs,
583};
584
585static const struct attribute_group mc_pmu_v3_events_attr_group = {
586 .name = "events",
587 .attrs = mc_pmu_v3_events_attrs,
588};
589
832c927d
TN		 590/*
591 * sysfs cpumask attributes
592 */
21ad02e6
Y		 593static ssize_t cpumask_show(struct device *dev,
594 struct device_attribute *attr, char *buf)
832c927d
TN		 595{
596 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev));
597
598 return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu);
599}
600
21ad02e6 601static DEVICE_ATTR_RO(cpumask);
832c927d
TN		 602
603static struct attribute *xgene_pmu_cpumask_attrs[] = {
604 &dev_attr_cpumask.attr,
605 NULL,
606};
607
608static const struct attribute_group pmu_cpumask_attr_group = {
609 .attrs = xgene_pmu_cpumask_attrs,
610};
611
612/*
c0f7f7ac 613 * Per PMU device attribute groups of PMU v1 and v2
832c927d
TN		 614 */
615static const struct attribute_group *l3c_pmu_attr_groups[] = {
616 &l3c_pmu_format_attr_group,
617 &pmu_cpumask_attr_group,
618 &l3c_pmu_events_attr_group,
619 NULL
620};
621
622static const struct attribute_group *iob_pmu_attr_groups[] = {
623 &iob_pmu_format_attr_group,
624 &pmu_cpumask_attr_group,
625 &iob_pmu_events_attr_group,
626 NULL
627};
628
629static const struct attribute_group *mcb_pmu_attr_groups[] = {
630 &mcb_pmu_format_attr_group,
631 &pmu_cpumask_attr_group,
632 &mcb_pmu_events_attr_group,
633 NULL
634};
635
636static const struct attribute_group *mc_pmu_attr_groups[] = {
637 &mc_pmu_format_attr_group,
638 &pmu_cpumask_attr_group,
639 &mc_pmu_events_attr_group,
640 NULL
641};
642
c0f7f7ac
HT		 643/*
644 * Per PMU device attribute groups of PMU v3
645 */
646static const struct attribute_group *l3c_pmu_v3_attr_groups[] = {
647 &l3c_pmu_v3_format_attr_group,
648 &pmu_cpumask_attr_group,
649 &l3c_pmu_v3_events_attr_group,
650 NULL
651};
652
653static const struct attribute_group *iob_fast_pmu_v3_attr_groups[] = {
654 &iob_pmu_v3_format_attr_group,
655 &pmu_cpumask_attr_group,
656 &iob_fast_pmu_v3_events_attr_group,
657 NULL
658};
659
660static const struct attribute_group *iob_slow_pmu_v3_attr_groups[] = {
661 &iob_slow_pmu_v3_format_attr_group,
662 &pmu_cpumask_attr_group,
663 &iob_slow_pmu_v3_events_attr_group,
664 NULL
665};
666
667static const struct attribute_group *mcb_pmu_v3_attr_groups[] = {
668 &mcb_pmu_v3_format_attr_group,
669 &pmu_cpumask_attr_group,
670 &mcb_pmu_v3_events_attr_group,
671 NULL
672};
673
674static const struct attribute_group *mc_pmu_v3_attr_groups[] = {
675 &mc_pmu_v3_format_attr_group,
676 &pmu_cpumask_attr_group,
677 &mc_pmu_v3_events_attr_group,
678 NULL
679};
680
832c927d
TN		 681static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev)
682{
683 int cntr;
684
685 cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask,
686 pmu_dev->max_counters);
687 if (cntr == pmu_dev->max_counters)
688 return -ENOSPC;
689 set_bit(cntr, pmu_dev->cntr_assign_mask);
690
691 return cntr;
692}
693
694static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr)
695{
696 clear_bit(cntr, pmu_dev->cntr_assign_mask);
697}
698
699static inline void xgene_pmu_mask_int(struct xgene_pmu *xgene_pmu)
700{
701 writel(PCPPMU_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
702}
703
c0f7f7ac
HT		 704static inline void xgene_pmu_v3_mask_int(struct xgene_pmu *xgene_pmu)
705{
706 writel(PCPPMU_V3_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
707}
708
832c927d
TN		 709static inline void xgene_pmu_unmask_int(struct xgene_pmu *xgene_pmu)
710{
711 writel(PCPPMU_INTCLRMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
712}
713
c0f7f7ac
HT		 714static inline void xgene_pmu_v3_unmask_int(struct xgene_pmu *xgene_pmu)
715{
716 writel(PCPPMU_V3_INTCLRMASK,
717 xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
718}
719
e35e0a04
HT		 720static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev,
721 int idx)
832c927d
TN		 722{
723 return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
724}
725
c0f7f7ac
HT		 726static inline u64 xgene_pmu_read_counter64(struct xgene_pmu_dev *pmu_dev,
727 int idx)
728{
729 u32 lo, hi;
730
731 /*
732 * v3 has 64-bit counter registers composed by 2 32-bit registers
733 * This can be a problem if the counter increases and carries
734 * out of bit [31] between 2 reads. The extra reads would help
735 * to prevent this issue.
736 */
737 do {
738 hi = xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1);
739 lo = xgene_pmu_read_counter32(pmu_dev, 2 * idx);
740 } while (hi != xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1));
741
742 return (((u64)hi << 32) | lo);
743}
744
832c927d 745static inline void
e35e0a04 746xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
832c927d
TN		 747{
748 writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
749}
750
c0f7f7ac
HT		 751static inline void
752xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
753{
754 u32 cnt_lo, cnt_hi;
755
756 cnt_hi = upper_32_bits(val);
757 cnt_lo = lower_32_bits(val);
758
759 /* v3 has 64-bit counter registers composed by 2 32-bit registers */
760 xgene_pmu_write_counter32(pmu_dev, 2 * idx, cnt_lo);
761 xgene_pmu_write_counter32(pmu_dev, 2 * idx + 1, cnt_hi);
762}
763
832c927d
TN		 764static inline void
765xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val)
766{
767 writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));
768}
769
770static inline void
771xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val)
772{
773 writel(val, pmu_dev->inf->csr + PMU_PMAMR0);
774}
775
c0f7f7ac
HT		 776static inline void
777xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
778
832c927d
TN		 779static inline void
780xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val)
781{
782 writel(val, pmu_dev->inf->csr + PMU_PMAMR1);
783}
784
c0f7f7ac
HT		 785static inline void
786xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
787
832c927d
TN		 788static inline void
789xgene_pmu_enable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
790{
791 u32 val;
792
793 val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);
794 val |= 1 << idx;
795 writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);
796}
797
798static inline void
799xgene_pmu_disable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
800{
801 u32 val;
802
803 val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);
804 val |= 1 << idx;
805 writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);
806}
807
808static inline void
809xgene_pmu_enable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
810{
811 u32 val;
812
813 val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);
814 val |= 1 << idx;
815 writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);
816}
817
818static inline void
819xgene_pmu_disable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
820{
821 u32 val;
822
823 val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);
824 val |= 1 << idx;
825 writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);
826}
827
828static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev)
829{
830 u32 val;
831
832 val = readl(pmu_dev->inf->csr + PMU_PMCR);
833 val |= PMU_PMCR_P;
834 writel(val, pmu_dev->inf->csr + PMU_PMCR);
835}
836
837static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev)
838{
839 u32 val;
840
841 val = readl(pmu_dev->inf->csr + PMU_PMCR);
842 val |= PMU_PMCR_E;
843 writel(val, pmu_dev->inf->csr + PMU_PMCR);
844}
845
846static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev)
847{
848 u32 val;
849
850 val = readl(pmu_dev->inf->csr + PMU_PMCR);
851 val &= ~PMU_PMCR_E;
852 writel(val, pmu_dev->inf->csr + PMU_PMCR);
853}
854
855static void xgene_perf_pmu_enable(struct pmu *pmu)
856{
857 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
e35e0a04 858 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
95ed57c7 859 bool enabled = !bitmap_empty(pmu_dev->cntr_assign_mask,
832c927d
TN		 860 pmu_dev->max_counters);
861
862 if (!enabled)
863 return;
864
e35e0a04 865 xgene_pmu->ops->start_counters(pmu_dev);
832c927d
TN		 866}
867
868static void xgene_perf_pmu_disable(struct pmu *pmu)
869{
870 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
e35e0a04 871 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d 872
e35e0a04 873 xgene_pmu->ops->stop_counters(pmu_dev);
832c927d
TN		 874}
875
876static int xgene_perf_event_init(struct perf_event *event)
877{
878 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
879 struct hw_perf_event *hw = &event->hw;
880 struct perf_event *sibling;
881
882 /* Test the event attr type check for PMU enumeration */
883 if (event->attr.type != event->pmu->type)
884 return -ENOENT;
885
886 /*
887 * SOC PMU counters are shared across all cores.
888 * Therefore, it does not support per-process mode.
889 * Also, it does not support event sampling mode.
890 */
891 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
892 return -EINVAL;
893
832c927d
TN		 894 if (event->cpu < 0)
895 return -EINVAL;
896 /*
897 * Many perf core operations (eg. events rotation) operate on a
898 * single CPU context. This is obvious for CPU PMUs, where one
899 * expects the same sets of events being observed on all CPUs,
900 * but can lead to issues for off-core PMUs, where each
901 * event could be theoretically assigned to a different CPU. To
902 * mitigate this, we enforce CPU assignment to one, selected
903 * processor (the one described in the "cpumask" attribute).
904 */
905 event->cpu = cpumask_first(&pmu_dev->parent->cpu);
906
907 hw->config = event->attr.config;
908 /*
909 * Each bit of the config1 field represents an agent from which the
910 * request of the event come. The event is counted only if it's caused
911 * by a request of an agent has the bit cleared.
912 * By default, the event is counted for all agents.
913 */
914 hw->config_base = event->attr.config1;
915
916 /*
917 * We must NOT create groups containing mixed PMUs, although software
918 * events are acceptable
919 */
920 if (event->group_leader->pmu != event->pmu &&
921 !is_software_event(event->group_leader))
922 return -EINVAL;
923
edb39592 924 for_each_sibling_event(sibling, event->group_leader) {
832c927d
TN		 925 if (sibling->pmu != event->pmu &&
926 !is_software_event(sibling))
927 return -EINVAL;
edb39592 928 }
832c927d
TN		 929
930 return 0;
931}
932
933static void xgene_perf_enable_event(struct perf_event *event)
934{
935 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 936 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d 937
e35e0a04
HT		 938 xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event),
939 GET_EVENTID(event));
940 xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event)));
832c927d 941 if (pmu_dev->inf->type == PMU_TYPE_IOB)
e35e0a04
HT		 942 xgene_pmu->ops->write_agent1msk(pmu_dev,
943 ~((u32)GET_AGENT1ID(event)));
832c927d 944
e35e0a04
HT		 945 xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event));
946 xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event));
832c927d
TN		 947}
948
949static void xgene_perf_disable_event(struct perf_event *event)
950{
951 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 952 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d 953
e35e0a04
HT		 954 xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event));
955 xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event));
832c927d
TN		 956}
957
958static void xgene_perf_event_set_period(struct perf_event *event)
959{
960 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 961 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d
TN		 962 struct hw_perf_event *hw = &event->hw;
963 /*
c0f7f7ac
HT		 964 * For 32 bit counter, it has a period of 2^32. To account for the
965 * possibility of extreme interrupt latency we program for a period of
966 * half that. Hopefully, we can handle the interrupt before another 2^31
832c927d 967 * events occur and the counter overtakes its previous value.
c0f7f7ac 968 * For 64 bit counter, we don't expect it overflow.
832c927d
TN		 969 */
970 u64 val = 1ULL << 31;
971
972 local64_set(&hw->prev_count, val);
e35e0a04 973 xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val);
832c927d
TN		 974}
975
976static void xgene_perf_event_update(struct perf_event *event)
977{
978 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 979 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d
TN		 980 struct hw_perf_event *hw = &event->hw;
981 u64 delta, prev_raw_count, new_raw_count;
982
983again:
984 prev_raw_count = local64_read(&hw->prev_count);
e35e0a04 985 new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event));
832c927d
TN		 986
987 if (local64_cmpxchg(&hw->prev_count, prev_raw_count,
988 new_raw_count) != prev_raw_count)
989 goto again;
990
991 delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period;
992
993 local64_add(delta, &event->count);
994}
995
996static void xgene_perf_read(struct perf_event *event)
997{
998 xgene_perf_event_update(event);
999}
1000
1001static void xgene_perf_start(struct perf_event *event, int flags)
1002{
1003 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 1004 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d
TN		 1005 struct hw_perf_event *hw = &event->hw;
1006
1007 if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED)))
1008 return;
1009
1010 WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE));
1011 hw->state = 0;
1012
1013 xgene_perf_event_set_period(event);
1014
1015 if (flags & PERF_EF_RELOAD) {
1016 u64 prev_raw_count = local64_read(&hw->prev_count);
1017
e35e0a04
HT		 1018 xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event),
1019 prev_raw_count);
832c927d
TN		 1020 }
1021
1022 xgene_perf_enable_event(event);
1023 perf_event_update_userpage(event);
1024}
1025
1026static void xgene_perf_stop(struct perf_event *event, int flags)
1027{
1028 struct hw_perf_event *hw = &event->hw;
832c927d
TN		 1029
1030 if (hw->state & PERF_HES_UPTODATE)
1031 return;
1032
1033 xgene_perf_disable_event(event);
1034 WARN_ON_ONCE(hw->state & PERF_HES_STOPPED);
1035 hw->state |= PERF_HES_STOPPED;
1036
1037 if (hw->state & PERF_HES_UPTODATE)
1038 return;
1039
832c927d
TN		 1040 xgene_perf_read(event);
1041 hw->state |= PERF_HES_UPTODATE;
1042}
1043
1044static int xgene_perf_add(struct perf_event *event, int flags)
1045{
1046 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1047 struct hw_perf_event *hw = &event->hw;
1048
1049 hw->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1050
1051 /* Allocate an event counter */
1052 hw->idx = get_next_avail_cntr(pmu_dev);
1053 if (hw->idx < 0)
1054 return -EAGAIN;
1055
1056 /* Update counter event pointer for Interrupt handler */
1057 pmu_dev->pmu_counter_event[hw->idx] = event;
1058
1059 if (flags & PERF_EF_START)
1060 xgene_perf_start(event, PERF_EF_RELOAD);
1061
1062 return 0;
1063}
1064
1065static void xgene_perf_del(struct perf_event *event, int flags)
1066{
1067 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1068 struct hw_perf_event *hw = &event->hw;
1069
1070 xgene_perf_stop(event, PERF_EF_UPDATE);
1071
1072 /* clear the assigned counter */
1073 clear_avail_cntr(pmu_dev, GET_CNTR(event));
1074
1075 perf_event_update_userpage(event);
1076 pmu_dev->pmu_counter_event[hw->idx] = NULL;
1077}
1078
1079static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name)
1080{
1081 struct xgene_pmu *xgene_pmu;
1082
c0f7f7ac
HT		 1083 if (pmu_dev->parent->version == PCP_PMU_V3)
1084 pmu_dev->max_period = PMU_V3_CNT_MAX_PERIOD;
1085 else
1086 pmu_dev->max_period = PMU_CNT_MAX_PERIOD;
832c927d
TN		 1087 /* First version PMU supports only single event counter */
1088 xgene_pmu = pmu_dev->parent;
1089 if (xgene_pmu->version == PCP_PMU_V1)
1090 pmu_dev->max_counters = 1;
1091 else
1092 pmu_dev->max_counters = PMU_MAX_COUNTERS;
1093
1094 /* Perf driver registration */
1095 pmu_dev->pmu = (struct pmu) {
1096 .attr_groups = pmu_dev->attr_groups,
1097 .task_ctx_nr = perf_invalid_context,
1098 .pmu_enable = xgene_perf_pmu_enable,
1099 .pmu_disable = xgene_perf_pmu_disable,
1100 .event_init = xgene_perf_event_init,
1101 .add = xgene_perf_add,
1102 .del = xgene_perf_del,
1103 .start = xgene_perf_start,
1104 .stop = xgene_perf_stop,
1105 .read = xgene_perf_read,
a66b0010 1106 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
832c927d
TN		 1107 };
1108
1109 /* Hardware counter init */
e35e0a04
HT		 1110 xgene_pmu->ops->stop_counters(pmu_dev);
1111 xgene_pmu->ops->reset_counters(pmu_dev);
832c927d
TN		 1112
1113 return perf_pmu_register(&pmu_dev->pmu, name, -1);
1114}
1115
1116static int
1117xgene_pmu_dev_add(struct xgene_pmu *xgene_pmu, struct xgene_pmu_dev_ctx *ctx)
1118{
1119 struct device *dev = xgene_pmu->dev;
1120 struct xgene_pmu_dev *pmu;
832c927d
TN		 1121
1122 pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL);
1123 if (!pmu)
1124 return -ENOMEM;
1125 pmu->parent = xgene_pmu;
1126 pmu->inf = &ctx->inf;
1127 ctx->pmu_dev = pmu;
1128
1129 switch (pmu->inf->type) {
1130 case PMU_TYPE_L3C:
c0f7f7ac 1131 if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))
c1be2ddb 1132 return -ENODEV;
c0f7f7ac
HT		 1133 if (xgene_pmu->version == PCP_PMU_V3)
1134 pmu->attr_groups = l3c_pmu_v3_attr_groups;
1135 else
1136 pmu->attr_groups = l3c_pmu_attr_groups;
832c927d
TN		 1137 break;
1138 case PMU_TYPE_IOB:
c0f7f7ac
HT		 1139 if (xgene_pmu->version == PCP_PMU_V3)
1140 pmu->attr_groups = iob_fast_pmu_v3_attr_groups;
1141 else
1142 pmu->attr_groups = iob_pmu_attr_groups;
1143 break;
1144 case PMU_TYPE_IOB_SLOW:
1145 if (xgene_pmu->version == PCP_PMU_V3)
1146 pmu->attr_groups = iob_slow_pmu_v3_attr_groups;
832c927d
TN		 1147 break;
1148 case PMU_TYPE_MCB:
1149 if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))
c1be2ddb 1150 return -ENODEV;
c0f7f7ac
HT		 1151 if (xgene_pmu->version == PCP_PMU_V3)
1152 pmu->attr_groups = mcb_pmu_v3_attr_groups;
1153 else
1154 pmu->attr_groups = mcb_pmu_attr_groups;
832c927d
TN		 1155 break;
1156 case PMU_TYPE_MC:
1157 if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))
c1be2ddb 1158 return -ENODEV;
c0f7f7ac
HT		 1159 if (xgene_pmu->version == PCP_PMU_V3)
1160 pmu->attr_groups = mc_pmu_v3_attr_groups;
1161 else
1162 pmu->attr_groups = mc_pmu_attr_groups;
832c927d
TN		 1163 break;
1164 default:
1165 return -EINVAL;
1166 }
1167
c1be2ddb 1168 if (xgene_init_perf(pmu, ctx->name)) {
832c927d 1169 dev_err(dev, "%s PMU: Failed to init perf driver\n", ctx->name);
c1be2ddb 1170 return -ENODEV;
832c927d
TN		 1171 }
1172
1173 dev_info(dev, "%s PMU registered\n", ctx->name);
1174
c1be2ddb 1175 return 0;
832c927d
TN		 1176}
1177
1178static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev)
1179{
1180 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
c0f7f7ac 1181 void __iomem *csr = pmu_dev->inf->csr;
832c927d
TN		 1182 u32 pmovsr;
1183 int idx;
1184
c0f7f7ac
HT		 1185 xgene_pmu->ops->stop_counters(pmu_dev);
1186
1187 if (xgene_pmu->version == PCP_PMU_V3)
1188 pmovsr = readl(csr + PMU_PMOVSSET) & PMU_OVERFLOW_MASK;
1189 else
1190 pmovsr = readl(csr + PMU_PMOVSR) & PMU_OVERFLOW_MASK;
1191
832c927d 1192 if (!pmovsr)
c0f7f7ac 1193 goto out;
832c927d
TN		 1194
1195 /* Clear interrupt flag */
1196 if (xgene_pmu->version == PCP_PMU_V1)
c0f7f7ac
HT		 1197 writel(0x0, csr + PMU_PMOVSR);
1198 else if (xgene_pmu->version == PCP_PMU_V2)
1199 writel(pmovsr, csr + PMU_PMOVSR);
832c927d 1200 else
c0f7f7ac 1201 writel(pmovsr, csr + PMU_PMOVSCLR);
832c927d
TN		 1202
1203 for (idx = 0; idx < PMU_MAX_COUNTERS; idx++) {
1204 struct perf_event *event = pmu_dev->pmu_counter_event[idx];
1205 int overflowed = pmovsr & BIT(idx);
1206
1207 /* Ignore if we don't have an event. */
1208 if (!event || !overflowed)
1209 continue;
1210 xgene_perf_event_update(event);
1211 xgene_perf_event_set_period(event);
1212 }
c0f7f7ac
HT		 1213
1214out:
1215 xgene_pmu->ops->start_counters(pmu_dev);
832c927d
TN		 1216}
1217
1218static irqreturn_t xgene_pmu_isr(int irq, void *dev_id)
1219{
c0f7f7ac 1220 u32 intr_mcu, intr_mcb, intr_l3c, intr_iob;
832c927d
TN		 1221 struct xgene_pmu_dev_ctx *ctx;
1222 struct xgene_pmu *xgene_pmu = dev_id;
832c927d
TN		 1223 u32 val;
1224
8ee37e0f 1225 raw_spin_lock(&xgene_pmu->lock);
832c927d
TN		 1226
1227 /* Get Interrupt PMU source */
1228 val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG);
c0f7f7ac
HT		 1229 if (xgene_pmu->version == PCP_PMU_V3) {
1230 intr_mcu = PCPPMU_V3_INT_MCU;
1231 intr_mcb = PCPPMU_V3_INT_MCB;
1232 intr_l3c = PCPPMU_V3_INT_L3C;
1233 intr_iob = PCPPMU_V3_INT_IOB;
1234 } else {
1235 intr_mcu = PCPPMU_INT_MCU;
1236 intr_mcb = PCPPMU_INT_MCB;
1237 intr_l3c = PCPPMU_INT_L3C;
1238 intr_iob = PCPPMU_INT_IOB;
1239 }
1240 if (val & intr_mcu) {
832c927d
TN		 1241 list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {
1242 _xgene_pmu_isr(irq, ctx->pmu_dev);
1243 }
1244 }
c0f7f7ac 1245 if (val & intr_mcb) {
832c927d
TN		 1246 list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {
1247 _xgene_pmu_isr(irq, ctx->pmu_dev);
1248 }
1249 }
c0f7f7ac 1250 if (val & intr_l3c) {
832c927d
TN		 1251 list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {
1252 _xgene_pmu_isr(irq, ctx->pmu_dev);
1253 }
1254 }
c0f7f7ac 1255 if (val & intr_iob) {
832c927d
TN		 1256 list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {
1257 _xgene_pmu_isr(irq, ctx->pmu_dev);
1258 }
1259 }
1260
8ee37e0f 1261 raw_spin_unlock(&xgene_pmu->lock);
832c927d
TN		 1262
1263 return IRQ_HANDLED;
1264}
1265
c0f7f7ac
HT		 1266static int acpi_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1267 struct platform_device *pdev)
832c927d
TN		 1268{
1269 void __iomem *csw_csr, *mcba_csr, *mcbb_csr;
832c927d
TN		 1270 unsigned int reg;
1271
7fdd7f7c 1272 csw_csr = devm_platform_ioremap_resource(pdev, 1);
832c927d
TN		 1273 if (IS_ERR(csw_csr)) {
1274 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
1275 return PTR_ERR(csw_csr);
1276 }
1277
7fdd7f7c 1278 mcba_csr = devm_platform_ioremap_resource(pdev, 2);
832c927d
TN		 1279 if (IS_ERR(mcba_csr)) {
1280 dev_err(&pdev->dev, "ioremap failed for MCBA CSR resource\n");
1281 return PTR_ERR(mcba_csr);
1282 }
1283
7fdd7f7c 1284 mcbb_csr = devm_platform_ioremap_resource(pdev, 3);
832c927d
TN		 1285 if (IS_ERR(mcbb_csr)) {
1286 dev_err(&pdev->dev, "ioremap failed for MCBB CSR resource\n");
1287 return PTR_ERR(mcbb_csr);
1288 }
1289
c0f7f7ac
HT		 1290 xgene_pmu->l3c_active_mask = 0x1;
1291
832c927d
TN		 1292 reg = readl(csw_csr + CSW_CSWCR);
1293 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1294 /* Dual MCB active */
1295 xgene_pmu->mcb_active_mask = 0x3;
1296 /* Probe all active MC(s) */
1297 reg = readl(mcbb_csr + CSW_CSWCR);
1298 xgene_pmu->mc_active_mask =
1299 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
1300 } else {
1301 /* Single MCB active */
1302 xgene_pmu->mcb_active_mask = 0x1;
1303 /* Probe all active MC(s) */
1304 reg = readl(mcba_csr + CSW_CSWCR);
1305 xgene_pmu->mc_active_mask =
1306 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
1307 }
1308
1309 return 0;
1310}
1311
c0f7f7ac
HT		 1312static int acpi_pmu_v3_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1313 struct platform_device *pdev)
1314{
1315 void __iomem *csw_csr;
c0f7f7ac
HT		 1316 unsigned int reg;
1317 u32 mcb0routing;
1318 u32 mcb1routing;
1319
7fdd7f7c 1320 csw_csr = devm_platform_ioremap_resource(pdev, 1);
c0f7f7ac
HT		 1321 if (IS_ERR(csw_csr)) {
1322 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
1323 return PTR_ERR(csw_csr);
1324 }
1325
1326 reg = readl(csw_csr + CSW_CSWCR);
1327 mcb0routing = CSW_CSWCR_MCB0_ROUTING(reg);
1328 mcb1routing = CSW_CSWCR_MCB1_ROUTING(reg);
1329 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1330 /* Dual MCB active */
1331 xgene_pmu->mcb_active_mask = 0x3;
1332 /* Probe all active L3C(s), maximum is 8 */
1333 xgene_pmu->l3c_active_mask = 0xFF;
1334 /* Probe all active MC(s), maximum is 8 */
1335 if ((mcb0routing == 0x2) && (mcb1routing == 0x2))
1336 xgene_pmu->mc_active_mask = 0xFF;
1337 else if ((mcb0routing == 0x1) && (mcb1routing == 0x1))
1338 xgene_pmu->mc_active_mask = 0x33;
1339 else
1340 xgene_pmu->mc_active_mask = 0x11;
1341 } else {
1342 /* Single MCB active */
1343 xgene_pmu->mcb_active_mask = 0x1;
1344 /* Probe all active L3C(s), maximum is 4 */
1345 xgene_pmu->l3c_active_mask = 0x0F;
1346 /* Probe all active MC(s), maximum is 4 */
1347 if (mcb0routing == 0x2)
1348 xgene_pmu->mc_active_mask = 0x0F;
1349 else if (mcb0routing == 0x1)
1350 xgene_pmu->mc_active_mask = 0x03;
1351 else
1352 xgene_pmu->mc_active_mask = 0x01;
1353 }
1354
1355 return 0;
1356}
1357
1358static int fdt_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1359 struct platform_device *pdev)
832c927d
TN		 1360{
1361 struct regmap *csw_map, *mcba_map, *mcbb_map;
1362 struct device_node *np = pdev->dev.of_node;
1363 unsigned int reg;
1364
1365 csw_map = syscon_regmap_lookup_by_phandle(np, "regmap-csw");
1366 if (IS_ERR(csw_map)) {
1367 dev_err(&pdev->dev, "unable to get syscon regmap csw\n");
1368 return PTR_ERR(csw_map);
1369 }
1370
1371 mcba_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcba");
1372 if (IS_ERR(mcba_map)) {
1373 dev_err(&pdev->dev, "unable to get syscon regmap mcba\n");
1374 return PTR_ERR(mcba_map);
1375 }
1376
1377 mcbb_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcbb");
1378 if (IS_ERR(mcbb_map)) {
1379 dev_err(&pdev->dev, "unable to get syscon regmap mcbb\n");
1380 return PTR_ERR(mcbb_map);
1381 }
1382
c0f7f7ac 1383 xgene_pmu->l3c_active_mask = 0x1;
832c927d
TN		 1384 if (regmap_read(csw_map, CSW_CSWCR, &reg))
1385 return -EINVAL;
1386
1387 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1388 /* Dual MCB active */
1389 xgene_pmu->mcb_active_mask = 0x3;
1390 /* Probe all active MC(s) */
1391 if (regmap_read(mcbb_map, MCBADDRMR, &reg))
1392 return 0;
1393 xgene_pmu->mc_active_mask =
1394 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
1395 } else {
1396 /* Single MCB active */
1397 xgene_pmu->mcb_active_mask = 0x1;
1398 /* Probe all active MC(s) */
1399 if (regmap_read(mcba_map, MCBADDRMR, &reg))
1400 return 0;
1401 xgene_pmu->mc_active_mask =
1402 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
1403 }
1404
1405 return 0;
1406}
1407
c0f7f7ac
HT		 1408static int xgene_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1409 struct platform_device *pdev)
832c927d 1410{
c0f7f7ac
HT		 1411 if (has_acpi_companion(&pdev->dev)) {
1412 if (xgene_pmu->version == PCP_PMU_V3)
1413 return acpi_pmu_v3_probe_active_mcb_mcu_l3c(xgene_pmu,
1414 pdev);
1415 else
1416 return acpi_pmu_probe_active_mcb_mcu_l3c(xgene_pmu,
1417 pdev);
1418 }
1419 return fdt_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
832c927d
TN		 1420}
1421
1422static char *xgene_pmu_dev_name(struct device *dev, u32 type, int id)
1423{
1424 switch (type) {
1425 case PMU_TYPE_L3C:
1426 return devm_kasprintf(dev, GFP_KERNEL, "l3c%d", id);
1427 case PMU_TYPE_IOB:
1428 return devm_kasprintf(dev, GFP_KERNEL, "iob%d", id);
c0f7f7ac 1429 case PMU_TYPE_IOB_SLOW:
a45fc268 1430 return devm_kasprintf(dev, GFP_KERNEL, "iob_slow%d", id);
832c927d
TN		 1431 case PMU_TYPE_MCB:
1432 return devm_kasprintf(dev, GFP_KERNEL, "mcb%d", id);
1433 case PMU_TYPE_MC:
1434 return devm_kasprintf(dev, GFP_KERNEL, "mc%d", id);
1435 default:
1436 return devm_kasprintf(dev, GFP_KERNEL, "unknown");
1437 }
1438}
1439
1440#if defined(CONFIG_ACPI)
832c927d
TN		 1441static struct
1442xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
1443 struct acpi_device *adev, u32 type)
1444{
1445 struct device *dev = xgene_pmu->dev;
1446 struct list_head resource_list;
1447 struct xgene_pmu_dev_ctx *ctx;
1448 const union acpi_object *obj;
1449 struct hw_pmu_info *inf;
1450 void __iomem *dev_csr;
1451 struct resource res;
a76b8236 1452 struct resource_entry *rentry;
832c927d
TN		 1453 int enable_bit;
1454 int rc;
1455
1456 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1457 if (!ctx)
1458 return NULL;
1459
1460 INIT_LIST_HEAD(&resource_list);
a76b8236
MS		 1461 rc = acpi_dev_get_resources(adev, &resource_list, NULL, NULL);
1462 if (rc <= 0) {
1463 dev_err(dev, "PMU type %d: No resources found\n", type);
1464 return NULL;
1465 }
1466
1467 list_for_each_entry(rentry, &resource_list, node) {
1468 if (resource_type(rentry->res) == IORESOURCE_MEM) {
1469 res = *rentry->res;
1470 rentry = NULL;
1471 break;
1472 }
1473 }
832c927d 1474 acpi_dev_free_resource_list(&resource_list);
a76b8236
MS		 1475
1476 if (rentry) {
1477 dev_err(dev, "PMU type %d: No memory resource found\n", type);
c1be2ddb 1478 return NULL;
832c927d
TN		 1479 }
1480
1481 dev_csr = devm_ioremap_resource(dev, &res);
1482 if (IS_ERR(dev_csr)) {
1483 dev_err(dev, "PMU type %d: Fail to map resource\n", type);
c1be2ddb 1484 return NULL;
832c927d
TN		 1485 }
1486
1487 /* A PMU device node without enable-bit-index is always enabled */
1488 rc = acpi_dev_get_property(adev, "enable-bit-index",
1489 ACPI_TYPE_INTEGER, &obj);
1490 if (rc < 0)
1491 enable_bit = 0;
1492 else
1493 enable_bit = (int) obj->integer.value;
1494
1495 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1496 if (!ctx->name) {
1497 dev_err(dev, "PMU type %d: Fail to get device name\n", type);
c1be2ddb 1498 return NULL;
832c927d
TN		 1499 }
1500 inf = &ctx->inf;
1501 inf->type = type;
1502 inf->csr = dev_csr;
1503 inf->enable_mask = 1 << enable_bit;
1504
1505 return ctx;
832c927d
TN		 1506}
1507
838955e2
HT		 1508static const struct acpi_device_id xgene_pmu_acpi_type_match[] = {
1509 {"APMC0D5D", PMU_TYPE_L3C},
1510 {"APMC0D5E", PMU_TYPE_IOB},
1511 {"APMC0D5F", PMU_TYPE_MCB},
1512 {"APMC0D60", PMU_TYPE_MC},
c0f7f7ac
HT		 1513 {"APMC0D84", PMU_TYPE_L3C},
1514 {"APMC0D85", PMU_TYPE_IOB},
1515 {"APMC0D86", PMU_TYPE_IOB_SLOW},
1516 {"APMC0D87", PMU_TYPE_MCB},
1517 {"APMC0D88", PMU_TYPE_MC},
838955e2
HT		 1518 {},
1519};
1520
1521static const struct acpi_device_id *xgene_pmu_acpi_match_type(
1522 const struct acpi_device_id *ids,
1523 struct acpi_device *adev)
1524{
1525 const struct acpi_device_id *match_id = NULL;
1526 const struct acpi_device_id *id;
1527
1528 for (id = ids; id->id[0] || id->cls; id++) {
1529 if (!acpi_match_device_ids(adev, id))
1530 match_id = id;
1531 else if (match_id)
1532 break;
1533 }
1534
1535 return match_id;
1536}
1537
832c927d
TN		 1538static acpi_status acpi_pmu_dev_add(acpi_handle handle, u32 level,
1539 void *data, void **return_value)
1540{
602c873e 1541 struct acpi_device *adev = acpi_fetch_acpi_dev(handle);
838955e2 1542 const struct acpi_device_id *acpi_id;
832c927d
TN		 1543 struct xgene_pmu *xgene_pmu = data;
1544 struct xgene_pmu_dev_ctx *ctx;
832c927d 1545
602c873e 1546 if (!adev || acpi_bus_get_status(adev) || !adev->status.present)
832c927d
TN		 1547 return AE_OK;
1548
838955e2
HT		 1549 acpi_id = xgene_pmu_acpi_match_type(xgene_pmu_acpi_type_match, adev);
1550 if (!acpi_id)
1551 return AE_OK;
832c927d 1552
838955e2 1553 ctx = acpi_get_pmu_hw_inf(xgene_pmu, adev, (u32)acpi_id->driver_data);
832c927d
TN		 1554 if (!ctx)
1555 return AE_OK;
1556
1557 if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
1558 /* Can't add the PMU device, skip it */
1559 devm_kfree(xgene_pmu->dev, ctx);
1560 return AE_OK;
1561 }
1562
1563 switch (ctx->inf.type) {
1564 case PMU_TYPE_L3C:
1565 list_add(&ctx->next, &xgene_pmu->l3cpmus);
1566 break;
1567 case PMU_TYPE_IOB:
1568 list_add(&ctx->next, &xgene_pmu->iobpmus);
1569 break;
c0f7f7ac
HT		 1570 case PMU_TYPE_IOB_SLOW:
1571 list_add(&ctx->next, &xgene_pmu->iobpmus);
1572 break;
832c927d
TN		 1573 case PMU_TYPE_MCB:
1574 list_add(&ctx->next, &xgene_pmu->mcbpmus);
1575 break;
1576 case PMU_TYPE_MC:
1577 list_add(&ctx->next, &xgene_pmu->mcpmus);
1578 break;
1579 }
1580 return AE_OK;
1581}
1582
1583static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1584 struct platform_device *pdev)
1585{
1586 struct device *dev = xgene_pmu->dev;
1587 acpi_handle handle;
1588 acpi_status status;
1589
1590 handle = ACPI_HANDLE(dev);
1591 if (!handle)
1592 return -EINVAL;
1593
1594 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1595 acpi_pmu_dev_add, NULL, xgene_pmu, NULL);
1596 if (ACPI_FAILURE(status)) {
1597 dev_err(dev, "failed to probe PMU devices\n");
1598 return -ENODEV;
1599 }
1600
1601 return 0;
1602}
1603#else
1604static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1605 struct platform_device *pdev)
1606{
1607 return 0;
1608}
1609#endif
1610
1611static struct
1612xgene_pmu_dev_ctx *fdt_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
1613 struct device_node *np, u32 type)
1614{
1615 struct device *dev = xgene_pmu->dev;
1616 struct xgene_pmu_dev_ctx *ctx;
1617 struct hw_pmu_info *inf;
1618 void __iomem *dev_csr;
1619 struct resource res;
1620 int enable_bit;
832c927d
TN		 1621
1622 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1623 if (!ctx)
1624 return NULL;
c1be2ddb
TN		 1625
1626 if (of_address_to_resource(np, 0, &res) < 0) {
832c927d 1627 dev_err(dev, "PMU type %d: No resource address found\n", type);
c1be2ddb 1628 return NULL;
832c927d 1629 }
c1be2ddb 1630
832c927d
TN		 1631 dev_csr = devm_ioremap_resource(dev, &res);
1632 if (IS_ERR(dev_csr)) {
1633 dev_err(dev, "PMU type %d: Fail to map resource\n", type);
c1be2ddb 1634 return NULL;
832c927d
TN		 1635 }
1636
1637 /* A PMU device node without enable-bit-index is always enabled */
1638 if (of_property_read_u32(np, "enable-bit-index", &enable_bit))
1639 enable_bit = 0;
1640
1641 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1642 if (!ctx->name) {
1643 dev_err(dev, "PMU type %d: Fail to get device name\n", type);
c1be2ddb 1644 return NULL;
832c927d 1645 }
c1be2ddb 1646
832c927d
TN		 1647 inf = &ctx->inf;
1648 inf->type = type;
1649 inf->csr = dev_csr;
1650 inf->enable_mask = 1 << enable_bit;
1651
1652 return ctx;
832c927d
TN		 1653}
1654
1655static int fdt_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1656 struct platform_device *pdev)
1657{
1658 struct xgene_pmu_dev_ctx *ctx;
1659 struct device_node *np;
1660
1661 for_each_child_of_node(pdev->dev.of_node, np) {
1662 if (!of_device_is_available(np))
1663 continue;
1664
1665 if (of_device_is_compatible(np, "apm,xgene-pmu-l3c"))
1666 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_L3C);
1667 else if (of_device_is_compatible(np, "apm,xgene-pmu-iob"))
1668 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_IOB);
1669 else if (of_device_is_compatible(np, "apm,xgene-pmu-mcb"))
1670 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MCB);
1671 else if (of_device_is_compatible(np, "apm,xgene-pmu-mc"))
1672 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MC);
1673 else
1674 ctx = NULL;
1675
1676 if (!ctx)
1677 continue;
1678
1679 if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
1680 /* Can't add the PMU device, skip it */
1681 devm_kfree(xgene_pmu->dev, ctx);
1682 continue;
1683 }
1684
1685 switch (ctx->inf.type) {
1686 case PMU_TYPE_L3C:
1687 list_add(&ctx->next, &xgene_pmu->l3cpmus);
1688 break;
1689 case PMU_TYPE_IOB:
1690 list_add(&ctx->next, &xgene_pmu->iobpmus);
1691 break;
c0f7f7ac
HT		 1692 case PMU_TYPE_IOB_SLOW:
1693 list_add(&ctx->next, &xgene_pmu->iobpmus);
1694 break;
832c927d
TN		 1695 case PMU_TYPE_MCB:
1696 list_add(&ctx->next, &xgene_pmu->mcbpmus);
1697 break;
1698 case PMU_TYPE_MC:
1699 list_add(&ctx->next, &xgene_pmu->mcpmus);
1700 break;
1701 }
1702 }
1703
1704 return 0;
1705}
1706
1707static int xgene_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1708 struct platform_device *pdev)
1709{
1710 if (has_acpi_companion(&pdev->dev))
1711 return acpi_pmu_probe_pmu_dev(xgene_pmu, pdev);
1712 return fdt_pmu_probe_pmu_dev(xgene_pmu, pdev);
1713}
1714
1715static const struct xgene_pmu_data xgene_pmu_data = {
1716 .id = PCP_PMU_V1,
1717};
1718
1719static const struct xgene_pmu_data xgene_pmu_v2_data = {
1720 .id = PCP_PMU_V2,
1721};
1722
1f33cdef
RH		 1723#ifdef CONFIG_ACPI
1724static const struct xgene_pmu_data xgene_pmu_v3_data = {
1725 .id = PCP_PMU_V3,
1726};
1727#endif
1728
e35e0a04
HT		 1729static const struct xgene_pmu_ops xgene_pmu_ops = {
1730 .mask_int = xgene_pmu_mask_int,
1731 .unmask_int = xgene_pmu_unmask_int,
1732 .read_counter = xgene_pmu_read_counter32,
1733 .write_counter = xgene_pmu_write_counter32,
1734 .write_evttype = xgene_pmu_write_evttype,
1735 .write_agentmsk = xgene_pmu_write_agentmsk,
1736 .write_agent1msk = xgene_pmu_write_agent1msk,
1737 .enable_counter = xgene_pmu_enable_counter,
1738 .disable_counter = xgene_pmu_disable_counter,
1739 .enable_counter_int = xgene_pmu_enable_counter_int,
1740 .disable_counter_int = xgene_pmu_disable_counter_int,
1741 .reset_counters = xgene_pmu_reset_counters,
1742 .start_counters = xgene_pmu_start_counters,
1743 .stop_counters = xgene_pmu_stop_counters,
1744};
1745
c0f7f7ac
HT		 1746static const struct xgene_pmu_ops xgene_pmu_v3_ops = {
1747 .mask_int = xgene_pmu_v3_mask_int,
1748 .unmask_int = xgene_pmu_v3_unmask_int,
1749 .read_counter = xgene_pmu_read_counter64,
1750 .write_counter = xgene_pmu_write_counter64,
1751 .write_evttype = xgene_pmu_write_evttype,
1752 .write_agentmsk = xgene_pmu_v3_write_agentmsk,
1753 .write_agent1msk = xgene_pmu_v3_write_agent1msk,
1754 .enable_counter = xgene_pmu_enable_counter,
1755 .disable_counter = xgene_pmu_disable_counter,
1756 .enable_counter_int = xgene_pmu_enable_counter_int,
1757 .disable_counter_int = xgene_pmu_disable_counter_int,
1758 .reset_counters = xgene_pmu_reset_counters,
1759 .start_counters = xgene_pmu_start_counters,
1760 .stop_counters = xgene_pmu_stop_counters,
1761};
1762
832c927d
TN		 1763static const struct of_device_id xgene_pmu_of_match[] = {
1764 { .compatible = "apm,xgene-pmu", .data = &xgene_pmu_data },
1765 { .compatible = "apm,xgene-pmu-v2", .data = &xgene_pmu_v2_data },
1766 {},
1767};
1768MODULE_DEVICE_TABLE(of, xgene_pmu_of_match);
1769#ifdef CONFIG_ACPI
1770static const struct acpi_device_id xgene_pmu_acpi_match[] = {
1f33cdef
RH		 1771 {"APMC0D5B", (kernel_ulong_t)&xgene_pmu_data},
1772 {"APMC0D5C", (kernel_ulong_t)&xgene_pmu_v2_data},
1773 {"APMC0D83", (kernel_ulong_t)&xgene_pmu_v3_data},
832c927d
TN		 1774 {},
1775};
1776MODULE_DEVICE_TABLE(acpi, xgene_pmu_acpi_match);
1777#endif
1778
cbb72a3c
HT		 1779static int xgene_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
1780{
1781 struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,
1782 node);
1783
1784 if (cpumask_empty(&xgene_pmu->cpu))
1785 cpumask_set_cpu(cpu, &xgene_pmu->cpu);
1786
1787 /* Overflow interrupt also should use the same CPU */
1788 WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));
1789
1790 return 0;
1791}
1792
1793static int xgene_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
1794{
1795 struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,
1796 node);
1797 struct xgene_pmu_dev_ctx *ctx;
1798 unsigned int target;
1799
1800 if (!cpumask_test_and_clear_cpu(cpu, &xgene_pmu->cpu))
1801 return 0;
1802 target = cpumask_any_but(cpu_online_mask, cpu);
1803 if (target >= nr_cpu_ids)
1804 return 0;
1805
1806 list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {
1807 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1808 }
1809 list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {
1810 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1811 }
1812 list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {
1813 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1814 }
1815 list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {
1816 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1817 }
1818
1819 cpumask_set_cpu(target, &xgene_pmu->cpu);
1820 /* Overflow interrupt also should use the same CPU */
1821 WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));
1822
1823 return 0;
1824}
1825
832c927d
TN		 1826static int xgene_pmu_probe(struct platform_device *pdev)
1827{
1828 const struct xgene_pmu_data *dev_data;
832c927d 1829 struct xgene_pmu *xgene_pmu;
832c927d
TN		 1830 int irq, rc;
1831 int version;
1832
cbb72a3c
HT		 1833 /* Install a hook to update the reader CPU in case it goes offline */
1834 rc = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1835 "CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE",
1836 xgene_pmu_online_cpu,
1837 xgene_pmu_offline_cpu);
1838 if (rc)
1839 return rc;
1840
832c927d
TN		 1841 xgene_pmu = devm_kzalloc(&pdev->dev, sizeof(*xgene_pmu), GFP_KERNEL);
1842 if (!xgene_pmu)
1843 return -ENOMEM;
1844 xgene_pmu->dev = &pdev->dev;
1845 platform_set_drvdata(pdev, xgene_pmu);
1846
1f33cdef
RH		 1847 dev_data = device_get_match_data(&pdev->dev);
1848 if (!dev_data)
832c927d 1849 return -ENODEV;
1f33cdef 1850 version = dev_data->id;
832c927d 1851
c0f7f7ac
HT		 1852 if (version == PCP_PMU_V3)
1853 xgene_pmu->ops = &xgene_pmu_v3_ops;
1854 else
1855 xgene_pmu->ops = &xgene_pmu_ops;
e35e0a04 1856
832c927d
TN		 1857 INIT_LIST_HEAD(&xgene_pmu->l3cpmus);
1858 INIT_LIST_HEAD(&xgene_pmu->iobpmus);
1859 INIT_LIST_HEAD(&xgene_pmu->mcbpmus);
1860 INIT_LIST_HEAD(&xgene_pmu->mcpmus);
1861
1862 xgene_pmu->version = version;
1863 dev_info(&pdev->dev, "X-Gene PMU version %d\n", xgene_pmu->version);
1864
c47ea342 1865 xgene_pmu->pcppmu_csr = devm_platform_ioremap_resource(pdev, 0);
832c927d
TN		 1866 if (IS_ERR(xgene_pmu->pcppmu_csr)) {
1867 dev_err(&pdev->dev, "ioremap failed for PCP PMU resource\n");
c1be2ddb 1868 return PTR_ERR(xgene_pmu->pcppmu_csr);
832c927d
TN		 1869 }
1870
1871 irq = platform_get_irq(pdev, 0);
228f855f 1872 if (irq < 0)
c1be2ddb 1873 return -EINVAL;
cbb72a3c 1874
832c927d
TN		 1875 rc = devm_request_irq(&pdev->dev, irq, xgene_pmu_isr,
1876 IRQF_NOBALANCING | IRQF_NO_THREAD,
1877 dev_name(&pdev->dev), xgene_pmu);
1878 if (rc) {
1879 dev_err(&pdev->dev, "Could not request IRQ %d\n", irq);
c1be2ddb 1880 return rc;
832c927d
TN		 1881 }
1882
cbb72a3c
HT		 1883 xgene_pmu->irq = irq;
1884
832c927d
TN		 1885 raw_spin_lock_init(&xgene_pmu->lock);
1886
1887 /* Check for active MCBs and MCUs */
c0f7f7ac 1888 rc = xgene_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
832c927d
TN		 1889 if (rc) {
1890 dev_warn(&pdev->dev, "Unknown MCB/MCU active status\n");
1891 xgene_pmu->mcb_active_mask = 0x1;
1892 xgene_pmu->mc_active_mask = 0x1;
1893 }
1894
cbb72a3c
HT		 1895 /* Add this instance to the list used by the hotplug callback */
1896 rc = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1897 &xgene_pmu->node);
832c927d 1898 if (rc) {
cbb72a3c 1899 dev_err(&pdev->dev, "Error %d registering hotplug", rc);
c1be2ddb 1900 return rc;
832c927d
TN		 1901 }
1902
1903 /* Walk through the tree for all PMU perf devices */
1904 rc = xgene_pmu_probe_pmu_dev(xgene_pmu, pdev);
1905 if (rc) {
1906 dev_err(&pdev->dev, "No PMU perf devices found!\n");
cbb72a3c 1907 goto out_unregister;
832c927d
TN		 1908 }
1909
1910 /* Enable interrupt */
e35e0a04 1911 xgene_pmu->ops->unmask_int(xgene_pmu);
832c927d
TN		 1912
1913 return 0;
cbb72a3c
HT		 1914
1915out_unregister:
1916 cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1917 &xgene_pmu->node);
1918 return rc;
832c927d
TN		 1919}
1920
1921static void
1922xgene_pmu_dev_cleanup(struct xgene_pmu *xgene_pmu, struct list_head *pmus)
1923{
1924 struct xgene_pmu_dev_ctx *ctx;
832c927d
TN		 1925
1926 list_for_each_entry(ctx, pmus, next) {
c1be2ddb 1927 perf_pmu_unregister(&ctx->pmu_dev->pmu);
832c927d
TN		 1928 }
1929}
1930
b07ebe8f 1931static void xgene_pmu_remove(struct platform_device *pdev)
832c927d
TN		 1932{
1933 struct xgene_pmu *xgene_pmu = dev_get_drvdata(&pdev->dev);
1934
1935 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->l3cpmus);
1936 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->iobpmus);
1937 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcbpmus);
1938 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcpmus);
cbb72a3c
HT		 1939 cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1940 &xgene_pmu->node);
832c927d
TN		 1941}
1942
1943static struct platform_driver xgene_pmu_driver = {
1944 .probe = xgene_pmu_probe,
b07ebe8f 1945 .remove_new = xgene_pmu_remove,
832c927d
TN		 1946 .driver = {
1947 .name = "xgene-pmu",
1948 .of_match_table = xgene_pmu_of_match,
1949 .acpi_match_table = ACPI_PTR(xgene_pmu_acpi_match),
f32ed8eb 1950 .suppress_bind_attrs = true,
832c927d
TN		 1951 },
1952};
1953
1954builtin_platform_driver(xgene_pmu_driver);
Linux 6.x block layer and io_uring tree(s)