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powerpc/mm: Drop the unnecessary region check
[linux-2.6-block.git] / drivers / perf / xgene_pmu.c
CommitLineData
832c927d
TN		 1/*
2 * APM X-Gene SoC PMU (Performance Monitor Unit)
3 *
4 * Copyright (c) 2016, Applied Micro Circuits Corporation
5 * Author: Hoan Tran <hotran@apm.com>
6 * Tai Nguyen <ttnguyen@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/acpi.h>
23#include <linux/clk.h>
cbb72a3c 24#include <linux/cpuhotplug.h>
832c927d
TN		 25#include <linux/cpumask.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/mfd/syscon.h>
c0bfc549 29#include <linux/module.h>
832c927d
TN		 30#include <linux/of_address.h>
31#include <linux/of_fdt.h>
32#include <linux/of_irq.h>
33#include <linux/of_platform.h>
34#include <linux/perf_event.h>
35#include <linux/platform_device.h>
36#include <linux/regmap.h>
37#include <linux/slab.h>
38
39#define CSW_CSWCR 0x0000
40#define CSW_CSWCR_DUALMCB_MASK BIT(0)
c0f7f7ac
HT		 41#define CSW_CSWCR_MCB0_ROUTING(x) (((x) & 0x0C) >> 2)
42#define CSW_CSWCR_MCB1_ROUTING(x) (((x) & 0x30) >> 4)
832c927d
TN		 43#define MCBADDRMR 0x0000
44#define MCBADDRMR_DUALMCU_MODE_MASK BIT(2)
45
46#define PCPPMU_INTSTATUS_REG 0x000
47#define PCPPMU_INTMASK_REG 0x004
48#define PCPPMU_INTMASK 0x0000000F
49#define PCPPMU_INTENMASK 0xFFFFFFFF
50#define PCPPMU_INTCLRMASK 0xFFFFFFF0
51#define PCPPMU_INT_MCU BIT(0)
52#define PCPPMU_INT_MCB BIT(1)
53#define PCPPMU_INT_L3C BIT(2)
54#define PCPPMU_INT_IOB BIT(3)
55
c0f7f7ac
HT		 56#define PCPPMU_V3_INTMASK 0x00FF33FF
57#define PCPPMU_V3_INTENMASK 0xFFFFFFFF
58#define PCPPMU_V3_INTCLRMASK 0xFF00CC00
59#define PCPPMU_V3_INT_MCU 0x000000FF
60#define PCPPMU_V3_INT_MCB 0x00000300
61#define PCPPMU_V3_INT_L3C 0x00FF0000
62#define PCPPMU_V3_INT_IOB 0x00003000
63
832c927d 64#define PMU_MAX_COUNTERS 4
c0f7f7ac
HT		 65#define PMU_CNT_MAX_PERIOD 0xFFFFFFFFULL
66#define PMU_V3_CNT_MAX_PERIOD 0xFFFFFFFFFFFFFFFFULL
832c927d
TN		 67#define PMU_OVERFLOW_MASK 0xF
68#define PMU_PMCR_E BIT(0)
69#define PMU_PMCR_P BIT(1)
70
71#define PMU_PMEVCNTR0 0x000
72#define PMU_PMEVCNTR1 0x004
73#define PMU_PMEVCNTR2 0x008
74#define PMU_PMEVCNTR3 0x00C
75#define PMU_PMEVTYPER0 0x400
76#define PMU_PMEVTYPER1 0x404
77#define PMU_PMEVTYPER2 0x408
78#define PMU_PMEVTYPER3 0x40C
79#define PMU_PMAMR0 0xA00
80#define PMU_PMAMR1 0xA04
81#define PMU_PMCNTENSET 0xC00
82#define PMU_PMCNTENCLR 0xC20
83#define PMU_PMINTENSET 0xC40
84#define PMU_PMINTENCLR 0xC60
85#define PMU_PMOVSR 0xC80
86#define PMU_PMCR 0xE04
87
c0f7f7ac
HT		 88/* PMU registers for V3 */
89#define PMU_PMOVSCLR 0xC80
90#define PMU_PMOVSSET 0xCC0
91
832c927d
TN		 92#define to_pmu_dev(p) container_of(p, struct xgene_pmu_dev, pmu)
93#define GET_CNTR(ev) (ev->hw.idx)
94#define GET_EVENTID(ev) (ev->hw.config & 0xFFULL)
95#define GET_AGENTID(ev) (ev->hw.config_base & 0xFFFFFFFFUL)
96#define GET_AGENT1ID(ev) ((ev->hw.config_base >> 32) & 0xFFFFFFFFUL)
97
98struct hw_pmu_info {
99 u32 type;
100 u32 enable_mask;
101 void __iomem *csr;
102};
103
104struct xgene_pmu_dev {
105 struct hw_pmu_info *inf;
106 struct xgene_pmu *parent;
107 struct pmu pmu;
108 u8 max_counters;
109 DECLARE_BITMAP(cntr_assign_mask, PMU_MAX_COUNTERS);
110 u64 max_period;
111 const struct attribute_group **attr_groups;
112 struct perf_event *pmu_counter_event[PMU_MAX_COUNTERS];
113};
114
e35e0a04
HT		 115struct xgene_pmu_ops {
116 void (*mask_int)(struct xgene_pmu *pmu);
117 void (*unmask_int)(struct xgene_pmu *pmu);
118 u64 (*read_counter)(struct xgene_pmu_dev *pmu, int idx);
119 void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val);
120 void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val);
121 void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val);
122 void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val);
123 void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
124 void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
125 void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
126 void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
127 void (*reset_counters)(struct xgene_pmu_dev *pmu_dev);
128 void (*start_counters)(struct xgene_pmu_dev *pmu_dev);
129 void (*stop_counters)(struct xgene_pmu_dev *pmu_dev);
130};
131
832c927d
TN		 132struct xgene_pmu {
133 struct device *dev;
cbb72a3c 134 struct hlist_node node;
832c927d
TN		 135 int version;
136 void __iomem *pcppmu_csr;
137 u32 mcb_active_mask;
138 u32 mc_active_mask;
c0f7f7ac 139 u32 l3c_active_mask;
832c927d 140 cpumask_t cpu;
cbb72a3c 141 int irq;
832c927d 142 raw_spinlock_t lock;
e35e0a04 143 const struct xgene_pmu_ops *ops;
832c927d
TN		 144 struct list_head l3cpmus;
145 struct list_head iobpmus;
146 struct list_head mcbpmus;
147 struct list_head mcpmus;
148};
149
150struct xgene_pmu_dev_ctx {
151 char *name;
152 struct list_head next;
153 struct xgene_pmu_dev *pmu_dev;
154 struct hw_pmu_info inf;
155};
156
157struct xgene_pmu_data {
158 int id;
159 u32 data;
160};
161
162enum xgene_pmu_version {
163 PCP_PMU_V1 = 1,
164 PCP_PMU_V2,
c0f7f7ac 165 PCP_PMU_V3,
832c927d
TN		 166};
167
168enum xgene_pmu_dev_type {
169 PMU_TYPE_L3C = 0,
170 PMU_TYPE_IOB,
c0f7f7ac 171 PMU_TYPE_IOB_SLOW,
832c927d
TN		 172 PMU_TYPE_MCB,
173 PMU_TYPE_MC,
174};
175
176/*
177 * sysfs format attributes
178 */
179static ssize_t xgene_pmu_format_show(struct device *dev,
180 struct device_attribute *attr, char *buf)
181{
182 struct dev_ext_attribute *eattr;
183
184 eattr = container_of(attr, struct dev_ext_attribute, attr);
185 return sprintf(buf, "%s\n", (char *) eattr->var);
186}
187
188#define XGENE_PMU_FORMAT_ATTR(_name, _config) \
189 (&((struct dev_ext_attribute[]) { \
190 { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_format_show, NULL), \
191 .var = (void *) _config, } \
192 })[0].attr.attr)
193
194static struct attribute *l3c_pmu_format_attrs[] = {
195 XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-7"),
196 XGENE_PMU_FORMAT_ATTR(l3c_agentid, "config1:0-9"),
197 NULL,
198};
199
200static struct attribute *iob_pmu_format_attrs[] = {
201 XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-7"),
202 XGENE_PMU_FORMAT_ATTR(iob_agentid, "config1:0-63"),
203 NULL,
204};
205
206static struct attribute *mcb_pmu_format_attrs[] = {
207 XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-5"),
208 XGENE_PMU_FORMAT_ATTR(mcb_agentid, "config1:0-9"),
209 NULL,
210};
211
212static struct attribute *mc_pmu_format_attrs[] = {
213 XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-28"),
214 NULL,
215};
216
217static const struct attribute_group l3c_pmu_format_attr_group = {
218 .name = "format",
219 .attrs = l3c_pmu_format_attrs,
220};
221
222static const struct attribute_group iob_pmu_format_attr_group = {
223 .name = "format",
224 .attrs = iob_pmu_format_attrs,
225};
226
227static const struct attribute_group mcb_pmu_format_attr_group = {
228 .name = "format",
229 .attrs = mcb_pmu_format_attrs,
230};
231
232static const struct attribute_group mc_pmu_format_attr_group = {
233 .name = "format",
234 .attrs = mc_pmu_format_attrs,
235};
236
c0f7f7ac
HT		 237static struct attribute *l3c_pmu_v3_format_attrs[] = {
238 XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-39"),
239 NULL,
240};
241
242static struct attribute *iob_pmu_v3_format_attrs[] = {
243 XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-47"),
244 NULL,
245};
246
247static struct attribute *iob_slow_pmu_v3_format_attrs[] = {
248 XGENE_PMU_FORMAT_ATTR(iob_slow_eventid, "config:0-16"),
249 NULL,
250};
251
252static struct attribute *mcb_pmu_v3_format_attrs[] = {
253 XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-35"),
254 NULL,
255};
256
257static struct attribute *mc_pmu_v3_format_attrs[] = {
258 XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-44"),
259 NULL,
260};
261
262static const struct attribute_group l3c_pmu_v3_format_attr_group = {
263 .name = "format",
264 .attrs = l3c_pmu_v3_format_attrs,
265};
266
267static const struct attribute_group iob_pmu_v3_format_attr_group = {
268 .name = "format",
269 .attrs = iob_pmu_v3_format_attrs,
270};
271
272static const struct attribute_group iob_slow_pmu_v3_format_attr_group = {
273 .name = "format",
274 .attrs = iob_slow_pmu_v3_format_attrs,
275};
276
277static const struct attribute_group mcb_pmu_v3_format_attr_group = {
278 .name = "format",
279 .attrs = mcb_pmu_v3_format_attrs,
280};
281
282static const struct attribute_group mc_pmu_v3_format_attr_group = {
283 .name = "format",
284 .attrs = mc_pmu_v3_format_attrs,
285};
286
832c927d
TN		 287/*
288 * sysfs event attributes
289 */
290static ssize_t xgene_pmu_event_show(struct device *dev,
291 struct device_attribute *attr, char *buf)
292{
293 struct dev_ext_attribute *eattr;
294
295 eattr = container_of(attr, struct dev_ext_attribute, attr);
296 return sprintf(buf, "config=0x%lx\n", (unsigned long) eattr->var);
297}
298
299#define XGENE_PMU_EVENT_ATTR(_name, _config) \
300 (&((struct dev_ext_attribute[]) { \
301 { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_event_show, NULL), \
302 .var = (void *) _config, } \
303 })[0].attr.attr)
304
305static struct attribute *l3c_pmu_events_attrs[] = {
306 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
307 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
308 XGENE_PMU_EVENT_ATTR(read-hit, 0x02),
309 XGENE_PMU_EVENT_ATTR(read-miss, 0x03),
310 XGENE_PMU_EVENT_ATTR(write-need-replacement, 0x06),
311 XGENE_PMU_EVENT_ATTR(write-not-need-replacement, 0x07),
312 XGENE_PMU_EVENT_ATTR(tq-full, 0x08),
313 XGENE_PMU_EVENT_ATTR(ackq-full, 0x09),
314 XGENE_PMU_EVENT_ATTR(wdb-full, 0x0a),
315 XGENE_PMU_EVENT_ATTR(bank-fifo-full, 0x0b),
316 XGENE_PMU_EVENT_ATTR(odb-full, 0x0c),
317 XGENE_PMU_EVENT_ATTR(wbq-full, 0x0d),
318 XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue, 0x0e),
319 XGENE_PMU_EVENT_ATTR(bank-fifo-issue, 0x0f),
320 NULL,
321};
322
323static struct attribute *iob_pmu_events_attrs[] = {
324 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
325 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
326 XGENE_PMU_EVENT_ATTR(axi0-read, 0x02),
327 XGENE_PMU_EVENT_ATTR(axi0-read-partial, 0x03),
328 XGENE_PMU_EVENT_ATTR(axi1-read, 0x04),
329 XGENE_PMU_EVENT_ATTR(axi1-read-partial, 0x05),
330 XGENE_PMU_EVENT_ATTR(csw-read-block, 0x06),
331 XGENE_PMU_EVENT_ATTR(csw-read-partial, 0x07),
332 XGENE_PMU_EVENT_ATTR(axi0-write, 0x10),
333 XGENE_PMU_EVENT_ATTR(axi0-write-partial, 0x11),
334 XGENE_PMU_EVENT_ATTR(axi1-write, 0x13),
335 XGENE_PMU_EVENT_ATTR(axi1-write-partial, 0x14),
336 XGENE_PMU_EVENT_ATTR(csw-inbound-dirty, 0x16),
337 NULL,
338};
339
340static struct attribute *mcb_pmu_events_attrs[] = {
341 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
342 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
343 XGENE_PMU_EVENT_ATTR(csw-read, 0x02),
344 XGENE_PMU_EVENT_ATTR(csw-write-request, 0x03),
345 XGENE_PMU_EVENT_ATTR(mcb-csw-stall, 0x04),
346 XGENE_PMU_EVENT_ATTR(cancel-read-gack, 0x05),
347 NULL,
348};
349
350static struct attribute *mc_pmu_events_attrs[] = {
351 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
352 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
353 XGENE_PMU_EVENT_ATTR(act-cmd-sent, 0x02),
354 XGENE_PMU_EVENT_ATTR(pre-cmd-sent, 0x03),
355 XGENE_PMU_EVENT_ATTR(rd-cmd-sent, 0x04),
356 XGENE_PMU_EVENT_ATTR(rda-cmd-sent, 0x05),
357 XGENE_PMU_EVENT_ATTR(wr-cmd-sent, 0x06),
358 XGENE_PMU_EVENT_ATTR(wra-cmd-sent, 0x07),
359 XGENE_PMU_EVENT_ATTR(pde-cmd-sent, 0x08),
360 XGENE_PMU_EVENT_ATTR(sre-cmd-sent, 0x09),
361 XGENE_PMU_EVENT_ATTR(prea-cmd-sent, 0x0a),
362 XGENE_PMU_EVENT_ATTR(ref-cmd-sent, 0x0b),
363 XGENE_PMU_EVENT_ATTR(rd-rda-cmd-sent, 0x0c),
364 XGENE_PMU_EVENT_ATTR(wr-wra-cmd-sent, 0x0d),
365 XGENE_PMU_EVENT_ATTR(in-rd-collision, 0x0e),
366 XGENE_PMU_EVENT_ATTR(in-wr-collision, 0x0f),
367 XGENE_PMU_EVENT_ATTR(collision-queue-not-empty, 0x10),
368 XGENE_PMU_EVENT_ATTR(collision-queue-full, 0x11),
369 XGENE_PMU_EVENT_ATTR(mcu-request, 0x12),
370 XGENE_PMU_EVENT_ATTR(mcu-rd-request, 0x13),
371 XGENE_PMU_EVENT_ATTR(mcu-hp-rd-request, 0x14),
372 XGENE_PMU_EVENT_ATTR(mcu-wr-request, 0x15),
373 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-all, 0x16),
374 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-cancel, 0x17),
375 XGENE_PMU_EVENT_ATTR(mcu-rd-response, 0x18),
376 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-all, 0x19),
377 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-cancel, 0x1a),
378 XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-all, 0x1b),
379 XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-cancel, 0x1c),
380 NULL,
381};
382
383static const struct attribute_group l3c_pmu_events_attr_group = {
384 .name = "events",
385 .attrs = l3c_pmu_events_attrs,
386};
387
388static const struct attribute_group iob_pmu_events_attr_group = {
389 .name = "events",
390 .attrs = iob_pmu_events_attrs,
391};
392
393static const struct attribute_group mcb_pmu_events_attr_group = {
394 .name = "events",
395 .attrs = mcb_pmu_events_attrs,
396};
397
398static const struct attribute_group mc_pmu_events_attr_group = {
399 .name = "events",
400 .attrs = mc_pmu_events_attrs,
401};
402
c0f7f7ac
HT		 403static struct attribute *l3c_pmu_v3_events_attrs[] = {
404 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
405 XGENE_PMU_EVENT_ATTR(read-hit, 0x01),
406 XGENE_PMU_EVENT_ATTR(read-miss, 0x02),
407 XGENE_PMU_EVENT_ATTR(index-flush-eviction, 0x03),
408 XGENE_PMU_EVENT_ATTR(write-caused-replacement, 0x04),
409 XGENE_PMU_EVENT_ATTR(write-not-caused-replacement, 0x05),
410 XGENE_PMU_EVENT_ATTR(clean-eviction, 0x06),
411 XGENE_PMU_EVENT_ATTR(dirty-eviction, 0x07),
412 XGENE_PMU_EVENT_ATTR(read, 0x08),
413 XGENE_PMU_EVENT_ATTR(write, 0x09),
414 XGENE_PMU_EVENT_ATTR(request, 0x0a),
415 XGENE_PMU_EVENT_ATTR(tq-bank-conflict-issue-stall, 0x0b),
416 XGENE_PMU_EVENT_ATTR(tq-full, 0x0c),
417 XGENE_PMU_EVENT_ATTR(ackq-full, 0x0d),
418 XGENE_PMU_EVENT_ATTR(wdb-full, 0x0e),
419 XGENE_PMU_EVENT_ATTR(odb-full, 0x10),
420 XGENE_PMU_EVENT_ATTR(wbq-full, 0x11),
421 XGENE_PMU_EVENT_ATTR(input-req-async-fifo-stall, 0x12),
422 XGENE_PMU_EVENT_ATTR(output-req-async-fifo-stall, 0x13),
423 XGENE_PMU_EVENT_ATTR(output-data-async-fifo-stall, 0x14),
424 XGENE_PMU_EVENT_ATTR(total-insertion, 0x15),
425 XGENE_PMU_EVENT_ATTR(sip-insertions-r-set, 0x16),
426 XGENE_PMU_EVENT_ATTR(sip-insertions-r-clear, 0x17),
427 XGENE_PMU_EVENT_ATTR(dip-insertions-r-set, 0x18),
428 XGENE_PMU_EVENT_ATTR(dip-insertions-r-clear, 0x19),
429 XGENE_PMU_EVENT_ATTR(dip-insertions-force-r-set, 0x1a),
430 XGENE_PMU_EVENT_ATTR(egression, 0x1b),
431 XGENE_PMU_EVENT_ATTR(replacement, 0x1c),
432 XGENE_PMU_EVENT_ATTR(old-replacement, 0x1d),
433 XGENE_PMU_EVENT_ATTR(young-replacement, 0x1e),
434 XGENE_PMU_EVENT_ATTR(r-set-replacement, 0x1f),
435 XGENE_PMU_EVENT_ATTR(r-clear-replacement, 0x20),
436 XGENE_PMU_EVENT_ATTR(old-r-replacement, 0x21),
437 XGENE_PMU_EVENT_ATTR(old-nr-replacement, 0x22),
438 XGENE_PMU_EVENT_ATTR(young-r-replacement, 0x23),
439 XGENE_PMU_EVENT_ATTR(young-nr-replacement, 0x24),
440 XGENE_PMU_EVENT_ATTR(bloomfilter-clearing, 0x25),
441 XGENE_PMU_EVENT_ATTR(generation-flip, 0x26),
442 XGENE_PMU_EVENT_ATTR(vcc-droop-detected, 0x27),
443 NULL,
444};
445
446static struct attribute *iob_fast_pmu_v3_events_attrs[] = {
447 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
448 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-all, 0x01),
449 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-rd, 0x02),
450 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-wr, 0x03),
451 XGENE_PMU_EVENT_ATTR(pa-all-cp-req, 0x04),
452 XGENE_PMU_EVENT_ATTR(pa-cp-blk-req, 0x05),
453 XGENE_PMU_EVENT_ATTR(pa-cp-ptl-req, 0x06),
454 XGENE_PMU_EVENT_ATTR(pa-cp-rd-req, 0x07),
455 XGENE_PMU_EVENT_ATTR(pa-cp-wr-req, 0x08),
456 XGENE_PMU_EVENT_ATTR(ba-all-req, 0x09),
457 XGENE_PMU_EVENT_ATTR(ba-rd-req, 0x0a),
458 XGENE_PMU_EVENT_ATTR(ba-wr-req, 0x0b),
459 XGENE_PMU_EVENT_ATTR(pa-rd-shared-req-issued, 0x10),
460 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-req-issued, 0x11),
461 XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-stashable, 0x12),
462 XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-nonstashable, 0x13),
463 XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-stashable, 0x14),
464 XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-nonstashable, 0x15),
465 XGENE_PMU_EVENT_ATTR(pa-ptl-wr-req, 0x16),
466 XGENE_PMU_EVENT_ATTR(pa-ptl-rd-req, 0x17),
467 XGENE_PMU_EVENT_ATTR(pa-wr-back-clean-data, 0x18),
468 XGENE_PMU_EVENT_ATTR(pa-wr-back-cancelled-on-SS, 0x1b),
469 XGENE_PMU_EVENT_ATTR(pa-barrier-occurrence, 0x1c),
470 XGENE_PMU_EVENT_ATTR(pa-barrier-cycles, 0x1d),
471 XGENE_PMU_EVENT_ATTR(pa-total-cp-snoops, 0x20),
472 XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop, 0x21),
473 XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop-hit, 0x22),
474 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop, 0x23),
475 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop-hit, 0x24),
476 XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop, 0x25),
477 XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop-hit, 0x26),
478 XGENE_PMU_EVENT_ATTR(pa-req-buffer-full, 0x28),
479 XGENE_PMU_EVENT_ATTR(cswlf-outbound-req-fifo-full, 0x29),
480 XGENE_PMU_EVENT_ATTR(cswlf-inbound-snoop-fifo-backpressure, 0x2a),
481 XGENE_PMU_EVENT_ATTR(cswlf-outbound-lack-fifo-full, 0x2b),
482 XGENE_PMU_EVENT_ATTR(cswlf-inbound-gack-fifo-backpressure, 0x2c),
483 XGENE_PMU_EVENT_ATTR(cswlf-outbound-data-fifo-full, 0x2d),
484 XGENE_PMU_EVENT_ATTR(cswlf-inbound-data-fifo-backpressure, 0x2e),
485 XGENE_PMU_EVENT_ATTR(cswlf-inbound-req-backpressure, 0x2f),
486 NULL,
487};
488
489static struct attribute *iob_slow_pmu_v3_events_attrs[] = {
490 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
491 XGENE_PMU_EVENT_ATTR(pa-axi0-rd-req, 0x01),
492 XGENE_PMU_EVENT_ATTR(pa-axi0-wr-req, 0x02),
493 XGENE_PMU_EVENT_ATTR(pa-axi1-rd-req, 0x03),
494 XGENE_PMU_EVENT_ATTR(pa-axi1-wr-req, 0x04),
495 XGENE_PMU_EVENT_ATTR(ba-all-axi-req, 0x07),
496 XGENE_PMU_EVENT_ATTR(ba-axi-rd-req, 0x08),
497 XGENE_PMU_EVENT_ATTR(ba-axi-wr-req, 0x09),
498 XGENE_PMU_EVENT_ATTR(ba-free-list-empty, 0x10),
499 NULL,
500};
501
502static struct attribute *mcb_pmu_v3_events_attrs[] = {
503 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
504 XGENE_PMU_EVENT_ATTR(req-receive, 0x01),
505 XGENE_PMU_EVENT_ATTR(rd-req-recv, 0x02),
506 XGENE_PMU_EVENT_ATTR(rd-req-recv-2, 0x03),
507 XGENE_PMU_EVENT_ATTR(wr-req-recv, 0x04),
508 XGENE_PMU_EVENT_ATTR(wr-req-recv-2, 0x05),
509 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu, 0x06),
510 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu-2, 0x07),
511 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu, 0x08),
512 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu-2, 0x09),
513 XGENE_PMU_EVENT_ATTR(glbl-ack-recv-for-rd-sent-to-spec-mcu, 0x0a),
514 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-for-rd-sent-to-spec-mcu, 0x0b),
515 XGENE_PMU_EVENT_ATTR(glbl-ack-nogo-recv-for-rd-sent-to-spec-mcu, 0x0c),
516 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req, 0x0d),
517 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req-2, 0x0e),
518 XGENE_PMU_EVENT_ATTR(wr-req-sent-to-mcu, 0x0f),
519 XGENE_PMU_EVENT_ATTR(gack-recv, 0x10),
520 XGENE_PMU_EVENT_ATTR(rd-gack-recv, 0x11),
521 XGENE_PMU_EVENT_ATTR(wr-gack-recv, 0x12),
522 XGENE_PMU_EVENT_ATTR(cancel-rd-gack, 0x13),
523 XGENE_PMU_EVENT_ATTR(cancel-wr-gack, 0x14),
524 XGENE_PMU_EVENT_ATTR(mcb-csw-req-stall, 0x15),
525 XGENE_PMU_EVENT_ATTR(mcu-req-intf-blocked, 0x16),
526 XGENE_PMU_EVENT_ATTR(mcb-mcu-rd-intf-stall, 0x17),
527 XGENE_PMU_EVENT_ATTR(csw-rd-intf-blocked, 0x18),
528 XGENE_PMU_EVENT_ATTR(csw-local-ack-intf-blocked, 0x19),
529 XGENE_PMU_EVENT_ATTR(mcu-req-table-full, 0x1a),
530 XGENE_PMU_EVENT_ATTR(mcu-stat-table-full, 0x1b),
531 XGENE_PMU_EVENT_ATTR(mcu-wr-table-full, 0x1c),
532 XGENE_PMU_EVENT_ATTR(mcu-rdreceipt-resp, 0x1d),
533 XGENE_PMU_EVENT_ATTR(mcu-wrcomplete-resp, 0x1e),
534 XGENE_PMU_EVENT_ATTR(mcu-retryack-resp, 0x1f),
535 XGENE_PMU_EVENT_ATTR(mcu-pcrdgrant-resp, 0x20),
536 XGENE_PMU_EVENT_ATTR(mcu-req-from-lastload, 0x21),
537 XGENE_PMU_EVENT_ATTR(mcu-req-from-bypass, 0x22),
538 XGENE_PMU_EVENT_ATTR(volt-droop-detect, 0x23),
539 NULL,
540};
541
542static struct attribute *mc_pmu_v3_events_attrs[] = {
543 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
544 XGENE_PMU_EVENT_ATTR(act-sent, 0x01),
545 XGENE_PMU_EVENT_ATTR(pre-sent, 0x02),
546 XGENE_PMU_EVENT_ATTR(rd-sent, 0x03),
547 XGENE_PMU_EVENT_ATTR(rda-sent, 0x04),
548 XGENE_PMU_EVENT_ATTR(wr-sent, 0x05),
549 XGENE_PMU_EVENT_ATTR(wra-sent, 0x06),
550 XGENE_PMU_EVENT_ATTR(pd-entry-vld, 0x07),
551 XGENE_PMU_EVENT_ATTR(sref-entry-vld, 0x08),
552 XGENE_PMU_EVENT_ATTR(prea-sent, 0x09),
553 XGENE_PMU_EVENT_ATTR(ref-sent, 0x0a),
554 XGENE_PMU_EVENT_ATTR(rd-rda-sent, 0x0b),
555 XGENE_PMU_EVENT_ATTR(wr-wra-sent, 0x0c),
556 XGENE_PMU_EVENT_ATTR(raw-hazard, 0x0d),
557 XGENE_PMU_EVENT_ATTR(war-hazard, 0x0e),
558 XGENE_PMU_EVENT_ATTR(waw-hazard, 0x0f),
559 XGENE_PMU_EVENT_ATTR(rar-hazard, 0x10),
560 XGENE_PMU_EVENT_ATTR(raw-war-waw-hazard, 0x11),
561 XGENE_PMU_EVENT_ATTR(hprd-lprd-wr-req-vld, 0x12),
562 XGENE_PMU_EVENT_ATTR(lprd-req-vld, 0x13),
563 XGENE_PMU_EVENT_ATTR(hprd-req-vld, 0x14),
564 XGENE_PMU_EVENT_ATTR(hprd-lprd-req-vld, 0x15),
565 XGENE_PMU_EVENT_ATTR(wr-req-vld, 0x16),
566 XGENE_PMU_EVENT_ATTR(partial-wr-req-vld, 0x17),
567 XGENE_PMU_EVENT_ATTR(rd-retry, 0x18),
568 XGENE_PMU_EVENT_ATTR(wr-retry, 0x19),
569 XGENE_PMU_EVENT_ATTR(retry-gnt, 0x1a),
570 XGENE_PMU_EVENT_ATTR(rank-change, 0x1b),
571 XGENE_PMU_EVENT_ATTR(dir-change, 0x1c),
572 XGENE_PMU_EVENT_ATTR(rank-dir-change, 0x1d),
573 XGENE_PMU_EVENT_ATTR(rank-active, 0x1e),
574 XGENE_PMU_EVENT_ATTR(rank-idle, 0x1f),
575 XGENE_PMU_EVENT_ATTR(rank-pd, 0x20),
576 XGENE_PMU_EVENT_ATTR(rank-sref, 0x21),
577 XGENE_PMU_EVENT_ATTR(queue-fill-gt-thresh, 0x22),
578 XGENE_PMU_EVENT_ATTR(queue-rds-gt-thresh, 0x23),
579 XGENE_PMU_EVENT_ATTR(queue-wrs-gt-thresh, 0x24),
580 XGENE_PMU_EVENT_ATTR(phy-updt-complt, 0x25),
581 XGENE_PMU_EVENT_ATTR(tz-fail, 0x26),
582 XGENE_PMU_EVENT_ATTR(dram-errc, 0x27),
583 XGENE_PMU_EVENT_ATTR(dram-errd, 0x28),
584 XGENE_PMU_EVENT_ATTR(rd-enq, 0x29),
585 XGENE_PMU_EVENT_ATTR(wr-enq, 0x2a),
586 XGENE_PMU_EVENT_ATTR(tmac-limit-reached, 0x2b),
587 XGENE_PMU_EVENT_ATTR(tmaw-tracker-full, 0x2c),
588 NULL,
589};
590
591static const struct attribute_group l3c_pmu_v3_events_attr_group = {
592 .name = "events",
593 .attrs = l3c_pmu_v3_events_attrs,
594};
595
596static const struct attribute_group iob_fast_pmu_v3_events_attr_group = {
597 .name = "events",
598 .attrs = iob_fast_pmu_v3_events_attrs,
599};
600
601static const struct attribute_group iob_slow_pmu_v3_events_attr_group = {
602 .name = "events",
603 .attrs = iob_slow_pmu_v3_events_attrs,
604};
605
606static const struct attribute_group mcb_pmu_v3_events_attr_group = {
607 .name = "events",
608 .attrs = mcb_pmu_v3_events_attrs,
609};
610
611static const struct attribute_group mc_pmu_v3_events_attr_group = {
612 .name = "events",
613 .attrs = mc_pmu_v3_events_attrs,
614};
615
832c927d
TN		 616/*
617 * sysfs cpumask attributes
618 */
619static ssize_t xgene_pmu_cpumask_show(struct device *dev,
620 struct device_attribute *attr, char *buf)
621{
622 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev));
623
624 return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu);
625}
626
627static DEVICE_ATTR(cpumask, S_IRUGO, xgene_pmu_cpumask_show, NULL);
628
629static struct attribute *xgene_pmu_cpumask_attrs[] = {
630 &dev_attr_cpumask.attr,
631 NULL,
632};
633
634static const struct attribute_group pmu_cpumask_attr_group = {
635 .attrs = xgene_pmu_cpumask_attrs,
636};
637
638/*
c0f7f7ac 639 * Per PMU device attribute groups of PMU v1 and v2
832c927d
TN		 640 */
641static const struct attribute_group *l3c_pmu_attr_groups[] = {
642 &l3c_pmu_format_attr_group,
643 &pmu_cpumask_attr_group,
644 &l3c_pmu_events_attr_group,
645 NULL
646};
647
648static const struct attribute_group *iob_pmu_attr_groups[] = {
649 &iob_pmu_format_attr_group,
650 &pmu_cpumask_attr_group,
651 &iob_pmu_events_attr_group,
652 NULL
653};
654
655static const struct attribute_group *mcb_pmu_attr_groups[] = {
656 &mcb_pmu_format_attr_group,
657 &pmu_cpumask_attr_group,
658 &mcb_pmu_events_attr_group,
659 NULL
660};
661
662static const struct attribute_group *mc_pmu_attr_groups[] = {
663 &mc_pmu_format_attr_group,
664 &pmu_cpumask_attr_group,
665 &mc_pmu_events_attr_group,
666 NULL
667};
668
c0f7f7ac
HT		 669/*
670 * Per PMU device attribute groups of PMU v3
671 */
672static const struct attribute_group *l3c_pmu_v3_attr_groups[] = {
673 &l3c_pmu_v3_format_attr_group,
674 &pmu_cpumask_attr_group,
675 &l3c_pmu_v3_events_attr_group,
676 NULL
677};
678
679static const struct attribute_group *iob_fast_pmu_v3_attr_groups[] = {
680 &iob_pmu_v3_format_attr_group,
681 &pmu_cpumask_attr_group,
682 &iob_fast_pmu_v3_events_attr_group,
683 NULL
684};
685
686static const struct attribute_group *iob_slow_pmu_v3_attr_groups[] = {
687 &iob_slow_pmu_v3_format_attr_group,
688 &pmu_cpumask_attr_group,
689 &iob_slow_pmu_v3_events_attr_group,
690 NULL
691};
692
693static const struct attribute_group *mcb_pmu_v3_attr_groups[] = {
694 &mcb_pmu_v3_format_attr_group,
695 &pmu_cpumask_attr_group,
696 &mcb_pmu_v3_events_attr_group,
697 NULL
698};
699
700static const struct attribute_group *mc_pmu_v3_attr_groups[] = {
701 &mc_pmu_v3_format_attr_group,
702 &pmu_cpumask_attr_group,
703 &mc_pmu_v3_events_attr_group,
704 NULL
705};
706
832c927d
TN		 707static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev)
708{
709 int cntr;
710
711 cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask,
712 pmu_dev->max_counters);
713 if (cntr == pmu_dev->max_counters)
714 return -ENOSPC;
715 set_bit(cntr, pmu_dev->cntr_assign_mask);
716
717 return cntr;
718}
719
720static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr)
721{
722 clear_bit(cntr, pmu_dev->cntr_assign_mask);
723}
724
725static inline void xgene_pmu_mask_int(struct xgene_pmu *xgene_pmu)
726{
727 writel(PCPPMU_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
728}
729
c0f7f7ac
HT		 730static inline void xgene_pmu_v3_mask_int(struct xgene_pmu *xgene_pmu)
731{
732 writel(PCPPMU_V3_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
733}
734
832c927d
TN		 735static inline void xgene_pmu_unmask_int(struct xgene_pmu *xgene_pmu)
736{
737 writel(PCPPMU_INTCLRMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
738}
739
c0f7f7ac
HT		 740static inline void xgene_pmu_v3_unmask_int(struct xgene_pmu *xgene_pmu)
741{
742 writel(PCPPMU_V3_INTCLRMASK,
743 xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
744}
745
e35e0a04
HT		 746static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev,
747 int idx)
832c927d
TN		 748{
749 return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
750}
751
c0f7f7ac
HT		 752static inline u64 xgene_pmu_read_counter64(struct xgene_pmu_dev *pmu_dev,
753 int idx)
754{
755 u32 lo, hi;
756
757 /*
758 * v3 has 64-bit counter registers composed by 2 32-bit registers
759 * This can be a problem if the counter increases and carries
760 * out of bit [31] between 2 reads. The extra reads would help
761 * to prevent this issue.
762 */
763 do {
764 hi = xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1);
765 lo = xgene_pmu_read_counter32(pmu_dev, 2 * idx);
766 } while (hi != xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1));
767
768 return (((u64)hi << 32) | lo);
769}
770
832c927d 771static inline void
e35e0a04 772xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
832c927d
TN		 773{
774 writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
775}
776
c0f7f7ac
HT		 777static inline void
778xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
779{
780 u32 cnt_lo, cnt_hi;
781
782 cnt_hi = upper_32_bits(val);
783 cnt_lo = lower_32_bits(val);
784
785 /* v3 has 64-bit counter registers composed by 2 32-bit registers */
786 xgene_pmu_write_counter32(pmu_dev, 2 * idx, cnt_lo);
787 xgene_pmu_write_counter32(pmu_dev, 2 * idx + 1, cnt_hi);
788}
789
832c927d
TN		 790static inline void
791xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val)
792{
793 writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));
794}
795
796static inline void
797xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val)
798{
799 writel(val, pmu_dev->inf->csr + PMU_PMAMR0);
800}
801
c0f7f7ac
HT		 802static inline void
803xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
804
832c927d
TN		 805static inline void
806xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val)
807{
808 writel(val, pmu_dev->inf->csr + PMU_PMAMR1);
809}
810
c0f7f7ac
HT		 811static inline void
812xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
813
832c927d
TN		 814static inline void
815xgene_pmu_enable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
816{
817 u32 val;
818
819 val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);
820 val |= 1 << idx;
821 writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);
822}
823
824static inline void
825xgene_pmu_disable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
826{
827 u32 val;
828
829 val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);
830 val |= 1 << idx;
831 writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);
832}
833
834static inline void
835xgene_pmu_enable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
836{
837 u32 val;
838
839 val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);
840 val |= 1 << idx;
841 writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);
842}
843
844static inline void
845xgene_pmu_disable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
846{
847 u32 val;
848
849 val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);
850 val |= 1 << idx;
851 writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);
852}
853
854static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev)
855{
856 u32 val;
857
858 val = readl(pmu_dev->inf->csr + PMU_PMCR);
859 val |= PMU_PMCR_P;
860 writel(val, pmu_dev->inf->csr + PMU_PMCR);
861}
862
863static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev)
864{
865 u32 val;
866
867 val = readl(pmu_dev->inf->csr + PMU_PMCR);
868 val |= PMU_PMCR_E;
869 writel(val, pmu_dev->inf->csr + PMU_PMCR);
870}
871
872static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev)
873{
874 u32 val;
875
876 val = readl(pmu_dev->inf->csr + PMU_PMCR);
877 val &= ~PMU_PMCR_E;
878 writel(val, pmu_dev->inf->csr + PMU_PMCR);
879}
880
881static void xgene_perf_pmu_enable(struct pmu *pmu)
882{
883 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
e35e0a04 884 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d
TN		 885 int enabled = bitmap_weight(pmu_dev->cntr_assign_mask,
886 pmu_dev->max_counters);
887
888 if (!enabled)
889 return;
890
e35e0a04 891 xgene_pmu->ops->start_counters(pmu_dev);
832c927d
TN		 892}
893
894static void xgene_perf_pmu_disable(struct pmu *pmu)
895{
896 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
e35e0a04 897 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d 898
e35e0a04 899 xgene_pmu->ops->stop_counters(pmu_dev);
832c927d
TN		 900}
901
902static int xgene_perf_event_init(struct perf_event *event)
903{
904 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
905 struct hw_perf_event *hw = &event->hw;
906 struct perf_event *sibling;
907
908 /* Test the event attr type check for PMU enumeration */
909 if (event->attr.type != event->pmu->type)
910 return -ENOENT;
911
912 /*
913 * SOC PMU counters are shared across all cores.
914 * Therefore, it does not support per-process mode.
915 * Also, it does not support event sampling mode.
916 */
917 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
918 return -EINVAL;
919
832c927d
TN		 920 if (event->cpu < 0)
921 return -EINVAL;
922 /*
923 * Many perf core operations (eg. events rotation) operate on a
924 * single CPU context. This is obvious for CPU PMUs, where one
925 * expects the same sets of events being observed on all CPUs,
926 * but can lead to issues for off-core PMUs, where each
927 * event could be theoretically assigned to a different CPU. To
928 * mitigate this, we enforce CPU assignment to one, selected
929 * processor (the one described in the "cpumask" attribute).
930 */
931 event->cpu = cpumask_first(&pmu_dev->parent->cpu);
932
933 hw->config = event->attr.config;
934 /*
935 * Each bit of the config1 field represents an agent from which the
936 * request of the event come. The event is counted only if it's caused
937 * by a request of an agent has the bit cleared.
938 * By default, the event is counted for all agents.
939 */
940 hw->config_base = event->attr.config1;
941
942 /*
943 * We must NOT create groups containing mixed PMUs, although software
944 * events are acceptable
945 */
946 if (event->group_leader->pmu != event->pmu &&
947 !is_software_event(event->group_leader))
948 return -EINVAL;
949
edb39592 950 for_each_sibling_event(sibling, event->group_leader) {
832c927d
TN		 951 if (sibling->pmu != event->pmu &&
952 !is_software_event(sibling))
953 return -EINVAL;
edb39592 954 }
832c927d
TN		 955
956 return 0;
957}
958
959static void xgene_perf_enable_event(struct perf_event *event)
960{
961 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 962 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d 963
e35e0a04
HT		 964 xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event),
965 GET_EVENTID(event));
966 xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event)));
832c927d 967 if (pmu_dev->inf->type == PMU_TYPE_IOB)
e35e0a04
HT		 968 xgene_pmu->ops->write_agent1msk(pmu_dev,
969 ~((u32)GET_AGENT1ID(event)));
832c927d 970
e35e0a04
HT		 971 xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event));
972 xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event));
832c927d
TN		 973}
974
975static void xgene_perf_disable_event(struct perf_event *event)
976{
977 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 978 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d 979
e35e0a04
HT		 980 xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event));
981 xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event));
832c927d
TN		 982}
983
984static void xgene_perf_event_set_period(struct perf_event *event)
985{
986 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 987 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d
TN		 988 struct hw_perf_event *hw = &event->hw;
989 /*
c0f7f7ac
HT		 990 * For 32 bit counter, it has a period of 2^32. To account for the
991 * possibility of extreme interrupt latency we program for a period of
992 * half that. Hopefully, we can handle the interrupt before another 2^31
832c927d 993 * events occur and the counter overtakes its previous value.
c0f7f7ac 994 * For 64 bit counter, we don't expect it overflow.
832c927d
TN		 995 */
996 u64 val = 1ULL << 31;
997
998 local64_set(&hw->prev_count, val);
e35e0a04 999 xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val);
832c927d
TN		 1000}
1001
1002static void xgene_perf_event_update(struct perf_event *event)
1003{
1004 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 1005 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d
TN		 1006 struct hw_perf_event *hw = &event->hw;
1007 u64 delta, prev_raw_count, new_raw_count;
1008
1009again:
1010 prev_raw_count = local64_read(&hw->prev_count);
e35e0a04 1011 new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event));
832c927d
TN		 1012
1013 if (local64_cmpxchg(&hw->prev_count, prev_raw_count,
1014 new_raw_count) != prev_raw_count)
1015 goto again;
1016
1017 delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period;
1018
1019 local64_add(delta, &event->count);
1020}
1021
1022static void xgene_perf_read(struct perf_event *event)
1023{
1024 xgene_perf_event_update(event);
1025}
1026
1027static void xgene_perf_start(struct perf_event *event, int flags)
1028{
1029 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
e35e0a04 1030 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
832c927d
TN		 1031 struct hw_perf_event *hw = &event->hw;
1032
1033 if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED)))
1034 return;
1035
1036 WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE));
1037 hw->state = 0;
1038
1039 xgene_perf_event_set_period(event);
1040
1041 if (flags & PERF_EF_RELOAD) {
1042 u64 prev_raw_count = local64_read(&hw->prev_count);
1043
e35e0a04
HT		 1044 xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event),
1045 prev_raw_count);
832c927d
TN		 1046 }
1047
1048 xgene_perf_enable_event(event);
1049 perf_event_update_userpage(event);
1050}
1051
1052static void xgene_perf_stop(struct perf_event *event, int flags)
1053{
1054 struct hw_perf_event *hw = &event->hw;
832c927d
TN		 1055
1056 if (hw->state & PERF_HES_UPTODATE)
1057 return;
1058
1059 xgene_perf_disable_event(event);
1060 WARN_ON_ONCE(hw->state & PERF_HES_STOPPED);
1061 hw->state |= PERF_HES_STOPPED;
1062
1063 if (hw->state & PERF_HES_UPTODATE)
1064 return;
1065
832c927d
TN		 1066 xgene_perf_read(event);
1067 hw->state |= PERF_HES_UPTODATE;
1068}
1069
1070static int xgene_perf_add(struct perf_event *event, int flags)
1071{
1072 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1073 struct hw_perf_event *hw = &event->hw;
1074
1075 hw->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1076
1077 /* Allocate an event counter */
1078 hw->idx = get_next_avail_cntr(pmu_dev);
1079 if (hw->idx < 0)
1080 return -EAGAIN;
1081
1082 /* Update counter event pointer for Interrupt handler */
1083 pmu_dev->pmu_counter_event[hw->idx] = event;
1084
1085 if (flags & PERF_EF_START)
1086 xgene_perf_start(event, PERF_EF_RELOAD);
1087
1088 return 0;
1089}
1090
1091static void xgene_perf_del(struct perf_event *event, int flags)
1092{
1093 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1094 struct hw_perf_event *hw = &event->hw;
1095
1096 xgene_perf_stop(event, PERF_EF_UPDATE);
1097
1098 /* clear the assigned counter */
1099 clear_avail_cntr(pmu_dev, GET_CNTR(event));
1100
1101 perf_event_update_userpage(event);
1102 pmu_dev->pmu_counter_event[hw->idx] = NULL;
1103}
1104
1105static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name)
1106{
1107 struct xgene_pmu *xgene_pmu;
1108
c0f7f7ac
HT		 1109 if (pmu_dev->parent->version == PCP_PMU_V3)
1110 pmu_dev->max_period = PMU_V3_CNT_MAX_PERIOD;
1111 else
1112 pmu_dev->max_period = PMU_CNT_MAX_PERIOD;
832c927d
TN		 1113 /* First version PMU supports only single event counter */
1114 xgene_pmu = pmu_dev->parent;
1115 if (xgene_pmu->version == PCP_PMU_V1)
1116 pmu_dev->max_counters = 1;
1117 else
1118 pmu_dev->max_counters = PMU_MAX_COUNTERS;
1119
1120 /* Perf driver registration */
1121 pmu_dev->pmu = (struct pmu) {
1122 .attr_groups = pmu_dev->attr_groups,
1123 .task_ctx_nr = perf_invalid_context,
1124 .pmu_enable = xgene_perf_pmu_enable,
1125 .pmu_disable = xgene_perf_pmu_disable,
1126 .event_init = xgene_perf_event_init,
1127 .add = xgene_perf_add,
1128 .del = xgene_perf_del,
1129 .start = xgene_perf_start,
1130 .stop = xgene_perf_stop,
1131 .read = xgene_perf_read,
a66b0010 1132 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
832c927d
TN		 1133 };
1134
1135 /* Hardware counter init */
e35e0a04
HT		 1136 xgene_pmu->ops->stop_counters(pmu_dev);
1137 xgene_pmu->ops->reset_counters(pmu_dev);
832c927d
TN		 1138
1139 return perf_pmu_register(&pmu_dev->pmu, name, -1);
1140}
1141
1142static int
1143xgene_pmu_dev_add(struct xgene_pmu *xgene_pmu, struct xgene_pmu_dev_ctx *ctx)
1144{
1145 struct device *dev = xgene_pmu->dev;
1146 struct xgene_pmu_dev *pmu;
832c927d
TN		 1147
1148 pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL);
1149 if (!pmu)
1150 return -ENOMEM;
1151 pmu->parent = xgene_pmu;
1152 pmu->inf = &ctx->inf;
1153 ctx->pmu_dev = pmu;
1154
1155 switch (pmu->inf->type) {
1156 case PMU_TYPE_L3C:
c0f7f7ac 1157 if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))
c1be2ddb 1158 return -ENODEV;
c0f7f7ac
HT		 1159 if (xgene_pmu->version == PCP_PMU_V3)
1160 pmu->attr_groups = l3c_pmu_v3_attr_groups;
1161 else
1162 pmu->attr_groups = l3c_pmu_attr_groups;
832c927d
TN		 1163 break;
1164 case PMU_TYPE_IOB:
c0f7f7ac
HT		 1165 if (xgene_pmu->version == PCP_PMU_V3)
1166 pmu->attr_groups = iob_fast_pmu_v3_attr_groups;
1167 else
1168 pmu->attr_groups = iob_pmu_attr_groups;
1169 break;
1170 case PMU_TYPE_IOB_SLOW:
1171 if (xgene_pmu->version == PCP_PMU_V3)
1172 pmu->attr_groups = iob_slow_pmu_v3_attr_groups;
832c927d
TN		 1173 break;
1174 case PMU_TYPE_MCB:
1175 if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))
c1be2ddb 1176 return -ENODEV;
c0f7f7ac
HT		 1177 if (xgene_pmu->version == PCP_PMU_V3)
1178 pmu->attr_groups = mcb_pmu_v3_attr_groups;
1179 else
1180 pmu->attr_groups = mcb_pmu_attr_groups;
832c927d
TN		 1181 break;
1182 case PMU_TYPE_MC:
1183 if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))
c1be2ddb 1184 return -ENODEV;
c0f7f7ac
HT		 1185 if (xgene_pmu->version == PCP_PMU_V3)
1186 pmu->attr_groups = mc_pmu_v3_attr_groups;
1187 else
1188 pmu->attr_groups = mc_pmu_attr_groups;
832c927d
TN		 1189 break;
1190 default:
1191 return -EINVAL;
1192 }
1193
c1be2ddb 1194 if (xgene_init_perf(pmu, ctx->name)) {
832c927d 1195 dev_err(dev, "%s PMU: Failed to init perf driver\n", ctx->name);
c1be2ddb 1196 return -ENODEV;
832c927d
TN		 1197 }
1198
1199 dev_info(dev, "%s PMU registered\n", ctx->name);
1200
c1be2ddb 1201 return 0;
832c927d
TN		 1202}
1203
1204static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev)
1205{
1206 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
c0f7f7ac 1207 void __iomem *csr = pmu_dev->inf->csr;
832c927d
TN		 1208 u32 pmovsr;
1209 int idx;
1210
c0f7f7ac
HT		 1211 xgene_pmu->ops->stop_counters(pmu_dev);
1212
1213 if (xgene_pmu->version == PCP_PMU_V3)
1214 pmovsr = readl(csr + PMU_PMOVSSET) & PMU_OVERFLOW_MASK;
1215 else
1216 pmovsr = readl(csr + PMU_PMOVSR) & PMU_OVERFLOW_MASK;
1217
832c927d 1218 if (!pmovsr)
c0f7f7ac 1219 goto out;
832c927d
TN		 1220
1221 /* Clear interrupt flag */
1222 if (xgene_pmu->version == PCP_PMU_V1)
c0f7f7ac
HT		 1223 writel(0x0, csr + PMU_PMOVSR);
1224 else if (xgene_pmu->version == PCP_PMU_V2)
1225 writel(pmovsr, csr + PMU_PMOVSR);
832c927d 1226 else
c0f7f7ac 1227 writel(pmovsr, csr + PMU_PMOVSCLR);
832c927d
TN		 1228
1229 for (idx = 0; idx < PMU_MAX_COUNTERS; idx++) {
1230 struct perf_event *event = pmu_dev->pmu_counter_event[idx];
1231 int overflowed = pmovsr & BIT(idx);
1232
1233 /* Ignore if we don't have an event. */
1234 if (!event || !overflowed)
1235 continue;
1236 xgene_perf_event_update(event);
1237 xgene_perf_event_set_period(event);
1238 }
c0f7f7ac
HT		 1239
1240out:
1241 xgene_pmu->ops->start_counters(pmu_dev);
832c927d
TN		 1242}
1243
1244static irqreturn_t xgene_pmu_isr(int irq, void *dev_id)
1245{
c0f7f7ac 1246 u32 intr_mcu, intr_mcb, intr_l3c, intr_iob;
832c927d
TN		 1247 struct xgene_pmu_dev_ctx *ctx;
1248 struct xgene_pmu *xgene_pmu = dev_id;
1249 unsigned long flags;
1250 u32 val;
1251
1252 raw_spin_lock_irqsave(&xgene_pmu->lock, flags);
1253
1254 /* Get Interrupt PMU source */
1255 val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG);
c0f7f7ac
HT		 1256 if (xgene_pmu->version == PCP_PMU_V3) {
1257 intr_mcu = PCPPMU_V3_INT_MCU;
1258 intr_mcb = PCPPMU_V3_INT_MCB;
1259 intr_l3c = PCPPMU_V3_INT_L3C;
1260 intr_iob = PCPPMU_V3_INT_IOB;
1261 } else {
1262 intr_mcu = PCPPMU_INT_MCU;
1263 intr_mcb = PCPPMU_INT_MCB;
1264 intr_l3c = PCPPMU_INT_L3C;
1265 intr_iob = PCPPMU_INT_IOB;
1266 }
1267 if (val & intr_mcu) {
832c927d
TN		 1268 list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {
1269 _xgene_pmu_isr(irq, ctx->pmu_dev);
1270 }
1271 }
c0f7f7ac 1272 if (val & intr_mcb) {
832c927d
TN		 1273 list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {
1274 _xgene_pmu_isr(irq, ctx->pmu_dev);
1275 }
1276 }
c0f7f7ac 1277 if (val & intr_l3c) {
832c927d
TN		 1278 list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {
1279 _xgene_pmu_isr(irq, ctx->pmu_dev);
1280 }
1281 }
c0f7f7ac 1282 if (val & intr_iob) {
832c927d
TN		 1283 list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {
1284 _xgene_pmu_isr(irq, ctx->pmu_dev);
1285 }
1286 }
1287
1288 raw_spin_unlock_irqrestore(&xgene_pmu->lock, flags);
1289
1290 return IRQ_HANDLED;
1291}
1292
c0f7f7ac
HT		 1293static int acpi_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1294 struct platform_device *pdev)
832c927d
TN		 1295{
1296 void __iomem *csw_csr, *mcba_csr, *mcbb_csr;
1297 struct resource *res;
1298 unsigned int reg;
1299
1300 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1301 csw_csr = devm_ioremap_resource(&pdev->dev, res);
1302 if (IS_ERR(csw_csr)) {
1303 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
1304 return PTR_ERR(csw_csr);
1305 }
1306
1307 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1308 mcba_csr = devm_ioremap_resource(&pdev->dev, res);
1309 if (IS_ERR(mcba_csr)) {
1310 dev_err(&pdev->dev, "ioremap failed for MCBA CSR resource\n");
1311 return PTR_ERR(mcba_csr);
1312 }
1313
1314 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1315 mcbb_csr = devm_ioremap_resource(&pdev->dev, res);
1316 if (IS_ERR(mcbb_csr)) {
1317 dev_err(&pdev->dev, "ioremap failed for MCBB CSR resource\n");
1318 return PTR_ERR(mcbb_csr);
1319 }
1320
c0f7f7ac
HT		 1321 xgene_pmu->l3c_active_mask = 0x1;
1322
832c927d
TN		 1323 reg = readl(csw_csr + CSW_CSWCR);
1324 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1325 /* Dual MCB active */
1326 xgene_pmu->mcb_active_mask = 0x3;
1327 /* Probe all active MC(s) */
1328 reg = readl(mcbb_csr + CSW_CSWCR);
1329 xgene_pmu->mc_active_mask =
1330 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
1331 } else {
1332 /* Single MCB active */
1333 xgene_pmu->mcb_active_mask = 0x1;
1334 /* Probe all active MC(s) */
1335 reg = readl(mcba_csr + CSW_CSWCR);
1336 xgene_pmu->mc_active_mask =
1337 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
1338 }
1339
1340 return 0;
1341}
1342
c0f7f7ac
HT		 1343static int acpi_pmu_v3_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1344 struct platform_device *pdev)
1345{
1346 void __iomem *csw_csr;
1347 struct resource *res;
1348 unsigned int reg;
1349 u32 mcb0routing;
1350 u32 mcb1routing;
1351
1352 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1353 csw_csr = devm_ioremap_resource(&pdev->dev, res);
1354 if (IS_ERR(csw_csr)) {
1355 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
1356 return PTR_ERR(csw_csr);
1357 }
1358
1359 reg = readl(csw_csr + CSW_CSWCR);
1360 mcb0routing = CSW_CSWCR_MCB0_ROUTING(reg);
1361 mcb1routing = CSW_CSWCR_MCB1_ROUTING(reg);
1362 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1363 /* Dual MCB active */
1364 xgene_pmu->mcb_active_mask = 0x3;
1365 /* Probe all active L3C(s), maximum is 8 */
1366 xgene_pmu->l3c_active_mask = 0xFF;
1367 /* Probe all active MC(s), maximum is 8 */
1368 if ((mcb0routing == 0x2) && (mcb1routing == 0x2))
1369 xgene_pmu->mc_active_mask = 0xFF;
1370 else if ((mcb0routing == 0x1) && (mcb1routing == 0x1))
1371 xgene_pmu->mc_active_mask = 0x33;
1372 else
1373 xgene_pmu->mc_active_mask = 0x11;
1374 } else {
1375 /* Single MCB active */
1376 xgene_pmu->mcb_active_mask = 0x1;
1377 /* Probe all active L3C(s), maximum is 4 */
1378 xgene_pmu->l3c_active_mask = 0x0F;
1379 /* Probe all active MC(s), maximum is 4 */
1380 if (mcb0routing == 0x2)
1381 xgene_pmu->mc_active_mask = 0x0F;
1382 else if (mcb0routing == 0x1)
1383 xgene_pmu->mc_active_mask = 0x03;
1384 else
1385 xgene_pmu->mc_active_mask = 0x01;
1386 }
1387
1388 return 0;
1389}
1390
1391static int fdt_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1392 struct platform_device *pdev)
832c927d
TN		 1393{
1394 struct regmap *csw_map, *mcba_map, *mcbb_map;
1395 struct device_node *np = pdev->dev.of_node;
1396 unsigned int reg;
1397
1398 csw_map = syscon_regmap_lookup_by_phandle(np, "regmap-csw");
1399 if (IS_ERR(csw_map)) {
1400 dev_err(&pdev->dev, "unable to get syscon regmap csw\n");
1401 return PTR_ERR(csw_map);
1402 }
1403
1404 mcba_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcba");
1405 if (IS_ERR(mcba_map)) {
1406 dev_err(&pdev->dev, "unable to get syscon regmap mcba\n");
1407 return PTR_ERR(mcba_map);
1408 }
1409
1410 mcbb_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcbb");
1411 if (IS_ERR(mcbb_map)) {
1412 dev_err(&pdev->dev, "unable to get syscon regmap mcbb\n");
1413 return PTR_ERR(mcbb_map);
1414 }
1415
c0f7f7ac 1416 xgene_pmu->l3c_active_mask = 0x1;
832c927d
TN		 1417 if (regmap_read(csw_map, CSW_CSWCR, &reg))
1418 return -EINVAL;
1419
1420 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1421 /* Dual MCB active */
1422 xgene_pmu->mcb_active_mask = 0x3;
1423 /* Probe all active MC(s) */
1424 if (regmap_read(mcbb_map, MCBADDRMR, &reg))
1425 return 0;
1426 xgene_pmu->mc_active_mask =
1427 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
1428 } else {
1429 /* Single MCB active */
1430 xgene_pmu->mcb_active_mask = 0x1;
1431 /* Probe all active MC(s) */
1432 if (regmap_read(mcba_map, MCBADDRMR, &reg))
1433 return 0;
1434 xgene_pmu->mc_active_mask =
1435 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
1436 }
1437
1438 return 0;
1439}
1440
c0f7f7ac
HT		 1441static int xgene_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1442 struct platform_device *pdev)
832c927d 1443{
c0f7f7ac
HT		 1444 if (has_acpi_companion(&pdev->dev)) {
1445 if (xgene_pmu->version == PCP_PMU_V3)
1446 return acpi_pmu_v3_probe_active_mcb_mcu_l3c(xgene_pmu,
1447 pdev);
1448 else
1449 return acpi_pmu_probe_active_mcb_mcu_l3c(xgene_pmu,
1450 pdev);
1451 }
1452 return fdt_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
832c927d
TN		 1453}
1454
1455static char *xgene_pmu_dev_name(struct device *dev, u32 type, int id)
1456{
1457 switch (type) {
1458 case PMU_TYPE_L3C:
1459 return devm_kasprintf(dev, GFP_KERNEL, "l3c%d", id);
1460 case PMU_TYPE_IOB:
1461 return devm_kasprintf(dev, GFP_KERNEL, "iob%d", id);
c0f7f7ac 1462 case PMU_TYPE_IOB_SLOW:
a45fc268 1463 return devm_kasprintf(dev, GFP_KERNEL, "iob_slow%d", id);
832c927d
TN		 1464 case PMU_TYPE_MCB:
1465 return devm_kasprintf(dev, GFP_KERNEL, "mcb%d", id);
1466 case PMU_TYPE_MC:
1467 return devm_kasprintf(dev, GFP_KERNEL, "mc%d", id);
1468 default:
1469 return devm_kasprintf(dev, GFP_KERNEL, "unknown");
1470 }
1471}
1472
1473#if defined(CONFIG_ACPI)
1474static int acpi_pmu_dev_add_resource(struct acpi_resource *ares, void *data)
1475{
1476 struct resource *res = data;
1477
1478 if (ares->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32)
1479 acpi_dev_resource_memory(ares, res);
1480
1481 /* Always tell the ACPI core to skip this resource */
1482 return 1;
1483}
1484
1485static struct
1486xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
1487 struct acpi_device *adev, u32 type)
1488{
1489 struct device *dev = xgene_pmu->dev;
1490 struct list_head resource_list;
1491 struct xgene_pmu_dev_ctx *ctx;
1492 const union acpi_object *obj;
1493 struct hw_pmu_info *inf;
1494 void __iomem *dev_csr;
1495 struct resource res;
1496 int enable_bit;
1497 int rc;
1498
1499 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1500 if (!ctx)
1501 return NULL;
1502
1503 INIT_LIST_HEAD(&resource_list);
1504 rc = acpi_dev_get_resources(adev, &resource_list,
1505 acpi_pmu_dev_add_resource, &res);
1506 acpi_dev_free_resource_list(&resource_list);
9a1a1f40 1507 if (rc < 0) {
832c927d 1508 dev_err(dev, "PMU type %d: No resource address found\n", type);
c1be2ddb 1509 return NULL;
832c927d
TN		 1510 }
1511
1512 dev_csr = devm_ioremap_resource(dev, &res);
1513 if (IS_ERR(dev_csr)) {
1514 dev_err(dev, "PMU type %d: Fail to map resource\n", type);
c1be2ddb 1515 return NULL;
832c927d
TN		 1516 }
1517
1518 /* A PMU device node without enable-bit-index is always enabled */
1519 rc = acpi_dev_get_property(adev, "enable-bit-index",
1520 ACPI_TYPE_INTEGER, &obj);
1521 if (rc < 0)
1522 enable_bit = 0;
1523 else
1524 enable_bit = (int) obj->integer.value;
1525
1526 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1527 if (!ctx->name) {
1528 dev_err(dev, "PMU type %d: Fail to get device name\n", type);
c1be2ddb 1529 return NULL;
832c927d
TN		 1530 }
1531 inf = &ctx->inf;
1532 inf->type = type;
1533 inf->csr = dev_csr;
1534 inf->enable_mask = 1 << enable_bit;
1535
1536 return ctx;
832c927d
TN		 1537}
1538
838955e2
HT		 1539static const struct acpi_device_id xgene_pmu_acpi_type_match[] = {
1540 {"APMC0D5D", PMU_TYPE_L3C},
1541 {"APMC0D5E", PMU_TYPE_IOB},
1542 {"APMC0D5F", PMU_TYPE_MCB},
1543 {"APMC0D60", PMU_TYPE_MC},
c0f7f7ac
HT		 1544 {"APMC0D84", PMU_TYPE_L3C},
1545 {"APMC0D85", PMU_TYPE_IOB},
1546 {"APMC0D86", PMU_TYPE_IOB_SLOW},
1547 {"APMC0D87", PMU_TYPE_MCB},
1548 {"APMC0D88", PMU_TYPE_MC},
838955e2
HT		 1549 {},
1550};
1551
1552static const struct acpi_device_id *xgene_pmu_acpi_match_type(
1553 const struct acpi_device_id *ids,
1554 struct acpi_device *adev)
1555{
1556 const struct acpi_device_id *match_id = NULL;
1557 const struct acpi_device_id *id;
1558
1559 for (id = ids; id->id[0] || id->cls; id++) {
1560 if (!acpi_match_device_ids(adev, id))
1561 match_id = id;
1562 else if (match_id)
1563 break;
1564 }
1565
1566 return match_id;
1567}
1568
832c927d
TN		 1569static acpi_status acpi_pmu_dev_add(acpi_handle handle, u32 level,
1570 void *data, void **return_value)
1571{
838955e2 1572 const struct acpi_device_id *acpi_id;
832c927d
TN		 1573 struct xgene_pmu *xgene_pmu = data;
1574 struct xgene_pmu_dev_ctx *ctx;
1575 struct acpi_device *adev;
1576
1577 if (acpi_bus_get_device(handle, &adev))
1578 return AE_OK;
1579 if (acpi_bus_get_status(adev) || !adev->status.present)
1580 return AE_OK;
1581
838955e2
HT		 1582 acpi_id = xgene_pmu_acpi_match_type(xgene_pmu_acpi_type_match, adev);
1583 if (!acpi_id)
1584 return AE_OK;
832c927d 1585
838955e2 1586 ctx = acpi_get_pmu_hw_inf(xgene_pmu, adev, (u32)acpi_id->driver_data);
832c927d
TN		 1587 if (!ctx)
1588 return AE_OK;
1589
1590 if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
1591 /* Can't add the PMU device, skip it */
1592 devm_kfree(xgene_pmu->dev, ctx);
1593 return AE_OK;
1594 }
1595
1596 switch (ctx->inf.type) {
1597 case PMU_TYPE_L3C:
1598 list_add(&ctx->next, &xgene_pmu->l3cpmus);
1599 break;
1600 case PMU_TYPE_IOB:
1601 list_add(&ctx->next, &xgene_pmu->iobpmus);
1602 break;
c0f7f7ac
HT		 1603 case PMU_TYPE_IOB_SLOW:
1604 list_add(&ctx->next, &xgene_pmu->iobpmus);
1605 break;
832c927d
TN		 1606 case PMU_TYPE_MCB:
1607 list_add(&ctx->next, &xgene_pmu->mcbpmus);
1608 break;
1609 case PMU_TYPE_MC:
1610 list_add(&ctx->next, &xgene_pmu->mcpmus);
1611 break;
1612 }
1613 return AE_OK;
1614}
1615
1616static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1617 struct platform_device *pdev)
1618{
1619 struct device *dev = xgene_pmu->dev;
1620 acpi_handle handle;
1621 acpi_status status;
1622
1623 handle = ACPI_HANDLE(dev);
1624 if (!handle)
1625 return -EINVAL;
1626
1627 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1628 acpi_pmu_dev_add, NULL, xgene_pmu, NULL);
1629 if (ACPI_FAILURE(status)) {
1630 dev_err(dev, "failed to probe PMU devices\n");
1631 return -ENODEV;
1632 }
1633
1634 return 0;
1635}
1636#else
1637static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1638 struct platform_device *pdev)
1639{
1640 return 0;
1641}
1642#endif
1643
1644static struct
1645xgene_pmu_dev_ctx *fdt_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
1646 struct device_node *np, u32 type)
1647{
1648 struct device *dev = xgene_pmu->dev;
1649 struct xgene_pmu_dev_ctx *ctx;
1650 struct hw_pmu_info *inf;
1651 void __iomem *dev_csr;
1652 struct resource res;
1653 int enable_bit;
832c927d
TN		 1654
1655 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1656 if (!ctx)
1657 return NULL;
c1be2ddb
TN		 1658
1659 if (of_address_to_resource(np, 0, &res) < 0) {
832c927d 1660 dev_err(dev, "PMU type %d: No resource address found\n", type);
c1be2ddb 1661 return NULL;
832c927d 1662 }
c1be2ddb 1663
832c927d
TN		 1664 dev_csr = devm_ioremap_resource(dev, &res);
1665 if (IS_ERR(dev_csr)) {
1666 dev_err(dev, "PMU type %d: Fail to map resource\n", type);
c1be2ddb 1667 return NULL;
832c927d
TN		 1668 }
1669
1670 /* A PMU device node without enable-bit-index is always enabled */
1671 if (of_property_read_u32(np, "enable-bit-index", &enable_bit))
1672 enable_bit = 0;
1673
1674 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1675 if (!ctx->name) {
1676 dev_err(dev, "PMU type %d: Fail to get device name\n", type);
c1be2ddb 1677 return NULL;
832c927d 1678 }
c1be2ddb 1679
832c927d
TN		 1680 inf = &ctx->inf;
1681 inf->type = type;
1682 inf->csr = dev_csr;
1683 inf->enable_mask = 1 << enable_bit;
1684
1685 return ctx;
832c927d
TN		 1686}
1687
1688static int fdt_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1689 struct platform_device *pdev)
1690{
1691 struct xgene_pmu_dev_ctx *ctx;
1692 struct device_node *np;
1693
1694 for_each_child_of_node(pdev->dev.of_node, np) {
1695 if (!of_device_is_available(np))
1696 continue;
1697
1698 if (of_device_is_compatible(np, "apm,xgene-pmu-l3c"))
1699 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_L3C);
1700 else if (of_device_is_compatible(np, "apm,xgene-pmu-iob"))
1701 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_IOB);
1702 else if (of_device_is_compatible(np, "apm,xgene-pmu-mcb"))
1703 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MCB);
1704 else if (of_device_is_compatible(np, "apm,xgene-pmu-mc"))
1705 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MC);
1706 else
1707 ctx = NULL;
1708
1709 if (!ctx)
1710 continue;
1711
1712 if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
1713 /* Can't add the PMU device, skip it */
1714 devm_kfree(xgene_pmu->dev, ctx);
1715 continue;
1716 }
1717
1718 switch (ctx->inf.type) {
1719 case PMU_TYPE_L3C:
1720 list_add(&ctx->next, &xgene_pmu->l3cpmus);
1721 break;
1722 case PMU_TYPE_IOB:
1723 list_add(&ctx->next, &xgene_pmu->iobpmus);
1724 break;
c0f7f7ac
HT		 1725 case PMU_TYPE_IOB_SLOW:
1726 list_add(&ctx->next, &xgene_pmu->iobpmus);
1727 break;
832c927d
TN		 1728 case PMU_TYPE_MCB:
1729 list_add(&ctx->next, &xgene_pmu->mcbpmus);
1730 break;
1731 case PMU_TYPE_MC:
1732 list_add(&ctx->next, &xgene_pmu->mcpmus);
1733 break;
1734 }
1735 }
1736
1737 return 0;
1738}
1739
1740static int xgene_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1741 struct platform_device *pdev)
1742{
1743 if (has_acpi_companion(&pdev->dev))
1744 return acpi_pmu_probe_pmu_dev(xgene_pmu, pdev);
1745 return fdt_pmu_probe_pmu_dev(xgene_pmu, pdev);
1746}
1747
1748static const struct xgene_pmu_data xgene_pmu_data = {
1749 .id = PCP_PMU_V1,
1750};
1751
1752static const struct xgene_pmu_data xgene_pmu_v2_data = {
1753 .id = PCP_PMU_V2,
1754};
1755
e35e0a04
HT		 1756static const struct xgene_pmu_ops xgene_pmu_ops = {
1757 .mask_int = xgene_pmu_mask_int,
1758 .unmask_int = xgene_pmu_unmask_int,
1759 .read_counter = xgene_pmu_read_counter32,
1760 .write_counter = xgene_pmu_write_counter32,
1761 .write_evttype = xgene_pmu_write_evttype,
1762 .write_agentmsk = xgene_pmu_write_agentmsk,
1763 .write_agent1msk = xgene_pmu_write_agent1msk,
1764 .enable_counter = xgene_pmu_enable_counter,
1765 .disable_counter = xgene_pmu_disable_counter,
1766 .enable_counter_int = xgene_pmu_enable_counter_int,
1767 .disable_counter_int = xgene_pmu_disable_counter_int,
1768 .reset_counters = xgene_pmu_reset_counters,
1769 .start_counters = xgene_pmu_start_counters,
1770 .stop_counters = xgene_pmu_stop_counters,
1771};
1772
c0f7f7ac
HT		 1773static const struct xgene_pmu_ops xgene_pmu_v3_ops = {
1774 .mask_int = xgene_pmu_v3_mask_int,
1775 .unmask_int = xgene_pmu_v3_unmask_int,
1776 .read_counter = xgene_pmu_read_counter64,
1777 .write_counter = xgene_pmu_write_counter64,
1778 .write_evttype = xgene_pmu_write_evttype,
1779 .write_agentmsk = xgene_pmu_v3_write_agentmsk,
1780 .write_agent1msk = xgene_pmu_v3_write_agent1msk,
1781 .enable_counter = xgene_pmu_enable_counter,
1782 .disable_counter = xgene_pmu_disable_counter,
1783 .enable_counter_int = xgene_pmu_enable_counter_int,
1784 .disable_counter_int = xgene_pmu_disable_counter_int,
1785 .reset_counters = xgene_pmu_reset_counters,
1786 .start_counters = xgene_pmu_start_counters,
1787 .stop_counters = xgene_pmu_stop_counters,
1788};
1789
832c927d
TN		 1790static const struct of_device_id xgene_pmu_of_match[] = {
1791 { .compatible = "apm,xgene-pmu", .data = &xgene_pmu_data },
1792 { .compatible = "apm,xgene-pmu-v2", .data = &xgene_pmu_v2_data },
1793 {},
1794};
1795MODULE_DEVICE_TABLE(of, xgene_pmu_of_match);
1796#ifdef CONFIG_ACPI
1797static const struct acpi_device_id xgene_pmu_acpi_match[] = {
1798 {"APMC0D5B", PCP_PMU_V1},
1799 {"APMC0D5C", PCP_PMU_V2},
c0f7f7ac 1800 {"APMC0D83", PCP_PMU_V3},
832c927d
TN		 1801 {},
1802};
1803MODULE_DEVICE_TABLE(acpi, xgene_pmu_acpi_match);
1804#endif
1805
cbb72a3c
HT		 1806static int xgene_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
1807{
1808 struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,
1809 node);
1810
1811 if (cpumask_empty(&xgene_pmu->cpu))
1812 cpumask_set_cpu(cpu, &xgene_pmu->cpu);
1813
1814 /* Overflow interrupt also should use the same CPU */
1815 WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));
1816
1817 return 0;
1818}
1819
1820static int xgene_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
1821{
1822 struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,
1823 node);
1824 struct xgene_pmu_dev_ctx *ctx;
1825 unsigned int target;
1826
1827 if (!cpumask_test_and_clear_cpu(cpu, &xgene_pmu->cpu))
1828 return 0;
1829 target = cpumask_any_but(cpu_online_mask, cpu);
1830 if (target >= nr_cpu_ids)
1831 return 0;
1832
1833 list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {
1834 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1835 }
1836 list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {
1837 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1838 }
1839 list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {
1840 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1841 }
1842 list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {
1843 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1844 }
1845
1846 cpumask_set_cpu(target, &xgene_pmu->cpu);
1847 /* Overflow interrupt also should use the same CPU */
1848 WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));
1849
1850 return 0;
1851}
1852
832c927d
TN		 1853static int xgene_pmu_probe(struct platform_device *pdev)
1854{
1855 const struct xgene_pmu_data *dev_data;
1856 const struct of_device_id *of_id;
1857 struct xgene_pmu *xgene_pmu;
1858 struct resource *res;
1859 int irq, rc;
1860 int version;
1861
cbb72a3c
HT		 1862 /* Install a hook to update the reader CPU in case it goes offline */
1863 rc = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1864 "CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE",
1865 xgene_pmu_online_cpu,
1866 xgene_pmu_offline_cpu);
1867 if (rc)
1868 return rc;
1869
832c927d
TN		 1870 xgene_pmu = devm_kzalloc(&pdev->dev, sizeof(*xgene_pmu), GFP_KERNEL);
1871 if (!xgene_pmu)
1872 return -ENOMEM;
1873 xgene_pmu->dev = &pdev->dev;
1874 platform_set_drvdata(pdev, xgene_pmu);
1875
1876 version = -EINVAL;
1877 of_id = of_match_device(xgene_pmu_of_match, &pdev->dev);
1878 if (of_id) {
1879 dev_data = (const struct xgene_pmu_data *) of_id->data;
1880 version = dev_data->id;
1881 }
1882
1883#ifdef CONFIG_ACPI
1884 if (ACPI_COMPANION(&pdev->dev)) {
1885 const struct acpi_device_id *acpi_id;
1886
1887 acpi_id = acpi_match_device(xgene_pmu_acpi_match, &pdev->dev);
1888 if (acpi_id)
1889 version = (int) acpi_id->driver_data;
1890 }
1891#endif
1892 if (version < 0)
1893 return -ENODEV;
1894
c0f7f7ac
HT		 1895 if (version == PCP_PMU_V3)
1896 xgene_pmu->ops = &xgene_pmu_v3_ops;
1897 else
1898 xgene_pmu->ops = &xgene_pmu_ops;
e35e0a04 1899
832c927d
TN		 1900 INIT_LIST_HEAD(&xgene_pmu->l3cpmus);
1901 INIT_LIST_HEAD(&xgene_pmu->iobpmus);
1902 INIT_LIST_HEAD(&xgene_pmu->mcbpmus);
1903 INIT_LIST_HEAD(&xgene_pmu->mcpmus);
1904
1905 xgene_pmu->version = version;
1906 dev_info(&pdev->dev, "X-Gene PMU version %d\n", xgene_pmu->version);
1907
1908 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1909 xgene_pmu->pcppmu_csr = devm_ioremap_resource(&pdev->dev, res);
1910 if (IS_ERR(xgene_pmu->pcppmu_csr)) {
1911 dev_err(&pdev->dev, "ioremap failed for PCP PMU resource\n");
c1be2ddb 1912 return PTR_ERR(xgene_pmu->pcppmu_csr);
832c927d
TN		 1913 }
1914
1915 irq = platform_get_irq(pdev, 0);
1916 if (irq < 0) {
1917 dev_err(&pdev->dev, "No IRQ resource\n");
c1be2ddb 1918 return -EINVAL;
832c927d 1919 }
cbb72a3c 1920
832c927d
TN		 1921 rc = devm_request_irq(&pdev->dev, irq, xgene_pmu_isr,
1922 IRQF_NOBALANCING | IRQF_NO_THREAD,
1923 dev_name(&pdev->dev), xgene_pmu);
1924 if (rc) {
1925 dev_err(&pdev->dev, "Could not request IRQ %d\n", irq);
c1be2ddb 1926 return rc;
832c927d
TN		 1927 }
1928
cbb72a3c
HT		 1929 xgene_pmu->irq = irq;
1930
832c927d
TN		 1931 raw_spin_lock_init(&xgene_pmu->lock);
1932
1933 /* Check for active MCBs and MCUs */
c0f7f7ac 1934 rc = xgene_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
832c927d
TN		 1935 if (rc) {
1936 dev_warn(&pdev->dev, "Unknown MCB/MCU active status\n");
1937 xgene_pmu->mcb_active_mask = 0x1;
1938 xgene_pmu->mc_active_mask = 0x1;
1939 }
1940
cbb72a3c
HT		 1941 /* Add this instance to the list used by the hotplug callback */
1942 rc = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1943 &xgene_pmu->node);
832c927d 1944 if (rc) {
cbb72a3c 1945 dev_err(&pdev->dev, "Error %d registering hotplug", rc);
c1be2ddb 1946 return rc;
832c927d
TN		 1947 }
1948
1949 /* Walk through the tree for all PMU perf devices */
1950 rc = xgene_pmu_probe_pmu_dev(xgene_pmu, pdev);
1951 if (rc) {
1952 dev_err(&pdev->dev, "No PMU perf devices found!\n");
cbb72a3c 1953 goto out_unregister;
832c927d
TN		 1954 }
1955
1956 /* Enable interrupt */
e35e0a04 1957 xgene_pmu->ops->unmask_int(xgene_pmu);
832c927d
TN		 1958
1959 return 0;
cbb72a3c
HT		 1960
1961out_unregister:
1962 cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1963 &xgene_pmu->node);
1964 return rc;
832c927d
TN		 1965}
1966
1967static void
1968xgene_pmu_dev_cleanup(struct xgene_pmu *xgene_pmu, struct list_head *pmus)
1969{
1970 struct xgene_pmu_dev_ctx *ctx;
832c927d
TN		 1971
1972 list_for_each_entry(ctx, pmus, next) {
c1be2ddb 1973 perf_pmu_unregister(&ctx->pmu_dev->pmu);
832c927d
TN		 1974 }
1975}
1976
1977static int xgene_pmu_remove(struct platform_device *pdev)
1978{
1979 struct xgene_pmu *xgene_pmu = dev_get_drvdata(&pdev->dev);
1980
1981 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->l3cpmus);
1982 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->iobpmus);
1983 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcbpmus);
1984 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcpmus);
cbb72a3c
HT		 1985 cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1986 &xgene_pmu->node);
832c927d 1987
832c927d
TN		 1988 return 0;
1989}
1990
1991static struct platform_driver xgene_pmu_driver = {
1992 .probe = xgene_pmu_probe,
1993 .remove = xgene_pmu_remove,
1994 .driver = {
1995 .name = "xgene-pmu",
1996 .of_match_table = xgene_pmu_of_match,
1997 .acpi_match_table = ACPI_PTR(xgene_pmu_acpi_match),
1998 },
1999};
2000
2001builtin_platform_driver(xgene_pmu_driver);
Linux 6.x block layer and io_uring tree(s)