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7d839b4b NL |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | ||
3 | /* | |
4 | * This driver adds support for perf events to use the Performance | |
5 | * Monitor Counter Groups (PMCG) associated with an SMMUv3 node | |
6 | * to monitor that node. | |
7 | * | |
8 | * SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where | |
9 | * <phys_addr_page> is the physical page address of the SMMU PMCG wrapped | |
10 | * to 4K boundary. For example, the PMCG at 0xff88840000 is named | |
11 | * smmuv3_pmcg_ff88840 | |
12 | * | |
13 | * Filtering by stream id is done by specifying filtering parameters | |
14 | * with the event. options are: | |
15 | * filter_enable - 0 = no filtering, 1 = filtering enabled | |
16 | * filter_span - 0 = exact match, 1 = pattern match | |
17 | * filter_stream_id - pattern to filter against | |
18 | * | |
19 | * To match a partial StreamID where the X most-significant bits must match | |
20 | * but the Y least-significant bits might differ, STREAMID is programmed | |
21 | * with a value that contains: | |
22 | * STREAMID[Y - 1] == 0. | |
23 | * STREAMID[Y - 2:0] == 1 (where Y > 1). | |
24 | * The remainder of implemented bits of STREAMID (X bits, from bit Y upwards) | |
25 | * contain a value to match from the corresponding bits of event StreamID. | |
26 | * | |
27 | * Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1, | |
28 | * filter_span=1,filter_stream_id=0x42/ -a netperf | |
29 | * Applies filter pattern 0x42 to transaction events, which means events | |
30 | * matching stream ids 0x42 and 0x43 are counted. Further filtering | |
31 | * information is available in the SMMU documentation. | |
32 | * | |
33 | * SMMU events are not attributable to a CPU, so task mode and sampling | |
34 | * are not supported. | |
35 | */ | |
36 | ||
37 | #include <linux/acpi.h> | |
24062fe8 | 38 | #include <linux/acpi_iort.h> |
7d839b4b NL |
39 | #include <linux/bitfield.h> |
40 | #include <linux/bitops.h> | |
41 | #include <linux/cpuhotplug.h> | |
42 | #include <linux/cpumask.h> | |
43 | #include <linux/device.h> | |
44 | #include <linux/errno.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/irq.h> | |
47 | #include <linux/kernel.h> | |
48 | #include <linux/list.h> | |
49 | #include <linux/msi.h> | |
3f7be435 | 50 | #include <linux/of.h> |
7d839b4b NL |
51 | #include <linux/perf_event.h> |
52 | #include <linux/platform_device.h> | |
53 | #include <linux/smp.h> | |
54 | #include <linux/sysfs.h> | |
55 | #include <linux/types.h> | |
56 | ||
57 | #define SMMU_PMCG_EVCNTR0 0x0 | |
58 | #define SMMU_PMCG_EVCNTR(n, stride) (SMMU_PMCG_EVCNTR0 + (n) * (stride)) | |
59 | #define SMMU_PMCG_EVTYPER0 0x400 | |
60 | #define SMMU_PMCG_EVTYPER(n) (SMMU_PMCG_EVTYPER0 + (n) * 4) | |
61 | #define SMMU_PMCG_SID_SPAN_SHIFT 29 | |
62 | #define SMMU_PMCG_SMR0 0xA00 | |
63 | #define SMMU_PMCG_SMR(n) (SMMU_PMCG_SMR0 + (n) * 4) | |
64 | #define SMMU_PMCG_CNTENSET0 0xC00 | |
65 | #define SMMU_PMCG_CNTENCLR0 0xC20 | |
66 | #define SMMU_PMCG_INTENSET0 0xC40 | |
67 | #define SMMU_PMCG_INTENCLR0 0xC60 | |
68 | #define SMMU_PMCG_OVSCLR0 0xC80 | |
69 | #define SMMU_PMCG_OVSSET0 0xCC0 | |
70 | #define SMMU_PMCG_CFGR 0xE00 | |
71 | #define SMMU_PMCG_CFGR_SID_FILTER_TYPE BIT(23) | |
f202cdab | 72 | #define SMMU_PMCG_CFGR_MSI BIT(21) |
7d839b4b NL |
73 | #define SMMU_PMCG_CFGR_RELOC_CTRS BIT(20) |
74 | #define SMMU_PMCG_CFGR_SIZE GENMASK(13, 8) | |
75 | #define SMMU_PMCG_CFGR_NCTR GENMASK(5, 0) | |
76 | #define SMMU_PMCG_CR 0xE04 | |
77 | #define SMMU_PMCG_CR_ENABLE BIT(0) | |
2c255223 | 78 | #define SMMU_PMCG_IIDR 0xE08 |
df457ca9 RM |
79 | #define SMMU_PMCG_IIDR_PRODUCTID GENMASK(31, 20) |
80 | #define SMMU_PMCG_IIDR_VARIANT GENMASK(19, 16) | |
81 | #define SMMU_PMCG_IIDR_REVISION GENMASK(15, 12) | |
82 | #define SMMU_PMCG_IIDR_IMPLEMENTER GENMASK(11, 0) | |
7d839b4b NL |
83 | #define SMMU_PMCG_CEID0 0xE20 |
84 | #define SMMU_PMCG_CEID1 0xE28 | |
85 | #define SMMU_PMCG_IRQ_CTRL 0xE50 | |
86 | #define SMMU_PMCG_IRQ_CTRL_IRQEN BIT(0) | |
87 | #define SMMU_PMCG_IRQ_CFG0 0xE58 | |
f202cdab SK |
88 | #define SMMU_PMCG_IRQ_CFG1 0xE60 |
89 | #define SMMU_PMCG_IRQ_CFG2 0xE64 | |
90 | ||
df457ca9 RM |
91 | /* IMP-DEF ID registers */ |
92 | #define SMMU_PMCG_PIDR0 0xFE0 | |
93 | #define SMMU_PMCG_PIDR0_PART_0 GENMASK(7, 0) | |
94 | #define SMMU_PMCG_PIDR1 0xFE4 | |
95 | #define SMMU_PMCG_PIDR1_DES_0 GENMASK(7, 4) | |
96 | #define SMMU_PMCG_PIDR1_PART_1 GENMASK(3, 0) | |
97 | #define SMMU_PMCG_PIDR2 0xFE8 | |
98 | #define SMMU_PMCG_PIDR2_REVISION GENMASK(7, 4) | |
99 | #define SMMU_PMCG_PIDR2_DES_1 GENMASK(2, 0) | |
100 | #define SMMU_PMCG_PIDR3 0xFEC | |
101 | #define SMMU_PMCG_PIDR3_REVAND GENMASK(7, 4) | |
102 | #define SMMU_PMCG_PIDR4 0xFD0 | |
103 | #define SMMU_PMCG_PIDR4_DES_2 GENMASK(3, 0) | |
104 | ||
f202cdab SK |
105 | /* MSI config fields */ |
106 | #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) | |
107 | #define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1 | |
7d839b4b NL |
108 | |
109 | #define SMMU_PMCG_DEFAULT_FILTER_SPAN 1 | |
110 | #define SMMU_PMCG_DEFAULT_FILTER_SID GENMASK(31, 0) | |
111 | ||
112 | #define SMMU_PMCG_MAX_COUNTERS 64 | |
113 | #define SMMU_PMCG_ARCH_MAX_EVENTS 128 | |
114 | ||
115 | #define SMMU_PMCG_PA_SHIFT 12 | |
116 | ||
24062fe8 SK |
117 | #define SMMU_PMCG_EVCNTR_RDONLY BIT(0) |
118 | ||
7d839b4b NL |
119 | static int cpuhp_state_num; |
120 | ||
121 | struct smmu_pmu { | |
122 | struct hlist_node node; | |
123 | struct perf_event *events[SMMU_PMCG_MAX_COUNTERS]; | |
124 | DECLARE_BITMAP(used_counters, SMMU_PMCG_MAX_COUNTERS); | |
125 | DECLARE_BITMAP(supported_events, SMMU_PMCG_ARCH_MAX_EVENTS); | |
126 | unsigned int irq; | |
127 | unsigned int on_cpu; | |
128 | struct pmu pmu; | |
129 | unsigned int num_counters; | |
130 | struct device *dev; | |
131 | void __iomem *reg_base; | |
132 | void __iomem *reloc_base; | |
133 | u64 counter_mask; | |
24062fe8 | 134 | u32 options; |
2c255223 | 135 | u32 iidr; |
7d839b4b | 136 | bool global_filter; |
7d839b4b NL |
137 | }; |
138 | ||
139 | #define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu)) | |
140 | ||
141 | #define SMMU_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, _end) \ | |
142 | static inline u32 get_##_name(struct perf_event *event) \ | |
143 | { \ | |
144 | return FIELD_GET(GENMASK_ULL(_end, _start), \ | |
145 | event->attr._config); \ | |
146 | } \ | |
147 | ||
148 | SMMU_PMU_EVENT_ATTR_EXTRACTOR(event, config, 0, 15); | |
149 | SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_stream_id, config1, 0, 31); | |
150 | SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_span, config1, 32, 32); | |
151 | SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_enable, config1, 33, 33); | |
152 | ||
153 | static inline void smmu_pmu_enable(struct pmu *pmu) | |
154 | { | |
155 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu); | |
156 | ||
157 | writel(SMMU_PMCG_IRQ_CTRL_IRQEN, | |
158 | smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL); | |
159 | writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR); | |
160 | } | |
161 | ||
162 | static inline void smmu_pmu_disable(struct pmu *pmu) | |
163 | { | |
164 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu); | |
165 | ||
166 | writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR); | |
167 | writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL); | |
168 | } | |
169 | ||
170 | static inline void smmu_pmu_counter_set_value(struct smmu_pmu *smmu_pmu, | |
171 | u32 idx, u64 value) | |
172 | { | |
173 | if (smmu_pmu->counter_mask & BIT(32)) | |
174 | writeq(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8)); | |
175 | else | |
176 | writel(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4)); | |
177 | } | |
178 | ||
179 | static inline u64 smmu_pmu_counter_get_value(struct smmu_pmu *smmu_pmu, u32 idx) | |
180 | { | |
181 | u64 value; | |
182 | ||
183 | if (smmu_pmu->counter_mask & BIT(32)) | |
184 | value = readq(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8)); | |
185 | else | |
186 | value = readl(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4)); | |
187 | ||
188 | return value; | |
189 | } | |
190 | ||
191 | static inline void smmu_pmu_counter_enable(struct smmu_pmu *smmu_pmu, u32 idx) | |
192 | { | |
193 | writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0); | |
194 | } | |
195 | ||
196 | static inline void smmu_pmu_counter_disable(struct smmu_pmu *smmu_pmu, u32 idx) | |
197 | { | |
198 | writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0); | |
199 | } | |
200 | ||
201 | static inline void smmu_pmu_interrupt_enable(struct smmu_pmu *smmu_pmu, u32 idx) | |
202 | { | |
203 | writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0); | |
204 | } | |
205 | ||
206 | static inline void smmu_pmu_interrupt_disable(struct smmu_pmu *smmu_pmu, | |
207 | u32 idx) | |
208 | { | |
209 | writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0); | |
210 | } | |
211 | ||
212 | static inline void smmu_pmu_set_evtyper(struct smmu_pmu *smmu_pmu, u32 idx, | |
213 | u32 val) | |
214 | { | |
215 | writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx)); | |
216 | } | |
217 | ||
218 | static inline void smmu_pmu_set_smr(struct smmu_pmu *smmu_pmu, u32 idx, u32 val) | |
219 | { | |
220 | writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx)); | |
221 | } | |
222 | ||
223 | static void smmu_pmu_event_update(struct perf_event *event) | |
224 | { | |
225 | struct hw_perf_event *hwc = &event->hw; | |
226 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu); | |
227 | u64 delta, prev, now; | |
228 | u32 idx = hwc->idx; | |
229 | ||
230 | do { | |
231 | prev = local64_read(&hwc->prev_count); | |
232 | now = smmu_pmu_counter_get_value(smmu_pmu, idx); | |
233 | } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev); | |
234 | ||
235 | /* handle overflow. */ | |
236 | delta = now - prev; | |
237 | delta &= smmu_pmu->counter_mask; | |
238 | ||
239 | local64_add(delta, &event->count); | |
240 | } | |
241 | ||
242 | static void smmu_pmu_set_period(struct smmu_pmu *smmu_pmu, | |
243 | struct hw_perf_event *hwc) | |
244 | { | |
245 | u32 idx = hwc->idx; | |
246 | u64 new; | |
247 | ||
24062fe8 SK |
248 | if (smmu_pmu->options & SMMU_PMCG_EVCNTR_RDONLY) { |
249 | /* | |
250 | * On platforms that require this quirk, if the counter starts | |
251 | * at < half_counter value and wraps, the current logic of | |
252 | * handling the overflow may not work. It is expected that, | |
253 | * those platforms will have full 64 counter bits implemented | |
254 | * so that such a possibility is remote(eg: HiSilicon HIP08). | |
255 | */ | |
256 | new = smmu_pmu_counter_get_value(smmu_pmu, idx); | |
257 | } else { | |
258 | /* | |
259 | * We limit the max period to half the max counter value | |
260 | * of the counter size, so that even in the case of extreme | |
261 | * interrupt latency the counter will (hopefully) not wrap | |
262 | * past its initial value. | |
263 | */ | |
264 | new = smmu_pmu->counter_mask >> 1; | |
265 | smmu_pmu_counter_set_value(smmu_pmu, idx, new); | |
266 | } | |
7d839b4b NL |
267 | |
268 | local64_set(&hwc->prev_count, new); | |
7d839b4b NL |
269 | } |
270 | ||
271 | static void smmu_pmu_set_event_filter(struct perf_event *event, | |
272 | int idx, u32 span, u32 sid) | |
273 | { | |
274 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu); | |
275 | u32 evtyper; | |
276 | ||
277 | evtyper = get_event(event) | span << SMMU_PMCG_SID_SPAN_SHIFT; | |
278 | smmu_pmu_set_evtyper(smmu_pmu, idx, evtyper); | |
279 | smmu_pmu_set_smr(smmu_pmu, idx, sid); | |
280 | } | |
281 | ||
3c934735 RM |
282 | static bool smmu_pmu_check_global_filter(struct perf_event *curr, |
283 | struct perf_event *new) | |
284 | { | |
285 | if (get_filter_enable(new) != get_filter_enable(curr)) | |
286 | return false; | |
287 | ||
288 | if (!get_filter_enable(new)) | |
289 | return true; | |
290 | ||
291 | return get_filter_span(new) == get_filter_span(curr) && | |
292 | get_filter_stream_id(new) == get_filter_stream_id(curr); | |
293 | } | |
294 | ||
7d839b4b NL |
295 | static int smmu_pmu_apply_event_filter(struct smmu_pmu *smmu_pmu, |
296 | struct perf_event *event, int idx) | |
297 | { | |
298 | u32 span, sid; | |
4c1daba1 | 299 | unsigned int cur_idx, num_ctrs = smmu_pmu->num_counters; |
7d839b4b NL |
300 | bool filter_en = !!get_filter_enable(event); |
301 | ||
302 | span = filter_en ? get_filter_span(event) : | |
303 | SMMU_PMCG_DEFAULT_FILTER_SPAN; | |
304 | sid = filter_en ? get_filter_stream_id(event) : | |
305 | SMMU_PMCG_DEFAULT_FILTER_SID; | |
306 | ||
4c1daba1 RM |
307 | cur_idx = find_first_bit(smmu_pmu->used_counters, num_ctrs); |
308 | /* | |
309 | * Per-counter filtering, or scheduling the first globally-filtered | |
310 | * event into an empty PMU so idx == 0 and it works out equivalent. | |
311 | */ | |
312 | if (!smmu_pmu->global_filter || cur_idx == num_ctrs) { | |
7d839b4b NL |
313 | smmu_pmu_set_event_filter(event, idx, span, sid); |
314 | return 0; | |
315 | } | |
316 | ||
4c1daba1 RM |
317 | /* Otherwise, must match whatever's currently scheduled */ |
318 | if (smmu_pmu_check_global_filter(smmu_pmu->events[cur_idx], event)) { | |
319 | smmu_pmu_set_evtyper(smmu_pmu, idx, get_event(event)); | |
7d839b4b | 320 | return 0; |
3c934735 | 321 | } |
7d839b4b | 322 | |
3c934735 | 323 | return -EAGAIN; |
7d839b4b NL |
324 | } |
325 | ||
326 | static int smmu_pmu_get_event_idx(struct smmu_pmu *smmu_pmu, | |
327 | struct perf_event *event) | |
328 | { | |
329 | int idx, err; | |
330 | unsigned int num_ctrs = smmu_pmu->num_counters; | |
331 | ||
332 | idx = find_first_zero_bit(smmu_pmu->used_counters, num_ctrs); | |
333 | if (idx == num_ctrs) | |
334 | /* The counters are all in use. */ | |
335 | return -EAGAIN; | |
336 | ||
337 | err = smmu_pmu_apply_event_filter(smmu_pmu, event, idx); | |
338 | if (err) | |
339 | return err; | |
340 | ||
341 | set_bit(idx, smmu_pmu->used_counters); | |
342 | ||
343 | return idx; | |
344 | } | |
345 | ||
3c934735 RM |
346 | static bool smmu_pmu_events_compatible(struct perf_event *curr, |
347 | struct perf_event *new) | |
348 | { | |
349 | if (new->pmu != curr->pmu) | |
350 | return false; | |
351 | ||
352 | if (to_smmu_pmu(new->pmu)->global_filter && | |
353 | !smmu_pmu_check_global_filter(curr, new)) | |
354 | return false; | |
355 | ||
356 | return true; | |
357 | } | |
358 | ||
7d839b4b NL |
359 | /* |
360 | * Implementation of abstract pmu functionality required by | |
361 | * the core perf events code. | |
362 | */ | |
363 | ||
364 | static int smmu_pmu_event_init(struct perf_event *event) | |
365 | { | |
366 | struct hw_perf_event *hwc = &event->hw; | |
367 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu); | |
368 | struct device *dev = smmu_pmu->dev; | |
369 | struct perf_event *sibling; | |
33e84ea4 | 370 | int group_num_events = 1; |
7d839b4b NL |
371 | u16 event_id; |
372 | ||
373 | if (event->attr.type != event->pmu->type) | |
374 | return -ENOENT; | |
375 | ||
376 | if (hwc->sample_period) { | |
377 | dev_dbg(dev, "Sampling not supported\n"); | |
378 | return -EOPNOTSUPP; | |
379 | } | |
380 | ||
381 | if (event->cpu < 0) { | |
382 | dev_dbg(dev, "Per-task mode not supported\n"); | |
383 | return -EOPNOTSUPP; | |
384 | } | |
385 | ||
386 | /* Verify specified event is supported on this PMU */ | |
387 | event_id = get_event(event); | |
388 | if (event_id < SMMU_PMCG_ARCH_MAX_EVENTS && | |
389 | (!test_bit(event_id, smmu_pmu->supported_events))) { | |
390 | dev_dbg(dev, "Invalid event %d for this PMU\n", event_id); | |
391 | return -EINVAL; | |
392 | } | |
393 | ||
394 | /* Don't allow groups with mixed PMUs, except for s/w events */ | |
33e84ea4 | 395 | if (!is_software_event(event->group_leader)) { |
3c934735 | 396 | if (!smmu_pmu_events_compatible(event->group_leader, event)) |
33e84ea4 RM |
397 | return -EINVAL; |
398 | ||
399 | if (++group_num_events > smmu_pmu->num_counters) | |
400 | return -EINVAL; | |
7d839b4b NL |
401 | } |
402 | ||
403 | for_each_sibling_event(sibling, event->group_leader) { | |
33e84ea4 RM |
404 | if (is_software_event(sibling)) |
405 | continue; | |
406 | ||
3c934735 | 407 | if (!smmu_pmu_events_compatible(sibling, event)) |
33e84ea4 RM |
408 | return -EINVAL; |
409 | ||
410 | if (++group_num_events > smmu_pmu->num_counters) | |
7d839b4b | 411 | return -EINVAL; |
7d839b4b NL |
412 | } |
413 | ||
414 | hwc->idx = -1; | |
415 | ||
416 | /* | |
417 | * Ensure all events are on the same cpu so all events are in the | |
418 | * same cpu context, to avoid races on pmu_enable etc. | |
419 | */ | |
420 | event->cpu = smmu_pmu->on_cpu; | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
425 | static void smmu_pmu_event_start(struct perf_event *event, int flags) | |
426 | { | |
427 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu); | |
428 | struct hw_perf_event *hwc = &event->hw; | |
429 | int idx = hwc->idx; | |
430 | ||
431 | hwc->state = 0; | |
432 | ||
433 | smmu_pmu_set_period(smmu_pmu, hwc); | |
434 | ||
435 | smmu_pmu_counter_enable(smmu_pmu, idx); | |
436 | } | |
437 | ||
438 | static void smmu_pmu_event_stop(struct perf_event *event, int flags) | |
439 | { | |
440 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu); | |
441 | struct hw_perf_event *hwc = &event->hw; | |
442 | int idx = hwc->idx; | |
443 | ||
444 | if (hwc->state & PERF_HES_STOPPED) | |
445 | return; | |
446 | ||
447 | smmu_pmu_counter_disable(smmu_pmu, idx); | |
448 | /* As the counter gets updated on _start, ignore PERF_EF_UPDATE */ | |
449 | smmu_pmu_event_update(event); | |
450 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
451 | } | |
452 | ||
453 | static int smmu_pmu_event_add(struct perf_event *event, int flags) | |
454 | { | |
455 | struct hw_perf_event *hwc = &event->hw; | |
456 | int idx; | |
457 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu); | |
458 | ||
459 | idx = smmu_pmu_get_event_idx(smmu_pmu, event); | |
460 | if (idx < 0) | |
461 | return idx; | |
462 | ||
463 | hwc->idx = idx; | |
464 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
465 | smmu_pmu->events[idx] = event; | |
466 | local64_set(&hwc->prev_count, 0); | |
467 | ||
468 | smmu_pmu_interrupt_enable(smmu_pmu, idx); | |
469 | ||
470 | if (flags & PERF_EF_START) | |
471 | smmu_pmu_event_start(event, flags); | |
472 | ||
473 | /* Propagate changes to the userspace mapping. */ | |
474 | perf_event_update_userpage(event); | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | static void smmu_pmu_event_del(struct perf_event *event, int flags) | |
480 | { | |
481 | struct hw_perf_event *hwc = &event->hw; | |
482 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu); | |
483 | int idx = hwc->idx; | |
484 | ||
485 | smmu_pmu_event_stop(event, flags | PERF_EF_UPDATE); | |
486 | smmu_pmu_interrupt_disable(smmu_pmu, idx); | |
487 | smmu_pmu->events[idx] = NULL; | |
488 | clear_bit(idx, smmu_pmu->used_counters); | |
489 | ||
490 | perf_event_update_userpage(event); | |
491 | } | |
492 | ||
493 | static void smmu_pmu_event_read(struct perf_event *event) | |
494 | { | |
495 | smmu_pmu_event_update(event); | |
496 | } | |
497 | ||
498 | /* cpumask */ | |
499 | ||
500 | static ssize_t smmu_pmu_cpumask_show(struct device *dev, | |
501 | struct device_attribute *attr, | |
502 | char *buf) | |
503 | { | |
504 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev)); | |
505 | ||
506 | return cpumap_print_to_pagebuf(true, buf, cpumask_of(smmu_pmu->on_cpu)); | |
507 | } | |
508 | ||
509 | static struct device_attribute smmu_pmu_cpumask_attr = | |
510 | __ATTR(cpumask, 0444, smmu_pmu_cpumask_show, NULL); | |
511 | ||
512 | static struct attribute *smmu_pmu_cpumask_attrs[] = { | |
513 | &smmu_pmu_cpumask_attr.attr, | |
514 | NULL | |
515 | }; | |
516 | ||
f0c14048 | 517 | static const struct attribute_group smmu_pmu_cpumask_group = { |
7d839b4b NL |
518 | .attrs = smmu_pmu_cpumask_attrs, |
519 | }; | |
520 | ||
521 | /* Events */ | |
522 | ||
523 | static ssize_t smmu_pmu_event_show(struct device *dev, | |
524 | struct device_attribute *attr, char *page) | |
525 | { | |
526 | struct perf_pmu_events_attr *pmu_attr; | |
527 | ||
528 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
529 | ||
fb62d675 | 530 | return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); |
7d839b4b NL |
531 | } |
532 | ||
7ac87a8d QL |
533 | #define SMMU_EVENT_ATTR(name, config) \ |
534 | PMU_EVENT_ATTR_ID(name, smmu_pmu_event_show, config) | |
7d839b4b NL |
535 | |
536 | static struct attribute *smmu_pmu_events[] = { | |
17474413 QL |
537 | SMMU_EVENT_ATTR(cycles, 0), |
538 | SMMU_EVENT_ATTR(transaction, 1), | |
539 | SMMU_EVENT_ATTR(tlb_miss, 2), | |
540 | SMMU_EVENT_ATTR(config_cache_miss, 3), | |
541 | SMMU_EVENT_ATTR(trans_table_walk_access, 4), | |
542 | SMMU_EVENT_ATTR(config_struct_access, 5), | |
543 | SMMU_EVENT_ATTR(pcie_ats_trans_rq, 6), | |
544 | SMMU_EVENT_ATTR(pcie_ats_trans_passed, 7), | |
7d839b4b NL |
545 | NULL |
546 | }; | |
547 | ||
548 | static umode_t smmu_pmu_event_is_visible(struct kobject *kobj, | |
549 | struct attribute *attr, int unused) | |
550 | { | |
551 | struct device *dev = kobj_to_dev(kobj); | |
552 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev)); | |
553 | struct perf_pmu_events_attr *pmu_attr; | |
554 | ||
555 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr); | |
556 | ||
557 | if (test_bit(pmu_attr->id, smmu_pmu->supported_events)) | |
558 | return attr->mode; | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
f0c14048 | 563 | static const struct attribute_group smmu_pmu_events_group = { |
7d839b4b NL |
564 | .name = "events", |
565 | .attrs = smmu_pmu_events, | |
566 | .is_visible = smmu_pmu_event_is_visible, | |
567 | }; | |
568 | ||
2c255223 JG |
569 | static ssize_t smmu_pmu_identifier_attr_show(struct device *dev, |
570 | struct device_attribute *attr, | |
571 | char *page) | |
572 | { | |
573 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev)); | |
574 | ||
700a9cf0 | 575 | return sysfs_emit(page, "0x%08x\n", smmu_pmu->iidr); |
2c255223 JG |
576 | } |
577 | ||
578 | static umode_t smmu_pmu_identifier_attr_visible(struct kobject *kobj, | |
579 | struct attribute *attr, | |
580 | int n) | |
581 | { | |
582 | struct device *dev = kobj_to_dev(kobj); | |
583 | struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev)); | |
584 | ||
585 | if (!smmu_pmu->iidr) | |
586 | return 0; | |
587 | return attr->mode; | |
588 | } | |
589 | ||
590 | static struct device_attribute smmu_pmu_identifier_attr = | |
591 | __ATTR(identifier, 0444, smmu_pmu_identifier_attr_show, NULL); | |
592 | ||
593 | static struct attribute *smmu_pmu_identifier_attrs[] = { | |
594 | &smmu_pmu_identifier_attr.attr, | |
595 | NULL | |
596 | }; | |
597 | ||
f0c14048 | 598 | static const struct attribute_group smmu_pmu_identifier_group = { |
2c255223 JG |
599 | .attrs = smmu_pmu_identifier_attrs, |
600 | .is_visible = smmu_pmu_identifier_attr_visible, | |
601 | }; | |
602 | ||
7d839b4b NL |
603 | /* Formats */ |
604 | PMU_FORMAT_ATTR(event, "config:0-15"); | |
605 | PMU_FORMAT_ATTR(filter_stream_id, "config1:0-31"); | |
606 | PMU_FORMAT_ATTR(filter_span, "config1:32"); | |
607 | PMU_FORMAT_ATTR(filter_enable, "config1:33"); | |
608 | ||
609 | static struct attribute *smmu_pmu_formats[] = { | |
610 | &format_attr_event.attr, | |
611 | &format_attr_filter_stream_id.attr, | |
612 | &format_attr_filter_span.attr, | |
613 | &format_attr_filter_enable.attr, | |
614 | NULL | |
615 | }; | |
616 | ||
f0c14048 | 617 | static const struct attribute_group smmu_pmu_format_group = { |
7d839b4b NL |
618 | .name = "format", |
619 | .attrs = smmu_pmu_formats, | |
620 | }; | |
621 | ||
622 | static const struct attribute_group *smmu_pmu_attr_grps[] = { | |
623 | &smmu_pmu_cpumask_group, | |
624 | &smmu_pmu_events_group, | |
625 | &smmu_pmu_format_group, | |
2c255223 | 626 | &smmu_pmu_identifier_group, |
7d839b4b NL |
627 | NULL |
628 | }; | |
629 | ||
630 | /* | |
631 | * Generic device handlers | |
632 | */ | |
633 | ||
634 | static int smmu_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) | |
635 | { | |
636 | struct smmu_pmu *smmu_pmu; | |
637 | unsigned int target; | |
638 | ||
639 | smmu_pmu = hlist_entry_safe(node, struct smmu_pmu, node); | |
640 | if (cpu != smmu_pmu->on_cpu) | |
641 | return 0; | |
642 | ||
643 | target = cpumask_any_but(cpu_online_mask, cpu); | |
644 | if (target >= nr_cpu_ids) | |
645 | return 0; | |
646 | ||
647 | perf_pmu_migrate_context(&smmu_pmu->pmu, cpu, target); | |
648 | smmu_pmu->on_cpu = target; | |
26210545 | 649 | WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(target))); |
7d839b4b NL |
650 | |
651 | return 0; | |
652 | } | |
653 | ||
654 | static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data) | |
655 | { | |
656 | struct smmu_pmu *smmu_pmu = data; | |
657 | u64 ovsr; | |
658 | unsigned int idx; | |
659 | ||
660 | ovsr = readq(smmu_pmu->reloc_base + SMMU_PMCG_OVSSET0); | |
661 | if (!ovsr) | |
662 | return IRQ_NONE; | |
663 | ||
664 | writeq(ovsr, smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0); | |
665 | ||
666 | for_each_set_bit(idx, (unsigned long *)&ovsr, smmu_pmu->num_counters) { | |
667 | struct perf_event *event = smmu_pmu->events[idx]; | |
668 | struct hw_perf_event *hwc; | |
669 | ||
670 | if (WARN_ON_ONCE(!event)) | |
671 | continue; | |
672 | ||
673 | smmu_pmu_event_update(event); | |
674 | hwc = &event->hw; | |
675 | ||
676 | smmu_pmu_set_period(smmu_pmu, hwc); | |
677 | } | |
678 | ||
679 | return IRQ_HANDLED; | |
680 | } | |
681 | ||
f202cdab SK |
682 | static void smmu_pmu_free_msis(void *data) |
683 | { | |
684 | struct device *dev = data; | |
685 | ||
686 | platform_msi_domain_free_irqs(dev); | |
687 | } | |
688 | ||
689 | static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) | |
690 | { | |
691 | phys_addr_t doorbell; | |
692 | struct device *dev = msi_desc_to_dev(desc); | |
693 | struct smmu_pmu *pmu = dev_get_drvdata(dev); | |
694 | ||
695 | doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; | |
696 | doorbell &= MSI_CFG0_ADDR_MASK; | |
697 | ||
698 | writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); | |
699 | writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1); | |
700 | writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE, | |
701 | pmu->reg_base + SMMU_PMCG_IRQ_CFG2); | |
702 | } | |
703 | ||
704 | static void smmu_pmu_setup_msi(struct smmu_pmu *pmu) | |
705 | { | |
706 | struct msi_desc *desc; | |
707 | struct device *dev = pmu->dev; | |
708 | int ret; | |
709 | ||
710 | /* Clear MSI address reg */ | |
711 | writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); | |
712 | ||
713 | /* MSI supported or not */ | |
714 | if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI)) | |
715 | return; | |
716 | ||
717 | ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg); | |
718 | if (ret) { | |
719 | dev_warn(dev, "failed to allocate MSIs\n"); | |
720 | return; | |
721 | } | |
722 | ||
723 | desc = first_msi_entry(dev); | |
724 | if (desc) | |
725 | pmu->irq = desc->irq; | |
726 | ||
727 | /* Add callback to free MSIs on teardown */ | |
728 | devm_add_action(dev, smmu_pmu_free_msis, dev); | |
729 | } | |
730 | ||
7d839b4b NL |
731 | static int smmu_pmu_setup_irq(struct smmu_pmu *pmu) |
732 | { | |
733 | unsigned long flags = IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD; | |
734 | int irq, ret = -ENXIO; | |
735 | ||
f202cdab SK |
736 | smmu_pmu_setup_msi(pmu); |
737 | ||
7d839b4b NL |
738 | irq = pmu->irq; |
739 | if (irq) | |
740 | ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq, | |
741 | flags, "smmuv3-pmu", pmu); | |
742 | return ret; | |
743 | } | |
744 | ||
745 | static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu) | |
746 | { | |
747 | u64 counter_present_mask = GENMASK_ULL(smmu_pmu->num_counters - 1, 0); | |
748 | ||
749 | smmu_pmu_disable(&smmu_pmu->pmu); | |
750 | ||
751 | /* Disable counter and interrupt */ | |
752 | writeq_relaxed(counter_present_mask, | |
753 | smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0); | |
754 | writeq_relaxed(counter_present_mask, | |
755 | smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0); | |
756 | writeq_relaxed(counter_present_mask, | |
757 | smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0); | |
758 | } | |
759 | ||
24062fe8 SK |
760 | static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu) |
761 | { | |
762 | u32 model; | |
763 | ||
764 | model = *(u32 *)dev_get_platdata(smmu_pmu->dev); | |
765 | ||
766 | switch (model) { | |
767 | case IORT_SMMU_V3_PMCG_HISI_HIP08: | |
768 | /* HiSilicon Erratum 162001800 */ | |
769 | smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY; | |
770 | break; | |
771 | } | |
772 | ||
773 | dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options); | |
774 | } | |
775 | ||
df457ca9 RM |
776 | static bool smmu_pmu_coresight_id_regs(struct smmu_pmu *smmu_pmu) |
777 | { | |
778 | return of_device_is_compatible(smmu_pmu->dev->of_node, | |
779 | "arm,mmu-600-pmcg"); | |
780 | } | |
781 | ||
782 | static void smmu_pmu_get_iidr(struct smmu_pmu *smmu_pmu) | |
783 | { | |
784 | u32 iidr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_IIDR); | |
785 | ||
786 | if (!iidr && smmu_pmu_coresight_id_regs(smmu_pmu)) { | |
787 | u32 pidr0 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR0); | |
788 | u32 pidr1 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR1); | |
789 | u32 pidr2 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR2); | |
790 | u32 pidr3 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR3); | |
791 | u32 pidr4 = readl(smmu_pmu->reg_base + SMMU_PMCG_PIDR4); | |
792 | ||
793 | u32 productid = FIELD_GET(SMMU_PMCG_PIDR0_PART_0, pidr0) | | |
794 | (FIELD_GET(SMMU_PMCG_PIDR1_PART_1, pidr1) << 8); | |
795 | u32 variant = FIELD_GET(SMMU_PMCG_PIDR2_REVISION, pidr2); | |
796 | u32 revision = FIELD_GET(SMMU_PMCG_PIDR3_REVAND, pidr3); | |
797 | u32 implementer = | |
798 | FIELD_GET(SMMU_PMCG_PIDR1_DES_0, pidr1) | | |
799 | (FIELD_GET(SMMU_PMCG_PIDR2_DES_1, pidr2) << 4) | | |
800 | (FIELD_GET(SMMU_PMCG_PIDR4_DES_2, pidr4) << 8); | |
801 | ||
802 | iidr = FIELD_PREP(SMMU_PMCG_IIDR_PRODUCTID, productid) | | |
803 | FIELD_PREP(SMMU_PMCG_IIDR_VARIANT, variant) | | |
804 | FIELD_PREP(SMMU_PMCG_IIDR_REVISION, revision) | | |
805 | FIELD_PREP(SMMU_PMCG_IIDR_IMPLEMENTER, implementer); | |
806 | } | |
807 | ||
808 | smmu_pmu->iidr = iidr; | |
809 | } | |
810 | ||
7d839b4b NL |
811 | static int smmu_pmu_probe(struct platform_device *pdev) |
812 | { | |
813 | struct smmu_pmu *smmu_pmu; | |
c8b0de76 | 814 | struct resource *res_0; |
7d839b4b NL |
815 | u32 cfgr, reg_size; |
816 | u64 ceid_64[2]; | |
817 | int irq, err; | |
818 | char *name; | |
819 | struct device *dev = &pdev->dev; | |
820 | ||
821 | smmu_pmu = devm_kzalloc(dev, sizeof(*smmu_pmu), GFP_KERNEL); | |
822 | if (!smmu_pmu) | |
823 | return -ENOMEM; | |
824 | ||
825 | smmu_pmu->dev = dev; | |
826 | platform_set_drvdata(pdev, smmu_pmu); | |
827 | ||
828 | smmu_pmu->pmu = (struct pmu) { | |
bdc5c744 | 829 | .module = THIS_MODULE, |
7d839b4b NL |
830 | .task_ctx_nr = perf_invalid_context, |
831 | .pmu_enable = smmu_pmu_enable, | |
832 | .pmu_disable = smmu_pmu_disable, | |
833 | .event_init = smmu_pmu_event_init, | |
834 | .add = smmu_pmu_event_add, | |
835 | .del = smmu_pmu_event_del, | |
836 | .start = smmu_pmu_event_start, | |
837 | .stop = smmu_pmu_event_stop, | |
838 | .read = smmu_pmu_event_read, | |
839 | .attr_groups = smmu_pmu_attr_grps, | |
840 | .capabilities = PERF_PMU_CAP_NO_EXCLUDE, | |
841 | }; | |
842 | ||
f011856c | 843 | smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res_0); |
7d839b4b NL |
844 | if (IS_ERR(smmu_pmu->reg_base)) |
845 | return PTR_ERR(smmu_pmu->reg_base); | |
846 | ||
847 | cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR); | |
848 | ||
849 | /* Determine if page 1 is present */ | |
850 | if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) { | |
c8b0de76 | 851 | smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1); |
7d839b4b NL |
852 | if (IS_ERR(smmu_pmu->reloc_base)) |
853 | return PTR_ERR(smmu_pmu->reloc_base); | |
854 | } else { | |
855 | smmu_pmu->reloc_base = smmu_pmu->reg_base; | |
856 | } | |
857 | ||
0ca2c031 | 858 | irq = platform_get_irq_optional(pdev, 0); |
7d839b4b NL |
859 | if (irq > 0) |
860 | smmu_pmu->irq = irq; | |
861 | ||
862 | ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0); | |
863 | ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1); | |
864 | bitmap_from_arr32(smmu_pmu->supported_events, (u32 *)ceid_64, | |
865 | SMMU_PMCG_ARCH_MAX_EVENTS); | |
866 | ||
867 | smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1; | |
868 | ||
869 | smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE); | |
870 | ||
871 | reg_size = FIELD_GET(SMMU_PMCG_CFGR_SIZE, cfgr); | |
872 | smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0); | |
873 | ||
874 | smmu_pmu_reset(smmu_pmu); | |
875 | ||
876 | err = smmu_pmu_setup_irq(smmu_pmu); | |
877 | if (err) { | |
878 | dev_err(dev, "Setup irq failed, PMU @%pa\n", &res_0->start); | |
879 | return err; | |
880 | } | |
881 | ||
df457ca9 | 882 | smmu_pmu_get_iidr(smmu_pmu); |
2c255223 | 883 | |
7d839b4b NL |
884 | name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "smmuv3_pmcg_%llx", |
885 | (res_0->start) >> SMMU_PMCG_PA_SHIFT); | |
886 | if (!name) { | |
887 | dev_err(dev, "Create name failed, PMU @%pa\n", &res_0->start); | |
888 | return -EINVAL; | |
889 | } | |
890 | ||
3f7be435 JPB |
891 | if (!dev->of_node) |
892 | smmu_pmu_get_acpi_options(smmu_pmu); | |
24062fe8 | 893 | |
7d839b4b NL |
894 | /* Pick one CPU to be the preferred one to use */ |
895 | smmu_pmu->on_cpu = raw_smp_processor_id(); | |
26210545 | 896 | WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu))); |
7d839b4b NL |
897 | |
898 | err = cpuhp_state_add_instance_nocalls(cpuhp_state_num, | |
899 | &smmu_pmu->node); | |
900 | if (err) { | |
901 | dev_err(dev, "Error %d registering hotplug, PMU @%pa\n", | |
902 | err, &res_0->start); | |
26210545 | 903 | return err; |
7d839b4b NL |
904 | } |
905 | ||
906 | err = perf_pmu_register(&smmu_pmu->pmu, name, -1); | |
907 | if (err) { | |
908 | dev_err(dev, "Error %d registering PMU @%pa\n", | |
909 | err, &res_0->start); | |
910 | goto out_unregister; | |
911 | } | |
912 | ||
913 | dev_info(dev, "Registered PMU @ %pa using %d counters with %s filter settings\n", | |
914 | &res_0->start, smmu_pmu->num_counters, | |
915 | smmu_pmu->global_filter ? "Global(Counter0)" : | |
916 | "Individual"); | |
917 | ||
918 | return 0; | |
919 | ||
920 | out_unregister: | |
921 | cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node); | |
7d839b4b NL |
922 | return err; |
923 | } | |
924 | ||
925 | static int smmu_pmu_remove(struct platform_device *pdev) | |
926 | { | |
927 | struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev); | |
928 | ||
929 | perf_pmu_unregister(&smmu_pmu->pmu); | |
930 | cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node); | |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
935 | static void smmu_pmu_shutdown(struct platform_device *pdev) | |
936 | { | |
937 | struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev); | |
938 | ||
939 | smmu_pmu_disable(&smmu_pmu->pmu); | |
940 | } | |
941 | ||
3f7be435 JPB |
942 | static const struct of_device_id smmu_pmu_of_match[] = { |
943 | { .compatible = "arm,smmu-v3-pmcg" }, | |
944 | {} | |
945 | }; | |
946 | MODULE_DEVICE_TABLE(of, smmu_pmu_of_match); | |
947 | ||
7d839b4b NL |
948 | static struct platform_driver smmu_pmu_driver = { |
949 | .driver = { | |
950 | .name = "arm-smmu-v3-pmcg", | |
3f7be435 | 951 | .of_match_table = of_match_ptr(smmu_pmu_of_match), |
f32ed8eb | 952 | .suppress_bind_attrs = true, |
7d839b4b NL |
953 | }, |
954 | .probe = smmu_pmu_probe, | |
955 | .remove = smmu_pmu_remove, | |
956 | .shutdown = smmu_pmu_shutdown, | |
957 | }; | |
958 | ||
959 | static int __init arm_smmu_pmu_init(void) | |
960 | { | |
961 | cpuhp_state_num = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, | |
962 | "perf/arm/pmcg:online", | |
963 | NULL, | |
964 | smmu_pmu_offline_cpu); | |
965 | if (cpuhp_state_num < 0) | |
966 | return cpuhp_state_num; | |
967 | ||
968 | return platform_driver_register(&smmu_pmu_driver); | |
969 | } | |
970 | module_init(arm_smmu_pmu_init); | |
971 | ||
972 | static void __exit arm_smmu_pmu_exit(void) | |
973 | { | |
974 | platform_driver_unregister(&smmu_pmu_driver); | |
975 | cpuhp_remove_multi_state(cpuhp_state_num); | |
976 | } | |
977 | ||
978 | module_exit(arm_smmu_pmu_exit); | |
979 | ||
980 | MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension"); | |
981 | MODULE_AUTHOR("Neil Leeder <nleeder@codeaurora.org>"); | |
982 | MODULE_AUTHOR("Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>"); | |
983 | MODULE_LICENSE("GPL v2"); |