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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
45736a72 MR |
2 | /* |
3 | * ACPI probing code for ARM performance counters. | |
4 | * | |
5 | * Copyright (C) 2017 ARM Ltd. | |
45736a72 MR |
6 | */ |
7 | ||
8 | #include <linux/acpi.h> | |
9 | #include <linux/cpumask.h> | |
10 | #include <linux/init.h> | |
43fc9a2f MR |
11 | #include <linux/irq.h> |
12 | #include <linux/irqdesc.h> | |
45736a72 MR |
13 | #include <linux/percpu.h> |
14 | #include <linux/perf/arm_pmu.h> | |
15 | ||
fe40ffdb | 16 | #include <asm/cpu.h> |
45736a72 MR |
17 | #include <asm/cputype.h> |
18 | ||
19 | static DEFINE_PER_CPU(struct arm_pmu *, probed_pmus); | |
20 | static DEFINE_PER_CPU(int, pmu_irqs); | |
21 | ||
22 | static int arm_pmu_acpi_register_irq(int cpu) | |
23 | { | |
24 | struct acpi_madt_generic_interrupt *gicc; | |
25 | int gsi, trigger; | |
26 | ||
27 | gicc = acpi_cpu_get_madt_gicc(cpu); | |
45736a72 MR |
28 | |
29 | gsi = gicc->performance_interrupt; | |
477c50e8 WH |
30 | |
31 | /* | |
32 | * Per the ACPI spec, the MADT cannot describe a PMU that doesn't | |
33 | * have an interrupt. QEMU advertises this by using a GSI of zero, | |
34 | * which is not known to be valid on any hardware despite being | |
35 | * valid per the spec. Take the pragmatic approach and reject a | |
36 | * GSI of zero for now. | |
37 | */ | |
38 | if (!gsi) | |
39 | return 0; | |
40 | ||
45736a72 MR |
41 | if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE) |
42 | trigger = ACPI_EDGE_SENSITIVE; | |
43 | else | |
44 | trigger = ACPI_LEVEL_SENSITIVE; | |
45 | ||
46 | /* | |
47 | * Helpfully, the MADT GICC doesn't have a polarity flag for the | |
48 | * "performance interrupt". Luckily, on compliant GICs the polarity is | |
49 | * a fixed value in HW (for both SPIs and PPIs) that we cannot change | |
50 | * from SW. | |
51 | * | |
52 | * Here we pass in ACPI_ACTIVE_HIGH to keep the core code happy. This | |
53 | * may not match the real polarity, but that should not matter. | |
54 | * | |
55 | * Other interrupt controllers are not supported with ACPI. | |
56 | */ | |
57 | return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH); | |
58 | } | |
59 | ||
60 | static void arm_pmu_acpi_unregister_irq(int cpu) | |
61 | { | |
62 | struct acpi_madt_generic_interrupt *gicc; | |
63 | int gsi; | |
64 | ||
65 | gicc = acpi_cpu_get_madt_gicc(cpu); | |
45736a72 MR |
66 | |
67 | gsi = gicc->performance_interrupt; | |
3ba52ad5 | 68 | if (gsi) |
69 | acpi_unregister_gsi(gsi); | |
45736a72 MR |
70 | } |
71 | ||
81e5ee47 AK |
72 | static int __maybe_unused |
73 | arm_acpi_register_pmu_device(struct platform_device *pdev, u8 len, | |
74 | u16 (*parse_gsi)(struct acpi_madt_generic_interrupt *)) | |
75 | { | |
76 | int cpu, this_hetid, hetid, irq, ret; | |
77 | u16 this_gsi = 0, gsi = 0; | |
78 | ||
79 | /* | |
80 | * Ensure that platform device must have IORESOURCE_IRQ | |
81 | * resource to hold gsi interrupt. | |
82 | */ | |
83 | if (pdev->num_resources != 1) | |
84 | return -ENXIO; | |
85 | ||
86 | if (pdev->resource[0].flags != IORESOURCE_IRQ) | |
87 | return -ENXIO; | |
88 | ||
89 | /* | |
90 | * Sanity check all the GICC tables for the same interrupt | |
91 | * number. For now, only support homogeneous ACPI machines. | |
92 | */ | |
93 | for_each_possible_cpu(cpu) { | |
94 | struct acpi_madt_generic_interrupt *gicc; | |
95 | ||
96 | gicc = acpi_cpu_get_madt_gicc(cpu); | |
97 | if (gicc->header.length < len) | |
98 | return gsi ? -ENXIO : 0; | |
99 | ||
100 | this_gsi = parse_gsi(gicc); | |
101 | this_hetid = find_acpi_cpu_topology_hetero_id(cpu); | |
102 | if (!gsi) { | |
103 | hetid = this_hetid; | |
104 | gsi = this_gsi; | |
105 | } else if (hetid != this_hetid || gsi != this_gsi) { | |
106 | pr_warn("ACPI: %s: must be homogeneous\n", pdev->name); | |
107 | return -ENXIO; | |
108 | } | |
109 | } | |
110 | ||
111 | if (!this_gsi) | |
112 | return 0; | |
113 | ||
114 | irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH); | |
115 | if (irq < 0) { | |
116 | pr_warn("ACPI: %s Unable to register interrupt: %d\n", pdev->name, gsi); | |
117 | return -ENXIO; | |
118 | } | |
119 | ||
120 | pdev->resource[0].start = irq; | |
121 | ret = platform_device_register(pdev); | |
122 | if (ret) | |
123 | acpi_unregister_gsi(gsi); | |
124 | ||
125 | return ret; | |
126 | } | |
127 | ||
d24a0c70 JL |
128 | #if IS_ENABLED(CONFIG_ARM_SPE_PMU) |
129 | static struct resource spe_resources[] = { | |
130 | { | |
131 | /* irq */ | |
132 | .flags = IORESOURCE_IRQ, | |
133 | } | |
134 | }; | |
135 | ||
136 | static struct platform_device spe_dev = { | |
137 | .name = ARMV8_SPE_PDEV_NAME, | |
138 | .id = -1, | |
139 | .resource = spe_resources, | |
140 | .num_resources = ARRAY_SIZE(spe_resources) | |
141 | }; | |
142 | ||
81e5ee47 AK |
143 | static u16 arm_spe_parse_gsi(struct acpi_madt_generic_interrupt *gicc) |
144 | { | |
145 | return gicc->spe_interrupt; | |
146 | } | |
147 | ||
d24a0c70 JL |
148 | /* |
149 | * For lack of a better place, hook the normal PMU MADT walk | |
150 | * and create a SPE device if we detect a recent MADT with | |
151 | * a homogeneous PPI mapping. | |
152 | */ | |
153 | static void arm_spe_acpi_register_device(void) | |
154 | { | |
81e5ee47 AK |
155 | int ret = arm_acpi_register_pmu_device(&spe_dev, ACPI_MADT_GICC_SPE, |
156 | arm_spe_parse_gsi); | |
157 | if (ret) | |
d24a0c70 | 158 | pr_warn("ACPI: SPE: Unable to register device\n"); |
d24a0c70 JL |
159 | } |
160 | #else | |
161 | static inline void arm_spe_acpi_register_device(void) | |
162 | { | |
163 | } | |
164 | #endif /* CONFIG_ARM_SPE_PMU */ | |
165 | ||
1aa3d027 AK |
166 | #if IS_ENABLED(CONFIG_CORESIGHT_TRBE) |
167 | static struct resource trbe_resources[] = { | |
168 | { | |
169 | /* irq */ | |
170 | .flags = IORESOURCE_IRQ, | |
171 | } | |
172 | }; | |
173 | ||
174 | static struct platform_device trbe_dev = { | |
175 | .name = ARMV8_TRBE_PDEV_NAME, | |
176 | .id = -1, | |
177 | .resource = trbe_resources, | |
178 | .num_resources = ARRAY_SIZE(trbe_resources) | |
179 | }; | |
180 | ||
181 | static u16 arm_trbe_parse_gsi(struct acpi_madt_generic_interrupt *gicc) | |
182 | { | |
183 | return gicc->trbe_interrupt; | |
184 | } | |
185 | ||
186 | static void arm_trbe_acpi_register_device(void) | |
187 | { | |
188 | int ret = arm_acpi_register_pmu_device(&trbe_dev, ACPI_MADT_GICC_TRBE, | |
189 | arm_trbe_parse_gsi); | |
190 | if (ret) | |
191 | pr_warn("ACPI: TRBE: Unable to register device\n"); | |
192 | } | |
193 | #else | |
194 | static inline void arm_trbe_acpi_register_device(void) | |
195 | { | |
196 | ||
197 | } | |
198 | #endif /* CONFIG_CORESIGHT_TRBE */ | |
199 | ||
45736a72 MR |
200 | static int arm_pmu_acpi_parse_irqs(void) |
201 | { | |
202 | int irq, cpu, irq_cpu, err; | |
203 | ||
204 | for_each_possible_cpu(cpu) { | |
205 | irq = arm_pmu_acpi_register_irq(cpu); | |
206 | if (irq < 0) { | |
207 | err = irq; | |
208 | pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n", | |
209 | cpu, err); | |
210 | goto out_err; | |
211 | } else if (irq == 0) { | |
212 | pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu); | |
213 | } | |
214 | ||
167e6143 MR |
215 | /* |
216 | * Log and request the IRQ so the core arm_pmu code can manage | |
217 | * it. We'll have to sanity-check IRQs later when we associate | |
218 | * them with their PMUs. | |
219 | */ | |
45736a72 | 220 | per_cpu(pmu_irqs, cpu) = irq; |
4b5b7129 RY |
221 | err = armpmu_request_irq(irq, cpu); |
222 | if (err) | |
223 | goto out_err; | |
45736a72 MR |
224 | } |
225 | ||
226 | return 0; | |
227 | ||
228 | out_err: | |
229 | for_each_possible_cpu(cpu) { | |
230 | irq = per_cpu(pmu_irqs, cpu); | |
231 | if (!irq) | |
232 | continue; | |
233 | ||
234 | arm_pmu_acpi_unregister_irq(cpu); | |
235 | ||
236 | /* | |
237 | * Blat all copies of the IRQ so that we only unregister the | |
238 | * corresponding GSI once (e.g. when we have PPIs). | |
239 | */ | |
240 | for_each_possible_cpu(irq_cpu) { | |
241 | if (per_cpu(pmu_irqs, irq_cpu) == irq) | |
242 | per_cpu(pmu_irqs, irq_cpu) = 0; | |
243 | } | |
244 | } | |
245 | ||
246 | return err; | |
247 | } | |
248 | ||
6349a247 | 249 | static struct arm_pmu *arm_pmu_acpi_find_pmu(void) |
45736a72 MR |
250 | { |
251 | unsigned long cpuid = read_cpuid_id(); | |
252 | struct arm_pmu *pmu; | |
253 | int cpu; | |
254 | ||
255 | for_each_possible_cpu(cpu) { | |
256 | pmu = per_cpu(probed_pmus, cpu); | |
257 | if (!pmu || pmu->acpi_cpuid != cpuid) | |
258 | continue; | |
259 | ||
260 | return pmu; | |
261 | } | |
262 | ||
6349a247 MR |
263 | return NULL; |
264 | } | |
265 | ||
43fc9a2f MR |
266 | /* |
267 | * Check whether the new IRQ is compatible with those already associated with | |
268 | * the PMU (e.g. we don't have mismatched PPIs). | |
269 | */ | |
270 | static bool pmu_irq_matches(struct arm_pmu *pmu, int irq) | |
271 | { | |
272 | struct pmu_hw_events __percpu *hw_events = pmu->hw_events; | |
273 | int cpu; | |
274 | ||
275 | if (!irq) | |
276 | return true; | |
277 | ||
278 | for_each_cpu(cpu, &pmu->supported_cpus) { | |
279 | int other_irq = per_cpu(hw_events->irq, cpu); | |
280 | if (!other_irq) | |
281 | continue; | |
282 | ||
283 | if (irq == other_irq) | |
284 | continue; | |
285 | if (!irq_is_percpu_devid(irq) && !irq_is_percpu_devid(other_irq)) | |
286 | continue; | |
287 | ||
288 | pr_warn("mismatched PPIs detected\n"); | |
289 | return false; | |
290 | } | |
291 | ||
292 | return true; | |
293 | } | |
294 | ||
ad51b504 MR |
295 | static void arm_pmu_acpi_associate_pmu_cpu(struct arm_pmu *pmu, |
296 | unsigned int cpu) | |
297 | { | |
298 | int irq = per_cpu(pmu_irqs, cpu); | |
299 | ||
300 | per_cpu(probed_pmus, cpu) = pmu; | |
301 | ||
302 | if (pmu_irq_matches(pmu, irq)) { | |
303 | struct pmu_hw_events __percpu *hw_events; | |
304 | hw_events = pmu->hw_events; | |
305 | per_cpu(hw_events->irq, cpu) = irq; | |
306 | } | |
307 | ||
308 | cpumask_set_cpu(cpu, &pmu->supported_cpus); | |
309 | } | |
310 | ||
45736a72 MR |
311 | /* |
312 | * This must run before the common arm_pmu hotplug logic, so that we can | |
313 | * associate a CPU and its interrupt before the common code tries to manage the | |
314 | * affinity and so on. | |
315 | * | |
316 | * Note that hotplug events are serialized, so we cannot race with another CPU | |
317 | * coming up. The perf core won't open events while a hotplug event is in | |
318 | * progress. | |
319 | */ | |
320 | static int arm_pmu_acpi_cpu_starting(unsigned int cpu) | |
321 | { | |
322 | struct arm_pmu *pmu; | |
45736a72 MR |
323 | |
324 | /* If we've already probed this CPU, we have nothing to do */ | |
325 | if (per_cpu(probed_pmus, cpu)) | |
326 | return 0; | |
327 | ||
fe40ffdb MR |
328 | pmu = arm_pmu_acpi_find_pmu(); |
329 | if (!pmu) { | |
330 | pr_warn_ratelimited("Unable to associate CPU%d with a PMU\n", | |
331 | cpu); | |
332 | return 0; | |
333 | } | |
45736a72 | 334 | |
ad51b504 | 335 | arm_pmu_acpi_associate_pmu_cpu(pmu, cpu); |
45736a72 MR |
336 | return 0; |
337 | } | |
338 | ||
fe40ffdb MR |
339 | static void arm_pmu_acpi_probe_matching_cpus(struct arm_pmu *pmu, |
340 | unsigned long cpuid) | |
341 | { | |
342 | int cpu; | |
343 | ||
344 | for_each_online_cpu(cpu) { | |
345 | unsigned long cpu_cpuid = per_cpu(cpu_data, cpu).reg_midr; | |
346 | ||
347 | if (cpu_cpuid == cpuid) | |
348 | arm_pmu_acpi_associate_pmu_cpu(pmu, cpu); | |
349 | } | |
350 | } | |
351 | ||
45736a72 MR |
352 | int arm_pmu_acpi_probe(armpmu_init_fn init_fn) |
353 | { | |
354 | int pmu_idx = 0; | |
fe40ffdb MR |
355 | unsigned int cpu; |
356 | int ret; | |
357 | ||
358 | ret = arm_pmu_acpi_parse_irqs(); | |
359 | if (ret) | |
360 | return ret; | |
361 | ||
362 | ret = cpuhp_setup_state_nocalls(CPUHP_AP_PERF_ARM_ACPI_STARTING, | |
363 | "perf/arm/pmu_acpi:starting", | |
364 | arm_pmu_acpi_cpu_starting, NULL); | |
365 | if (ret) | |
366 | return ret; | |
45736a72 | 367 | |
45736a72 MR |
368 | /* |
369 | * Initialise and register the set of PMUs which we know about right | |
370 | * now. Ideally we'd do this in arm_pmu_acpi_cpu_starting() so that we | |
371 | * could handle late hotplug, but this may lead to deadlock since we | |
372 | * might try to register a hotplug notifier instance from within a | |
373 | * hotplug notifier. | |
374 | * | |
375 | * There's also the problem of having access to the right init_fn, | |
376 | * without tying this too deeply into the "real" PMU driver. | |
377 | * | |
378 | * For the moment, as with the platform/DT case, we need at least one | |
379 | * of a PMU's CPUs to be online at probe time. | |
380 | */ | |
fe40ffdb | 381 | for_each_online_cpu(cpu) { |
45736a72 | 382 | struct arm_pmu *pmu = per_cpu(probed_pmus, cpu); |
fe40ffdb | 383 | unsigned long cpuid; |
45736a72 MR |
384 | char *base_name; |
385 | ||
fe40ffdb MR |
386 | /* If we've already probed this CPU, we have nothing to do */ |
387 | if (pmu) | |
45736a72 MR |
388 | continue; |
389 | ||
fe40ffdb MR |
390 | pmu = armpmu_alloc(); |
391 | if (!pmu) { | |
392 | pr_warn("Unable to allocate PMU for CPU%d\n", | |
393 | cpu); | |
a8731264 | 394 | return -ENOMEM; |
fe40ffdb MR |
395 | } |
396 | ||
397 | cpuid = per_cpu(cpu_data, cpu).reg_midr; | |
398 | pmu->acpi_cpuid = cpuid; | |
399 | ||
400 | arm_pmu_acpi_probe_matching_cpus(pmu, cpuid); | |
401 | ||
45736a72 MR |
402 | ret = init_fn(pmu); |
403 | if (ret == -ENODEV) { | |
404 | /* PMU not handled by this driver, or not present */ | |
405 | continue; | |
406 | } else if (ret) { | |
407 | pr_warn("Unable to initialise PMU for CPU%d\n", cpu); | |
408 | return ret; | |
409 | } | |
410 | ||
411 | base_name = pmu->name; | |
412 | pmu->name = kasprintf(GFP_KERNEL, "%s_%d", base_name, pmu_idx++); | |
413 | if (!pmu->name) { | |
414 | pr_warn("Unable to allocate PMU name for CPU%d\n", cpu); | |
415 | return -ENOMEM; | |
416 | } | |
417 | ||
418 | ret = armpmu_register(pmu); | |
419 | if (ret) { | |
420 | pr_warn("Failed to register PMU for CPU%d\n", cpu); | |
a88dc7ba | 421 | kfree(pmu->name); |
45736a72 MR |
422 | return ret; |
423 | } | |
424 | } | |
425 | ||
fe40ffdb | 426 | return ret; |
45736a72 MR |
427 | } |
428 | ||
429 | static int arm_pmu_acpi_init(void) | |
430 | { | |
45736a72 MR |
431 | if (acpi_disabled) |
432 | return 0; | |
433 | ||
d24a0c70 | 434 | arm_spe_acpi_register_device(); |
1aa3d027 | 435 | arm_trbe_acpi_register_device(); |
d24a0c70 | 436 | |
fe40ffdb | 437 | return 0; |
45736a72 MR |
438 | } |
439 | subsys_initcall(arm_pmu_acpi_init) |