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powerpc/mm: Drop the unnecessary region check
[linux-2.6-block.git] / drivers / perf / arm-ccn.c
CommitLineData
a33b0daa
PM		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2014 ARM Limited
12 */
13
14#include <linux/ctype.h>
15#include <linux/hrtimer.h>
16#include <linux/idr.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
ac316725 20#include <linux/mod_devicetable.h>
a33b0daa
PM		 21#include <linux/perf_event.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24
25#define CCN_NUM_XP_PORTS 2
26#define CCN_NUM_VCS 4
27#define CCN_NUM_REGIONS 256
28#define CCN_REGION_SIZE 0x10000
29
30#define CCN_ALL_OLY_ID 0xff00
31#define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0
32#define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f
33#define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8
34#define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f
35
36#define CCN_MN_ERRINT_STATUS 0x0008
37#define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11
38#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02
39#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20
40#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22
41#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04
42#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
43#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44
44#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08
45#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80
46#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88
47#define CCN_MN_OLY_COMP_LIST_63_0 0x01e0
48#define CCN_MN_ERR_SIG_VAL_63_0 0x0300
49#define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1)
50
51#define CCN_DT_ACTIVE_DSM 0x0000
52#define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8)
53#define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff
54#define CCN_DT_CTL 0x0028
55#define CCN_DT_CTL__DT_EN (1 << 0)
56#define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8)
57#define CCN_DT_PMCCNTR 0x0140
58#define CCN_DT_PMCCNTRSR 0x0190
59#define CCN_DT_PMOVSR 0x0198
60#define CCN_DT_PMOVSR_CLR 0x01a0
fa637bf0 61#define CCN_DT_PMOVSR_CLR__MASK 0x1f
a33b0daa
PM		 62#define CCN_DT_PMCR 0x01a8
63#define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6)
64#define CCN_DT_PMCR__PMU_EN (1 << 0)
65#define CCN_DT_PMSR 0x01b0
66#define CCN_DT_PMSR_REQ 0x01b8
67#define CCN_DT_PMSR_CLR 0x01c0
68
69#define CCN_HNF_PMU_EVENT_SEL 0x0600
70#define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
71#define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf
72
73#define CCN_XP_DT_CONFIG 0x0300
74#define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4)
75#define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf
76#define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0
77#define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1
78#define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n))
79#define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n))
80#define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
81#define CCN_XP_DT_INTERFACE_SEL 0x0308
82#define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8)
83#define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1
84#define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8)
85#define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1
86#define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8)
87#define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3
88#define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40)
89#define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40)
90#define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40)
91#define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40)
92#define CCN_XP_DT_CONTROL 0x0370
93#define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0)
94#define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4)
95#define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf
96#define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf
97#define CCN_XP_PMU_EVENT_SEL 0x0600
98#define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7)
99#define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f
100
101#define CCN_SBAS_PMU_EVENT_SEL 0x0600
102#define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
103#define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf
104
105#define CCN_RNI_PMU_EVENT_SEL 0x0600
106#define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
107#define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf
108
109#define CCN_TYPE_MN 0x01
110#define CCN_TYPE_DT 0x02
111#define CCN_TYPE_HNF 0x04
112#define CCN_TYPE_HNI 0x05
113#define CCN_TYPE_XP 0x08
114#define CCN_TYPE_SBSX 0x0c
115#define CCN_TYPE_SBAS 0x10
116#define CCN_TYPE_RNI_1P 0x14
117#define CCN_TYPE_RNI_2P 0x15
118#define CCN_TYPE_RNI_3P 0x16
119#define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
120#define CCN_TYPE_RND_2P 0x19
121#define CCN_TYPE_RND_3P 0x1a
122#define CCN_TYPE_CYCLES 0xff /* Pseudotype */
123
124#define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
125
126#define CCN_NUM_PMU_EVENTS 4
127#define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
128#define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
129#define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS
130
131#define CCN_NUM_PREDEFINED_MASKS 4
132#define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0)
133#define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1)
134#define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2)
135#define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3)
136
137struct arm_ccn_component {
138 void __iomem *base;
139 u32 type;
140
141 DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
142 union {
143 struct {
144 DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
145 } xp;
146 };
147};
148
149#define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
150 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
151
152struct arm_ccn_dt {
153 int id;
154 void __iomem *base;
155
156 spinlock_t config_lock;
157
158 DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
159 struct {
160 struct arm_ccn_component *source;
161 struct perf_event *event;
162 } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
163
164 struct {
165 u64 l, h;
166 } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
167
168 struct hrtimer hrtimer;
169
ffa41524 170 cpumask_t cpu;
8df03872 171 struct hlist_node node;
ffa41524 172
a33b0daa
PM		 173 struct pmu pmu;
174};
175
176struct arm_ccn {
177 struct device *dev;
178 void __iomem *base;
ffa41524
PM		 179 unsigned int irq;
180
a33b0daa
PM		 181 unsigned sbas_present:1;
182 unsigned sbsx_present:1;
183
184 int num_nodes;
185 struct arm_ccn_component *node;
186
187 int num_xps;
188 struct arm_ccn_component *xp;
189
190 struct arm_ccn_dt dt;
4e486cba 191 int mn_id;
a33b0daa
PM		 192};
193
a33b0daa
PM		 194static int arm_ccn_node_to_xp(int node)
195{
196 return node / CCN_NUM_XP_PORTS;
197}
198
199static int arm_ccn_node_to_xp_port(int node)
200{
201 return node % CCN_NUM_XP_PORTS;
202}
203
204
205/*
206 * Bit shifts and masks in these defines must be kept in sync with
207 * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
208 */
209#define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff)
210#define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff)
211#define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
212#define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
213#define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
90d11e26 214#define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3)
a33b0daa
PM		 215#define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
216#define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
217#define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
218
219static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
220{
a18f8e97 221 *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
a33b0daa
PM		 222 *config |= (node_xp << 0) | (type << 8) | (port << 24);
223}
224
225static ssize_t arm_ccn_pmu_format_show(struct device *dev,
226 struct device_attribute *attr, char *buf)
227{
228 struct dev_ext_attribute *ea = container_of(attr,
229 struct dev_ext_attribute, attr);
230
231 return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var);
232}
233
234#define CCN_FORMAT_ATTR(_name, _config) \
235 struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
236 { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
237 NULL), _config }
238
239static CCN_FORMAT_ATTR(node, "config:0-7");
240static CCN_FORMAT_ATTR(xp, "config:0-7");
241static CCN_FORMAT_ATTR(type, "config:8-15");
242static CCN_FORMAT_ATTR(event, "config:16-23");
243static CCN_FORMAT_ATTR(port, "config:24-25");
90d11e26 244static CCN_FORMAT_ATTR(bus, "config:24-25");
a33b0daa
PM		 245static CCN_FORMAT_ATTR(vc, "config:26-28");
246static CCN_FORMAT_ATTR(dir, "config:29-29");
247static CCN_FORMAT_ATTR(mask, "config:30-33");
248static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
249static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
250
251static struct attribute *arm_ccn_pmu_format_attrs[] = {
252 &arm_ccn_pmu_format_attr_node.attr.attr,
253 &arm_ccn_pmu_format_attr_xp.attr.attr,
254 &arm_ccn_pmu_format_attr_type.attr.attr,
255 &arm_ccn_pmu_format_attr_event.attr.attr,
256 &arm_ccn_pmu_format_attr_port.attr.attr,
90d11e26 257 &arm_ccn_pmu_format_attr_bus.attr.attr,
a33b0daa
PM		 258 &arm_ccn_pmu_format_attr_vc.attr.attr,
259 &arm_ccn_pmu_format_attr_dir.attr.attr,
260 &arm_ccn_pmu_format_attr_mask.attr.attr,
261 &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
262 &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
263 NULL
264};
265
8a84bf45 266static const struct attribute_group arm_ccn_pmu_format_attr_group = {
a33b0daa
PM		 267 .name = "format",
268 .attrs = arm_ccn_pmu_format_attrs,
269};
270
271
272struct arm_ccn_pmu_event {
273 struct device_attribute attr;
274 u32 type;
275 u32 event;
276 int num_ports;
277 int num_vcs;
278 const char *def;
279 int mask;
280};
281
282#define CCN_EVENT_ATTR(_name) \
283 __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
284
285/*
286 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
287 * their ports in XP they are connected to. For the sake of usability they are
288 * explicitly defined here (and translated into a relevant watchpoint in
289 * arm_ccn_pmu_event_init()) so the user can easily request them without deep
290 * knowledge of the flit format.
291 */
292
293#define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
294 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
295 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
296 .def = _def, .mask = _mask, }
297
298#define CCN_EVENT_HNI(_name, _def, _mask) { \
299 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
300 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
301 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
302
303#define CCN_EVENT_SBSX(_name, _def, _mask) { \
304 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
305 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
306 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
307
308#define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
309 .type = CCN_TYPE_HNF, .event = _event, }
310
311#define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
312 .type = CCN_TYPE_XP, .event = _event, \
313 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
314
315/*
316 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
317 * on configuration. One of them is picked to represent the whole group,
318 * as they all share the same event types.
319 */
320#define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
321 .type = CCN_TYPE_RNI_3P, .event = _event, }
322
323#define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
324 .type = CCN_TYPE_SBAS, .event = _event, }
325
326#define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
327 .type = CCN_TYPE_CYCLES }
328
329
330static ssize_t arm_ccn_pmu_event_show(struct device *dev,
331 struct device_attribute *attr, char *buf)
332{
4e486cba 333 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
a33b0daa
PM		 334 struct arm_ccn_pmu_event *event = container_of(attr,
335 struct arm_ccn_pmu_event, attr);
336 ssize_t res;
337
338 res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type);
339 if (event->event)
340 res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x",
341 event->event);
342 if (event->def)
343 res += snprintf(buf + res, PAGE_SIZE - res, ",%s",
344 event->def);
345 if (event->mask)
346 res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x",
347 event->mask);
8f06c51f
PM		 348
349 /* Arguments required by an event */
350 switch (event->type) {
351 case CCN_TYPE_CYCLES:
352 break;
353 case CCN_TYPE_XP:
354 res += snprintf(buf + res, PAGE_SIZE - res,
90d11e26 355 ",xp=?,vc=?");
8f06c51f
PM		 356 if (event->event == CCN_EVENT_WATCHPOINT)
357 res += snprintf(buf + res, PAGE_SIZE - res,
90d11e26
PM		 358 ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?");
359 else
360 res += snprintf(buf + res, PAGE_SIZE - res,
361 ",bus=?");
362
8f06c51f 363 break;
4e486cba
PM		 364 case CCN_TYPE_MN:
365 res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id);
366 break;
8f06c51f
PM		 367 default:
368 res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
369 break;
370 }
371
a33b0daa
PM		 372 res += snprintf(buf + res, PAGE_SIZE - res, "\n");
373
374 return res;
375}
376
377static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
378 struct attribute *attr, int index)
379{
380 struct device *dev = kobj_to_dev(kobj);
381 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
382 struct device_attribute *dev_attr = container_of(attr,
383 struct device_attribute, attr);
384 struct arm_ccn_pmu_event *event = container_of(dev_attr,
385 struct arm_ccn_pmu_event, attr);
386
387 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
388 return 0;
389 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
390 return 0;
391
392 return attr->mode;
393}
394
395static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
4e486cba
PM		 396 CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
397 CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
398 CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
a33b0daa
PM		 399 CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
400 CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
401 CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
402 CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
403 CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
404 CCN_IDX_MASK_ORDER),
405 CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
406 CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
407 CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
408 CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
409 CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
410 CCN_IDX_MASK_ORDER),
411 CCN_EVENT_HNF(cache_miss, 0x1),
412 CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
413 CCN_EVENT_HNF(cache_fill, 0x3),
414 CCN_EVENT_HNF(pocq_retry, 0x4),
415 CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
416 CCN_EVENT_HNF(sf_hit, 0x6),
417 CCN_EVENT_HNF(sf_evictions, 0x7),
418 CCN_EVENT_HNF(snoops_sent, 0x8),
419 CCN_EVENT_HNF(snoops_broadcast, 0x9),
420 CCN_EVENT_HNF(l3_eviction, 0xa),
421 CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
422 CCN_EVENT_HNF(mc_retries, 0xc),
423 CCN_EVENT_HNF(mc_reqs, 0xd),
424 CCN_EVENT_HNF(qos_hh_retry, 0xe),
425 CCN_EVENT_RNI(rdata_beats_p0, 0x1),
426 CCN_EVENT_RNI(rdata_beats_p1, 0x2),
427 CCN_EVENT_RNI(rdata_beats_p2, 0x3),
428 CCN_EVENT_RNI(rxdat_flits, 0x4),
429 CCN_EVENT_RNI(txdat_flits, 0x5),
430 CCN_EVENT_RNI(txreq_flits, 0x6),
431 CCN_EVENT_RNI(txreq_flits_retried, 0x7),
432 CCN_EVENT_RNI(rrt_full, 0x8),
433 CCN_EVENT_RNI(wrt_full, 0x9),
434 CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
435 CCN_EVENT_XP(upload_starvation, 0x1),
436 CCN_EVENT_XP(download_starvation, 0x2),
437 CCN_EVENT_XP(respin, 0x3),
438 CCN_EVENT_XP(valid_flit, 0x4),
439 CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
440 CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
441 CCN_EVENT_SBAS(rxdat_flits, 0x4),
442 CCN_EVENT_SBAS(txdat_flits, 0x5),
443 CCN_EVENT_SBAS(txreq_flits, 0x6),
444 CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
445 CCN_EVENT_SBAS(rrt_full, 0x8),
446 CCN_EVENT_SBAS(wrt_full, 0x9),
447 CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
448 CCN_EVENT_CYCLES(cycles),
449};
450
451/* Populated in arm_ccn_init() */
452static struct attribute
453 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
454
8a84bf45 455static const struct attribute_group arm_ccn_pmu_events_attr_group = {
a33b0daa
PM		 456 .name = "events",
457 .is_visible = arm_ccn_pmu_events_is_visible,
458 .attrs = arm_ccn_pmu_events_attrs,
459};
460
461
462static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
463{
464 unsigned long i;
465
466 if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
467 return NULL;
468 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
469
470 switch (name[1]) {
471 case 'l':
472 return &ccn->dt.cmp_mask[i].l;
473 case 'h':
474 return &ccn->dt.cmp_mask[i].h;
475 default:
476 return NULL;
477 }
478}
479
480static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
481 struct device_attribute *attr, char *buf)
482{
483 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
484 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
485
486 return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL;
487}
488
489static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
490 struct device_attribute *attr, const char *buf, size_t count)
491{
492 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
493 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
494 int err = -EINVAL;
495
496 if (mask)
497 err = kstrtoull(buf, 0, mask);
498
499 return err ? err : count;
500}
501
502#define CCN_CMP_MASK_ATTR(_name) \
503 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
504 __ATTR(_name, S_IRUGO | S_IWUSR, \
505 arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
506
507#define CCN_CMP_MASK_ATTR_RO(_name) \
508 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
509 __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
510
511static CCN_CMP_MASK_ATTR(0l);
512static CCN_CMP_MASK_ATTR(0h);
513static CCN_CMP_MASK_ATTR(1l);
514static CCN_CMP_MASK_ATTR(1h);
515static CCN_CMP_MASK_ATTR(2l);
516static CCN_CMP_MASK_ATTR(2h);
517static CCN_CMP_MASK_ATTR(3l);
518static CCN_CMP_MASK_ATTR(3h);
519static CCN_CMP_MASK_ATTR(4l);
520static CCN_CMP_MASK_ATTR(4h);
521static CCN_CMP_MASK_ATTR(5l);
522static CCN_CMP_MASK_ATTR(5h);
523static CCN_CMP_MASK_ATTR(6l);
524static CCN_CMP_MASK_ATTR(6h);
525static CCN_CMP_MASK_ATTR(7l);
526static CCN_CMP_MASK_ATTR(7h);
527static CCN_CMP_MASK_ATTR_RO(8l);
528static CCN_CMP_MASK_ATTR_RO(8h);
529static CCN_CMP_MASK_ATTR_RO(9l);
530static CCN_CMP_MASK_ATTR_RO(9h);
531static CCN_CMP_MASK_ATTR_RO(al);
532static CCN_CMP_MASK_ATTR_RO(ah);
533static CCN_CMP_MASK_ATTR_RO(bl);
534static CCN_CMP_MASK_ATTR_RO(bh);
535
536static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
537 &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
538 &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
539 &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
540 &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
541 &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
542 &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
543 &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
544 &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
545 &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
546 &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
547 &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
548 &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
549 NULL
550};
551
8a84bf45 552static const struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
a33b0daa
PM		 553 .name = "cmp_mask",
554 .attrs = arm_ccn_pmu_cmp_mask_attrs,
555};
556
ffa41524
PM		 557static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
558 struct device_attribute *attr, char *buf)
559{
560 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
561
562 return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu);
563}
564
565static struct device_attribute arm_ccn_pmu_cpumask_attr =
566 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
567
568static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
569 &arm_ccn_pmu_cpumask_attr.attr,
570 NULL,
571};
572
8a84bf45 573static const struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
ffa41524
PM		 574 .attrs = arm_ccn_pmu_cpumask_attrs,
575};
a33b0daa
PM		 576
577/*
578 * Default poll period is 10ms, which is way over the top anyway,
579 * as in the worst case scenario (an event every cycle), with 1GHz
580 * clocked bus, the smallest, 32 bit counter will overflow in
581 * more than 4s.
582 */
583static unsigned int arm_ccn_pmu_poll_period_us = 10000;
584module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
585 S_IRUGO | S_IWUSR);
586
587static ktime_t arm_ccn_pmu_timer_period(void)
588{
589 return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
590}
591
592
593static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
594 &arm_ccn_pmu_events_attr_group,
595 &arm_ccn_pmu_format_attr_group,
596 &arm_ccn_pmu_cmp_mask_attr_group,
ffa41524 597 &arm_ccn_pmu_cpumask_attr_group,
a33b0daa
PM		 598 NULL
599};
600
601
602static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
603{
604 int bit;
605
606 do {
607 bit = find_first_zero_bit(bitmap, size);
608 if (bit >= size)
609 return -EAGAIN;
610 } while (test_and_set_bit(bit, bitmap));
611
612 return bit;
613}
614
615/* All RN-I and RN-D nodes have identical PMUs */
616static int arm_ccn_pmu_type_eq(u32 a, u32 b)
617{
618 if (a == b)
619 return 1;
620
621 switch (a) {
622 case CCN_TYPE_RNI_1P:
623 case CCN_TYPE_RNI_2P:
624 case CCN_TYPE_RNI_3P:
625 case CCN_TYPE_RND_1P:
626 case CCN_TYPE_RND_2P:
627 case CCN_TYPE_RND_3P:
628 switch (b) {
629 case CCN_TYPE_RNI_1P:
630 case CCN_TYPE_RNI_2P:
631 case CCN_TYPE_RNI_3P:
632 case CCN_TYPE_RND_1P:
633 case CCN_TYPE_RND_2P:
634 case CCN_TYPE_RND_3P:
635 return 1;
636 }
637 break;
638 }
639
640 return 0;
641}
642
57006d3e
PM		 643static int arm_ccn_pmu_event_alloc(struct perf_event *event)
644{
645 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
646 struct hw_perf_event *hw = &event->hw;
647 u32 node_xp, type, event_id;
648 struct arm_ccn_component *source;
649 int bit;
650
651 node_xp = CCN_CONFIG_NODE(event->attr.config);
652 type = CCN_CONFIG_TYPE(event->attr.config);
653 event_id = CCN_CONFIG_EVENT(event->attr.config);
654
655 /* Allocate the cycle counter */
656 if (type == CCN_TYPE_CYCLES) {
657 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
658 ccn->dt.pmu_counters_mask))
659 return -EAGAIN;
660
661 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
662 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
663
664 return 0;
665 }
666
667 /* Allocate an event counter */
668 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
669 CCN_NUM_PMU_EVENT_COUNTERS);
670 if (hw->idx < 0) {
671 dev_dbg(ccn->dev, "No more counters available!\n");
672 return -EAGAIN;
673 }
674
675 if (type == CCN_TYPE_XP)
676 source = &ccn->xp[node_xp];
677 else
678 source = &ccn->node[node_xp];
679 ccn->dt.pmu_counters[hw->idx].source = source;
680
681 /* Allocate an event source or a watchpoint */
682 if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
683 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
684 CCN_NUM_XP_WATCHPOINTS);
685 else
686 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
687 CCN_NUM_PMU_EVENTS);
688 if (bit < 0) {
689 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
690 node_xp);
691 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
692 return -EAGAIN;
693 }
694 hw->config_base = bit;
695
696 ccn->dt.pmu_counters[hw->idx].event = event;
697
698 return 0;
699}
700
701static void arm_ccn_pmu_event_release(struct perf_event *event)
8fb22264
PM		 702{
703 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
704 struct hw_perf_event *hw = &event->hw;
705
706 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
707 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
708 } else {
709 struct arm_ccn_component *source =
710 ccn->dt.pmu_counters[hw->idx].source;
711
712 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
713 CCN_CONFIG_EVENT(event->attr.config) ==
714 CCN_EVENT_WATCHPOINT)
715 clear_bit(hw->config_base, source->xp.dt_cmp_mask);
716 else
717 clear_bit(hw->config_base, source->pmu_events_mask);
718 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
719 }
720
721 ccn->dt.pmu_counters[hw->idx].source = NULL;
722 ccn->dt.pmu_counters[hw->idx].event = NULL;
723}
724
a33b0daa
PM		 725static int arm_ccn_pmu_event_init(struct perf_event *event)
726{
727 struct arm_ccn *ccn;
728 struct hw_perf_event *hw = &event->hw;
729 u32 node_xp, type, event_id;
57006d3e 730 int valid;
a33b0daa 731 int i;
9ce1aa86 732 struct perf_event *sibling;
a33b0daa
PM		 733
734 if (event->attr.type != event->pmu->type)
735 return -ENOENT;
736
737 ccn = pmu_to_arm_ccn(event->pmu);
738
739 if (hw->sample_period) {
1898eb61 740 dev_dbg(ccn->dev, "Sampling not supported!\n");
a33b0daa
PM		 741 return -EOPNOTSUPP;
742 }
743
30656398 744 if (has_branch_stack(event)) {
1898eb61 745 dev_dbg(ccn->dev, "Can't exclude execution levels!\n");
3249bce4 746 return -EINVAL;
a33b0daa
PM		 747 }
748
749 if (event->cpu < 0) {
1898eb61 750 dev_dbg(ccn->dev, "Can't provide per-task data!\n");
a33b0daa
PM		 751 return -EOPNOTSUPP;
752 }
ffa41524
PM		 753 /*
754 * Many perf core operations (eg. events rotation) operate on a
755 * single CPU context. This is obvious for CPU PMUs, where one
756 * expects the same sets of events being observed on all CPUs,
757 * but can lead to issues for off-core PMUs, like CCN, where each
758 * event could be theoretically assigned to a different CPU. To
759 * mitigate this, we enforce CPU assignment to one, selected
760 * processor (the one described in the "cpumask" attribute).
761 */
762 event->cpu = cpumask_first(&ccn->dt.cpu);
a33b0daa
PM		 763
764 node_xp = CCN_CONFIG_NODE(event->attr.config);
765 type = CCN_CONFIG_TYPE(event->attr.config);
766 event_id = CCN_CONFIG_EVENT(event->attr.config);
767
768 /* Validate node/xp vs topology */
769 switch (type) {
4e486cba
PM		 770 case CCN_TYPE_MN:
771 if (node_xp != ccn->mn_id) {
1898eb61 772 dev_dbg(ccn->dev, "Invalid MN ID %d!\n", node_xp);
4e486cba
PM		 773 return -EINVAL;
774 }
775 break;
a33b0daa
PM		 776 case CCN_TYPE_XP:
777 if (node_xp >= ccn->num_xps) {
1898eb61 778 dev_dbg(ccn->dev, "Invalid XP ID %d!\n", node_xp);
a33b0daa
PM		 779 return -EINVAL;
780 }
781 break;
782 case CCN_TYPE_CYCLES:
783 break;
784 default:
785 if (node_xp >= ccn->num_nodes) {
1898eb61 786 dev_dbg(ccn->dev, "Invalid node ID %d!\n", node_xp);
a33b0daa
PM		 787 return -EINVAL;
788 }
789 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
1898eb61 790 dev_dbg(ccn->dev, "Invalid type 0x%x for node %d!\n",
a33b0daa
PM		 791 type, node_xp);
792 return -EINVAL;
793 }
794 break;
795 }
796
797 /* Validate event ID vs available for the type */
798 for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
799 i++) {
800 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
801 u32 port = CCN_CONFIG_PORT(event->attr.config);
802 u32 vc = CCN_CONFIG_VC(event->attr.config);
803
804 if (!arm_ccn_pmu_type_eq(type, e->type))
805 continue;
806 if (event_id != e->event)
807 continue;
808 if (e->num_ports && port >= e->num_ports) {
1898eb61 809 dev_dbg(ccn->dev, "Invalid port %d for node/XP %d!\n",
a33b0daa
PM		 810 port, node_xp);
811 return -EINVAL;
812 }
813 if (e->num_vcs && vc >= e->num_vcs) {
1898eb61 814 dev_dbg(ccn->dev, "Invalid vc %d for node/XP %d!\n",
bf87bb12 815 vc, node_xp);
a33b0daa
PM		 816 return -EINVAL;
817 }
818 valid = 1;
819 }
820 if (!valid) {
1898eb61 821 dev_dbg(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
a33b0daa
PM		 822 event_id, node_xp);
823 return -EINVAL;
824 }
825
826 /* Watchpoint-based event for a node is actually set on XP */
827 if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
828 u32 port;
829
830 type = CCN_TYPE_XP;
831 port = arm_ccn_node_to_xp_port(node_xp);
832 node_xp = arm_ccn_node_to_xp(node_xp);
833
834 arm_ccn_pmu_config_set(&event->attr.config,
835 node_xp, type, port);
836 }
837
9ce1aa86
PM		 838 /*
839 * We must NOT create groups containing mixed PMUs, although software
840 * events are acceptable (for example to create a CCN group
841 * periodically read when a hrtimer aka cpu-clock leader triggers).
842 */
843 if (event->group_leader->pmu != event->pmu &&
844 !is_software_event(event->group_leader))
845 return -EINVAL;
846
edb39592 847 for_each_sibling_event(sibling, event->group_leader) {
9ce1aa86
PM		 848 if (sibling->pmu != event->pmu &&
849 !is_software_event(sibling))
850 return -EINVAL;
edb39592 851 }
9ce1aa86 852
a33b0daa
PM		 853 return 0;
854}
855
a33b0daa
PM		 856static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
857{
858 u64 res;
859
860 if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
861#ifdef readq
862 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
863#else
864 /* 40 bit counter, can do snapshot and read in two parts */
865 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
866 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
867 ;
868 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
869 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
870 res <<= 32;
871 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
872#endif
873 } else {
874 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
875 }
876
877 return res;
878}
879
880static void arm_ccn_pmu_event_update(struct perf_event *event)
881{
882 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
883 struct hw_perf_event *hw = &event->hw;
884 u64 prev_count, new_count, mask;
885
886 do {
887 prev_count = local64_read(&hw->prev_count);
888 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
889 } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
890
891 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
892
893 local64_add((new_count - prev_count) & mask, &event->count);
894}
895
896static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
897{
898 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
899 struct hw_perf_event *hw = &event->hw;
900 struct arm_ccn_component *xp;
901 u32 val, dt_cfg;
902
b7c1beb2
PM		 903 /* Nothing to do for cycle counter */
904 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
905 return;
906
a33b0daa
PM		 907 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
908 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
909 else
910 xp = &ccn->xp[arm_ccn_node_to_xp(
911 CCN_CONFIG_NODE(event->attr.config))];
912
913 if (enable)
914 dt_cfg = hw->event_base;
915 else
916 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
917
918 spin_lock(&ccn->dt.config_lock);
919
920 val = readl(xp->base + CCN_XP_DT_CONFIG);
921 val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
922 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
923 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
924 writel(val, xp->base + CCN_XP_DT_CONFIG);
925
926 spin_unlock(&ccn->dt.config_lock);
927}
928
929static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
930{
931 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
932 struct hw_perf_event *hw = &event->hw;
933
934 local64_set(&event->hw.prev_count,
935 arm_ccn_pmu_read_counter(ccn, hw->idx));
936 hw->state = 0;
937
a33b0daa
PM		 938 /* Set the DT bus input, engaging the counter */
939 arm_ccn_pmu_xp_dt_config(event, 1);
940}
941
942static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
943{
a33b0daa 944 struct hw_perf_event *hw = &event->hw;
a33b0daa
PM		 945
946 /* Disable counting, setting the DT bus to pass-through mode */
947 arm_ccn_pmu_xp_dt_config(event, 0);
948
a33b0daa
PM		 949 if (flags & PERF_EF_UPDATE)
950 arm_ccn_pmu_event_update(event);
951
952 hw->state |= PERF_HES_STOPPED;
953}
954
955static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
956{
957 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
958 struct hw_perf_event *hw = &event->hw;
959 struct arm_ccn_component *source =
960 ccn->dt.pmu_counters[hw->idx].source;
961 unsigned long wp = hw->config_base;
962 u32 val;
963 u64 cmp_l = event->attr.config1;
964 u64 cmp_h = event->attr.config2;
965 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
966 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
967
968 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
969
970 /* Direction (RX/TX), device (port) & virtual channel */
971 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
972 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
973 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
974 val |= CCN_CONFIG_DIR(event->attr.config) <<
975 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
976 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
977 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
978 val |= CCN_CONFIG_PORT(event->attr.config) <<
979 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
980 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
981 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
982 val |= CCN_CONFIG_VC(event->attr.config) <<
983 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
984 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
985
986 /* Comparison values */
987 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
b928466b 988 writel((cmp_l >> 32) & 0x7fffffff,
a33b0daa
PM		 989 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
990 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
991 writel((cmp_h >> 32) & 0x0fffffff,
992 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
993
994 /* Mask */
995 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
b928466b 996 writel((mask_l >> 32) & 0x7fffffff,
a33b0daa
PM		 997 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
998 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
999 writel((mask_h >> 32) & 0x0fffffff,
1000 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
1001}
1002
1003static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
1004{
1005 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1006 struct hw_perf_event *hw = &event->hw;
1007 struct arm_ccn_component *source =
1008 ccn->dt.pmu_counters[hw->idx].source;
1009 u32 val, id;
1010
1011 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1012
1013 id = (CCN_CONFIG_VC(event->attr.config) << 4) |
90d11e26 1014 (CCN_CONFIG_BUS(event->attr.config) << 3) |
a33b0daa
PM		 1015 (CCN_CONFIG_EVENT(event->attr.config) << 0);
1016
1017 val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
1018 val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
1019 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1020 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1021 writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1022}
1023
1024static void arm_ccn_pmu_node_event_config(struct perf_event *event)
1025{
1026 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1027 struct hw_perf_event *hw = &event->hw;
1028 struct arm_ccn_component *source =
1029 ccn->dt.pmu_counters[hw->idx].source;
1030 u32 type = CCN_CONFIG_TYPE(event->attr.config);
1031 u32 val, port;
1032
1033 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
1034 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
1035 hw->config_base);
1036
1037 /* These *_event_sel regs should be identical, but let's make sure... */
1038 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
1039 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
1040 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
1041 CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
1042 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
1043 CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
1044 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
1045 CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
1046 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
1047 CCN_RNI_PMU_EVENT_SEL__ID__MASK);
1048 if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
1049 !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
1050 return;
1051
1052 /* Set the event id for the pre-allocated counter */
1053 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1054 val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1055 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1056 val |= CCN_CONFIG_EVENT(event->attr.config) <<
1057 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1058 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1059}
1060
1061static void arm_ccn_pmu_event_config(struct perf_event *event)
1062{
1063 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1064 struct hw_perf_event *hw = &event->hw;
1065 u32 xp, offset, val;
1066
1067 /* Cycle counter requires no setup */
1068 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1069 return;
1070
1071 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1072 xp = CCN_CONFIG_XP(event->attr.config);
1073 else
1074 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1075
1076 spin_lock(&ccn->dt.config_lock);
1077
1078 /* Set the DT bus "distance" register */
1079 offset = (hw->idx / 4) * 4;
1080 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1081 val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1082 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1083 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1084 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1085
1086 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1087 if (CCN_CONFIG_EVENT(event->attr.config) ==
1088 CCN_EVENT_WATCHPOINT)
1089 arm_ccn_pmu_xp_watchpoint_config(event);
1090 else
1091 arm_ccn_pmu_xp_event_config(event);
1092 } else {
1093 arm_ccn_pmu_node_event_config(event);
1094 }
1095
1096 spin_unlock(&ccn->dt.config_lock);
1097}
1098
5b1e01f3
MR		 1099static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn)
1100{
1101 return bitmap_weight(ccn->dt.pmu_counters_mask,
1102 CCN_NUM_PMU_EVENT_COUNTERS + 1);
1103}
1104
a33b0daa
PM		 1105static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1106{
57006d3e 1107 int err;
a33b0daa 1108 struct hw_perf_event *hw = &event->hw;
5b1e01f3 1109 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
a33b0daa 1110
57006d3e
PM		 1111 err = arm_ccn_pmu_event_alloc(event);
1112 if (err)
1113 return err;
1114
5b1e01f3
MR		 1115 /*
1116 * Pin the timer, so that the overflows are handled by the chosen
1117 * event->cpu (this is the same one as presented in "cpumask"
1118 * attribute).
1119 */
1120 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1)
1121 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
1122 HRTIMER_MODE_REL_PINNED);
1123
a33b0daa
PM		 1124 arm_ccn_pmu_event_config(event);
1125
1126 hw->state = PERF_HES_STOPPED;
1127
1128 if (flags & PERF_EF_START)
1129 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1130
1131 return 0;
1132}
1133
1134static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1135{
5b1e01f3
MR		 1136 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1137
a33b0daa 1138 arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
57006d3e
PM		 1139
1140 arm_ccn_pmu_event_release(event);
5b1e01f3
MR		 1141
1142 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0)
1143 hrtimer_cancel(&ccn->dt.hrtimer);
a33b0daa
PM		 1144}
1145
1146static void arm_ccn_pmu_event_read(struct perf_event *event)
1147{
1148 arm_ccn_pmu_event_update(event);
1149}
1150
d662ed2e
MR		 1151static void arm_ccn_pmu_enable(struct pmu *pmu)
1152{
1153 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1154
1155 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1156 val |= CCN_DT_PMCR__PMU_EN;
1157 writel(val, ccn->dt.base + CCN_DT_PMCR);
1158}
1159
1160static void arm_ccn_pmu_disable(struct pmu *pmu)
1161{
1162 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1163
1164 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1165 val &= ~CCN_DT_PMCR__PMU_EN;
1166 writel(val, ccn->dt.base + CCN_DT_PMCR);
1167}
1168
a33b0daa
PM		 1169static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1170{
1171 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1172 int idx;
1173
1174 if (!pmovsr)
1175 return IRQ_NONE;
1176
1177 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1178
1179 BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1180
1181 for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1182 struct perf_event *event = dt->pmu_counters[idx].event;
1183 int overflowed = pmovsr & BIT(idx);
1184
fa637bf0
PM		 1185 WARN_ON_ONCE(overflowed && !event &&
1186 idx != CCN_IDX_PMU_CYCLE_COUNTER);
a33b0daa
PM		 1187
1188 if (!event || !overflowed)
1189 continue;
1190
1191 arm_ccn_pmu_event_update(event);
1192 }
1193
1194 return IRQ_HANDLED;
1195}
1196
1197static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1198{
1199 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1200 hrtimer);
1201 unsigned long flags;
1202
1203 local_irq_save(flags);
1204 arm_ccn_pmu_overflow_handler(dt);
1205 local_irq_restore(flags);
1206
1207 hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1208 return HRTIMER_RESTART;
1209}
1210
1211
8df03872 1212static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
ffa41524 1213{
8df03872
SAS		 1214 struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node);
1215 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
ffa41524
PM		 1216 unsigned int target;
1217
8df03872
SAS		 1218 if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu))
1219 return 0;
1220 target = cpumask_any_but(cpu_online_mask, cpu);
1221 if (target >= nr_cpu_ids)
1222 return 0;
1223 perf_pmu_migrate_context(&dt->pmu, cpu, target);
1224 cpumask_set_cpu(target, &dt->cpu);
1225 if (ccn->irq)
1226 WARN_ON(irq_set_affinity_hint(ccn->irq, &dt->cpu) != 0);
fdc15a36 1227 return 0;
ffa41524
PM		 1228}
1229
a33b0daa
PM		 1230static DEFINE_IDA(arm_ccn_pmu_ida);
1231
1232static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1233{
1234 int i;
1235 char *name;
ffa41524 1236 int err;
a33b0daa
PM		 1237
1238 /* Initialize DT subsystem */
1239 ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1240 spin_lock_init(&ccn->dt.config_lock);
fa637bf0 1241 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
a33b0daa
PM		 1242 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1243 writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1244 ccn->dt.base + CCN_DT_PMCR);
1245 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1246 for (i = 0; i < ccn->num_xps; i++) {
1247 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1248 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1249 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1250 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1251 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1252 CCN_XP_DT_CONTROL__DT_ENABLE,
1253 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1254 }
1255 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1256 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1257 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1258 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1259 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1260 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1261 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1262 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1263
1264 /* Get a convenient /sys/event_source/devices/ name */
1265 ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);
1266 if (ccn->dt.id == 0) {
1267 name = "ccn";
1268 } else {
0f9afd36
CJ		 1269 name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d",
1270 ccn->dt.id);
24771179
CJ		 1271 if (!name) {
1272 err = -ENOMEM;
1273 goto error_choose_name;
1274 }
a33b0daa
PM		 1275 }
1276
1277 /* Perf driver registration */
1278 ccn->dt.pmu = (struct pmu) {
c7f5828b 1279 .module = THIS_MODULE,
a33b0daa
PM		 1280 .attr_groups = arm_ccn_pmu_attr_groups,
1281 .task_ctx_nr = perf_invalid_context,
1282 .event_init = arm_ccn_pmu_event_init,
1283 .add = arm_ccn_pmu_event_add,
1284 .del = arm_ccn_pmu_event_del,
1285 .start = arm_ccn_pmu_event_start,
1286 .stop = arm_ccn_pmu_event_stop,
1287 .read = arm_ccn_pmu_event_read,
d662ed2e
MR		 1288 .pmu_enable = arm_ccn_pmu_enable,
1289 .pmu_disable = arm_ccn_pmu_disable,
30656398 1290 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
a33b0daa
PM		 1291 };
1292
1293 /* No overflow interrupt? Have to use a timer instead. */
ffa41524 1294 if (!ccn->irq) {
a33b0daa
PM		 1295 dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1296 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
1297 HRTIMER_MODE_REL);
1298 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
1299 }
1300
ffa41524 1301 /* Pick one CPU which we will use to collect data from CCN... */
b18c2b94 1302 cpumask_set_cpu(get_cpu(), &ccn->dt.cpu);
ffa41524 1303
ffa41524
PM		 1304 /* Also make sure that the overflow interrupt is handled by this CPU */
1305 if (ccn->irq) {
5420f9fd 1306 err = irq_set_affinity_hint(ccn->irq, &ccn->dt.cpu);
ffa41524
PM		 1307 if (err) {
1308 dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
1309 goto error_set_affinity;
1310 }
1311 }
1312
1313 err = perf_pmu_register(&ccn->dt.pmu, name, -1);
1314 if (err)
1315 goto error_pmu_register;
1316
8df03872
SAS		 1317 cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1318 &ccn->dt.node);
b18c2b94 1319 put_cpu();
ffa41524
PM		 1320 return 0;
1321
1322error_pmu_register:
1323error_set_affinity:
b18c2b94 1324 put_cpu();
24771179 1325error_choose_name:
ffa41524
PM		 1326 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1327 for (i = 0; i < ccn->num_xps; i++)
1328 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1329 writel(0, ccn->dt.base + CCN_DT_PMCR);
1330 return err;
a33b0daa
PM		 1331}
1332
1333static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1334{
1335 int i;
1336
8df03872
SAS		 1337 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1338 &ccn->dt.node);
5420f9fd
SP		 1339 if (ccn->irq)
1340 irq_set_affinity_hint(ccn->irq, NULL);
a33b0daa
PM		 1341 for (i = 0; i < ccn->num_xps; i++)
1342 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1343 writel(0, ccn->dt.base + CCN_DT_PMCR);
1344 perf_pmu_unregister(&ccn->dt.pmu);
1345 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1346}
1347
a33b0daa
PM		 1348static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1349 int (*callback)(struct arm_ccn *ccn, int region,
1350 void __iomem *base, u32 type, u32 id))
1351{
1352 int region;
1353
1354 for (region = 0; region < CCN_NUM_REGIONS; region++) {
1355 u32 val, type, id;
1356 void __iomem *base;
1357 int err;
1358
1359 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1360 4 * (region / 32));
1361 if (!(val & (1 << (region % 32))))
1362 continue;
1363
1364 base = ccn->base + region * CCN_REGION_SIZE;
1365 val = readl(base + CCN_ALL_OLY_ID);
1366 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1367 CCN_ALL_OLY_ID__OLY_ID__MASK;
1368 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1369 CCN_ALL_OLY_ID__NODE_ID__MASK;
1370
1371 err = callback(ccn, region, base, type, id);
1372 if (err)
1373 return err;
1374 }
1375
1376 return 0;
1377}
1378
1379static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1380 void __iomem *base, u32 type, u32 id)
1381{
1382
1383 if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1384 ccn->num_xps = id + 1;
1385 else if (id >= ccn->num_nodes)
1386 ccn->num_nodes = id + 1;
1387
1388 return 0;
1389}
1390
1391static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1392 void __iomem *base, u32 type, u32 id)
1393{
1394 struct arm_ccn_component *component;
1395
1396 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1397
1398 switch (type) {
1399 case CCN_TYPE_MN:
4e486cba
PM		 1400 ccn->mn_id = id;
1401 return 0;
a33b0daa
PM		 1402 case CCN_TYPE_DT:
1403 return 0;
1404 case CCN_TYPE_XP:
1405 component = &ccn->xp[id];
1406 break;
1407 case CCN_TYPE_SBSX:
1408 ccn->sbsx_present = 1;
1409 component = &ccn->node[id];
1410 break;
1411 case CCN_TYPE_SBAS:
1412 ccn->sbas_present = 1;
1413 /* Fall-through */
1414 default:
1415 component = &ccn->node[id];
1416 break;
1417 }
1418
1419 component->base = base;
1420 component->type = type;
1421
1422 return 0;
1423}
1424
1425
1426static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1427 const u32 *err_sig_val)
1428{
1429 /* This should be really handled by firmware... */
1430 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1431 err_sig_val[5], err_sig_val[4], err_sig_val[3],
1432 err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1433 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1434 writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1435 ccn->base + CCN_MN_ERRINT_STATUS);
1436
1437 return IRQ_HANDLED;
1438}
1439
1440
1441static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1442{
1443 irqreturn_t res = IRQ_NONE;
1444 struct arm_ccn *ccn = dev_id;
1445 u32 err_sig_val[6];
1446 u32 err_or;
1447 int i;
1448
1449 /* PMU overflow is a special case */
1450 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1451 if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1452 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1453 res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1454 }
1455
1456 /* Have to read all err_sig_vals to clear them */
1457 for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1458 err_sig_val[i] = readl(ccn->base +
1459 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1460 err_or |= err_sig_val[i];
1461 }
1462 if (err_or)
1463 res |= arm_ccn_error_handler(ccn, err_sig_val);
1464
1465 if (res != IRQ_NONE)
1466 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1467 ccn->base + CCN_MN_ERRINT_STATUS);
1468
1469 return res;
1470}
1471
1472
1473static int arm_ccn_probe(struct platform_device *pdev)
1474{
1475 struct arm_ccn *ccn;
1476 struct resource *res;
ffa41524 1477 unsigned int irq;
a33b0daa
PM		 1478 int err;
1479
1480 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1481 if (!ccn)
1482 return -ENOMEM;
1483 ccn->dev = &pdev->dev;
1484 platform_set_drvdata(pdev, ccn);
1485
1486 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
809092dc
SH		 1487 ccn->base = devm_ioremap_resource(ccn->dev, res);
1488 if (IS_ERR(ccn->base))
1489 return PTR_ERR(ccn->base);
a33b0daa
PM		 1490
1491 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1492 if (!res)
1493 return -EINVAL;
ffa41524 1494 irq = res->start;
a33b0daa
PM		 1495
1496 /* Check if we can use the interrupt */
1497 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1498 ccn->base + CCN_MN_ERRINT_STATUS);
1499 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1500 CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1501 /* Can set 'disable' bits, so can acknowledge interrupts */
1502 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1503 ccn->base + CCN_MN_ERRINT_STATUS);
0811ef7e
MR		 1504 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler,
1505 IRQF_NOBALANCING | IRQF_NO_THREAD,
1506 dev_name(ccn->dev), ccn);
a33b0daa
PM		 1507 if (err)
1508 return err;
1509
ffa41524 1510 ccn->irq = irq;
a33b0daa
PM		 1511 }
1512
1513
1514 /* Build topology */
1515
1516 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1517 if (err)
1518 return err;
1519
0a240c5b
ME		 1520 ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node),
1521 GFP_KERNEL);
1522 ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node),
1523 GFP_KERNEL);
a33b0daa
PM		 1524 if (!ccn->node || !ccn->xp)
1525 return -ENOMEM;
1526
1527 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1528 if (err)
1529 return err;
1530
1531 return arm_ccn_pmu_init(ccn);
1532}
1533
1534static int arm_ccn_remove(struct platform_device *pdev)
1535{
1536 struct arm_ccn *ccn = platform_get_drvdata(pdev);
1537
1538 arm_ccn_pmu_cleanup(ccn);
1539
1540 return 0;
1541}
1542
1543static const struct of_device_id arm_ccn_match[] = {
2941be21 1544 { .compatible = "arm,ccn-502", },
a33b0daa
PM		 1545 { .compatible = "arm,ccn-504", },
1546 {},
1547};
60aba820 1548MODULE_DEVICE_TABLE(of, arm_ccn_match);
a33b0daa
PM		 1549
1550static struct platform_driver arm_ccn_driver = {
1551 .driver = {
1552 .name = "arm-ccn",
1553 .of_match_table = arm_ccn_match,
1554 },
1555 .probe = arm_ccn_probe,
1556 .remove = arm_ccn_remove,
1557};
1558
1559static int __init arm_ccn_init(void)
1560{
fdc15a36
SAS		 1561 int i, ret;
1562
8df03872 1563 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CCN_ONLINE,
73c1b41e 1564 "perf/arm/ccn:online", NULL,
8df03872 1565 arm_ccn_pmu_offline_cpu);
fdc15a36
SAS		 1566 if (ret)
1567 return ret;
a33b0daa
PM		 1568
1569 for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1570 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1571
26242b33
TG		 1572 ret = platform_driver_register(&arm_ccn_driver);
1573 if (ret)
1574 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1575 return ret;
a33b0daa
PM		 1576}
1577
1578static void __exit arm_ccn_exit(void)
1579{
1580 platform_driver_unregister(&arm_ccn_driver);
b69f63eb 1581 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
a33b0daa
PM		 1582}
1583
1584module_init(arm_ccn_init);
1585module_exit(arm_ccn_exit);
1586
1587MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
75dc3441 1588MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)