projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| fa8ad788 MR |
1 | # |
| 2 | # Performance Monitor Drivers | |
| 3 | # | |
| 4 | ||
| 5 | menu "Performance monitor support" | |
| bddb9b68 | 6 | depends on PERF_EVENTS |
| fa8ad788 | 7 | |
| 1888d3dd RM |
8 | config ARM_CCN |
| 9 | tristate "ARM CCN driver support" | |
| 10 | depends on ARM || ARM64 | |
| 11 | help | |
| 12 | PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) | |
| 13 | interconnect. | |
| 14 | ||
| fa8ad788 | 15 | config ARM_PMU |
| bddb9b68 | 16 | depends on ARM || ARM64 |
| fa8ad788 MR |
17 | bool "ARM PMU framework" |
| 18 | default y | |
| 19 | help | |
| 20 | Say y if you want to use CPU performance monitors on ARM-based | |
| 21 | systems. | |
| 22 | ||
| 45736a72 MR |
23 | config ARM_PMU_ACPI |
| 24 | depends on ARM_PMU && ACPI | |
| 25 | def_bool y | |
| 26 | ||
| 7520fa99 SP |
27 | config ARM_DSU_PMU |
| 28 | tristate "ARM DynamIQ Shared Unit (DSU) PMU" | |
| 29 | depends on ARM64 | |
| 30 | help | |
| 31 | Provides support for performance monitor unit in ARM DynamIQ Shared | |
| 32 | Unit (DSU). The DSU integrates one or more cores with an L3 memory | |
| 33 | system, control logic. The PMU allows counting various events related | |
| 34 | to DSU. | |
| 35 | ||
| 6ce4ef94 SZ |
36 | config HISI_PMU |
| 37 | bool "HiSilicon SoC PMU" | |
| 38 | depends on ARM64 && ACPI | |
| 39 | help | |
| 40 | Support for HiSilicon SoC uncore performance monitoring | |
| 41 | unit (PMU), such as: L3C, HHA and DDRC. | |
| 42 | ||
| 21bdbb71 NL |
43 | config QCOM_L2_PMU |
| 44 | bool "Qualcomm Technologies L2-cache PMU" | |
| bddb9b68 | 45 | depends on ARCH_QCOM && ARM64 && ACPI |
| 21bdbb71 NL |
46 | help |
| 47 | Provides support for the L2 cache performance monitor unit (PMU) | |
| 48 | in Qualcomm Technologies processors. | |
| 49 | Adds the L2 cache PMU into the perf events subsystem for | |
| 50 | monitoring L2 cache events. | |
| 51 | ||
| 3071f13d AVF |
52 | config QCOM_L3_PMU |
| 53 | bool "Qualcomm Technologies L3-cache PMU" | |
| bddb9b68 | 54 | depends on ARCH_QCOM && ARM64 && ACPI |
| 3071f13d AVF |
55 | select QCOM_IRQ_COMBINER |
| 56 | help | |
| 57 | Provides support for the L3 cache performance monitor unit (PMU) | |
| 58 | in Qualcomm Technologies processors. | |
| 59 | Adds the L3 cache PMU into the perf events subsystem for | |
| 60 | monitoring L3 cache events. | |
| 61 | ||
| 832c927d | 62 | config XGENE_PMU |
| bddb9b68 | 63 | depends on ARCH_XGENE |
| 832c927d TN |
64 | bool "APM X-Gene SoC PMU" |
| 65 | default n | |
| 66 | help | |
| 67 | Say y if you want to use APM X-Gene SoC performance monitors. | |
| 68 | ||
| d5d9696b WD |
69 | config ARM_SPE_PMU |
| 70 | tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" | |
| 71 | depends on PERF_EVENTS && ARM64 | |
| 72 | help | |
| 73 | Enable perf support for the ARMv8.2 Statistical Profiling | |
| 74 | Extension, which provides periodic sampling of operations in | |
| 75 | the CPU pipeline and reports this via the perf AUX interface. | |
| 76 | ||
| fa8ad788 | 77 | endmenu |