[linux-2.6-block.git] / drivers / perf / Kconfig

# SPDX-License-Identifier: GPL-2.0-only
#
# Performance Monitor Drivers
#

menu "Performance monitor support"
	depends on PERF_EVENTS

config ARM_CCI_PMU
	tristate "ARM CCI PMU driver"
	depends on (ARM && CPU_V7) || ARM64
	select ARM_CCI
	help
	  Support for PMU events monitoring on the ARM CCI (Cache Coherent
	  Interconnect) family of products.

	  If compiled as a module, it will be called arm-cci.

config ARM_CCI400_PMU
	bool "support CCI-400"
	default y
	depends on ARM_CCI_PMU
	select ARM_CCI400_COMMON
	help
	  CCI-400 provides 4 independent event counters counting events related
	  to the connected slave/master interfaces, plus a cycle counter.

config ARM_CCI5xx_PMU
	bool "support CCI-500/CCI-550"
	default y
	depends on ARM_CCI_PMU
	help
	  CCI-500/CCI-550 both provide 8 independent event counters, which can
	  count events pertaining to the slave/master interfaces as well as the
	  internal events to the CCI.

config ARM_CCN
	tristate "ARM CCN driver support"
	depends on ARM || ARM64
	help
	  PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
	  interconnect.

config ARM_PMU
	depends on ARM || ARM64
	bool "ARM PMU framework"
	default y
	help
	  Say y if you want to use CPU performance monitors on ARM-based
	  systems.

config ARM_PMU_ACPI
	depends on ARM_PMU && ACPI
	def_bool y

config ARM_SMMU_V3_PMU
	 tristate "ARM SMMUv3 Performance Monitors Extension"
	 depends on ARM64 && ACPI && ARM_SMMU_V3
	   help
	   Provides support for the ARM SMMUv3 Performance Monitor Counter
	   Groups (PMCG), which provide monitoring of transactions passing
	   through the SMMU and allow the resulting information to be filtered
	   based on the Stream ID of the corresponding master.

config ARM_DSU_PMU
	tristate "ARM DynamIQ Shared Unit (DSU) PMU"
	depends on ARM64
	  help
	  Provides support for performance monitor unit in ARM DynamIQ Shared
	  Unit (DSU). The DSU integrates one or more cores with an L3 memory
	  system, control logic. The PMU allows counting various events related
	  to DSU.

config HISI_PMU
       bool "HiSilicon SoC PMU"
       depends on ARM64 && ACPI
       help
         Support for HiSilicon SoC uncore performance monitoring
         unit (PMU), such as: L3C, HHA and DDRC.

config QCOM_L2_PMU
	bool "Qualcomm Technologies L2-cache PMU"
	depends on ARCH_QCOM && ARM64 && ACPI
	  help
	  Provides support for the L2 cache performance monitor unit (PMU)
	  in Qualcomm Technologies processors.
	  Adds the L2 cache PMU into the perf events subsystem for
	  monitoring L2 cache events.

config QCOM_L3_PMU
	bool "Qualcomm Technologies L3-cache PMU"
	depends on ARCH_QCOM && ARM64 && ACPI
	select QCOM_IRQ_COMBINER
	help
	   Provides support for the L3 cache performance monitor unit (PMU)
	   in Qualcomm Technologies processors.
	   Adds the L3 cache PMU into the perf events subsystem for
	   monitoring L3 cache events.

config THUNDERX2_PMU
	tristate "Cavium ThunderX2 SoC PMU UNCORE"
	depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
	default m
	help
	   Provides support for ThunderX2 UNCORE events.
	   The SoC has PMU support in its L3 cache controller (L3C) and
	   in the DDR4 Memory Controller (DMC).

config XGENE_PMU
        depends on ARCH_XGENE
        bool "APM X-Gene SoC PMU"
        default n
        help
          Say y if you want to use APM X-Gene SoC performance monitors.

config ARM_SPE_PMU
	tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
	depends on ARM64
	help
	  Enable perf support for the ARMv8.2 Statistical Profiling
	  Extension, which provides periodic sampling of operations in
	  the CPU pipeline and reports this via the perf AUX interface.

endmenu
Commit	Line	Data
ec8f24b7	1	# SPDX-License-Identifier: GPL-2.0-only
fa8ad788 MR	2	#
	3	# Performance Monitor Drivers
	4	#
	5
	6	menu "Performance monitor support"
bddb9b68	7	depends on PERF_EVENTS
fa8ad788	8
3de6be7a	9	config ARM_CCI_PMU
8b0c93c2 RM	10	tristate "ARM CCI PMU driver"
8b0c93c2 RM	11	depends on (ARM && CPU_V7) \|\| ARM64
3de6be7a	12	select ARM_CCI
8b0c93c2 RM	13	help
	14	Support for PMU events monitoring on the ARM CCI (Cache Coherent
	15	Interconnect) family of products.
	16
	17	If compiled as a module, it will be called arm-cci.
3de6be7a RM	18
3de6be7a RM	19	config ARM_CCI400_PMU
8b0c93c2 RM	20	bool "support CCI-400"
	21	default y
	22	depends on ARM_CCI_PMU
3de6be7a	23	select ARM_CCI400_COMMON
3de6be7a	24	help
8b0c93c2 RM	25	CCI-400 provides 4 independent event counters counting events related
8b0c93c2 RM	26	to the connected slave/master interfaces, plus a cycle counter.
3de6be7a RM	27
3de6be7a RM	28	config ARM_CCI5xx_PMU
8b0c93c2 RM	29	bool "support CCI-500/CCI-550"
	30	default y
	31	depends on ARM_CCI_PMU
3de6be7a	32	help
8b0c93c2 RM	33	CCI-500/CCI-550 both provide 8 independent event counters, which can
	34	count events pertaining to the slave/master interfaces as well as the
	35	internal events to the CCI.
3de6be7a	36
1888d3dd RM	37	config ARM_CCN
	38	tristate "ARM CCN driver support"
	39	depends on ARM \|\| ARM64
	40	help
	41	PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
	42	interconnect.
	43
fa8ad788	44	config ARM_PMU
bddb9b68	45	depends on ARM \|\| ARM64
fa8ad788 MR	46	bool "ARM PMU framework"
	47	default y
	48	help
	49	Say y if you want to use CPU performance monitors on ARM-based
	50	systems.
	51
45736a72 MR	52	config ARM_PMU_ACPI
	53	depends on ARM_PMU && ACPI
	54	def_bool y
	55
7d839b4b NL	56	config ARM_SMMU_V3_PMU
	57	tristate "ARM SMMUv3 Performance Monitors Extension"
	58	depends on ARM64 && ACPI && ARM_SMMU_V3
	59	help
	60	Provides support for the ARM SMMUv3 Performance Monitor Counter
	61	Groups (PMCG), which provide monitoring of transactions passing
	62	through the SMMU and allow the resulting information to be filtered
	63	based on the Stream ID of the corresponding master.
	64
7520fa99 SP	65	config ARM_DSU_PMU
	66	tristate "ARM DynamIQ Shared Unit (DSU) PMU"
	67	depends on ARM64
	68	help
	69	Provides support for performance monitor unit in ARM DynamIQ Shared
	70	Unit (DSU). The DSU integrates one or more cores with an L3 memory
	71	system, control logic. The PMU allows counting various events related
	72	to DSU.
	73
6ce4ef94 SZ	74	config HISI_PMU
	75	bool "HiSilicon SoC PMU"
	76	depends on ARM64 && ACPI
	77	help
	78	Support for HiSilicon SoC uncore performance monitoring
	79	unit (PMU), such as: L3C, HHA and DDRC.
	80
21bdbb71 NL	81	config QCOM_L2_PMU
21bdbb71 NL	82	bool "Qualcomm Technologies L2-cache PMU"
bddb9b68	83	depends on ARCH_QCOM && ARM64 && ACPI
21bdbb71 NL	84	help
	85	Provides support for the L2 cache performance monitor unit (PMU)
	86	in Qualcomm Technologies processors.
	87	Adds the L2 cache PMU into the perf events subsystem for
	88	monitoring L2 cache events.
	89
3071f13d AVF	90	config QCOM_L3_PMU
3071f13d AVF	91	bool "Qualcomm Technologies L3-cache PMU"
bddb9b68	92	depends on ARCH_QCOM && ARM64 && ACPI
3071f13d AVF	93	select QCOM_IRQ_COMBINER
	94	help
	95	Provides support for the L3 cache performance monitor unit (PMU)
	96	in Qualcomm Technologies processors.
	97	Adds the L3 cache PMU into the perf events subsystem for
	98	monitoring L3 cache events.
	99
69c32972 KG	100	config THUNDERX2_PMU
	101	tristate "Cavium ThunderX2 SoC PMU UNCORE"
	102	depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
	103	default m
	104	help
	105	Provides support for ThunderX2 UNCORE events.
	106	The SoC has PMU support in its L3 cache controller (L3C) and
	107	in the DDR4 Memory Controller (DMC).
	108
832c927d	109	config XGENE_PMU
bddb9b68	110	depends on ARCH_XGENE
832c927d TN	111	bool "APM X-Gene SoC PMU"
	112	default n
	113	help
	114	Say y if you want to use APM X-Gene SoC performance monitors.
	115
d5d9696b WD	116	config ARM_SPE_PMU
d5d9696b WD	117	tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
b89205bd	118	depends on ARM64
d5d9696b WD	119	help
	120	Enable perf support for the ARMv8.2 Statistical Profiling
	121	Extension, which provides periodic sampling of operations in
	122	the CPU pipeline and reports this via the perf AUX interface.
	123
fa8ad788	124	endmenu