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fa8ad788 MR |
1 | # |
2 | # Performance Monitor Drivers | |
3 | # | |
4 | ||
5 | menu "Performance monitor support" | |
bddb9b68 | 6 | depends on PERF_EVENTS |
fa8ad788 | 7 | |
3de6be7a | 8 | config ARM_CCI_PMU |
8b0c93c2 RM |
9 | tristate "ARM CCI PMU driver" |
10 | depends on (ARM && CPU_V7) || ARM64 | |
3de6be7a | 11 | select ARM_CCI |
8b0c93c2 RM |
12 | help |
13 | Support for PMU events monitoring on the ARM CCI (Cache Coherent | |
14 | Interconnect) family of products. | |
15 | ||
16 | If compiled as a module, it will be called arm-cci. | |
3de6be7a RM |
17 | |
18 | config ARM_CCI400_PMU | |
8b0c93c2 RM |
19 | bool "support CCI-400" |
20 | default y | |
21 | depends on ARM_CCI_PMU | |
3de6be7a | 22 | select ARM_CCI400_COMMON |
3de6be7a | 23 | help |
8b0c93c2 RM |
24 | CCI-400 provides 4 independent event counters counting events related |
25 | to the connected slave/master interfaces, plus a cycle counter. | |
3de6be7a RM |
26 | |
27 | config ARM_CCI5xx_PMU | |
8b0c93c2 RM |
28 | bool "support CCI-500/CCI-550" |
29 | default y | |
30 | depends on ARM_CCI_PMU | |
3de6be7a | 31 | help |
8b0c93c2 RM |
32 | CCI-500/CCI-550 both provide 8 independent event counters, which can |
33 | count events pertaining to the slave/master interfaces as well as the | |
34 | internal events to the CCI. | |
3de6be7a | 35 | |
1888d3dd RM |
36 | config ARM_CCN |
37 | tristate "ARM CCN driver support" | |
38 | depends on ARM || ARM64 | |
39 | help | |
40 | PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) | |
41 | interconnect. | |
42 | ||
fa8ad788 | 43 | config ARM_PMU |
bddb9b68 | 44 | depends on ARM || ARM64 |
fa8ad788 MR |
45 | bool "ARM PMU framework" |
46 | default y | |
47 | help | |
48 | Say y if you want to use CPU performance monitors on ARM-based | |
49 | systems. | |
50 | ||
45736a72 MR |
51 | config ARM_PMU_ACPI |
52 | depends on ARM_PMU && ACPI | |
53 | def_bool y | |
54 | ||
7520fa99 SP |
55 | config ARM_DSU_PMU |
56 | tristate "ARM DynamIQ Shared Unit (DSU) PMU" | |
57 | depends on ARM64 | |
58 | help | |
59 | Provides support for performance monitor unit in ARM DynamIQ Shared | |
60 | Unit (DSU). The DSU integrates one or more cores with an L3 memory | |
61 | system, control logic. The PMU allows counting various events related | |
62 | to DSU. | |
63 | ||
6ce4ef94 SZ |
64 | config HISI_PMU |
65 | bool "HiSilicon SoC PMU" | |
66 | depends on ARM64 && ACPI | |
67 | help | |
68 | Support for HiSilicon SoC uncore performance monitoring | |
69 | unit (PMU), such as: L3C, HHA and DDRC. | |
70 | ||
21bdbb71 NL |
71 | config QCOM_L2_PMU |
72 | bool "Qualcomm Technologies L2-cache PMU" | |
bddb9b68 | 73 | depends on ARCH_QCOM && ARM64 && ACPI |
21bdbb71 NL |
74 | help |
75 | Provides support for the L2 cache performance monitor unit (PMU) | |
76 | in Qualcomm Technologies processors. | |
77 | Adds the L2 cache PMU into the perf events subsystem for | |
78 | monitoring L2 cache events. | |
79 | ||
3071f13d AVF |
80 | config QCOM_L3_PMU |
81 | bool "Qualcomm Technologies L3-cache PMU" | |
bddb9b68 | 82 | depends on ARCH_QCOM && ARM64 && ACPI |
3071f13d AVF |
83 | select QCOM_IRQ_COMBINER |
84 | help | |
85 | Provides support for the L3 cache performance monitor unit (PMU) | |
86 | in Qualcomm Technologies processors. | |
87 | Adds the L3 cache PMU into the perf events subsystem for | |
88 | monitoring L3 cache events. | |
89 | ||
69c32972 KG |
90 | config THUNDERX2_PMU |
91 | tristate "Cavium ThunderX2 SoC PMU UNCORE" | |
92 | depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA | |
93 | default m | |
94 | help | |
95 | Provides support for ThunderX2 UNCORE events. | |
96 | The SoC has PMU support in its L3 cache controller (L3C) and | |
97 | in the DDR4 Memory Controller (DMC). | |
98 | ||
832c927d | 99 | config XGENE_PMU |
bddb9b68 | 100 | depends on ARCH_XGENE |
832c927d TN |
101 | bool "APM X-Gene SoC PMU" |
102 | default n | |
103 | help | |
104 | Say y if you want to use APM X-Gene SoC performance monitors. | |
105 | ||
d5d9696b WD |
106 | config ARM_SPE_PMU |
107 | tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" | |
b89205bd | 108 | depends on ARM64 |
d5d9696b WD |
109 | help |
110 | Enable perf support for the ARMv8.2 Statistical Profiling | |
111 | Extension, which provides periodic sampling of operations in | |
112 | the CPU pipeline and reports this via the perf AUX interface. | |
113 | ||
fa8ad788 | 114 | endmenu |