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ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
fa8ad788 MR |
2 | # |
3 | # Performance Monitor Drivers | |
4 | # | |
5 | ||
6 | menu "Performance monitor support" | |
bddb9b68 | 7 | depends on PERF_EVENTS |
fa8ad788 | 8 | |
3de6be7a | 9 | config ARM_CCI_PMU |
8b0c93c2 RM |
10 | tristate "ARM CCI PMU driver" |
11 | depends on (ARM && CPU_V7) || ARM64 | |
3de6be7a | 12 | select ARM_CCI |
8b0c93c2 RM |
13 | help |
14 | Support for PMU events monitoring on the ARM CCI (Cache Coherent | |
15 | Interconnect) family of products. | |
16 | ||
17 | If compiled as a module, it will be called arm-cci. | |
3de6be7a RM |
18 | |
19 | config ARM_CCI400_PMU | |
8b0c93c2 RM |
20 | bool "support CCI-400" |
21 | default y | |
22 | depends on ARM_CCI_PMU | |
3de6be7a | 23 | select ARM_CCI400_COMMON |
3de6be7a | 24 | help |
8b0c93c2 RM |
25 | CCI-400 provides 4 independent event counters counting events related |
26 | to the connected slave/master interfaces, plus a cycle counter. | |
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27 | |
28 | config ARM_CCI5xx_PMU | |
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29 | bool "support CCI-500/CCI-550" |
30 | default y | |
31 | depends on ARM_CCI_PMU | |
3de6be7a | 32 | help |
8b0c93c2 RM |
33 | CCI-500/CCI-550 both provide 8 independent event counters, which can |
34 | count events pertaining to the slave/master interfaces as well as the | |
35 | internal events to the CCI. | |
3de6be7a | 36 | |
1888d3dd RM |
37 | config ARM_CCN |
38 | tristate "ARM CCN driver support" | |
39 | depends on ARM || ARM64 | |
40 | help | |
41 | PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) | |
42 | interconnect. | |
43 | ||
fa8ad788 | 44 | config ARM_PMU |
bddb9b68 | 45 | depends on ARM || ARM64 |
fa8ad788 MR |
46 | bool "ARM PMU framework" |
47 | default y | |
48 | help | |
49 | Say y if you want to use CPU performance monitors on ARM-based | |
50 | systems. | |
51 | ||
45736a72 MR |
52 | config ARM_PMU_ACPI |
53 | depends on ARM_PMU && ACPI | |
54 | def_bool y | |
55 | ||
7d839b4b NL |
56 | config ARM_SMMU_V3_PMU |
57 | tristate "ARM SMMUv3 Performance Monitors Extension" | |
58 | depends on ARM64 && ACPI && ARM_SMMU_V3 | |
59 | help | |
60 | Provides support for the ARM SMMUv3 Performance Monitor Counter | |
61 | Groups (PMCG), which provide monitoring of transactions passing | |
62 | through the SMMU and allow the resulting information to be filtered | |
63 | based on the Stream ID of the corresponding master. | |
64 | ||
7520fa99 SP |
65 | config ARM_DSU_PMU |
66 | tristate "ARM DynamIQ Shared Unit (DSU) PMU" | |
67 | depends on ARM64 | |
68 | help | |
69 | Provides support for performance monitor unit in ARM DynamIQ Shared | |
70 | Unit (DSU). The DSU integrates one or more cores with an L3 memory | |
71 | system, control logic. The PMU allows counting various events related | |
72 | to DSU. | |
73 | ||
9a66d36c FL |
74 | config FSL_IMX8_DDR_PMU |
75 | tristate "Freescale i.MX8 DDR perf monitor" | |
76 | depends on ARCH_MXC | |
77 | help | |
78 | Provides support for the DDR performance monitor in i.MX8, which | |
79 | can give information about memory throughput and other related | |
80 | events. | |
81 | ||
6ce4ef94 SZ |
82 | config HISI_PMU |
83 | bool "HiSilicon SoC PMU" | |
84 | depends on ARM64 && ACPI | |
85 | help | |
86 | Support for HiSilicon SoC uncore performance monitoring | |
87 | unit (PMU), such as: L3C, HHA and DDRC. | |
88 | ||
21bdbb71 NL |
89 | config QCOM_L2_PMU |
90 | bool "Qualcomm Technologies L2-cache PMU" | |
bddb9b68 | 91 | depends on ARCH_QCOM && ARM64 && ACPI |
21bdbb71 NL |
92 | help |
93 | Provides support for the L2 cache performance monitor unit (PMU) | |
94 | in Qualcomm Technologies processors. | |
95 | Adds the L2 cache PMU into the perf events subsystem for | |
96 | monitoring L2 cache events. | |
97 | ||
3071f13d AVF |
98 | config QCOM_L3_PMU |
99 | bool "Qualcomm Technologies L3-cache PMU" | |
bddb9b68 | 100 | depends on ARCH_QCOM && ARM64 && ACPI |
3071f13d AVF |
101 | select QCOM_IRQ_COMBINER |
102 | help | |
103 | Provides support for the L3 cache performance monitor unit (PMU) | |
104 | in Qualcomm Technologies processors. | |
105 | Adds the L3 cache PMU into the perf events subsystem for | |
106 | monitoring L3 cache events. | |
107 | ||
69c32972 KG |
108 | config THUNDERX2_PMU |
109 | tristate "Cavium ThunderX2 SoC PMU UNCORE" | |
110 | depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA | |
111 | default m | |
112 | help | |
113 | Provides support for ThunderX2 UNCORE events. | |
114 | The SoC has PMU support in its L3 cache controller (L3C) and | |
115 | in the DDR4 Memory Controller (DMC). | |
116 | ||
832c927d | 117 | config XGENE_PMU |
bddb9b68 | 118 | depends on ARCH_XGENE |
832c927d TN |
119 | bool "APM X-Gene SoC PMU" |
120 | default n | |
121 | help | |
122 | Say y if you want to use APM X-Gene SoC performance monitors. | |
123 | ||
d5d9696b WD |
124 | config ARM_SPE_PMU |
125 | tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" | |
b89205bd | 126 | depends on ARM64 |
d5d9696b WD |
127 | help |
128 | Enable perf support for the ARMv8.2 Statistical Profiling | |
129 | Extension, which provides periodic sampling of operations in | |
130 | the CPU pipeline and reports this via the perf AUX interface. | |
131 | ||
fa8ad788 | 132 | endmenu |