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1da177e4 LT |
1 | /* |
2 | * ti113x.h 1.16 1999/10/25 20:03:34 | |
3 | * | |
4 | * The contents of this file are subject to the Mozilla Public License | |
5 | * Version 1.1 (the "License"); you may not use this file except in | |
6 | * compliance with the License. You may obtain a copy of the License | |
7 | * at http://www.mozilla.org/MPL/ | |
8 | * | |
9 | * Software distributed under the License is distributed on an "AS IS" | |
10 | * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See | |
11 | * the License for the specific language governing rights and | |
12 | * limitations under the License. | |
13 | * | |
14 | * The initial developer of the original code is David A. Hinds | |
15 | * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds | |
16 | * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. | |
17 | * | |
18 | * Alternatively, the contents of this file may be used under the | |
19 | * terms of the GNU General Public License version 2 (the "GPL"), in which | |
20 | * case the provisions of the GPL are applicable instead of the | |
21 | * above. If you wish to allow the use of your version of this file | |
22 | * only under the terms of the GPL and not to allow others to use | |
23 | * your version of this file under the MPL, indicate your decision by | |
24 | * deleting the provisions above and replace them with the notice and | |
25 | * other provisions required by the GPL. If you do not delete the | |
26 | * provisions above, a recipient may use your version of this file | |
27 | * under either the MPL or the GPL. | |
28 | */ | |
29 | ||
30 | #ifndef _LINUX_TI113X_H | |
31 | #define _LINUX_TI113X_H | |
32 | ||
1da177e4 LT |
33 | |
34 | /* Register definitions for TI 113X PCI-to-CardBus bridges */ | |
35 | ||
36 | /* System Control Register */ | |
37 | #define TI113X_SYSTEM_CONTROL 0x0080 /* 32 bit */ | |
38 | #define TI113X_SCR_SMIROUTE 0x04000000 | |
39 | #define TI113X_SCR_SMISTATUS 0x02000000 | |
40 | #define TI113X_SCR_SMIENB 0x01000000 | |
41 | #define TI113X_SCR_VCCPROT 0x00200000 | |
42 | #define TI113X_SCR_REDUCEZV 0x00100000 | |
43 | #define TI113X_SCR_CDREQEN 0x00080000 | |
44 | #define TI113X_SCR_CDMACHAN 0x00070000 | |
45 | #define TI113X_SCR_SOCACTIVE 0x00002000 | |
46 | #define TI113X_SCR_PWRSTREAM 0x00000800 | |
47 | #define TI113X_SCR_DELAYUP 0x00000400 | |
48 | #define TI113X_SCR_DELAYDOWN 0x00000200 | |
49 | #define TI113X_SCR_INTERROGATE 0x00000100 | |
50 | #define TI113X_SCR_CLKRUN_SEL 0x00000080 | |
51 | #define TI113X_SCR_PWRSAVINGS 0x00000040 | |
52 | #define TI113X_SCR_SUBSYSRW 0x00000020 | |
53 | #define TI113X_SCR_CB_DPAR 0x00000010 | |
54 | #define TI113X_SCR_CDMA_EN 0x00000008 | |
55 | #define TI113X_SCR_ASYNC_IRQ 0x00000004 | |
56 | #define TI113X_SCR_KEEPCLK 0x00000002 | |
57 | #define TI113X_SCR_CLKRUN_ENA 0x00000001 | |
58 | ||
59 | #define TI122X_SCR_SER_STEP 0xc0000000 | |
60 | #define TI122X_SCR_INTRTIE 0x20000000 | |
6c1a10db | 61 | #define TIXX21_SCR_TIEALL 0x10000000 |
1da177e4 LT |
62 | #define TI122X_SCR_CBRSVD 0x00400000 |
63 | #define TI122X_SCR_MRBURSTDN 0x00008000 | |
64 | #define TI122X_SCR_MRBURSTUP 0x00004000 | |
65 | #define TI122X_SCR_RIMUX 0x00000001 | |
66 | ||
67 | /* Multimedia Control Register */ | |
68 | #define TI1250_MULTIMEDIA_CTL 0x0084 /* 8 bit */ | |
69 | #define TI1250_MMC_ZVOUTEN 0x80 | |
70 | #define TI1250_MMC_PORTSEL 0x40 | |
71 | #define TI1250_MMC_ZVEN1 0x02 | |
72 | #define TI1250_MMC_ZVEN0 0x01 | |
73 | ||
74 | #define TI1250_GENERAL_STATUS 0x0085 /* 8 bit */ | |
75 | #define TI1250_GPIO0_CONTROL 0x0088 /* 8 bit */ | |
76 | #define TI1250_GPIO1_CONTROL 0x0089 /* 8 bit */ | |
77 | #define TI1250_GPIO2_CONTROL 0x008a /* 8 bit */ | |
78 | #define TI1250_GPIO3_CONTROL 0x008b /* 8 bit */ | |
79 | #define TI1250_GPIO_MODE_MASK 0xc0 | |
80 | ||
81 | /* IRQMUX/MFUNC Register */ | |
82 | #define TI122X_MFUNC 0x008c /* 32 bit */ | |
83 | #define TI122X_MFUNC0_MASK 0x0000000f | |
84 | #define TI122X_MFUNC1_MASK 0x000000f0 | |
85 | #define TI122X_MFUNC2_MASK 0x00000f00 | |
86 | #define TI122X_MFUNC3_MASK 0x0000f000 | |
87 | #define TI122X_MFUNC4_MASK 0x000f0000 | |
88 | #define TI122X_MFUNC5_MASK 0x00f00000 | |
89 | #define TI122X_MFUNC6_MASK 0x0f000000 | |
90 | ||
91 | #define TI122X_MFUNC0_INTA 0x00000002 | |
92 | #define TI125X_MFUNC0_INTB 0x00000001 | |
93 | #define TI122X_MFUNC1_INTB 0x00000020 | |
94 | #define TI122X_MFUNC3_IRQSER 0x00001000 | |
95 | ||
96 | ||
97 | /* Retry Status Register */ | |
98 | #define TI113X_RETRY_STATUS 0x0090 /* 8 bit */ | |
99 | #define TI113X_RSR_PCIRETRY 0x80 | |
100 | #define TI113X_RSR_CBRETRY 0x40 | |
101 | #define TI113X_RSR_TEXP_CBB 0x20 | |
102 | #define TI113X_RSR_MEXP_CBB 0x10 | |
103 | #define TI113X_RSR_TEXP_CBA 0x08 | |
104 | #define TI113X_RSR_MEXP_CBA 0x04 | |
105 | #define TI113X_RSR_TEXP_PCI 0x02 | |
106 | #define TI113X_RSR_MEXP_PCI 0x01 | |
107 | ||
108 | /* Card Control Register */ | |
109 | #define TI113X_CARD_CONTROL 0x0091 /* 8 bit */ | |
110 | #define TI113X_CCR_RIENB 0x80 | |
111 | #define TI113X_CCR_ZVENABLE 0x40 | |
112 | #define TI113X_CCR_PCI_IRQ_ENA 0x20 | |
113 | #define TI113X_CCR_PCI_IREQ 0x10 | |
114 | #define TI113X_CCR_PCI_CSC 0x08 | |
115 | #define TI113X_CCR_SPKROUTEN 0x02 | |
116 | #define TI113X_CCR_IFG 0x01 | |
117 | ||
118 | #define TI1220_CCR_PORT_SEL 0x20 | |
119 | #define TI122X_CCR_AUD2MUX 0x04 | |
120 | ||
121 | /* Device Control Register */ | |
122 | #define TI113X_DEVICE_CONTROL 0x0092 /* 8 bit */ | |
123 | #define TI113X_DCR_5V_FORCE 0x40 | |
124 | #define TI113X_DCR_3V_FORCE 0x20 | |
125 | #define TI113X_DCR_IMODE_MASK 0x06 | |
126 | #define TI113X_DCR_IMODE_ISA 0x02 | |
127 | #define TI113X_DCR_IMODE_SERIAL 0x04 | |
128 | ||
129 | #define TI12XX_DCR_IMODE_PCI_ONLY 0x00 | |
130 | #define TI12XX_DCR_IMODE_ALL_SERIAL 0x06 | |
131 | ||
132 | /* Buffer Control Register */ | |
133 | #define TI113X_BUFFER_CONTROL 0x0093 /* 8 bit */ | |
134 | #define TI113X_BCR_CB_READ_DEPTH 0x08 | |
135 | #define TI113X_BCR_CB_WRITE_DEPTH 0x04 | |
136 | #define TI113X_BCR_PCI_READ_DEPTH 0x02 | |
137 | #define TI113X_BCR_PCI_WRITE_DEPTH 0x01 | |
138 | ||
139 | /* Diagnostic Register */ | |
140 | #define TI1250_DIAGNOSTIC 0x0093 /* 8 bit */ | |
141 | #define TI1250_DIAG_TRUE_VALUE 0x80 | |
142 | #define TI1250_DIAG_PCI_IREQ 0x40 | |
143 | #define TI1250_DIAG_PCI_CSC 0x20 | |
144 | #define TI1250_DIAG_ASYNC_CSC 0x01 | |
145 | ||
146 | /* DMA Registers */ | |
147 | #define TI113X_DMA_0 0x0094 /* 32 bit */ | |
148 | #define TI113X_DMA_1 0x0098 /* 32 bit */ | |
149 | ||
150 | /* ExCA IO offset registers */ | |
151 | #define TI113X_IO_OFFSET(map) (0x36+((map)<<1)) | |
152 | ||
153 | /* EnE test register */ | |
154 | #define ENE_TEST_C9 0xc9 /* 8bit */ | |
155 | #define ENE_TEST_C9_TLTENABLE 0x02 | |
8c3520d4 DR |
156 | #define ENE_TEST_C9_PFENABLE_F0 0x04 |
157 | #define ENE_TEST_C9_PFENABLE_F1 0x08 | |
14540c6d | 158 | #define ENE_TEST_C9_PFENABLE (ENE_TEST_C9_PFENABLE_F0 | ENE_TEST_C9_PFENABLE_F1) |
8c3520d4 DR |
159 | #define ENE_TEST_C9_WPDISALBLE_F0 0x40 |
160 | #define ENE_TEST_C9_WPDISALBLE_F1 0x80 | |
161 | #define ENE_TEST_C9_WPDISALBLE (ENE_TEST_C9_WPDISALBLE_F0 | ENE_TEST_C9_WPDISALBLE_F1) | |
1da177e4 | 162 | |
1da177e4 LT |
163 | /* |
164 | * Texas Instruments CardBus controller overrides. | |
165 | */ | |
166 | #define ti_sysctl(socket) ((socket)->private[0]) | |
167 | #define ti_cardctl(socket) ((socket)->private[1]) | |
168 | #define ti_devctl(socket) ((socket)->private[2]) | |
169 | #define ti_diag(socket) ((socket)->private[3]) | |
170 | #define ti_mfunc(socket) ((socket)->private[4]) | |
171 | #define ene_test_c9(socket) ((socket)->private[5]) | |
172 | ||
173 | /* | |
174 | * These are the TI specific power management handlers. | |
175 | */ | |
176 | static void ti_save_state(struct yenta_socket *socket) | |
177 | { | |
178 | ti_sysctl(socket) = config_readl(socket, TI113X_SYSTEM_CONTROL); | |
179 | ti_mfunc(socket) = config_readl(socket, TI122X_MFUNC); | |
180 | ti_cardctl(socket) = config_readb(socket, TI113X_CARD_CONTROL); | |
181 | ti_devctl(socket) = config_readb(socket, TI113X_DEVICE_CONTROL); | |
182 | ti_diag(socket) = config_readb(socket, TI1250_DIAGNOSTIC); | |
183 | ||
184 | if (socket->dev->vendor == PCI_VENDOR_ID_ENE) | |
185 | ene_test_c9(socket) = config_readb(socket, ENE_TEST_C9); | |
186 | } | |
187 | ||
188 | static void ti_restore_state(struct yenta_socket *socket) | |
189 | { | |
190 | config_writel(socket, TI113X_SYSTEM_CONTROL, ti_sysctl(socket)); | |
191 | config_writel(socket, TI122X_MFUNC, ti_mfunc(socket)); | |
192 | config_writeb(socket, TI113X_CARD_CONTROL, ti_cardctl(socket)); | |
193 | config_writeb(socket, TI113X_DEVICE_CONTROL, ti_devctl(socket)); | |
194 | config_writeb(socket, TI1250_DIAGNOSTIC, ti_diag(socket)); | |
195 | ||
196 | if (socket->dev->vendor == PCI_VENDOR_ID_ENE) | |
197 | config_writeb(socket, ENE_TEST_C9, ene_test_c9(socket)); | |
198 | } | |
199 | ||
200 | /* | |
201 | * Zoom video control for TI122x/113x chips | |
202 | */ | |
203 | ||
204 | static void ti_zoom_video(struct pcmcia_socket *sock, int onoff) | |
205 | { | |
206 | u8 reg; | |
207 | struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket); | |
208 | ||
209 | /* If we don't have a Zoom Video switch this is harmless, | |
210 | we just tristate the unused (ZV) lines */ | |
211 | reg = config_readb(socket, TI113X_CARD_CONTROL); | |
212 | if (onoff) | |
213 | /* Zoom zoom, we will all go together, zoom zoom, zoom zoom */ | |
214 | reg |= TI113X_CCR_ZVENABLE; | |
215 | else | |
216 | reg &= ~TI113X_CCR_ZVENABLE; | |
217 | config_writeb(socket, TI113X_CARD_CONTROL, reg); | |
218 | } | |
219 | ||
220 | /* | |
221 | * The 145x series can also use this. They have an additional | |
222 | * ZV autodetect mode we don't use but don't actually need. | |
223 | * FIXME: manual says its in func0 and func1 but disagrees with | |
224 | * itself about this - do we need to force func0, if so we need | |
225 | * to know a lot more about socket pairings in pcmcia_socket than | |
226 | * we do now.. uggh. | |
227 | */ | |
228 | ||
229 | static void ti1250_zoom_video(struct pcmcia_socket *sock, int onoff) | |
230 | { | |
231 | struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket); | |
232 | int shift = 0; | |
233 | u8 reg; | |
234 | ||
235 | ti_zoom_video(sock, onoff); | |
236 | ||
237 | reg = config_readb(socket, TI1250_MULTIMEDIA_CTL); | |
238 | reg |= TI1250_MMC_ZVOUTEN; /* ZV bus enable */ | |
239 | ||
240 | if(PCI_FUNC(socket->dev->devfn)==1) | |
241 | shift = 1; | |
242 | ||
243 | if(onoff) | |
244 | { | |
245 | reg &= ~(1<<6); /* Clear select bit */ | |
246 | reg |= shift<<6; /* Favour our socket */ | |
247 | reg |= 1<<shift; /* Socket zoom video on */ | |
248 | } | |
249 | else | |
250 | { | |
251 | reg &= ~(1<<6); /* Clear select bit */ | |
252 | reg |= (1^shift)<<6; /* Favour other socket */ | |
253 | reg &= ~(1<<shift); /* Socket zoon video off */ | |
254 | } | |
255 | ||
256 | config_writeb(socket, TI1250_MULTIMEDIA_CTL, reg); | |
257 | } | |
258 | ||
259 | static void ti_set_zv(struct yenta_socket *socket) | |
260 | { | |
261 | if(socket->dev->vendor == PCI_VENDOR_ID_TI) | |
262 | { | |
263 | switch(socket->dev->device) | |
264 | { | |
265 | /* There may be more .. */ | |
266 | case PCI_DEVICE_ID_TI_1220: | |
267 | case PCI_DEVICE_ID_TI_1221: | |
268 | case PCI_DEVICE_ID_TI_1225: | |
269 | case PCI_DEVICE_ID_TI_4510: | |
270 | socket->socket.zoom_video = ti_zoom_video; | |
271 | break; | |
272 | case PCI_DEVICE_ID_TI_1250: | |
273 | case PCI_DEVICE_ID_TI_1251A: | |
274 | case PCI_DEVICE_ID_TI_1251B: | |
275 | case PCI_DEVICE_ID_TI_1450: | |
276 | socket->socket.zoom_video = ti1250_zoom_video; | |
277 | } | |
278 | } | |
279 | } | |
280 | ||
281 | ||
282 | /* | |
283 | * Generic TI init - TI has an extension for the | |
284 | * INTCTL register that sets the PCI CSC interrupt. | |
285 | * Make sure we set it correctly at open and init | |
286 | * time | |
287 | * - override: disable the PCI CSC interrupt. This makes | |
288 | * it possible to use the CSC interrupt to probe the | |
289 | * ISA interrupts. | |
290 | * - init: set the interrupt to match our PCI state. | |
291 | * This makes us correctly get PCI CSC interrupt | |
292 | * events. | |
293 | */ | |
294 | static int ti_init(struct yenta_socket *socket) | |
295 | { | |
296 | u8 new, reg = exca_readb(socket, I365_INTCTL); | |
297 | ||
298 | new = reg & ~I365_INTR_ENA; | |
299 | if (socket->cb_irq) | |
300 | new |= I365_INTR_ENA; | |
301 | if (new != reg) | |
302 | exca_writeb(socket, I365_INTCTL, new); | |
303 | return 0; | |
304 | } | |
305 | ||
306 | static int ti_override(struct yenta_socket *socket) | |
307 | { | |
308 | u8 new, reg = exca_readb(socket, I365_INTCTL); | |
309 | ||
310 | new = reg & ~I365_INTR_ENA; | |
311 | if (new != reg) | |
312 | exca_writeb(socket, I365_INTCTL, new); | |
313 | ||
314 | ti_set_zv(socket); | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
319 | static int ti113x_override(struct yenta_socket *socket) | |
320 | { | |
321 | u8 cardctl; | |
322 | ||
323 | cardctl = config_readb(socket, TI113X_CARD_CONTROL); | |
324 | cardctl &= ~(TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_IREQ | TI113X_CCR_PCI_CSC); | |
325 | if (socket->cb_irq) | |
326 | cardctl |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_CSC | TI113X_CCR_PCI_IREQ; | |
327 | config_writeb(socket, TI113X_CARD_CONTROL, cardctl); | |
328 | ||
329 | return ti_override(socket); | |
330 | } | |
331 | ||
332 | ||
333 | /* irqrouting for func0, probes PCI interrupt and ISA interrupts */ | |
334 | static void ti12xx_irqroute_func0(struct yenta_socket *socket) | |
335 | { | |
336 | u32 mfunc, mfunc_old, devctl; | |
337 | u8 gpio3, gpio3_old; | |
338 | int pci_irq_status; | |
339 | ||
340 | mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC); | |
341 | devctl = config_readb(socket, TI113X_DEVICE_CONTROL); | |
dd797d81 DB |
342 | dev_printk(KERN_INFO, &socket->dev->dev, |
343 | "TI: mfunc 0x%08x, devctl 0x%02x\n", mfunc, devctl); | |
1da177e4 LT |
344 | |
345 | /* make sure PCI interrupts are enabled before probing */ | |
346 | ti_init(socket); | |
347 | ||
348 | /* test PCI interrupts first. only try fixing if return value is 0! */ | |
349 | pci_irq_status = yenta_probe_cb_irq(socket); | |
350 | if (pci_irq_status) | |
351 | goto out; | |
352 | ||
353 | /* | |
354 | * We're here which means PCI interrupts are _not_ delivered. try to | |
355 | * find the right setting (all serial or parallel) | |
356 | */ | |
dd797d81 DB |
357 | dev_printk(KERN_INFO, &socket->dev->dev, |
358 | "TI: probing PCI interrupt failed, trying to fix\n"); | |
1da177e4 LT |
359 | |
360 | /* for serial PCI make sure MFUNC3 is set to IRQSER */ | |
361 | if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) { | |
362 | switch (socket->dev->device) { | |
363 | case PCI_DEVICE_ID_TI_1250: | |
364 | case PCI_DEVICE_ID_TI_1251A: | |
365 | case PCI_DEVICE_ID_TI_1251B: | |
366 | case PCI_DEVICE_ID_TI_1450: | |
367 | case PCI_DEVICE_ID_TI_1451A: | |
368 | case PCI_DEVICE_ID_TI_4450: | |
369 | case PCI_DEVICE_ID_TI_4451: | |
370 | /* these chips have no IRQSER setting in MFUNC3 */ | |
371 | break; | |
372 | ||
373 | default: | |
374 | mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER; | |
375 | ||
376 | /* write down if changed, probe */ | |
377 | if (mfunc != mfunc_old) { | |
378 | config_writel(socket, TI122X_MFUNC, mfunc); | |
379 | ||
380 | pci_irq_status = yenta_probe_cb_irq(socket); | |
381 | if (pci_irq_status == 1) { | |
dd797d81 DB |
382 | dev_printk(KERN_INFO, &socket->dev->dev, |
383 | "TI: all-serial interrupts ok\n"); | |
1da177e4 LT |
384 | mfunc_old = mfunc; |
385 | goto out; | |
386 | } | |
387 | ||
388 | /* not working, back to old value */ | |
389 | mfunc = mfunc_old; | |
390 | config_writel(socket, TI122X_MFUNC, mfunc); | |
391 | ||
392 | if (pci_irq_status == -1) | |
393 | goto out; | |
394 | } | |
395 | } | |
396 | ||
397 | /* serial PCI interrupts not working fall back to parallel */ | |
dd797d81 DB |
398 | dev_printk(KERN_INFO, &socket->dev->dev, |
399 | "TI: falling back to parallel PCI interrupts\n"); | |
1da177e4 LT |
400 | devctl &= ~TI113X_DCR_IMODE_MASK; |
401 | devctl |= TI113X_DCR_IMODE_SERIAL; /* serial ISA could be right */ | |
402 | config_writeb(socket, TI113X_DEVICE_CONTROL, devctl); | |
403 | } | |
404 | ||
405 | /* parallel PCI interrupts: route INTA */ | |
406 | switch (socket->dev->device) { | |
407 | case PCI_DEVICE_ID_TI_1250: | |
408 | case PCI_DEVICE_ID_TI_1251A: | |
409 | case PCI_DEVICE_ID_TI_1251B: | |
410 | case PCI_DEVICE_ID_TI_1450: | |
411 | /* make sure GPIO3 is set to INTA */ | |
412 | gpio3 = gpio3_old = config_readb(socket, TI1250_GPIO3_CONTROL); | |
413 | gpio3 &= ~TI1250_GPIO_MODE_MASK; | |
414 | if (gpio3 != gpio3_old) | |
415 | config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3); | |
416 | break; | |
417 | ||
418 | default: | |
419 | gpio3 = gpio3_old = 0; | |
420 | ||
421 | mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI122X_MFUNC0_INTA; | |
422 | if (mfunc != mfunc_old) | |
423 | config_writel(socket, TI122X_MFUNC, mfunc); | |
424 | } | |
425 | ||
426 | /* time to probe again */ | |
427 | pci_irq_status = yenta_probe_cb_irq(socket); | |
428 | if (pci_irq_status == 1) { | |
429 | mfunc_old = mfunc; | |
dd797d81 DB |
430 | dev_printk(KERN_INFO, &socket->dev->dev, |
431 | "TI: parallel PCI interrupts ok\n"); | |
1da177e4 LT |
432 | } else { |
433 | /* not working, back to old value */ | |
434 | mfunc = mfunc_old; | |
435 | config_writel(socket, TI122X_MFUNC, mfunc); | |
436 | if (gpio3 != gpio3_old) | |
437 | config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3_old); | |
438 | } | |
439 | ||
440 | out: | |
441 | if (pci_irq_status < 1) { | |
442 | socket->cb_irq = 0; | |
dd797d81 DB |
443 | dev_printk(KERN_INFO, &socket->dev->dev, |
444 | "Yenta TI: no PCI interrupts. Fish. " | |
445 | "Please report.\n"); | |
1da177e4 LT |
446 | } |
447 | } | |
448 | ||
449 | ||
c835a388 DR |
450 | /* changes the irq of func1 to match that of func0 */ |
451 | static int ti12xx_align_irqs(struct yenta_socket *socket, int *old_irq) | |
452 | { | |
453 | struct pci_dev *func0; | |
454 | ||
455 | /* find func0 device */ | |
456 | func0 = pci_get_slot(socket->dev->bus, socket->dev->devfn & ~0x07); | |
457 | if (!func0) | |
458 | return 0; | |
459 | ||
460 | if (old_irq) | |
461 | *old_irq = socket->cb_irq; | |
462 | socket->cb_irq = socket->dev->irq = func0->irq; | |
463 | ||
464 | pci_dev_put(func0); | |
465 | ||
466 | return 1; | |
467 | } | |
468 | ||
1da177e4 LT |
469 | /* |
470 | * ties INTA and INTB together. also changes the devices irq to that of | |
471 | * the function 0 device. call from func1 only. | |
472 | * returns 1 if INTRTIE changed, 0 otherwise. | |
473 | */ | |
474 | static int ti12xx_tie_interrupts(struct yenta_socket *socket, int *old_irq) | |
475 | { | |
1da177e4 | 476 | u32 sysctl; |
c835a388 | 477 | int ret; |
1da177e4 LT |
478 | |
479 | sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL); | |
480 | if (sysctl & TI122X_SCR_INTRTIE) | |
481 | return 0; | |
482 | ||
c835a388 DR |
483 | /* align */ |
484 | ret = ti12xx_align_irqs(socket, old_irq); | |
485 | if (!ret) | |
1da177e4 LT |
486 | return 0; |
487 | ||
c835a388 | 488 | /* tie */ |
1da177e4 LT |
489 | sysctl |= TI122X_SCR_INTRTIE; |
490 | config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl); | |
491 | ||
1da177e4 LT |
492 | return 1; |
493 | } | |
494 | ||
495 | /* undo what ti12xx_tie_interrupts() did */ | |
496 | static void ti12xx_untie_interrupts(struct yenta_socket *socket, int old_irq) | |
497 | { | |
498 | u32 sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL); | |
499 | sysctl &= ~TI122X_SCR_INTRTIE; | |
500 | config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl); | |
501 | ||
502 | socket->cb_irq = socket->dev->irq = old_irq; | |
503 | } | |
504 | ||
505 | /* | |
506 | * irqrouting for func1, plays with INTB routing | |
507 | * only touches MFUNC for INTB routing. all other bits are taken | |
508 | * care of in func0 already. | |
509 | */ | |
510 | static void ti12xx_irqroute_func1(struct yenta_socket *socket) | |
511 | { | |
c835a388 | 512 | u32 mfunc, mfunc_old, devctl, sysctl; |
1da177e4 LT |
513 | int pci_irq_status; |
514 | ||
515 | mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC); | |
516 | devctl = config_readb(socket, TI113X_DEVICE_CONTROL); | |
dd797d81 DB |
517 | dev_printk(KERN_INFO, &socket->dev->dev, |
518 | "TI: mfunc 0x%08x, devctl 0x%02x\n", | |
519 | mfunc, devctl); | |
1da177e4 | 520 | |
c835a388 DR |
521 | /* if IRQs are configured as tied, align irq of func1 with func0 */ |
522 | sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL); | |
523 | if (sysctl & TI122X_SCR_INTRTIE) | |
524 | ti12xx_align_irqs(socket, NULL); | |
525 | ||
1da177e4 LT |
526 | /* make sure PCI interrupts are enabled before probing */ |
527 | ti_init(socket); | |
528 | ||
529 | /* test PCI interrupts first. only try fixing if return value is 0! */ | |
530 | pci_irq_status = yenta_probe_cb_irq(socket); | |
531 | if (pci_irq_status) | |
532 | goto out; | |
533 | ||
534 | /* | |
535 | * We're here which means PCI interrupts are _not_ delivered. try to | |
536 | * find the right setting | |
537 | */ | |
dd797d81 DB |
538 | dev_printk(KERN_INFO, &socket->dev->dev, |
539 | "TI: probing PCI interrupt failed, trying to fix\n"); | |
1da177e4 LT |
540 | |
541 | /* if all serial: set INTRTIE, probe again */ | |
542 | if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) { | |
543 | int old_irq; | |
544 | ||
545 | if (ti12xx_tie_interrupts(socket, &old_irq)) { | |
546 | pci_irq_status = yenta_probe_cb_irq(socket); | |
547 | if (pci_irq_status == 1) { | |
dd797d81 DB |
548 | dev_printk(KERN_INFO, &socket->dev->dev, |
549 | "TI: all-serial interrupts, tied ok\n"); | |
1da177e4 LT |
550 | goto out; |
551 | } | |
552 | ||
553 | ti12xx_untie_interrupts(socket, old_irq); | |
554 | } | |
555 | } | |
556 | /* parallel PCI: route INTB, probe again */ | |
557 | else { | |
558 | int old_irq; | |
559 | ||
560 | switch (socket->dev->device) { | |
561 | case PCI_DEVICE_ID_TI_1250: | |
562 | /* the 1250 has one pin for IRQSER/INTB depending on devctl */ | |
563 | break; | |
564 | ||
565 | case PCI_DEVICE_ID_TI_1251A: | |
566 | case PCI_DEVICE_ID_TI_1251B: | |
567 | case PCI_DEVICE_ID_TI_1450: | |
568 | /* | |
569 | * those have a pin for IRQSER/INTB plus INTB in MFUNC0 | |
570 | * we alread probed the shared pin, now go for MFUNC0 | |
571 | */ | |
572 | mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI125X_MFUNC0_INTB; | |
573 | break; | |
574 | ||
575 | default: | |
576 | mfunc = (mfunc & ~TI122X_MFUNC1_MASK) | TI122X_MFUNC1_INTB; | |
577 | break; | |
578 | } | |
579 | ||
580 | /* write, probe */ | |
581 | if (mfunc != mfunc_old) { | |
582 | config_writel(socket, TI122X_MFUNC, mfunc); | |
583 | ||
584 | pci_irq_status = yenta_probe_cb_irq(socket); | |
585 | if (pci_irq_status == 1) { | |
dd797d81 DB |
586 | dev_printk(KERN_INFO, &socket->dev->dev, |
587 | "TI: parallel PCI interrupts ok\n"); | |
1da177e4 LT |
588 | goto out; |
589 | } | |
590 | ||
591 | mfunc = mfunc_old; | |
592 | config_writel(socket, TI122X_MFUNC, mfunc); | |
593 | ||
594 | if (pci_irq_status == -1) | |
595 | goto out; | |
596 | } | |
dd797d81 | 597 | |
1da177e4 LT |
598 | /* still nothing: set INTRTIE */ |
599 | if (ti12xx_tie_interrupts(socket, &old_irq)) { | |
600 | pci_irq_status = yenta_probe_cb_irq(socket); | |
601 | if (pci_irq_status == 1) { | |
dd797d81 DB |
602 | dev_printk(KERN_INFO, &socket->dev->dev, |
603 | "TI: parallel PCI interrupts, tied ok\n"); | |
1da177e4 LT |
604 | goto out; |
605 | } | |
606 | ||
607 | ti12xx_untie_interrupts(socket, old_irq); | |
608 | } | |
609 | } | |
610 | ||
611 | out: | |
612 | if (pci_irq_status < 1) { | |
613 | socket->cb_irq = 0; | |
dd797d81 DB |
614 | dev_printk(KERN_INFO, &socket->dev->dev, |
615 | "TI: no PCI interrupts. Fish. Please report.\n"); | |
1da177e4 LT |
616 | } |
617 | } | |
618 | ||
fa912bcb DR |
619 | |
620 | /* Returns true value if the second slot of a two-slot controller is empty */ | |
621 | static int ti12xx_2nd_slot_empty(struct yenta_socket *socket) | |
622 | { | |
623 | struct pci_dev *func; | |
624 | struct yenta_socket *slot2; | |
625 | int devfn; | |
626 | unsigned int state; | |
627 | int ret = 1; | |
6c1a10db | 628 | u32 sysctl; |
fa912bcb DR |
629 | |
630 | /* catch the two-slot controllers */ | |
631 | switch (socket->dev->device) { | |
632 | case PCI_DEVICE_ID_TI_1220: | |
633 | case PCI_DEVICE_ID_TI_1221: | |
634 | case PCI_DEVICE_ID_TI_1225: | |
635 | case PCI_DEVICE_ID_TI_1251A: | |
636 | case PCI_DEVICE_ID_TI_1251B: | |
637 | case PCI_DEVICE_ID_TI_1420: | |
638 | case PCI_DEVICE_ID_TI_1450: | |
639 | case PCI_DEVICE_ID_TI_1451A: | |
640 | case PCI_DEVICE_ID_TI_1520: | |
641 | case PCI_DEVICE_ID_TI_1620: | |
642 | case PCI_DEVICE_ID_TI_4520: | |
643 | case PCI_DEVICE_ID_TI_4450: | |
644 | case PCI_DEVICE_ID_TI_4451: | |
645 | /* | |
646 | * there are way more, but they need to be added in yenta_socket.c | |
647 | * and pci_ids.h first anyway. | |
648 | */ | |
649 | break; | |
650 | ||
59e35ba1 | 651 | case PCI_DEVICE_ID_TI_XX12: |
6c1a10db DR |
652 | case PCI_DEVICE_ID_TI_X515: |
653 | case PCI_DEVICE_ID_TI_X420: | |
654 | case PCI_DEVICE_ID_TI_X620: | |
655 | case PCI_DEVICE_ID_TI_XX21_XX11: | |
656 | case PCI_DEVICE_ID_TI_7410: | |
657 | case PCI_DEVICE_ID_TI_7610: | |
658 | /* | |
659 | * those are either single or dual slot CB with additional functions | |
660 | * like 1394, smartcard reader, etc. check the TIEALL flag for them | |
661 | * the TIEALL flag binds the IRQ of all functions toghether. | |
662 | * we catch the single slot variants later. | |
663 | */ | |
664 | sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL); | |
665 | if (sysctl & TIXX21_SCR_TIEALL) | |
666 | return 0; | |
667 | ||
668 | break; | |
669 | ||
fa912bcb DR |
670 | /* single-slot controllers have the 2nd slot empty always :) */ |
671 | default: | |
672 | return 1; | |
673 | } | |
674 | ||
675 | /* get other slot */ | |
676 | devfn = socket->dev->devfn & ~0x07; | |
677 | func = pci_get_slot(socket->dev->bus, | |
678 | (socket->dev->devfn & 0x07) ? devfn : devfn | 0x01); | |
679 | if (!func) | |
680 | return 1; | |
681 | ||
6c1a10db DR |
682 | /* |
683 | * check that the device id of both slots match. this is needed for the | |
684 | * XX21 and the XX11 controller that share the same device id for single | |
685 | * and dual slot controllers. return '2nd slot empty'. we already checked | |
686 | * if the interrupt is tied to another function. | |
687 | */ | |
688 | if (socket->dev->device != func->device) | |
689 | goto out; | |
690 | ||
fa912bcb DR |
691 | slot2 = pci_get_drvdata(func); |
692 | if (!slot2) | |
693 | goto out; | |
694 | ||
695 | /* check state */ | |
05f43d48 | 696 | yenta_get_status(&slot2->socket, &state); |
fa912bcb DR |
697 | if (state & SS_DETECT) { |
698 | ret = 0; | |
699 | goto out; | |
700 | } | |
701 | ||
702 | out: | |
703 | pci_dev_put(func); | |
704 | return ret; | |
705 | } | |
706 | ||
707 | /* | |
708 | * TI specifiy parts for the power hook. | |
709 | * | |
710 | * some TI's with some CB's produces interrupt storm on power on. it has been | |
711 | * seen with atheros wlan cards on TI1225 and TI1410. solution is simply to | |
712 | * disable any CB interrupts during this time. | |
713 | */ | |
714 | static int ti12xx_power_hook(struct pcmcia_socket *sock, int operation) | |
715 | { | |
716 | struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket); | |
717 | u32 mfunc, devctl, sysctl; | |
718 | u8 gpio3; | |
719 | ||
720 | /* only POWER_PRE and POWER_POST are interesting */ | |
721 | if ((operation != HOOK_POWER_PRE) && (operation != HOOK_POWER_POST)) | |
722 | return 0; | |
723 | ||
724 | devctl = config_readb(socket, TI113X_DEVICE_CONTROL); | |
725 | sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL); | |
726 | mfunc = config_readl(socket, TI122X_MFUNC); | |
727 | ||
728 | /* | |
729 | * all serial/tied: only disable when modparm set. always doing it | |
730 | * would mean a regression for working setups 'cos it disables the | |
731 | * interrupts for both both slots on 2-slot controllers | |
732 | * (and users of single slot controllers where it's save have to | |
733 | * live with setting the modparm, most don't have to anyway) | |
734 | */ | |
735 | if (((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) && | |
736 | (pwr_irqs_off || ti12xx_2nd_slot_empty(socket))) { | |
737 | switch (socket->dev->device) { | |
738 | case PCI_DEVICE_ID_TI_1250: | |
739 | case PCI_DEVICE_ID_TI_1251A: | |
740 | case PCI_DEVICE_ID_TI_1251B: | |
741 | case PCI_DEVICE_ID_TI_1450: | |
742 | case PCI_DEVICE_ID_TI_1451A: | |
743 | case PCI_DEVICE_ID_TI_4450: | |
744 | case PCI_DEVICE_ID_TI_4451: | |
745 | /* these chips have no IRQSER setting in MFUNC3 */ | |
746 | break; | |
747 | ||
748 | default: | |
749 | if (operation == HOOK_POWER_PRE) | |
750 | mfunc = (mfunc & ~TI122X_MFUNC3_MASK); | |
751 | else | |
752 | mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER; | |
753 | } | |
754 | ||
755 | return 0; | |
756 | } | |
757 | ||
758 | /* do the job differently for func0/1 */ | |
759 | if ((PCI_FUNC(socket->dev->devfn) == 0) || | |
760 | ((sysctl & TI122X_SCR_INTRTIE) && | |
761 | (pwr_irqs_off || ti12xx_2nd_slot_empty(socket)))) { | |
762 | /* some bridges are different */ | |
763 | switch (socket->dev->device) { | |
764 | case PCI_DEVICE_ID_TI_1250: | |
765 | case PCI_DEVICE_ID_TI_1251A: | |
766 | case PCI_DEVICE_ID_TI_1251B: | |
767 | case PCI_DEVICE_ID_TI_1450: | |
768 | /* those oldies use gpio3 for INTA */ | |
769 | gpio3 = config_readb(socket, TI1250_GPIO3_CONTROL); | |
770 | if (operation == HOOK_POWER_PRE) | |
771 | gpio3 = (gpio3 & ~TI1250_GPIO_MODE_MASK) | 0x40; | |
772 | else | |
773 | gpio3 &= ~TI1250_GPIO_MODE_MASK; | |
774 | config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3); | |
775 | break; | |
776 | ||
777 | default: | |
778 | /* all new bridges are the same */ | |
779 | if (operation == HOOK_POWER_PRE) | |
780 | mfunc &= ~TI122X_MFUNC0_MASK; | |
781 | else | |
782 | mfunc |= TI122X_MFUNC0_INTA; | |
783 | config_writel(socket, TI122X_MFUNC, mfunc); | |
784 | } | |
785 | } else { | |
786 | switch (socket->dev->device) { | |
787 | case PCI_DEVICE_ID_TI_1251A: | |
788 | case PCI_DEVICE_ID_TI_1251B: | |
789 | case PCI_DEVICE_ID_TI_1450: | |
790 | /* those have INTA elsewhere and INTB in MFUNC0 */ | |
791 | if (operation == HOOK_POWER_PRE) | |
792 | mfunc &= ~TI122X_MFUNC0_MASK; | |
793 | else | |
794 | mfunc |= TI125X_MFUNC0_INTB; | |
795 | config_writel(socket, TI122X_MFUNC, mfunc); | |
796 | ||
797 | break; | |
798 | ||
799 | default: | |
800 | /* all new bridges are the same */ | |
801 | if (operation == HOOK_POWER_PRE) | |
802 | mfunc &= ~TI122X_MFUNC1_MASK; | |
803 | else | |
804 | mfunc |= TI122X_MFUNC1_INTB; | |
805 | config_writel(socket, TI122X_MFUNC, mfunc); | |
806 | } | |
807 | } | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
1da177e4 LT |
812 | static int ti12xx_override(struct yenta_socket *socket) |
813 | { | |
814 | u32 val, val_orig; | |
815 | ||
816 | /* make sure that memory burst is active */ | |
817 | val_orig = val = config_readl(socket, TI113X_SYSTEM_CONTROL); | |
818 | if (disable_clkrun && PCI_FUNC(socket->dev->devfn) == 0) { | |
dd797d81 DB |
819 | dev_printk(KERN_INFO, &socket->dev->dev, |
820 | "Disabling CLKRUN feature\n"); | |
1da177e4 LT |
821 | val |= TI113X_SCR_KEEPCLK; |
822 | } | |
823 | if (!(val & TI122X_SCR_MRBURSTUP)) { | |
dd797d81 DB |
824 | dev_printk(KERN_INFO, &socket->dev->dev, |
825 | "Enabling burst memory read transactions\n"); | |
1da177e4 LT |
826 | val |= TI122X_SCR_MRBURSTUP; |
827 | } | |
828 | if (val_orig != val) | |
829 | config_writel(socket, TI113X_SYSTEM_CONTROL, val); | |
830 | ||
1da177e4 LT |
831 | /* |
832 | * Yenta expects controllers to use CSCINT to route | |
833 | * CSC interrupts to PCI rather than INTVAL. | |
834 | */ | |
835 | val = config_readb(socket, TI1250_DIAGNOSTIC); | |
dd797d81 DB |
836 | dev_printk(KERN_INFO, &socket->dev->dev, |
837 | "Using %s to route CSC interrupts to PCI\n", | |
838 | (val & TI1250_DIAG_PCI_CSC) ? "CSCINT" : "INTVAL"); | |
839 | dev_printk(KERN_INFO, &socket->dev->dev, | |
840 | "Routing CardBus interrupts to %s\n", | |
841 | (val & TI1250_DIAG_PCI_IREQ) ? "PCI" : "ISA"); | |
1da177e4 LT |
842 | |
843 | /* do irqrouting, depending on function */ | |
844 | if (PCI_FUNC(socket->dev->devfn) == 0) | |
845 | ti12xx_irqroute_func0(socket); | |
846 | else | |
847 | ti12xx_irqroute_func1(socket); | |
848 | ||
fa912bcb DR |
849 | /* install power hook */ |
850 | socket->socket.power_hook = ti12xx_power_hook; | |
851 | ||
1da177e4 LT |
852 | return ti_override(socket); |
853 | } | |
854 | ||
855 | ||
856 | static int ti1250_override(struct yenta_socket *socket) | |
857 | { | |
858 | u8 old, diag; | |
859 | ||
860 | old = config_readb(socket, TI1250_DIAGNOSTIC); | |
861 | diag = old & ~(TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ); | |
862 | if (socket->cb_irq) | |
863 | diag |= TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ; | |
864 | ||
865 | if (diag != old) { | |
dd797d81 DB |
866 | dev_printk(KERN_INFO, &socket->dev->dev, |
867 | "adjusting diagnostic: %02x -> %02x\n", | |
868 | old, diag); | |
1da177e4 LT |
869 | config_writeb(socket, TI1250_DIAGNOSTIC, diag); |
870 | } | |
871 | ||
872 | return ti12xx_override(socket); | |
873 | } | |
874 | ||
8c3520d4 DR |
875 | |
876 | /** | |
877 | * EnE specific part. EnE bridges are register compatible with TI bridges but | |
878 | * have their own test registers and more important their own little problems. | |
879 | * Some fixup code to make everybody happy (TM). | |
880 | */ | |
881 | ||
63e7ebd0 | 882 | #ifdef CONFIG_YENTA_ENE_TUNE |
78187865 | 883 | /* |
8c3520d4 DR |
884 | * set/clear various test bits: |
885 | * Defaults to clear the bit. | |
886 | * - mask (u8) defines what bits to change | |
887 | * - bits (u8) is the values to change them to | |
888 | * -> it's | |
889 | * current = (current & ~mask) | bits | |
890 | */ | |
891 | /* pci ids of devices that wants to have the bit set */ | |
892 | #define DEVID(_vend,_dev,_subvend,_subdev,mask,bits) { \ | |
893 | .vendor = _vend, \ | |
894 | .device = _dev, \ | |
895 | .subvendor = _subvend, \ | |
896 | .subdevice = _subdev, \ | |
897 | .driver_data = ((mask) << 8 | (bits)), \ | |
898 | } | |
899 | static struct pci_device_id ene_tune_tbl[] = { | |
900 | /* Echo Audio products based on motorola DSP56301 and DSP56361 */ | |
901 | DEVID(PCI_VENDOR_ID_MOTOROLA, 0x1801, 0xECC0, PCI_ANY_ID, | |
902 | ENE_TEST_C9_TLTENABLE | ENE_TEST_C9_PFENABLE, ENE_TEST_C9_TLTENABLE), | |
903 | DEVID(PCI_VENDOR_ID_MOTOROLA, 0x3410, 0xECC0, PCI_ANY_ID, | |
904 | ENE_TEST_C9_TLTENABLE | ENE_TEST_C9_PFENABLE, ENE_TEST_C9_TLTENABLE), | |
905 | ||
906 | {} | |
907 | }; | |
908 | ||
909 | static void ene_tune_bridge(struct pcmcia_socket *sock, struct pci_bus *bus) | |
910 | { | |
911 | struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket); | |
912 | struct pci_dev *dev; | |
913 | struct pci_device_id *id = NULL; | |
914 | u8 test_c9, old_c9, mask, bits; | |
915 | ||
916 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
917 | id = (struct pci_device_id *) pci_match_id(ene_tune_tbl, dev); | |
918 | if (id) | |
919 | break; | |
920 | } | |
921 | ||
922 | test_c9 = old_c9 = config_readb(socket, ENE_TEST_C9); | |
923 | if (id) { | |
924 | mask = (id->driver_data >> 8) & 0xFF; | |
925 | bits = id->driver_data & 0xFF; | |
926 | ||
927 | test_c9 = (test_c9 & ~mask) | bits; | |
928 | } | |
929 | else | |
930 | /* default to clear TLTEnable bit, old behaviour */ | |
931 | test_c9 &= ~ENE_TEST_C9_TLTENABLE; | |
932 | ||
dd797d81 DB |
933 | dev_printk(KERN_INFO, &socket->dev->dev, |
934 | "EnE: chaning testregister 0xC9, %02x -> %02x\n", | |
935 | old_c9, test_c9); | |
8c3520d4 DR |
936 | config_writeb(socket, ENE_TEST_C9, test_c9); |
937 | } | |
938 | ||
8c3520d4 DR |
939 | static int ene_override(struct yenta_socket *socket) |
940 | { | |
941 | /* install tune_bridge() function */ | |
942 | socket->socket.tune_bridge = ene_tune_bridge; | |
943 | ||
944 | return ti1250_override(socket); | |
945 | } | |
c2059b2e DV |
946 | #else |
947 | # define ene_override ti1250_override | |
63e7ebd0 | 948 | #endif /* !CONFIG_YENTA_ENE_TUNE */ |
8c3520d4 | 949 | |
1da177e4 LT |
950 | #endif /* _LINUX_TI113X_H */ |
951 |