Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /*====================================================================== |
2 | ||
3 | Device driver for the PCMCIA control functionality of PXA2xx | |
4 | microprocessors. | |
5 | ||
6 | The contents of this file may be used under the | |
7 | terms of the GNU Public License version 2 (the "GPL") | |
8 | ||
9 | (c) Ian Molton (spyro@f2s.com) 2003 | |
10 | (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4 | |
11 | ||
12 | derived from sa11xx_base.c | |
13 | ||
14 | Portions created by John G. Dorsey are | |
15 | Copyright (C) 1999 John G. Dorsey. | |
16 | ||
17 | ======================================================================*/ | |
18 | ||
19 | #include <linux/module.h> | |
5a0e3ad6 | 20 | #include <linux/slab.h> |
1da177e4 | 21 | #include <linux/init.h> |
1da177e4 LT |
22 | #include <linux/cpufreq.h> |
23 | #include <linux/ioport.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/spinlock.h> | |
d052d1be | 26 | #include <linux/platform_device.h> |
1da177e4 | 27 | |
a09e64fb | 28 | #include <mach/hardware.h> |
ad68bb9f | 29 | #include <mach/smemc.h> |
1da177e4 LT |
30 | #include <asm/io.h> |
31 | #include <asm/irq.h> | |
32 | #include <asm/system.h> | |
a09e64fb | 33 | #include <mach/pxa2xx-regs.h> |
20f18ff3 | 34 | #include <asm/mach-types.h> |
1da177e4 | 35 | |
1da177e4 | 36 | #include <pcmcia/ss.h> |
1da177e4 LT |
37 | #include <pcmcia/cistpl.h> |
38 | ||
1da177e4 LT |
39 | #include "soc_common.h" |
40 | #include "pxa2xx_base.h" | |
41 | ||
b393c696 EM |
42 | /* |
43 | * Personal Computer Memory Card International Association (PCMCIA) sockets | |
44 | */ | |
45 | ||
46 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ | |
47 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ | |
48 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ | |
49 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ | |
50 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ | |
51 | ||
52 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ | |
53 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ | |
54 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ | |
55 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ | |
56 | ||
57 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ | |
58 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ | |
59 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ | |
60 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ | |
61 | ||
62 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ | |
63 | (0x20000000 + (Nb) * PCMCIASp) | |
64 | #define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */ | |
65 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ | |
66 | (_PCMCIA(Nb) + 2 * PCMCIAPrtSp) | |
67 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ | |
68 | (_PCMCIA(Nb) + 3 * PCMCIAPrtSp) | |
69 | ||
70 | #define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */ | |
71 | #define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */ | |
72 | #define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */ | |
73 | #define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */ | |
74 | ||
75 | #define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */ | |
76 | #define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */ | |
77 | #define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */ | |
78 | #define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */ | |
79 | ||
1da177e4 LT |
80 | |
81 | #define MCXX_SETUP_MASK (0x7f) | |
82 | #define MCXX_ASST_MASK (0x1f) | |
83 | #define MCXX_HOLD_MASK (0x3f) | |
84 | #define MCXX_SETUP_SHIFT (0) | |
85 | #define MCXX_ASST_SHIFT (7) | |
86 | #define MCXX_HOLD_SHIFT (14) | |
87 | ||
88 | static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns, | |
89 | u_int mem_clk_10khz) | |
90 | { | |
91 | u_int code = pcmcia_cycle_ns * mem_clk_10khz; | |
92 | return (code / 300000) + ((code % 300000) ? 1 : 0) - 1; | |
93 | } | |
94 | ||
95 | static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns, | |
96 | u_int mem_clk_10khz) | |
97 | { | |
98 | u_int code = pcmcia_cycle_ns * mem_clk_10khz; | |
24d6572b | 99 | return (code / 300000) + ((code % 300000) ? 1 : 0) + 1; |
1da177e4 LT |
100 | } |
101 | ||
102 | static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns, | |
103 | u_int mem_clk_10khz) | |
104 | { | |
105 | u_int code = pcmcia_cycle_ns * mem_clk_10khz; | |
106 | return (code / 100000) + ((code % 100000) ? 1 : 0) - 1; | |
107 | } | |
108 | ||
109 | /* This function returns the (approximate) command assertion period, in | |
110 | * nanoseconds, for a given CPU clock frequency and MCXX_ASST value: | |
111 | */ | |
112 | static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz, | |
113 | u_int pcmcia_mcxx_asst) | |
114 | { | |
115 | return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz); | |
116 | } | |
117 | ||
118 | static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock ) | |
119 | { | |
ad68bb9f MV |
120 | uint32_t val; |
121 | ||
122 | val = ((pxa2xx_mcxx_setup(speed, clock) | |
1da177e4 LT |
123 | & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) |
124 | | ((pxa2xx_mcxx_asst(speed, clock) | |
125 | & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) | |
126 | | ((pxa2xx_mcxx_hold(speed, clock) | |
127 | & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); | |
128 | ||
ad68bb9f MV |
129 | __raw_writel(val, MCMEM(sock)); |
130 | ||
1da177e4 LT |
131 | return 0; |
132 | } | |
133 | ||
134 | static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock ) | |
135 | { | |
ad68bb9f MV |
136 | uint32_t val; |
137 | ||
138 | val = ((pxa2xx_mcxx_setup(speed, clock) | |
1da177e4 LT |
139 | & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) |
140 | | ((pxa2xx_mcxx_asst(speed, clock) | |
141 | & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) | |
142 | | ((pxa2xx_mcxx_hold(speed, clock) | |
143 | & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); | |
144 | ||
ad68bb9f MV |
145 | __raw_writel(val, MCIO(sock)); |
146 | ||
1da177e4 LT |
147 | return 0; |
148 | } | |
149 | ||
150 | static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock ) | |
151 | { | |
ad68bb9f MV |
152 | uint32_t val; |
153 | ||
154 | val = ((pxa2xx_mcxx_setup(speed, clock) | |
1da177e4 LT |
155 | & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT) |
156 | | ((pxa2xx_mcxx_asst(speed, clock) | |
157 | & MCXX_ASST_MASK) << MCXX_ASST_SHIFT) | |
158 | | ((pxa2xx_mcxx_hold(speed, clock) | |
159 | & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT); | |
160 | ||
ad68bb9f MV |
161 | __raw_writel(val, MCATT(sock)); |
162 | ||
1da177e4 LT |
163 | return 0; |
164 | } | |
165 | ||
166 | static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk) | |
167 | { | |
168 | struct soc_pcmcia_timing timing; | |
169 | int sock = skt->nr; | |
170 | ||
171 | soc_common_pcmcia_get_timing(skt, &timing); | |
172 | ||
173 | pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk); | |
174 | pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk); | |
175 | pxa2xx_pcmcia_set_mcio(sock, timing.io, clk); | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
180 | static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt) | |
181 | { | |
182 | unsigned int clk = get_memclk_frequency_10khz(); | |
183 | return pxa2xx_pcmcia_set_mcxx(skt, clk); | |
184 | } | |
185 | ||
186 | #ifdef CONFIG_CPU_FREQ | |
187 | ||
188 | static int | |
189 | pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt, | |
190 | unsigned long val, | |
191 | struct cpufreq_freqs *freqs) | |
192 | { | |
1da177e4 LT |
193 | switch (val) { |
194 | case CPUFREQ_PRECHANGE: | |
195 | if (freqs->new > freqs->old) { | |
196 | debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, " | |
197 | "pre-updating\n", | |
198 | freqs->new / 1000, (freqs->new / 100) % 10, | |
199 | freqs->old / 1000, (freqs->old / 100) % 10); | |
d344a21a | 200 | pxa2xx_pcmcia_set_timing(skt); |
1da177e4 LT |
201 | } |
202 | break; | |
203 | ||
204 | case CPUFREQ_POSTCHANGE: | |
205 | if (freqs->new < freqs->old) { | |
206 | debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, " | |
207 | "post-updating\n", | |
208 | freqs->new / 1000, (freqs->new / 100) % 10, | |
209 | freqs->old / 1000, (freqs->old / 100) % 10); | |
d344a21a | 210 | pxa2xx_pcmcia_set_timing(skt); |
1da177e4 LT |
211 | } |
212 | break; | |
213 | } | |
214 | return 0; | |
215 | } | |
216 | #endif | |
217 | ||
20f18ff3 MZ |
218 | static void pxa2xx_configure_sockets(struct device *dev) |
219 | { | |
220 | struct pcmcia_low_level *ops = dev->platform_data; | |
20f18ff3 MZ |
221 | /* |
222 | * We have at least one socket, so set MECR:CIT | |
223 | * (Card Is There) | |
224 | */ | |
ad68bb9f | 225 | uint32_t mecr = MECR_CIT; |
20f18ff3 MZ |
226 | |
227 | /* Set MECR:NOS (Number Of Sockets) */ | |
c2de1c38 MZ |
228 | if ((ops->first + ops->nr) > 1 || |
229 | machine_is_viper() || machine_is_arcom_zeus()) | |
ad68bb9f MV |
230 | mecr |= MECR_NOS; |
231 | ||
232 | __raw_writel(mecr, MECR); | |
20f18ff3 MZ |
233 | } |
234 | ||
b393c696 EM |
235 | static const char *skt_names[] = { |
236 | "PCMCIA socket 0", | |
237 | "PCMCIA socket 1", | |
238 | }; | |
239 | ||
240 | #define SKT_DEV_INFO_SIZE(n) \ | |
241 | (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket)) | |
242 | ||
701a5dc0 | 243 | int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt) |
da4f0073 RKAL |
244 | { |
245 | skt->res_skt.start = _PCMCIA(skt->nr); | |
246 | skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1; | |
247 | skt->res_skt.name = skt_names[skt->nr]; | |
248 | skt->res_skt.flags = IORESOURCE_MEM; | |
249 | ||
250 | skt->res_io.start = _PCMCIAIO(skt->nr); | |
251 | skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1; | |
252 | skt->res_io.name = "io"; | |
253 | skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
254 | ||
255 | skt->res_mem.start = _PCMCIAMem(skt->nr); | |
256 | skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1; | |
257 | skt->res_mem.name = "memory"; | |
258 | skt->res_mem.flags = IORESOURCE_MEM; | |
259 | ||
260 | skt->res_attr.start = _PCMCIAAttr(skt->nr); | |
261 | skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1; | |
262 | skt->res_attr.name = "attribute"; | |
263 | skt->res_attr.flags = IORESOURCE_MEM; | |
264 | ||
265 | return soc_pcmcia_add_one(skt); | |
266 | } | |
d0d26c33 | 267 | EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one); |
da4f0073 | 268 | |
701a5dc0 RKAL |
269 | void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops) |
270 | { | |
271 | /* Provide our PXA2xx specific timing routines. */ | |
272 | ops->set_timing = pxa2xx_pcmcia_set_timing; | |
273 | #ifdef CONFIG_CPU_FREQ | |
274 | ops->frequency_change = pxa2xx_pcmcia_frequency_change; | |
275 | #endif | |
276 | } | |
d0d26c33 | 277 | EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops); |
701a5dc0 | 278 | |
d0d26c33 | 279 | static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev) |
1da177e4 | 280 | { |
701a5dc0 | 281 | int i, ret = 0; |
1da177e4 | 282 | struct pcmcia_low_level *ops; |
b393c696 EM |
283 | struct skt_dev_info *sinfo; |
284 | struct soc_pcmcia_socket *skt; | |
1da177e4 | 285 | |
d0d26c33 RK |
286 | ops = (struct pcmcia_low_level *)dev->dev.platform_data; |
287 | if (!ops) | |
1da177e4 LT |
288 | return -ENODEV; |
289 | ||
701a5dc0 | 290 | pxa2xx_drv_pcmcia_ops(ops); |
da4f0073 | 291 | |
b393c696 EM |
292 | sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL); |
293 | if (!sinfo) | |
294 | return -ENOMEM; | |
295 | ||
296 | sinfo->nskt = ops->nr; | |
297 | ||
298 | /* Initialize processor specific parameters */ | |
299 | for (i = 0; i < ops->nr; i++) { | |
300 | skt = &sinfo->skt[i]; | |
301 | ||
da4f0073 | 302 | skt->nr = ops->first + i; |
da4f0073 RKAL |
303 | skt->ops = ops; |
304 | skt->socket.owner = ops->owner; | |
a7a5ac58 | 305 | skt->socket.dev.parent = &dev->dev; |
66024db5 | 306 | skt->socket.pci_irq = NO_IRQ; |
b393c696 | 307 | |
da4f0073 RKAL |
308 | ret = pxa2xx_drv_pcmcia_add_one(skt); |
309 | if (ret) | |
310 | break; | |
b393c696 EM |
311 | } |
312 | ||
da4f0073 RKAL |
313 | if (ret) { |
314 | while (--i >= 0) | |
315 | soc_pcmcia_remove_one(&sinfo->skt[i]); | |
316 | kfree(sinfo); | |
317 | } else { | |
a7a5ac58 MZ |
318 | pxa2xx_configure_sockets(&dev->dev); |
319 | dev_set_drvdata(&dev->dev, sinfo); | |
da4f0073 | 320 | } |
1da177e4 LT |
321 | |
322 | return ret; | |
323 | } | |
9468613b RK |
324 | |
325 | static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev) | |
326 | { | |
be85458e RKAL |
327 | struct skt_dev_info *sinfo = platform_get_drvdata(dev); |
328 | int i; | |
329 | ||
330 | platform_set_drvdata(dev, NULL); | |
331 | ||
332 | for (i = 0; i < sinfo->nskt; i++) | |
333 | soc_pcmcia_remove_one(&sinfo->skt[i]); | |
334 | ||
335 | kfree(sinfo); | |
336 | return 0; | |
9468613b RK |
337 | } |
338 | ||
85c61021 | 339 | static int pxa2xx_drv_pcmcia_resume(struct device *dev) |
1da177e4 | 340 | { |
85c61021 | 341 | pxa2xx_configure_sockets(dev); |
d7646f76 | 342 | return 0; |
1da177e4 LT |
343 | } |
344 | ||
47145210 | 345 | static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = { |
85c61021 MR |
346 | .resume = pxa2xx_drv_pcmcia_resume, |
347 | }; | |
348 | ||
9468613b | 349 | static struct platform_driver pxa2xx_pcmcia_driver = { |
1da177e4 | 350 | .probe = pxa2xx_drv_pcmcia_probe, |
9468613b | 351 | .remove = pxa2xx_drv_pcmcia_remove, |
9468613b RK |
352 | .driver = { |
353 | .name = "pxa2xx-pcmcia", | |
12c2c019 | 354 | .owner = THIS_MODULE, |
85c61021 | 355 | .pm = &pxa2xx_drv_pcmcia_pm_ops, |
9468613b | 356 | }, |
1da177e4 LT |
357 | }; |
358 | ||
359 | static int __init pxa2xx_pcmcia_init(void) | |
360 | { | |
9468613b | 361 | return platform_driver_register(&pxa2xx_pcmcia_driver); |
1da177e4 LT |
362 | } |
363 | ||
364 | static void __exit pxa2xx_pcmcia_exit(void) | |
365 | { | |
9468613b | 366 | platform_driver_unregister(&pxa2xx_pcmcia_driver); |
1da177e4 LT |
367 | } |
368 | ||
f36598ae | 369 | fs_initcall(pxa2xx_pcmcia_init); |
1da177e4 LT |
370 | module_exit(pxa2xx_pcmcia_exit); |
371 | ||
372 | MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>"); | |
373 | MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver"); | |
374 | MODULE_LICENSE("GPL"); | |
12c2c019 | 375 | MODULE_ALIAS("platform:pxa2xx-pcmcia"); |