[linux-2.6-block.git] / drivers / pcmcia / pxa2xx_base.c

// SPDX-License-Identifier: GPL-2.0-only
/*======================================================================

  Device driver for the PCMCIA control functionality of PXA2xx
  microprocessors.


    (c) Ian Molton (spyro@f2s.com) 2003
    (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4

    derived from sa11xx_base.c

     Portions created by John G. Dorsey are
     Copyright (C) 1999 John G. Dorsey.

  ======================================================================*/

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>

#include <mach/hardware.h>
#include <mach/smemc.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <mach/pxa2xx-regs.h>
#include <asm/mach-types.h>

#include <pcmcia/ss.h>
#include <pcmcia/cistpl.h>

#include "soc_common.h"
#include "pxa2xx_base.h"

/*
 * Personal Computer Memory Card International Association (PCMCIA) sockets
 */

#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]         */
#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]      */

#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]           */
#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]       */
#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */

#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]           */
#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]       */
#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */

#define _PCMCIA(Nb)			/* PCMCIA [0..1]                   */ \
			(0x20000000 + (Nb) * PCMCIASp)
#define _PCMCIAIO(Nb)	_PCMCIA(Nb)	/* PCMCIA I/O [0..1]               */
#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]         */ \
			(_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]            */ \
			(_PCMCIA(Nb) + 3 * PCMCIAPrtSp)

#define _PCMCIA0	_PCMCIA(0)	/* PCMCIA 0                        */
#define _PCMCIA0IO	_PCMCIAIO(0)	/* PCMCIA 0 I/O                    */
#define _PCMCIA0Attr	_PCMCIAAttr(0)	/* PCMCIA 0 Attribute              */
#define _PCMCIA0Mem	_PCMCIAMem(0)	/* PCMCIA 0 Memory                 */

#define _PCMCIA1	_PCMCIA(1)	/* PCMCIA 1                        */
#define _PCMCIA1IO	_PCMCIAIO(1)	/* PCMCIA 1 I/O                    */
#define _PCMCIA1Attr	_PCMCIAAttr(1)	/* PCMCIA 1 Attribute              */
#define _PCMCIA1Mem	_PCMCIAMem(1)	/* PCMCIA 1 Memory                 */


#define MCXX_SETUP_MASK     (0x7f)
#define MCXX_ASST_MASK      (0x1f)
#define MCXX_HOLD_MASK      (0x3f)
#define MCXX_SETUP_SHIFT    (0)
#define MCXX_ASST_SHIFT     (7)
#define MCXX_HOLD_SHIFT     (14)

static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
				     u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
}

static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
				     u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
}

static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
				      u_int mem_clk_10khz)
{
	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
}

/* This function returns the (approximate) command assertion period, in
 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
 */
static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
					   u_int pcmcia_mcxx_asst)
{
	return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
}

static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
{
	uint32_t val;

	val = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	__raw_writel(val, MCMEM(sock));

	return 0;
}

static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
{
	uint32_t val;

	val = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	__raw_writel(val, MCIO(sock));

	return 0;
}

static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
{
	uint32_t val;

	val = ((pxa2xx_mcxx_setup(speed, clock)
		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
		| ((pxa2xx_mcxx_asst(speed, clock)
		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
		| ((pxa2xx_mcxx_hold(speed, clock)
		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);

	__raw_writel(val, MCATT(sock));

	return 0;
}

static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
{
	struct soc_pcmcia_timing timing;
	int sock = skt->nr;

	soc_common_pcmcia_get_timing(skt, &timing);

	pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
	pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
	pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);

	return 0;
}

static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
{
	unsigned long clk = clk_get_rate(skt->clk);
	return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000);
}

#ifdef CONFIG_CPU_FREQ

static int
pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
			       unsigned long val,
			       struct cpufreq_freqs *freqs)
{
	switch (val) {
	case CPUFREQ_PRECHANGE:
		if (freqs->new > freqs->old) {
			debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
			       "pre-updating\n",
			       freqs->new / 1000, (freqs->new / 100) % 10,
			       freqs->old / 1000, (freqs->old / 100) % 10);
			pxa2xx_pcmcia_set_timing(skt);
		}
		break;

	case CPUFREQ_POSTCHANGE:
		if (freqs->new < freqs->old) {
			debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
			       "post-updating\n",
			       freqs->new / 1000, (freqs->new / 100) % 10,
			       freqs->old / 1000, (freqs->old / 100) % 10);
			pxa2xx_pcmcia_set_timing(skt);
		}
		break;
	}
	return 0;
}
#endif

void pxa2xx_configure_sockets(struct device *dev, struct pcmcia_low_level *ops)
{
	/*
	 * We have at least one socket, so set MECR:CIT
	 * (Card Is There)
	 */
	uint32_t mecr = MECR_CIT;

	/* Set MECR:NOS (Number Of Sockets) */
	if ((ops->first + ops->nr) > 1 ||
	    machine_is_viper() || machine_is_arcom_zeus())
		mecr |= MECR_NOS;

	__raw_writel(mecr, MECR);
}
EXPORT_SYMBOL(pxa2xx_configure_sockets);

static const char *skt_names[] = {
	"PCMCIA socket 0",
	"PCMCIA socket 1",
};

#define SKT_DEV_INFO_SIZE(n) \
	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))

int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
{
	skt->res_skt.start = _PCMCIA(skt->nr);
	skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
	skt->res_skt.name = skt_names[skt->nr];
	skt->res_skt.flags = IORESOURCE_MEM;

	skt->res_io.start = _PCMCIAIO(skt->nr);
	skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
	skt->res_io.name = "io";
	skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;

	skt->res_mem.start = _PCMCIAMem(skt->nr);
	skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
	skt->res_mem.name = "memory";
	skt->res_mem.flags = IORESOURCE_MEM;

	skt->res_attr.start = _PCMCIAAttr(skt->nr);
	skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
	skt->res_attr.name = "attribute";
	skt->res_attr.flags = IORESOURCE_MEM;

	return soc_pcmcia_add_one(skt);
}
EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);

void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
{
	/* Provide our PXA2xx specific timing routines. */
	ops->set_timing  = pxa2xx_pcmcia_set_timing;
#ifdef CONFIG_CPU_FREQ
	ops->frequency_change = pxa2xx_pcmcia_frequency_change;
#endif
}
EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);

static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
{
	int i, ret = 0;
	struct pcmcia_low_level *ops;
	struct skt_dev_info *sinfo;
	struct soc_pcmcia_socket *skt;
	struct clk *clk;

	ops = (struct pcmcia_low_level *)dev->dev.platform_data;
	if (!ops) {
		ret = -ENODEV;
		goto err0;
	}

	if (cpu_is_pxa320() && ops->nr > 1) {
		dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
		ret = -EINVAL;
		goto err0;
	}

	clk = devm_clk_get(&dev->dev, NULL);
	if (IS_ERR(clk))
		return -ENODEV;

	pxa2xx_drv_pcmcia_ops(ops);

	sinfo = devm_kzalloc(&dev->dev, SKT_DEV_INFO_SIZE(ops->nr),
			     GFP_KERNEL);
	if (!sinfo)
		return -ENOMEM;

	sinfo->nskt = ops->nr;

	/* Initialize processor specific parameters */
	for (i = 0; i < ops->nr; i++) {
		skt = &sinfo->skt[i];

		skt->nr = ops->first + i;
		skt->clk = clk;
		soc_pcmcia_init_one(skt, ops, &dev->dev);

		ret = pxa2xx_drv_pcmcia_add_one(skt);
		if (ret)
			goto err1;
	}

	pxa2xx_configure_sockets(&dev->dev, ops);
	dev_set_drvdata(&dev->dev, sinfo);

	return 0;

err1:
	while (--i >= 0)
		soc_pcmcia_remove_one(&sinfo->skt[i]);

err0:
	return ret;
}

static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
{
	struct skt_dev_info *sinfo = platform_get_drvdata(dev);
	int i;

	for (i = 0; i < sinfo->nskt; i++)
		soc_pcmcia_remove_one(&sinfo->skt[i]);

	return 0;
}

static int pxa2xx_drv_pcmcia_resume(struct device *dev)
{
	struct pcmcia_low_level *ops = (struct pcmcia_low_level *)dev->platform_data;

	pxa2xx_configure_sockets(dev, ops);
	return 0;
}

static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
	.resume		= pxa2xx_drv_pcmcia_resume,
};

static struct platform_driver pxa2xx_pcmcia_driver = {
	.probe		= pxa2xx_drv_pcmcia_probe,
	.remove		= pxa2xx_drv_pcmcia_remove,
	.driver		= {
		.name	= "pxa2xx-pcmcia",
		.pm	= &pxa2xx_drv_pcmcia_pm_ops,
	},
};

static int __init pxa2xx_pcmcia_init(void)
{
	return platform_driver_register(&pxa2xx_pcmcia_driver);
}

static void __exit pxa2xx_pcmcia_exit(void)
{
	platform_driver_unregister(&pxa2xx_pcmcia_driver);
}

fs_initcall(pxa2xx_pcmcia_init);
module_exit(pxa2xx_pcmcia_exit);

MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa2xx-pcmcia");
Commit	Line	Data
f7be8ec1	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4 LT	2	/*======================================================================
	3
	4	Device driver for the PCMCIA control functionality of PXA2xx
	5	microprocessors.
	6
1da177e4 LT	7
	8	(c) Ian Molton (spyro@f2s.com) 2003
	9	(c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
	10
	11	derived from sa11xx_base.c
	12
	13	Portions created by John G. Dorsey are
	14	Copyright (C) 1999 John G. Dorsey.
	15
	16	======================================================================*/
	17
	18	#include <linux/module.h>
5a0e3ad6	19	#include <linux/slab.h>
1da177e4	20	#include <linux/init.h>
1da177e4 LT	21	#include <linux/cpufreq.h>
	22	#include <linux/ioport.h>
	23	#include <linux/kernel.h>
	24	#include <linux/spinlock.h>
d052d1be	25	#include <linux/platform_device.h>
1da177e4	26
a09e64fb	27	#include <mach/hardware.h>
ad68bb9f	28	#include <mach/smemc.h>
1da177e4 LT	29	#include <asm/io.h>
1da177e4 LT	30	#include <asm/irq.h>
a09e64fb	31	#include <mach/pxa2xx-regs.h>
20f18ff3	32	#include <asm/mach-types.h>
1da177e4	33
1da177e4	34	#include <pcmcia/ss.h>
1da177e4 LT	35	#include <pcmcia/cistpl.h>
1da177e4 LT	36
1da177e4 LT	37	#include "soc_common.h"
	38	#include "pxa2xx_base.h"
	39
b393c696 EM	40	/*
	41	* Personal Computer Memory Card International Association (PCMCIA) sockets
	42	*/
	43
	44	#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
	45	#define PCMCIASp (4PCMCIAPrtSp) / PCMCIA Space [byte] */
	46	#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
	47	#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
	48	#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
	49
	50	#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
	51	#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
	52	#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
	53	#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
	54
	55	#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
	56	#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
	57	#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
	58	#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
	59
	60	#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
	61	(0x20000000 + (Nb) * PCMCIASp)
	62	#define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
	63	#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
	64	(_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
	65	#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
	66	(_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
	67
	68	#define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
	69	#define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
	70	#define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
	71	#define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
	72
	73	#define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
	74	#define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
	75	#define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
	76	#define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
	77
1da177e4 LT	78
	79	#define MCXX_SETUP_MASK (0x7f)
	80	#define MCXX_ASST_MASK (0x1f)
	81	#define MCXX_HOLD_MASK (0x3f)
	82	#define MCXX_SETUP_SHIFT (0)
	83	#define MCXX_ASST_SHIFT (7)
	84	#define MCXX_HOLD_SHIFT (14)
	85
	86	static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
	87	u_int mem_clk_10khz)
	88	{
	89	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	90	return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
	91	}
	92
	93	static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
	94	u_int mem_clk_10khz)
	95	{
	96	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
24d6572b	97	return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
1da177e4 LT	98	}
	99
	100	static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
	101	u_int mem_clk_10khz)
	102	{
	103	u_int code = pcmcia_cycle_ns * mem_clk_10khz;
	104	return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
	105	}
	106
	107	/* This function returns the (approximate) command assertion period, in
	108	* nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
	109	*/
	110	static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
	111	u_int pcmcia_mcxx_asst)
	112	{
	113	return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
	114	}
	115
	116	static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
	117	{
ad68bb9f MV	118	uint32_t val;
	119
	120	val = ((pxa2xx_mcxx_setup(speed, clock)
1da177e4 LT	121	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	122	\| ((pxa2xx_mcxx_asst(speed, clock)
	123	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	124	\| ((pxa2xx_mcxx_hold(speed, clock)
	125	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	126
ad68bb9f MV	127	__raw_writel(val, MCMEM(sock));
ad68bb9f MV	128
1da177e4 LT	129	return 0;
	130	}
	131
	132	static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
	133	{
ad68bb9f MV	134	uint32_t val;
	135
	136	val = ((pxa2xx_mcxx_setup(speed, clock)
1da177e4 LT	137	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	138	\| ((pxa2xx_mcxx_asst(speed, clock)
	139	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	140	\| ((pxa2xx_mcxx_hold(speed, clock)
	141	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	142
ad68bb9f MV	143	__raw_writel(val, MCIO(sock));
ad68bb9f MV	144
1da177e4 LT	145	return 0;
	146	}
	147
	148	static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
	149	{
ad68bb9f MV	150	uint32_t val;
	151
	152	val = ((pxa2xx_mcxx_setup(speed, clock)
1da177e4 LT	153	& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
	154	\| ((pxa2xx_mcxx_asst(speed, clock)
	155	& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
	156	\| ((pxa2xx_mcxx_hold(speed, clock)
	157	& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
	158
ad68bb9f MV	159	__raw_writel(val, MCATT(sock));
ad68bb9f MV	160
1da177e4 LT	161	return 0;
	162	}
	163
	164	static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
	165	{
	166	struct soc_pcmcia_timing timing;
	167	int sock = skt->nr;
	168
	169	soc_common_pcmcia_get_timing(skt, &timing);
	170
	171	pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
	172	pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
	173	pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
	174
	175	return 0;
	176	}
	177
	178	static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
	179	{
2a125dd5 EM	180	unsigned long clk = clk_get_rate(skt->clk);
2a125dd5 EM	181	return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000);
1da177e4 LT	182	}
	183
	184	#ifdef CONFIG_CPU_FREQ
	185
	186	static int
	187	pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
	188	unsigned long val,
	189	struct cpufreq_freqs *freqs)
	190	{
1da177e4 LT	191	switch (val) {
	192	case CPUFREQ_PRECHANGE:
	193	if (freqs->new > freqs->old) {
	194	debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
	195	"pre-updating\n",
	196	freqs->new / 1000, (freqs->new / 100) % 10,
	197	freqs->old / 1000, (freqs->old / 100) % 10);
d344a21a	198	pxa2xx_pcmcia_set_timing(skt);
1da177e4 LT	199	}
	200	break;
	201
	202	case CPUFREQ_POSTCHANGE:
	203	if (freqs->new < freqs->old) {
	204	debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
	205	"post-updating\n",
	206	freqs->new / 1000, (freqs->new / 100) % 10,
	207	freqs->old / 1000, (freqs->old / 100) % 10);
d344a21a	208	pxa2xx_pcmcia_set_timing(skt);
1da177e4 LT	209	}
	210	break;
	211	}
	212	return 0;
	213	}
	214	#endif
	215
817ed574	216	void pxa2xx_configure_sockets(struct device dev, struct pcmcia_low_level ops)
20f18ff3	217	{
20f18ff3 MZ	218	/*
	219	* We have at least one socket, so set MECR:CIT
	220	* (Card Is There)
	221	*/
ad68bb9f	222	uint32_t mecr = MECR_CIT;
20f18ff3 MZ	223
20f18ff3 MZ	224	/* Set MECR:NOS (Number Of Sockets) */
c2de1c38 MZ	225	if ((ops->first + ops->nr) > 1 \|\|
c2de1c38 MZ	226	machine_is_viper() \|\| machine_is_arcom_zeus())
ad68bb9f MV	227	mecr \|= MECR_NOS;
	228
	229	__raw_writel(mecr, MECR);
20f18ff3	230	}
d5240dfd	231	EXPORT_SYMBOL(pxa2xx_configure_sockets);
20f18ff3	232
b393c696 EM	233	static const char *skt_names[] = {
	234	"PCMCIA socket 0",
	235	"PCMCIA socket 1",
	236	};
	237
	238	#define SKT_DEV_INFO_SIZE(n) \
	239	(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
	240
701a5dc0	241	int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
da4f0073 RKAL	242	{
	243	skt->res_skt.start = _PCMCIA(skt->nr);
	244	skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
	245	skt->res_skt.name = skt_names[skt->nr];
	246	skt->res_skt.flags = IORESOURCE_MEM;
	247
	248	skt->res_io.start = _PCMCIAIO(skt->nr);
	249	skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
	250	skt->res_io.name = "io";
	251	skt->res_io.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
	252
	253	skt->res_mem.start = _PCMCIAMem(skt->nr);
	254	skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
	255	skt->res_mem.name = "memory";
	256	skt->res_mem.flags = IORESOURCE_MEM;
	257
	258	skt->res_attr.start = _PCMCIAAttr(skt->nr);
	259	skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
	260	skt->res_attr.name = "attribute";
	261	skt->res_attr.flags = IORESOURCE_MEM;
	262
	263	return soc_pcmcia_add_one(skt);
	264	}
d0d26c33	265	EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
da4f0073	266
701a5dc0 RKAL	267	void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
	268	{
	269	/* Provide our PXA2xx specific timing routines. */
	270	ops->set_timing = pxa2xx_pcmcia_set_timing;
	271	#ifdef CONFIG_CPU_FREQ
	272	ops->frequency_change = pxa2xx_pcmcia_frequency_change;
	273	#endif
	274	}
d0d26c33	275	EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
701a5dc0	276
d0d26c33	277	static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
1da177e4	278	{
701a5dc0	279	int i, ret = 0;
1da177e4	280	struct pcmcia_low_level *ops;
b393c696 EM	281	struct skt_dev_info *sinfo;
b393c696 EM	282	struct soc_pcmcia_socket *skt;
2a125dd5	283	struct clk *clk;
1da177e4	284
d0d26c33	285	ops = (struct pcmcia_low_level *)dev->dev.platform_data;
a4257af5 MV	286	if (!ops) {
	287	ret = -ENODEV;
	288	goto err0;
	289	}
	290
	291	if (cpu_is_pxa320() && ops->nr > 1) {
	292	dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
	293	ret = -EINVAL;
	294	goto err0;
	295	}
1da177e4	296
ac92f151	297	clk = devm_clk_get(&dev->dev, NULL);
e09a7164	298	if (IS_ERR(clk))
2a125dd5 EM	299	return -ENODEV;
2a125dd5 EM	300
701a5dc0	301	pxa2xx_drv_pcmcia_ops(ops);
da4f0073	302
8e2caf0d RK	303	sinfo = devm_kzalloc(&dev->dev, SKT_DEV_INFO_SIZE(ops->nr),
8e2caf0d RK	304	GFP_KERNEL);
ac92f151	305	if (!sinfo)
b393c696 EM	306	return -ENOMEM;
	307
	308	sinfo->nskt = ops->nr;
	309
	310	/* Initialize processor specific parameters */
	311	for (i = 0; i < ops->nr; i++) {
	312	skt = &sinfo->skt[i];
	313
da4f0073	314	skt->nr = ops->first + i;
2a125dd5	315	skt->clk = clk;
e0d21178	316	soc_pcmcia_init_one(skt, ops, &dev->dev);
b393c696	317
da4f0073 RKAL	318	ret = pxa2xx_drv_pcmcia_add_one(skt);
da4f0073 RKAL	319	if (ret)
a4257af5	320	goto err1;
b393c696 EM	321	}
b393c696 EM	322
817ed574	323	pxa2xx_configure_sockets(&dev->dev, ops);
8fb28231	324	dev_set_drvdata(&dev->dev, sinfo);
1da177e4	325
a4257af5 MV	326	return 0;
	327
	328	err1:
	329	while (--i >= 0)
	330	soc_pcmcia_remove_one(&sinfo->skt[i]);
8e2caf0d	331
a4257af5	332	err0:
1da177e4 LT	333	return ret;
1da177e4 LT	334	}
9468613b RK	335
	336	static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
	337	{
be85458e RKAL	338	struct skt_dev_info *sinfo = platform_get_drvdata(dev);
	339	int i;
	340
be85458e RKAL	341	for (i = 0; i < sinfo->nskt; i++)
	342	soc_pcmcia_remove_one(&sinfo->skt[i]);
	343
be85458e	344	return 0;
9468613b RK	345	}
9468613b RK	346
85c61021	347	static int pxa2xx_drv_pcmcia_resume(struct device *dev)
1da177e4	348	{
817ed574 RJ	349	struct pcmcia_low_level ops = (struct pcmcia_low_level )dev->platform_data;
	350
	351	pxa2xx_configure_sockets(dev, ops);
d7646f76	352	return 0;
1da177e4 LT	353	}
1da177e4 LT	354
47145210	355	static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
85c61021 MR	356	.resume = pxa2xx_drv_pcmcia_resume,
	357	};
	358
9468613b	359	static struct platform_driver pxa2xx_pcmcia_driver = {
1da177e4	360	.probe = pxa2xx_drv_pcmcia_probe,
9468613b	361	.remove = pxa2xx_drv_pcmcia_remove,
9468613b RK	362	.driver = {
9468613b RK	363	.name = "pxa2xx-pcmcia",
85c61021	364	.pm = &pxa2xx_drv_pcmcia_pm_ops,
9468613b	365	},
1da177e4 LT	366	};
	367
	368	static int __init pxa2xx_pcmcia_init(void)
	369	{
9468613b	370	return platform_driver_register(&pxa2xx_pcmcia_driver);
1da177e4 LT	371	}
	372
	373	static void __exit pxa2xx_pcmcia_exit(void)
	374	{
9468613b	375	platform_driver_unregister(&pxa2xx_pcmcia_driver);
1da177e4 LT	376	}
1da177e4 LT	377
f36598ae	378	fs_initcall(pxa2xx_pcmcia_init);
1da177e4 LT	379	module_exit(pxa2xx_pcmcia_exit);
	380
	381	MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
	382	MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
	383	MODULE_LICENSE("GPL");
12c2c019	384	MODULE_ALIAS("platform:pxa2xx-pcmcia");