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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Driver for Intel I82092AA PCI-PCMCIA bridge. | |
4 | * | |
5 | * (C) 2001 Red Hat, Inc. | |
6 | * | |
7 | * Author: Arjan Van De Ven <arjanv@redhat.com> | |
8 | * Loosly based on i82365.c from the pcmcia-cs package | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
1da177e4 LT |
12 | #include <linux/module.h> |
13 | #include <linux/pci.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/workqueue.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/device.h> | |
18 | ||
1da177e4 | 19 | #include <pcmcia/ss.h> |
1da177e4 | 20 | |
1da177e4 LT |
21 | #include <asm/io.h> |
22 | ||
23 | #include "i82092aa.h" | |
24 | #include "i82365.h" | |
25 | ||
26 | MODULE_LICENSE("GPL"); | |
27 | ||
28 | /* PCI core routines */ | |
0178a7a5 | 29 | static const struct pci_device_id i82092aa_pci_ids[] = { |
2b2c5d8c AL |
30 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82092AA_0) }, |
31 | { } | |
1da177e4 LT |
32 | }; |
33 | MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids); | |
34 | ||
ba66ddfa | 35 | static struct pci_driver i82092aa_pci_driver = { |
1da177e4 LT |
36 | .name = "i82092aa", |
37 | .id_table = i82092aa_pci_ids, | |
38 | .probe = i82092aa_pci_probe, | |
96364e3a | 39 | .remove = i82092aa_pci_remove, |
1da177e4 LT |
40 | }; |
41 | ||
42 | ||
43 | /* the pccard structure and its functions */ | |
44 | static struct pccard_operations i82092aa_operations = { | |
45 | .init = i82092aa_init, | |
46 | .get_status = i82092aa_get_status, | |
1da177e4 LT |
47 | .set_socket = i82092aa_set_socket, |
48 | .set_io_map = i82092aa_set_io_map, | |
49 | .set_mem_map = i82092aa_set_mem_map, | |
50 | }; | |
51 | ||
25985edc | 52 | /* The card can do up to 4 sockets, allocate a structure for each of them */ |
1da177e4 LT |
53 | |
54 | struct socket_info { | |
55 | int number; | |
56 | int card_state; /* 0 = no socket, | |
57 | 1 = empty socket, | |
58 | 2 = card but not initialized, | |
59 | 3 = operational card */ | |
906da809 | 60 | unsigned int io_base; /* base io address of the socket */ |
1da177e4 LT |
61 | |
62 | struct pcmcia_socket socket; | |
63 | struct pci_dev *dev; /* The PCI device for the socket */ | |
64 | }; | |
65 | ||
66 | #define MAX_SOCKETS 4 | |
67 | static struct socket_info sockets[MAX_SOCKETS]; | |
68 | static int socket_count; /* shortcut */ | |
69 | ||
70 | ||
34cdf25a | 71 | static int i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 LT |
72 | { |
73 | unsigned char configbyte; | |
74 | int i, ret; | |
75 | ||
76 | enter("i82092aa_pci_probe"); | |
77 | ||
78 | if ((ret = pci_enable_device(dev))) | |
79 | return ret; | |
80 | ||
81 | pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */ | |
82 | switch(configbyte&6) { | |
83 | case 0: | |
84 | socket_count = 2; | |
85 | break; | |
86 | case 2: | |
87 | socket_count = 1; | |
88 | break; | |
89 | case 4: | |
90 | case 6: | |
91 | socket_count = 4; | |
92 | break; | |
93 | ||
94 | default: | |
95 | printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n"); | |
96 | ret = -EIO; | |
97 | goto err_out_disable; | |
98 | } | |
99 | printk(KERN_INFO "i82092aa: configured as a %d socket device.\n", socket_count); | |
100 | ||
101 | if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) { | |
102 | ret = -EBUSY; | |
103 | goto err_out_disable; | |
104 | } | |
105 | ||
106 | for (i = 0;i<socket_count;i++) { | |
107 | sockets[i].card_state = 1; /* 1 = present but empty */ | |
108 | sockets[i].io_base = pci_resource_start(dev, 0); | |
109 | sockets[i].socket.features |= SS_CAP_PCCARD; | |
110 | sockets[i].socket.map_size = 0x1000; | |
111 | sockets[i].socket.irq_mask = 0; | |
112 | sockets[i].socket.pci_irq = dev->irq; | |
7a96e87d | 113 | sockets[i].socket.cb_dev = dev; |
1da177e4 LT |
114 | sockets[i].socket.owner = THIS_MODULE; |
115 | ||
116 | sockets[i].number = i; | |
117 | ||
118 | if (card_present(i)) { | |
119 | sockets[i].card_state = 3; | |
120 | dprintk(KERN_DEBUG "i82092aa: slot %i is occupied\n",i); | |
121 | } else { | |
122 | dprintk(KERN_DEBUG "i82092aa: slot %i is vacant\n",i); | |
123 | } | |
124 | } | |
125 | ||
126 | /* Now, specifiy that all interrupts are to be done as PCI interrupts */ | |
127 | configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */ | |
128 | pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */ | |
129 | ||
130 | /* Register the interrupt handler */ | |
131 | dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq); | |
dace1453 | 132 | if ((ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, "i82092aa", i82092aa_interrupt))) { |
1da177e4 LT |
133 | printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq); |
134 | goto err_out_free_res; | |
135 | } | |
136 | ||
1da177e4 | 137 | for (i = 0; i<socket_count; i++) { |
87373318 | 138 | sockets[i].socket.dev.parent = &dev->dev; |
1da177e4 LT |
139 | sockets[i].socket.ops = &i82092aa_operations; |
140 | sockets[i].socket.resource_ops = &pccard_nonstatic_ops; | |
141 | ret = pcmcia_register_socket(&sockets[i].socket); | |
142 | if (ret) { | |
143 | goto err_out_free_sockets; | |
144 | } | |
145 | } | |
146 | ||
147 | leave("i82092aa_pci_probe"); | |
148 | return 0; | |
149 | ||
150 | err_out_free_sockets: | |
151 | if (i) { | |
152 | for (i--;i>=0;i--) { | |
153 | pcmcia_unregister_socket(&sockets[i].socket); | |
154 | } | |
155 | } | |
156 | free_irq(dev->irq, i82092aa_interrupt); | |
157 | err_out_free_res: | |
158 | release_region(pci_resource_start(dev, 0), 2); | |
159 | err_out_disable: | |
160 | pci_disable_device(dev); | |
161 | return ret; | |
162 | } | |
163 | ||
e765a02c | 164 | static void i82092aa_pci_remove(struct pci_dev *dev) |
1da177e4 | 165 | { |
36c286d5 | 166 | int i; |
1da177e4 LT |
167 | |
168 | enter("i82092aa_pci_remove"); | |
169 | ||
170 | free_irq(dev->irq, i82092aa_interrupt); | |
171 | ||
36c286d5 DC |
172 | for (i = 0; i < socket_count; i++) |
173 | pcmcia_unregister_socket(&sockets[i].socket); | |
1da177e4 LT |
174 | |
175 | leave("i82092aa_pci_remove"); | |
176 | } | |
177 | ||
178 | static DEFINE_SPINLOCK(port_lock); | |
179 | ||
180 | /* basic value read/write functions */ | |
181 | ||
182 | static unsigned char indirect_read(int socket, unsigned short reg) | |
183 | { | |
184 | unsigned short int port; | |
185 | unsigned char val; | |
186 | unsigned long flags; | |
187 | spin_lock_irqsave(&port_lock,flags); | |
188 | reg += socket * 0x40; | |
189 | port = sockets[socket].io_base; | |
190 | outb(reg,port); | |
191 | val = inb(port+1); | |
192 | spin_unlock_irqrestore(&port_lock,flags); | |
193 | return val; | |
194 | } | |
195 | ||
196 | #if 0 | |
197 | static unsigned short indirect_read16(int socket, unsigned short reg) | |
198 | { | |
199 | unsigned short int port; | |
200 | unsigned short tmp; | |
201 | unsigned long flags; | |
202 | spin_lock_irqsave(&port_lock,flags); | |
203 | reg = reg + socket * 0x40; | |
204 | port = sockets[socket].io_base; | |
205 | outb(reg,port); | |
206 | tmp = inb(port+1); | |
207 | reg++; | |
208 | outb(reg,port); | |
209 | tmp = tmp | (inb(port+1)<<8); | |
210 | spin_unlock_irqrestore(&port_lock,flags); | |
211 | return tmp; | |
212 | } | |
213 | #endif | |
214 | ||
215 | static void indirect_write(int socket, unsigned short reg, unsigned char value) | |
216 | { | |
217 | unsigned short int port; | |
218 | unsigned long flags; | |
219 | spin_lock_irqsave(&port_lock,flags); | |
220 | reg = reg + socket * 0x40; | |
221 | port = sockets[socket].io_base; | |
222 | outb(reg,port); | |
223 | outb(value,port+1); | |
224 | spin_unlock_irqrestore(&port_lock,flags); | |
225 | } | |
226 | ||
227 | static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) | |
228 | { | |
229 | unsigned short int port; | |
230 | unsigned char val; | |
231 | unsigned long flags; | |
232 | spin_lock_irqsave(&port_lock,flags); | |
233 | reg = reg + socket * 0x40; | |
234 | port = sockets[socket].io_base; | |
235 | outb(reg,port); | |
236 | val = inb(port+1); | |
237 | val |= mask; | |
238 | outb(reg,port); | |
239 | outb(val,port+1); | |
240 | spin_unlock_irqrestore(&port_lock,flags); | |
241 | } | |
242 | ||
243 | ||
244 | static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask) | |
245 | { | |
246 | unsigned short int port; | |
247 | unsigned char val; | |
248 | unsigned long flags; | |
249 | spin_lock_irqsave(&port_lock,flags); | |
250 | reg = reg + socket * 0x40; | |
251 | port = sockets[socket].io_base; | |
252 | outb(reg,port); | |
253 | val = inb(port+1); | |
254 | val &= ~mask; | |
255 | outb(reg,port); | |
256 | outb(val,port+1); | |
257 | spin_unlock_irqrestore(&port_lock,flags); | |
258 | } | |
259 | ||
260 | static void indirect_write16(int socket, unsigned short reg, unsigned short value) | |
261 | { | |
262 | unsigned short int port; | |
263 | unsigned char val; | |
264 | unsigned long flags; | |
265 | spin_lock_irqsave(&port_lock,flags); | |
266 | reg = reg + socket * 0x40; | |
267 | port = sockets[socket].io_base; | |
268 | ||
269 | outb(reg,port); | |
270 | val = value & 255; | |
271 | outb(val,port+1); | |
272 | ||
273 | reg++; | |
274 | ||
275 | outb(reg,port); | |
276 | val = value>>8; | |
277 | outb(val,port+1); | |
278 | spin_unlock_irqrestore(&port_lock,flags); | |
279 | } | |
280 | ||
281 | /* simple helper functions */ | |
282 | /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ | |
283 | static int cycle_time = 120; | |
284 | ||
285 | static int to_cycles(int ns) | |
286 | { | |
287 | if (cycle_time!=0) | |
288 | return ns/cycle_time; | |
289 | else | |
290 | return 0; | |
291 | } | |
292 | ||
293 | ||
294 | /* Interrupt handler functionality */ | |
295 | ||
7d12e780 | 296 | static irqreturn_t i82092aa_interrupt(int irq, void *dev) |
1da177e4 LT |
297 | { |
298 | int i; | |
299 | int loopcount = 0; | |
300 | int handled = 0; | |
301 | ||
302 | unsigned int events, active=0; | |
303 | ||
304 | /* enter("i82092aa_interrupt");*/ | |
305 | ||
306 | while (1) { | |
307 | loopcount++; | |
308 | if (loopcount>20) { | |
309 | printk(KERN_ERR "i82092aa: infinite eventloop in interrupt \n"); | |
310 | break; | |
311 | } | |
312 | ||
313 | active = 0; | |
314 | ||
315 | for (i=0;i<socket_count;i++) { | |
316 | int csc; | |
317 | if (sockets[i].card_state==0) /* Inactive socket, should not happen */ | |
318 | continue; | |
319 | ||
320 | csc = indirect_read(i,I365_CSC); /* card status change register */ | |
321 | ||
322 | if (csc==0) /* no events on this socket */ | |
323 | continue; | |
324 | handled = 1; | |
325 | events = 0; | |
326 | ||
327 | if (csc & I365_CSC_DETECT) { | |
328 | events |= SS_DETECT; | |
329 | printk("Card detected in socket %i!\n",i); | |
330 | } | |
331 | ||
332 | if (indirect_read(i,I365_INTCTL) & I365_PC_IOCARD) { | |
333 | /* For IO/CARDS, bit 0 means "read the card" */ | |
334 | events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; | |
335 | } else { | |
336 | /* Check for battery/ready events */ | |
337 | events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; | |
338 | events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; | |
339 | events |= (csc & I365_CSC_READY) ? SS_READY : 0; | |
340 | } | |
341 | ||
342 | if (events) { | |
343 | pcmcia_parse_events(&sockets[i].socket, events); | |
344 | } | |
345 | active |= events; | |
346 | } | |
347 | ||
348 | if (active==0) /* no more events to handle */ | |
349 | break; | |
350 | ||
351 | } | |
352 | return IRQ_RETVAL(handled); | |
353 | /* leave("i82092aa_interrupt");*/ | |
354 | } | |
355 | ||
356 | ||
357 | ||
358 | /* socket functions */ | |
359 | ||
360 | static int card_present(int socketno) | |
361 | { | |
362 | unsigned int val; | |
363 | enter("card_present"); | |
364 | ||
365 | if ((socketno<0) || (socketno >= MAX_SOCKETS)) | |
366 | return 0; | |
367 | if (sockets[socketno].io_base == 0) | |
368 | return 0; | |
369 | ||
370 | ||
371 | val = indirect_read(socketno, 1); /* Interface status register */ | |
372 | if ((val&12)==12) { | |
373 | leave("card_present 1"); | |
374 | return 1; | |
375 | } | |
376 | ||
377 | leave("card_present 0"); | |
378 | return 0; | |
379 | } | |
380 | ||
381 | static void set_bridge_state(int sock) | |
382 | { | |
383 | enter("set_bridge_state"); | |
384 | indirect_write(sock, I365_GBLCTL,0x00); | |
385 | indirect_write(sock, I365_GENCTL,0x00); | |
386 | ||
387 | indirect_setbit(sock, I365_INTCTL,0x08); | |
388 | leave("set_bridge_state"); | |
389 | } | |
390 | ||
391 | ||
392 | ||
393 | ||
394 | ||
395 | ||
396 | static int i82092aa_init(struct pcmcia_socket *sock) | |
397 | { | |
398 | int i; | |
399 | struct resource res = { .start = 0, .end = 0x0fff }; | |
400 | pccard_io_map io = { 0, 0, 0, 0, 1 }; | |
401 | pccard_mem_map mem = { .res = &res, }; | |
402 | ||
403 | enter("i82092aa_init"); | |
404 | ||
405 | for (i = 0; i < 2; i++) { | |
406 | io.map = i; | |
407 | i82092aa_set_io_map(sock, &io); | |
408 | } | |
409 | for (i = 0; i < 5; i++) { | |
410 | mem.map = i; | |
411 | i82092aa_set_mem_map(sock, &mem); | |
412 | } | |
413 | ||
414 | leave("i82092aa_init"); | |
415 | return 0; | |
416 | } | |
417 | ||
418 | static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value) | |
419 | { | |
420 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
421 | unsigned int status; | |
422 | ||
423 | enter("i82092aa_get_status"); | |
424 | ||
425 | status = indirect_read(sock,I365_STATUS); /* Interface Status Register */ | |
426 | *value = 0; | |
427 | ||
428 | if ((status & I365_CS_DETECT) == I365_CS_DETECT) { | |
429 | *value |= SS_DETECT; | |
430 | } | |
431 | ||
432 | /* IO cards have a different meaning of bits 0,1 */ | |
433 | /* Also notice the inverse-logic on the bits */ | |
434 | if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) { | |
435 | /* IO card */ | |
436 | if (!(status & I365_CS_STSCHG)) | |
437 | *value |= SS_STSCHG; | |
438 | } else { /* non I/O card */ | |
439 | if (!(status & I365_CS_BVD1)) | |
440 | *value |= SS_BATDEAD; | |
441 | if (!(status & I365_CS_BVD2)) | |
442 | *value |= SS_BATWARN; | |
443 | ||
444 | } | |
445 | ||
446 | if (status & I365_CS_WRPROT) | |
447 | (*value) |= SS_WRPROT; /* card is write protected */ | |
448 | ||
449 | if (status & I365_CS_READY) | |
450 | (*value) |= SS_READY; /* card is not busy */ | |
451 | ||
452 | if (status & I365_CS_POWERON) | |
453 | (*value) |= SS_POWERON; /* power is applied to the card */ | |
454 | ||
455 | ||
456 | leave("i82092aa_get_status"); | |
457 | return 0; | |
458 | } | |
459 | ||
460 | ||
1da177e4 LT |
461 | static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state) |
462 | { | |
463 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
464 | unsigned char reg; | |
465 | ||
466 | enter("i82092aa_set_socket"); | |
467 | ||
468 | /* First, set the global controller options */ | |
469 | ||
470 | set_bridge_state(sock); | |
471 | ||
472 | /* Values for the IGENC register */ | |
473 | ||
474 | reg = 0; | |
475 | if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */ | |
476 | reg = reg | I365_PC_RESET; | |
477 | if (state->flags & SS_IOCARD) | |
478 | reg = reg | I365_PC_IOCARD; | |
479 | ||
480 | indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */ | |
481 | ||
482 | /* Power registers */ | |
483 | ||
484 | reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ | |
485 | ||
486 | if (state->flags & SS_PWR_AUTO) { | |
487 | printk("Auto power\n"); | |
488 | reg |= I365_PWR_AUTO; /* automatic power mngmnt */ | |
489 | } | |
490 | if (state->flags & SS_OUTPUT_ENA) { | |
491 | printk("Power Enabled \n"); | |
492 | reg |= I365_PWR_OUT; /* enable power */ | |
493 | } | |
494 | ||
495 | switch (state->Vcc) { | |
496 | case 0: | |
497 | break; | |
498 | case 50: | |
499 | printk("setting voltage to Vcc to 5V on socket %i\n",sock); | |
500 | reg |= I365_VCC_5V; | |
501 | break; | |
502 | default: | |
503 | printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc); | |
504 | leave("i82092aa_set_socket"); | |
505 | return -EINVAL; | |
506 | } | |
507 | ||
508 | ||
509 | switch (state->Vpp) { | |
510 | case 0: | |
511 | printk("not setting Vpp on socket %i\n",sock); | |
512 | break; | |
513 | case 50: | |
514 | printk("setting Vpp to 5.0 for socket %i\n",sock); | |
515 | reg |= I365_VPP1_5V | I365_VPP2_5V; | |
516 | break; | |
517 | case 120: | |
518 | printk("setting Vpp to 12.0\n"); | |
519 | reg |= I365_VPP1_12V | I365_VPP2_12V; | |
520 | break; | |
521 | default: | |
522 | printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc); | |
523 | leave("i82092aa_set_socket"); | |
524 | return -EINVAL; | |
525 | } | |
526 | ||
527 | if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */ | |
528 | indirect_write(sock,I365_POWER,reg); | |
529 | ||
530 | /* Enable specific interrupt events */ | |
531 | ||
532 | reg = 0x00; | |
533 | if (state->csc_mask & SS_DETECT) { | |
534 | reg |= I365_CSC_DETECT; | |
535 | } | |
536 | if (state->flags & SS_IOCARD) { | |
537 | if (state->csc_mask & SS_STSCHG) | |
538 | reg |= I365_CSC_STSCHG; | |
539 | } else { | |
540 | if (state->csc_mask & SS_BATDEAD) | |
541 | reg |= I365_CSC_BVD1; | |
542 | if (state->csc_mask & SS_BATWARN) | |
543 | reg |= I365_CSC_BVD2; | |
544 | if (state->csc_mask & SS_READY) | |
545 | reg |= I365_CSC_READY; | |
546 | ||
547 | } | |
548 | ||
549 | /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/ | |
550 | ||
551 | indirect_write(sock,I365_CSCINT,reg); | |
552 | (void)indirect_read(sock,I365_CSC); | |
553 | ||
554 | leave("i82092aa_set_socket"); | |
555 | return 0; | |
556 | } | |
557 | ||
558 | static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io) | |
559 | { | |
560 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
561 | unsigned char map, ioctl; | |
562 | ||
563 | enter("i82092aa_set_io_map"); | |
564 | ||
565 | map = io->map; | |
566 | ||
567 | /* Check error conditions */ | |
568 | if (map > 1) { | |
569 | leave("i82092aa_set_io_map with invalid map"); | |
570 | return -EINVAL; | |
571 | } | |
572 | if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){ | |
573 | leave("i82092aa_set_io_map with invalid io"); | |
574 | return -EINVAL; | |
575 | } | |
576 | ||
577 | /* Turn off the window before changing anything */ | |
578 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map)) | |
579 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); | |
580 | ||
581 | /* printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop); */ | |
582 | ||
583 | /* write the new values */ | |
584 | indirect_write16(sock,I365_IO(map)+I365_W_START,io->start); | |
585 | indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop); | |
586 | ||
587 | ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map); | |
588 | ||
589 | if (io->flags & (MAP_16BIT|MAP_AUTOSZ)) | |
590 | ioctl |= I365_IOCTL_16BIT(map); | |
591 | ||
592 | indirect_write(sock,I365_IOCTL,ioctl); | |
593 | ||
594 | /* Turn the window back on if needed */ | |
595 | if (io->flags & MAP_ACTIVE) | |
596 | indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map)); | |
597 | ||
598 | leave("i82092aa_set_io_map"); | |
599 | return 0; | |
600 | } | |
601 | ||
602 | static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem) | |
603 | { | |
604 | struct socket_info *sock_info = container_of(socket, struct socket_info, socket); | |
605 | unsigned int sock = sock_info->number; | |
606 | struct pci_bus_region region; | |
607 | unsigned short base, i; | |
608 | unsigned char map; | |
609 | ||
610 | enter("i82092aa_set_mem_map"); | |
611 | ||
fc279850 | 612 | pcibios_resource_to_bus(sock_info->dev->bus, ®ion, mem->res); |
1da177e4 LT |
613 | |
614 | map = mem->map; | |
615 | if (map > 4) { | |
616 | leave("i82092aa_set_mem_map: invalid map"); | |
617 | return -EINVAL; | |
618 | } | |
619 | ||
620 | ||
621 | if ( (mem->card_start > 0x3ffffff) || (region.start > region.end) || | |
622 | (mem->speed > 1000) ) { | |
623 | leave("i82092aa_set_mem_map: invalid address / speed"); | |
f96ee7a4 AM |
624 | printk("invalid mem map for socket %i: %llx to %llx with a " |
625 | "start of %x\n", | |
626 | sock, | |
627 | (unsigned long long)region.start, | |
628 | (unsigned long long)region.end, | |
629 | mem->card_start); | |
1da177e4 LT |
630 | return -EINVAL; |
631 | } | |
632 | ||
633 | /* Turn off the window before changing anything */ | |
634 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map)) | |
635 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); | |
636 | ||
637 | ||
638 | /* printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, region.start,region.end,sock,mem->speed,mem->flags & MAP_ACTIVE); */ | |
639 | ||
640 | /* write the start address */ | |
641 | base = I365_MEM(map); | |
642 | i = (region.start >> 12) & 0x0fff; | |
643 | if (mem->flags & MAP_16BIT) | |
644 | i |= I365_MEM_16BIT; | |
645 | if (mem->flags & MAP_0WS) | |
646 | i |= I365_MEM_0WS; | |
647 | indirect_write16(sock,base+I365_W_START,i); | |
648 | ||
649 | /* write the stop address */ | |
650 | ||
651 | i= (region.end >> 12) & 0x0fff; | |
652 | switch (to_cycles(mem->speed)) { | |
653 | case 0: | |
654 | break; | |
655 | case 1: | |
656 | i |= I365_MEM_WS0; | |
657 | break; | |
658 | case 2: | |
659 | i |= I365_MEM_WS1; | |
660 | break; | |
661 | default: | |
662 | i |= I365_MEM_WS1 | I365_MEM_WS0; | |
663 | break; | |
664 | } | |
665 | ||
666 | indirect_write16(sock,base+I365_W_STOP,i); | |
667 | ||
668 | /* card start */ | |
669 | ||
670 | i = ((mem->card_start - region.start) >> 12) & 0x3fff; | |
671 | if (mem->flags & MAP_WRPROT) | |
672 | i |= I365_MEM_WRPROT; | |
673 | if (mem->flags & MAP_ATTRIB) { | |
674 | /* printk("requesting attribute memory for socket %i\n",sock);*/ | |
675 | i |= I365_MEM_REG; | |
676 | } else { | |
677 | /* printk("requesting normal memory for socket %i\n",sock);*/ | |
678 | } | |
679 | indirect_write16(sock,base+I365_W_OFF,i); | |
680 | ||
681 | /* Enable the window if necessary */ | |
682 | if (mem->flags & MAP_ACTIVE) | |
683 | indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); | |
684 | ||
685 | leave("i82092aa_set_mem_map"); | |
686 | return 0; | |
687 | } | |
688 | ||
689 | static int i82092aa_module_init(void) | |
690 | { | |
ba66ddfa | 691 | return pci_register_driver(&i82092aa_pci_driver); |
1da177e4 LT |
692 | } |
693 | ||
694 | static void i82092aa_module_exit(void) | |
695 | { | |
696 | enter("i82092aa_module_exit"); | |
ba66ddfa | 697 | pci_unregister_driver(&i82092aa_pci_driver); |
1da177e4 LT |
698 | if (sockets[0].io_base>0) |
699 | release_region(sockets[0].io_base, 2); | |
700 | leave("i82092aa_module_exit"); | |
701 | } | |
702 | ||
703 | module_init(i82092aa_module_init); | |
704 | module_exit(i82092aa_module_exit); | |
705 |