[linux-2.6-block.git] / drivers / pci / vpd.c

// SPDX-License-Identifier: GPL-2.0
/*
 * PCI VPD support
 *
 * Copyright (C) 2010 Broadcom Corporation.
 */

#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/sched/signal.h>
#include "pci.h"

/* VPD access through PCI 2.2+ VPD capability */

static struct pci_dev *pci_get_func0_dev(struct pci_dev *dev)
{
	return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
}

#define PCI_VPD_MAX_SIZE	(PCI_VPD_ADDR_MASK + 1)
#define PCI_VPD_SZ_INVALID	UINT_MAX

/**
 * pci_vpd_size - determine actual size of Vital Product Data
 * @dev:	pci device struct
 */
static size_t pci_vpd_size(struct pci_dev *dev)
{
	size_t off = 0, size;
	unsigned char tag, header[1+2];	/* 1 byte tag, 2 bytes length */

	/* Otherwise the following reads would fail. */
	dev->vpd.len = PCI_VPD_MAX_SIZE;

	while (pci_read_vpd(dev, off, 1, header) == 1) {
		size = 0;

		if (off == 0 && (header[0] == 0x00 || header[0] == 0xff))
			goto error;

		if (header[0] & PCI_VPD_LRDT) {
			/* Large Resource Data Type Tag */
			if (pci_read_vpd(dev, off + 1, 2, &header[1]) != 2) {
				pci_warn(dev, "failed VPD read at offset %zu\n",
					 off + 1);
				return off ?: PCI_VPD_SZ_INVALID;
			}
			size = pci_vpd_lrdt_size(header);
			if (off + size > PCI_VPD_MAX_SIZE)
				goto error;

			off += PCI_VPD_LRDT_TAG_SIZE + size;
		} else {
			/* Short Resource Data Type Tag */
			tag = pci_vpd_srdt_tag(header);
			size = pci_vpd_srdt_size(header);
			if (off + size > PCI_VPD_MAX_SIZE)
				goto error;

			off += PCI_VPD_SRDT_TAG_SIZE + size;
			if (tag == PCI_VPD_STIN_END)	/* End tag descriptor */
				return off;
		}
	}
	return off;

error:
	pci_info(dev, "invalid VPD tag %#04x (size %zu) at offset %zu%s\n",
		 header[0], size, off, off == 0 ?
		 "; assume missing optional EEPROM" : "");
	return off ?: PCI_VPD_SZ_INVALID;
}

/*
 * Wait for last operation to complete.
 * This code has to spin since there is no other notification from the PCI
 * hardware. Since the VPD is often implemented by serial attachment to an
 * EEPROM, it may take many milliseconds to complete.
 * @set: if true wait for flag to be set, else wait for it to be cleared
 *
 * Returns 0 on success, negative values indicate error.
 */
static int pci_vpd_wait(struct pci_dev *dev, bool set)
{
	struct pci_vpd *vpd = &dev->vpd;
	unsigned long timeout = jiffies + msecs_to_jiffies(125);
	unsigned long max_sleep = 16;
	u16 status;
	int ret;

	do {
		ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						&status);
		if (ret < 0)
			return ret;

		if (!!(status & PCI_VPD_ADDR_F) == set)
			return 0;

		if (time_after(jiffies, timeout))
			break;

		usleep_range(10, max_sleep);
		if (max_sleep < 1024)
			max_sleep *= 2;
	} while (true);

	pci_warn(dev, "VPD access failed.  This is likely a firmware bug on this device.  Contact the card vendor for a firmware update\n");
	return -ETIMEDOUT;
}

static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
			    void *arg)
{
	struct pci_vpd *vpd = &dev->vpd;
	int ret = 0;
	loff_t end = pos + count;
	u8 *buf = arg;

	if (!vpd->cap)
		return -ENODEV;

	if (pos < 0)
		return -EINVAL;

	if (pos > vpd->len)
		return 0;

	if (end > vpd->len) {
		end = vpd->len;
		count = end - pos;
	}

	if (mutex_lock_killable(&vpd->lock))
		return -EINTR;

	while (pos < end) {
		u32 val;
		unsigned int i, skip;

		if (fatal_signal_pending(current)) {
			ret = -EINTR;
			break;
		}

		ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						 pos & ~3);
		if (ret < 0)
			break;
		ret = pci_vpd_wait(dev, true);
		if (ret < 0)
			break;

		ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
		if (ret < 0)
			break;

		skip = pos & 3;
		for (i = 0;  i < sizeof(u32); i++) {
			if (i >= skip) {
				*buf++ = val;
				if (++pos == end)
					break;
			}
			val >>= 8;
		}
	}

	mutex_unlock(&vpd->lock);
	return ret ? ret : count;
}

static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
			     const void *arg)
{
	struct pci_vpd *vpd = &dev->vpd;
	const u8 *buf = arg;
	loff_t end = pos + count;
	int ret = 0;

	if (!vpd->cap)
		return -ENODEV;

	if (pos < 0 || (pos & 3) || (count & 3))
		return -EINVAL;

	if (end > vpd->len)
		return -EINVAL;

	if (mutex_lock_killable(&vpd->lock))
		return -EINTR;

	while (pos < end) {
		u32 val;

		val = *buf++;
		val |= *buf++ << 8;
		val |= *buf++ << 16;
		val |= *buf++ << 24;

		ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
		if (ret < 0)
			break;
		ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						 pos | PCI_VPD_ADDR_F);
		if (ret < 0)
			break;

		ret = pci_vpd_wait(dev, false);
		if (ret < 0)
			break;

		pos += sizeof(u32);
	}

	mutex_unlock(&vpd->lock);
	return ret ? ret : count;
}

void pci_vpd_init(struct pci_dev *dev)
{
	dev->vpd.cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
	mutex_init(&dev->vpd.lock);

	if (!dev->vpd.len)
		dev->vpd.len = pci_vpd_size(dev);

	if (dev->vpd.len == PCI_VPD_SZ_INVALID)
		dev->vpd.cap = 0;
}

static ssize_t vpd_read(struct file *filp, struct kobject *kobj,
			struct bin_attribute *bin_attr, char *buf, loff_t off,
			size_t count)
{
	struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));

	return pci_read_vpd(dev, off, count, buf);
}

static ssize_t vpd_write(struct file *filp, struct kobject *kobj,
			 struct bin_attribute *bin_attr, char *buf, loff_t off,
			 size_t count)
{
	struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));

	return pci_write_vpd(dev, off, count, buf);
}
static BIN_ATTR(vpd, 0600, vpd_read, vpd_write, 0);

static struct bin_attribute *vpd_attrs[] = {
	&bin_attr_vpd,
	NULL,
};

static umode_t vpd_attr_is_visible(struct kobject *kobj,
				   struct bin_attribute *a, int n)
{
	struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));

	if (!pdev->vpd.cap)
		return 0;

	return a->attr.mode;
}

const struct attribute_group pci_dev_vpd_attr_group = {
	.bin_attrs = vpd_attrs,
	.is_bin_visible = vpd_attr_is_visible,
};

void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size)
{
	unsigned int len = dev->vpd.len;
	void *buf;
	int cnt;

	if (!dev->vpd.cap)
		return ERR_PTR(-ENODEV);

	buf = kmalloc(len, GFP_KERNEL);
	if (!buf)
		return ERR_PTR(-ENOMEM);

	cnt = pci_read_vpd(dev, 0, len, buf);
	if (cnt != len) {
		kfree(buf);
		return ERR_PTR(-EIO);
	}

	if (size)
		*size = len;

	return buf;
}
EXPORT_SYMBOL_GPL(pci_vpd_alloc);

int pci_vpd_find_tag(const u8 *buf, unsigned int len, u8 rdt)
{
	int i = 0;

	/* look for LRDT tags only, end tag is the only SRDT tag */
	while (i + PCI_VPD_LRDT_TAG_SIZE <= len && buf[i] & PCI_VPD_LRDT) {
		if (buf[i] == rdt)
			return i;

		i += PCI_VPD_LRDT_TAG_SIZE + pci_vpd_lrdt_size(buf + i);
	}

	return -ENOENT;
}
EXPORT_SYMBOL_GPL(pci_vpd_find_tag);

int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
			      unsigned int len, const char *kw)
{
	int i;

	for (i = off; i + PCI_VPD_INFO_FLD_HDR_SIZE <= off + len;) {
		if (buf[i + 0] == kw[0] &&
		    buf[i + 1] == kw[1])
			return i;

		i += PCI_VPD_INFO_FLD_HDR_SIZE +
		     pci_vpd_info_field_size(&buf[i]);
	}

	return -ENOENT;
}
EXPORT_SYMBOL_GPL(pci_vpd_find_info_keyword);

/**
 * pci_read_vpd - Read one entry from Vital Product Data
 * @dev:	PCI device struct
 * @pos:	offset in VPD space
 * @count:	number of bytes to read
 * @buf:	pointer to where to store result
 */
ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
{
	ssize_t ret;

	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
		dev = pci_get_func0_dev(dev);
		if (!dev)
			return -ENODEV;

		ret = pci_vpd_read(dev, pos, count, buf);
		pci_dev_put(dev);
		return ret;
	}

	return pci_vpd_read(dev, pos, count, buf);
}
EXPORT_SYMBOL(pci_read_vpd);

/**
 * pci_write_vpd - Write entry to Vital Product Data
 * @dev:	PCI device struct
 * @pos:	offset in VPD space
 * @count:	number of bytes to write
 * @buf:	buffer containing write data
 */
ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
{
	ssize_t ret;

	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
		dev = pci_get_func0_dev(dev);
		if (!dev)
			return -ENODEV;

		ret = pci_vpd_write(dev, pos, count, buf);
		pci_dev_put(dev);
		return ret;
	}

	return pci_vpd_write(dev, pos, count, buf);
}
EXPORT_SYMBOL(pci_write_vpd);

#ifdef CONFIG_PCI_QUIRKS
/*
 * Quirk non-zero PCI functions to route VPD access through function 0 for
 * devices that share VPD resources between functions.  The functions are
 * expected to be identical devices.
 */
static void quirk_f0_vpd_link(struct pci_dev *dev)
{
	struct pci_dev *f0;

	if (!PCI_FUNC(dev->devfn))
		return;

	f0 = pci_get_func0_dev(dev);
	if (!f0)
		return;

	if (f0->vpd.cap && dev->class == f0->class &&
	    dev->vendor == f0->vendor && dev->device == f0->device)
		dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;

	pci_dev_put(f0);
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
			      PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);

/*
 * If a device follows the VPD format spec, the PCI core will not read or
 * write past the VPD End Tag.  But some vendors do not follow the VPD
 * format spec, so we can't tell how much data is safe to access.  Devices
 * may behave unpredictably if we access too much.  Blacklist these devices
 * so we don't touch VPD at all.
 */
static void quirk_blacklist_vpd(struct pci_dev *dev)
{
	dev->vpd.len = PCI_VPD_SZ_INVALID;
	pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID, quirk_blacklist_vpd);
/*
 * The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
 * device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
 */
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
			       PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);

static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
{
	int chip = (dev->device & 0xf000) >> 12;
	int func = (dev->device & 0x0f00) >>  8;
	int prod = (dev->device & 0x00ff) >>  0;

	/*
	 * If this is a T3-based adapter, there's a 1KB VPD area at offset
	 * 0xc00 which contains the preferred VPD values.  If this is a T4 or
	 * later based adapter, the special VPD is at offset 0x400 for the
	 * Physical Functions (the SR-IOV Virtual Functions have no VPD
	 * Capabilities).  The PCI VPD Access core routines will normally
	 * compute the size of the VPD by parsing the VPD Data Structure at
	 * offset 0x000.  This will result in silent failures when attempting
	 * to accesses these other VPD areas which are beyond those computed
	 * limits.
	 */
	if (chip == 0x0 && prod >= 0x20)
		dev->vpd.len = 8192;
	else if (chip >= 0x4 && func < 0x8)
		dev->vpd.len = 2048;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
			 quirk_chelsio_extend_vpd);

#endif
Commit	Line	Data
7328c8f4	1	// SPDX-License-Identifier: GPL-2.0
b55ac1b2	2	/*
df62ab5e	3	* PCI VPD support
b55ac1b2 MC	4	*
	5	* Copyright (C) 2010 Broadcom Corporation.
	6	*/
	7
	8	#include <linux/pci.h>
f0eb77ae	9	#include <linux/delay.h>
363c75db	10	#include <linux/export.h>
f0eb77ae BH	11	#include <linux/sched/signal.h>
	12	#include "pci.h"
	13
	14	/* VPD access through PCI 2.2+ VPD capability */
	15
5881b389 HK	16	static struct pci_dev pci_get_func0_dev(struct pci_dev dev)
	17	{
	18	return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
	19	}
	20
22ff2bce HK	21	#define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
22ff2bce HK	22	#define PCI_VPD_SZ_INVALID UINT_MAX
f0eb77ae BH	23
	24	/**
	25	* pci_vpd_size - determine actual size of Vital Product Data
	26	* @dev: pci device struct
f0eb77ae	27	*/
1285762c	28	static size_t pci_vpd_size(struct pci_dev *dev)
f0eb77ae	29	{
6303049d BH	30	size_t off = 0, size;
6303049d BH	31	unsigned char tag, header[1+2]; /* 1 byte tag, 2 bytes length */
f0eb77ae	32
22ff2bce	33	/* Otherwise the following reads would fail. */
fd00faa3	34	dev->vpd.len = PCI_VPD_MAX_SIZE;
22ff2bce	35
1285762c	36	while (pci_read_vpd(dev, off, 1, header) == 1) {
6303049d	37	size = 0;
f0eb77ae	38
4e0d77f8 HK	39	if (off == 0 && (header[0] == 0x00 \|\| header[0] == 0xff))
4e0d77f8 HK	40	goto error;
d1df5f3f	41
f0eb77ae BH	42	if (header[0] & PCI_VPD_LRDT) {
f0eb77ae BH	43	/* Large Resource Data Type Tag */
7fa75dd8 BH	44	if (pci_read_vpd(dev, off + 1, 2, &header[1]) != 2) {
	45	pci_warn(dev, "failed VPD read at offset %zu\n",
	46	off + 1);
22ff2bce	47	return off ?: PCI_VPD_SZ_INVALID;
f0eb77ae	48	}
7fa75dd8 BH	49	size = pci_vpd_lrdt_size(header);
	50	if (off + size > PCI_VPD_MAX_SIZE)
	51	goto error;
	52
	53	off += PCI_VPD_LRDT_TAG_SIZE + size;
f0eb77ae BH	54	} else {
f0eb77ae BH	55	/* Short Resource Data Type Tag */
f0eb77ae	56	tag = pci_vpd_srdt_tag(header);
6303049d BH	57	size = pci_vpd_srdt_size(header);
	58	if (off + size > PCI_VPD_MAX_SIZE)
	59	goto error;
	60
	61	off += PCI_VPD_SRDT_TAG_SIZE + size;
70730db0 BH	62	if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
70730db0 BH	63	return off;
f0eb77ae BH	64	}
f0eb77ae BH	65	}
5fe204ea	66	return off;
4e0d77f8 HK	67
4e0d77f8 HK	68	error:
6303049d BH	69	pci_info(dev, "invalid VPD tag %#04x (size %zu) at offset %zu%s\n",
6303049d BH	70	header[0], size, off, off == 0 ?
4e0d77f8	71	"; assume missing optional EEPROM" : "");
22ff2bce	72	return off ?: PCI_VPD_SZ_INVALID;
f0eb77ae BH	73	}
	74
	75	/*
	76	* Wait for last operation to complete.
	77	* This code has to spin since there is no other notification from the PCI
	78	* hardware. Since the VPD is often implemented by serial attachment to an
	79	* EEPROM, it may take many milliseconds to complete.
fe943bd8	80	* @set: if true wait for flag to be set, else wait for it to be cleared
f0eb77ae BH	81	*
	82	* Returns 0 on success, negative values indicate error.
	83	*/
fe943bd8	84	static int pci_vpd_wait(struct pci_dev *dev, bool set)
f0eb77ae	85	{
fd00faa3	86	struct pci_vpd *vpd = &dev->vpd;
f0eb77ae BH	87	unsigned long timeout = jiffies + msecs_to_jiffies(125);
	88	unsigned long max_sleep = 16;
	89	u16 status;
	90	int ret;
	91
6eaf2781	92	do {
f0eb77ae BH	93	ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
	94	&status);
	95	if (ret < 0)
	96	return ret;
	97
fe943bd8	98	if (!!(status & PCI_VPD_ADDR_F) == set)
f0eb77ae	99	return 0;
f0eb77ae	100
6eaf2781 BK	101	if (time_after(jiffies, timeout))
	102	break;
	103
f0eb77ae BH	104	usleep_range(10, max_sleep);
	105	if (max_sleep < 1024)
	106	max_sleep *= 2;
6eaf2781	107	} while (true);
f0eb77ae BH	108
	109	pci_warn(dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
	110	return -ETIMEDOUT;
	111	}
	112
	113	static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
	114	void *arg)
	115	{
fd00faa3	116	struct pci_vpd *vpd = &dev->vpd;
91ab5d9d	117	int ret = 0;
f0eb77ae BH	118	loff_t end = pos + count;
	119	u8 *buf = arg;
	120
fd00faa3	121	if (!vpd->cap)
a38fccdb HK	122	return -ENODEV;
a38fccdb HK	123
f0eb77ae BH	124	if (pos < 0)
	125	return -EINVAL;
	126
f0eb77ae BH	127	if (pos > vpd->len)
	128	return 0;
	129
	130	if (end > vpd->len) {
	131	end = vpd->len;
	132	count = end - pos;
	133	}
	134
	135	if (mutex_lock_killable(&vpd->lock))
	136	return -EINTR;
	137
f0eb77ae BH	138	while (pos < end) {
	139	u32 val;
	140	unsigned int i, skip;
	141
91ab5d9d HK	142	if (fatal_signal_pending(current)) {
	143	ret = -EINTR;
	144	break;
	145	}
	146
f0eb77ae BH	147	ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
	148	pos & ~3);
	149	if (ret < 0)
	150	break;
fe943bd8	151	ret = pci_vpd_wait(dev, true);
f0eb77ae BH	152	if (ret < 0)
	153	break;
	154
	155	ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
	156	if (ret < 0)
	157	break;
	158
	159	skip = pos & 3;
	160	for (i = 0; i < sizeof(u32); i++) {
	161	if (i >= skip) {
	162	*buf++ = val;
	163	if (++pos == end)
	164	break;
	165	}
	166	val >>= 8;
	167	}
	168	}
91ab5d9d	169
f0eb77ae BH	170	mutex_unlock(&vpd->lock);
	171	return ret ? ret : count;
	172	}
	173
	174	static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
	175	const void *arg)
	176	{
fd00faa3	177	struct pci_vpd *vpd = &dev->vpd;
f0eb77ae BH	178	const u8 *buf = arg;
	179	loff_t end = pos + count;
	180	int ret = 0;
	181
fd00faa3	182	if (!vpd->cap)
a38fccdb HK	183	return -ENODEV;
a38fccdb HK	184
f0eb77ae BH	185	if (pos < 0 \|\| (pos & 3) \|\| (count & 3))
	186	return -EINVAL;
	187
f0eb77ae BH	188	if (end > vpd->len)
	189	return -EINVAL;
	190
	191	if (mutex_lock_killable(&vpd->lock))
	192	return -EINTR;
	193
f0eb77ae BH	194	while (pos < end) {
	195	u32 val;
	196
	197	val = *buf++;
	198	val \|= *buf++ << 8;
	199	val \|= *buf++ << 16;
	200	val \|= *buf++ << 24;
	201
	202	ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
	203	if (ret < 0)
	204	break;
	205	ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
	206	pos \| PCI_VPD_ADDR_F);
	207	if (ret < 0)
	208	break;
	209
fe943bd8	210	ret = pci_vpd_wait(dev, false);
f0eb77ae BH	211	if (ret < 0)
	212	break;
	213
	214	pos += sizeof(u32);
	215	}
91ab5d9d	216
f0eb77ae BH	217	mutex_unlock(&vpd->lock);
	218	return ret ? ret : count;
	219	}
	220
e947e7b1	221	void pci_vpd_init(struct pci_dev *dev)
f0eb77ae	222	{
fd00faa3 HK	223	dev->vpd.cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
fd00faa3 HK	224	mutex_init(&dev->vpd.lock);
7bac5449 HK	225
	226	if (!dev->vpd.len)
	227	dev->vpd.len = pci_vpd_size(dev);
fe7568cf HK	228
	229	if (dev->vpd.len == PCI_VPD_SZ_INVALID)
	230	dev->vpd.cap = 0;
f0eb77ae	231	}
b55ac1b2	232
07b4523e BH	233	static ssize_t vpd_read(struct file filp, struct kobject kobj,
	234	struct bin_attribute bin_attr, char buf, loff_t off,
	235	size_t count)
b1c615c4 BH	236	{
	237	struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
	238
b1c615c4 BH	239	return pci_read_vpd(dev, off, count, buf);
	240	}
	241
07b4523e BH	242	static ssize_t vpd_write(struct file filp, struct kobject kobj,
	243	struct bin_attribute bin_attr, char buf, loff_t off,
	244	size_t count)
b1c615c4 BH	245	{
	246	struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
	247
b1c615c4 BH	248	return pci_write_vpd(dev, off, count, buf);
b1c615c4 BH	249	}
d93f8399	250	static BIN_ATTR(vpd, 0600, vpd_read, vpd_write, 0);
b1c615c4	251
d93f8399 KW	252	static struct bin_attribute *vpd_attrs[] = {
	253	&bin_attr_vpd,
	254	NULL,
	255	};
b1c615c4	256
d93f8399 KW	257	static umode_t vpd_attr_is_visible(struct kobject *kobj,
d93f8399 KW	258	struct bin_attribute *a, int n)
b1c615c4	259	{
d93f8399	260	struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
b1c615c4	261
fd00faa3	262	if (!pdev->vpd.cap)
d93f8399	263	return 0;
b1c615c4	264
d93f8399	265	return a->attr.mode;
b1c615c4 BH	266	}
b1c615c4 BH	267
d93f8399 KW	268	const struct attribute_group pci_dev_vpd_attr_group = {
	269	.bin_attrs = vpd_attrs,
	270	.is_bin_visible = vpd_attr_is_visible,
	271	};
b55ac1b2	272
76f3c032 HK	273	void pci_vpd_alloc(struct pci_dev dev, unsigned int *size)
	274	{
	275	unsigned int len = dev->vpd.len;
	276	void *buf;
	277	int cnt;
	278
	279	if (!dev->vpd.cap)
	280	return ERR_PTR(-ENODEV);
	281
	282	buf = kmalloc(len, GFP_KERNEL);
	283	if (!buf)
	284	return ERR_PTR(-ENOMEM);
	285
	286	cnt = pci_read_vpd(dev, 0, len, buf);
	287	if (cnt != len) {
	288	kfree(buf);
	289	return ERR_PTR(-EIO);
	290	}
	291
	292	if (size)
	293	*size = len;
	294
	295	return buf;
	296	}
	297	EXPORT_SYMBOL_GPL(pci_vpd_alloc);
	298
4cf0abbc	299	int pci_vpd_find_tag(const u8 *buf, unsigned int len, u8 rdt)
b55ac1b2	300	{
0a08bc07	301	int i = 0;
b55ac1b2	302
0a08bc07 HK	303	/* look for LRDT tags only, end tag is the only SRDT tag */
	304	while (i + PCI_VPD_LRDT_TAG_SIZE <= len && buf[i] & PCI_VPD_LRDT) {
	305	if (buf[i] == rdt)
	306	return i;
b55ac1b2	307
0a08bc07	308	i += PCI_VPD_LRDT_TAG_SIZE + pci_vpd_lrdt_size(buf + i);
b55ac1b2 MC	309	}
	310
	311	return -ENOENT;
	312	}
	313	EXPORT_SYMBOL_GPL(pci_vpd_find_tag);
4067a854 MC	314
	315	int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
	316	unsigned int len, const char *kw)
	317	{
	318	int i;
	319
	320	for (i = off; i + PCI_VPD_INFO_FLD_HDR_SIZE <= off + len;) {
	321	if (buf[i + 0] == kw[0] &&
	322	buf[i + 1] == kw[1])
	323	return i;
	324
	325	i += PCI_VPD_INFO_FLD_HDR_SIZE +
	326	pci_vpd_info_field_size(&buf[i]);
	327	}
	328
	329	return -ENOENT;
	330	}
	331	EXPORT_SYMBOL_GPL(pci_vpd_find_info_keyword);
99605857	332
d27f7344 HK	333	/**
	334	* pci_read_vpd - Read one entry from Vital Product Data
	335	* @dev: PCI device struct
	336	* @pos: offset in VPD space
	337	* @count: number of bytes to read
	338	* @buf: pointer to where to store result
	339	*/
	340	ssize_t pci_read_vpd(struct pci_dev dev, loff_t pos, size_t count, void buf)
	341	{
a38fccdb HK	342	ssize_t ret;
	343
	344	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
	345	dev = pci_get_func0_dev(dev);
	346	if (!dev)
	347	return -ENODEV;
	348
	349	ret = pci_vpd_read(dev, pos, count, buf);
	350	pci_dev_put(dev);
	351	return ret;
	352	}
	353
	354	return pci_vpd_read(dev, pos, count, buf);
d27f7344 HK	355	}
	356	EXPORT_SYMBOL(pci_read_vpd);
	357
	358	/**
	359	* pci_write_vpd - Write entry to Vital Product Data
	360	* @dev: PCI device struct
	361	* @pos: offset in VPD space
	362	* @count: number of bytes to write
	363	* @buf: buffer containing write data
	364	*/
	365	ssize_t pci_write_vpd(struct pci_dev dev, loff_t pos, size_t count, const void buf)
	366	{
a38fccdb HK	367	ssize_t ret;
	368
	369	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
	370	dev = pci_get_func0_dev(dev);
	371	if (!dev)
	372	return -ENODEV;
	373
	374	ret = pci_vpd_write(dev, pos, count, buf);
	375	pci_dev_put(dev);
	376	return ret;
	377	}
	378
	379	return pci_vpd_write(dev, pos, count, buf);
d27f7344 HK	380	}
	381	EXPORT_SYMBOL(pci_write_vpd);
	382
99605857 BH	383	#ifdef CONFIG_PCI_QUIRKS
	384	/*
	385	* Quirk non-zero PCI functions to route VPD access through function 0 for
	386	* devices that share VPD resources between functions. The functions are
	387	* expected to be identical devices.
	388	*/
	389	static void quirk_f0_vpd_link(struct pci_dev *dev)
	390	{
	391	struct pci_dev *f0;
	392
	393	if (!PCI_FUNC(dev->devfn))
	394	return;
	395
5881b389	396	f0 = pci_get_func0_dev(dev);
99605857 BH	397	if (!f0)
	398	return;
	399
fd00faa3	400	if (f0->vpd.cap && dev->class == f0->class &&
99605857 BH	401	dev->vendor == f0->vendor && dev->device == f0->device)
	402	dev->dev_flags \|= PCI_DEV_FLAGS_VPD_REF_F0;
	403
	404	pci_dev_put(f0);
	405	}
	406	DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
	407	PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
	408
	409	/*
	410	* If a device follows the VPD format spec, the PCI core will not read or
	411	* write past the VPD End Tag. But some vendors do not follow the VPD
	412	* format spec, so we can't tell how much data is safe to access. Devices
	413	* may behave unpredictably if we access too much. Blacklist these devices
	414	* so we don't touch VPD at all.
	415	*/
	416	static void quirk_blacklist_vpd(struct pci_dev *dev)
	417	{
fd00faa3 HK	418	dev->vpd.len = PCI_VPD_SZ_INVALID;
fd00faa3 HK	419	pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
99605857	420	}
7bac5449 HK	421	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
	422	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
	423	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
	424	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
	425	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
	426	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
	427	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
	428	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
	429	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
	430	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
	431	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
	432	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID, quirk_blacklist_vpd);
a638b5de JC	433	/*
	434	* The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
	435	* device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
	436	*/
7bac5449 HK	437	DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
7bac5449 HK	438	PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);
99605857	439
99605857 BH	440	static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
99605857 BH	441	{
3c0d551e LT	442	int chip = (dev->device & 0xf000) >> 12;
	443	int func = (dev->device & 0x0f00) >> 8;
	444	int prod = (dev->device & 0x00ff) >> 0;
	445
	446	/*
	447	* If this is a T3-based adapter, there's a 1KB VPD area at offset
	448	* 0xc00 which contains the preferred VPD values. If this is a T4 or
	449	* later based adapter, the special VPD is at offset 0x400 for the
	450	* Physical Functions (the SR-IOV Virtual Functions have no VPD
	451	* Capabilities). The PCI VPD Access core routines will normally
	452	* compute the size of the VPD by parsing the VPD Data Structure at
	453	* offset 0x000. This will result in silent failures when attempting
	454	* to accesses these other VPD areas which are beyond those computed
	455	* limits.
	456	*/
	457	if (chip == 0x0 && prod >= 0x20)
fd00faa3	458	dev->vpd.len = 8192;
3c0d551e	459	else if (chip >= 0x4 && func < 0x8)
fd00faa3	460	dev->vpd.len = 2048;
99605857	461	}
3c0d551e	462
7bac5449 HK	463	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
7bac5449 HK	464	quirk_chelsio_extend_vpd);
3c0d551e	465
99605857	466	#endif