[linux-block.git] / drivers / pci / vpd.c

// SPDX-License-Identifier: GPL-2.0
/*
 * PCI VPD support
 *
 * Copyright (C) 2010 Broadcom Corporation.
 */

#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/sched/signal.h>
#include <asm/unaligned.h>
#include "pci.h"

#define PCI_VPD_LRDT_TAG_SIZE		3
#define PCI_VPD_SRDT_LEN_MASK		0x07
#define PCI_VPD_SRDT_TAG_SIZE		1
#define PCI_VPD_STIN_END		0x0f
#define PCI_VPD_INFO_FLD_HDR_SIZE	3

static u16 pci_vpd_lrdt_size(const u8 *lrdt)
{
	return get_unaligned_le16(lrdt + 1);
}

static u8 pci_vpd_srdt_tag(const u8 *srdt)
{
	return *srdt >> 3;
}

static u8 pci_vpd_srdt_size(const u8 *srdt)
{
	return *srdt & PCI_VPD_SRDT_LEN_MASK;
}

static u8 pci_vpd_info_field_size(const u8 *info_field)
{
	return info_field[2];
}

/* VPD access through PCI 2.2+ VPD capability */

static struct pci_dev *pci_get_func0_dev(struct pci_dev *dev)
{
	return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
}

#define PCI_VPD_MAX_SIZE	(PCI_VPD_ADDR_MASK + 1)
#define PCI_VPD_SZ_INVALID	UINT_MAX

/**
 * pci_vpd_size - determine actual size of Vital Product Data
 * @dev:	pci device struct
 */
static size_t pci_vpd_size(struct pci_dev *dev)
{
	size_t off = 0, size;
	unsigned char tag, header[1+2];	/* 1 byte tag, 2 bytes length */

	while (pci_read_vpd_any(dev, off, 1, header) == 1) {
		size = 0;

		if (off == 0 && (header[0] == 0x00 || header[0] == 0xff))
			goto error;

		if (header[0] & PCI_VPD_LRDT) {
			/* Large Resource Data Type Tag */
			if (pci_read_vpd_any(dev, off + 1, 2, &header[1]) != 2) {
				pci_warn(dev, "failed VPD read at offset %zu\n",
					 off + 1);
				return off ?: PCI_VPD_SZ_INVALID;
			}
			size = pci_vpd_lrdt_size(header);
			if (off + size > PCI_VPD_MAX_SIZE)
				goto error;

			off += PCI_VPD_LRDT_TAG_SIZE + size;
		} else {
			/* Short Resource Data Type Tag */
			tag = pci_vpd_srdt_tag(header);
			size = pci_vpd_srdt_size(header);
			if (off + size > PCI_VPD_MAX_SIZE)
				goto error;

			off += PCI_VPD_SRDT_TAG_SIZE + size;
			if (tag == PCI_VPD_STIN_END)	/* End tag descriptor */
				return off;
		}
	}
	return off;

error:
	pci_info(dev, "invalid VPD tag %#04x (size %zu) at offset %zu%s\n",
		 header[0], size, off, off == 0 ?
		 "; assume missing optional EEPROM" : "");
	return off ?: PCI_VPD_SZ_INVALID;
}

static bool pci_vpd_available(struct pci_dev *dev, bool check_size)
{
	struct pci_vpd *vpd = &dev->vpd;

	if (!vpd->cap)
		return false;

	if (vpd->len == 0 && check_size) {
		vpd->len = pci_vpd_size(dev);
		if (vpd->len == PCI_VPD_SZ_INVALID) {
			vpd->cap = 0;
			return false;
		}
	}

	return true;
}

/*
 * Wait for last operation to complete.
 * This code has to spin since there is no other notification from the PCI
 * hardware. Since the VPD is often implemented by serial attachment to an
 * EEPROM, it may take many milliseconds to complete.
 * @set: if true wait for flag to be set, else wait for it to be cleared
 *
 * Returns 0 on success, negative values indicate error.
 */
static int pci_vpd_wait(struct pci_dev *dev, bool set)
{
	struct pci_vpd *vpd = &dev->vpd;
	unsigned long timeout = jiffies + msecs_to_jiffies(125);
	unsigned long max_sleep = 16;
	u16 status;
	int ret;

	do {
		ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						&status);
		if (ret < 0)
			return ret;

		if (!!(status & PCI_VPD_ADDR_F) == set)
			return 0;

		if (time_after(jiffies, timeout))
			break;

		usleep_range(10, max_sleep);
		if (max_sleep < 1024)
			max_sleep *= 2;
	} while (true);

	pci_warn(dev, "VPD access failed.  This is likely a firmware bug on this device.  Contact the card vendor for a firmware update\n");
	return -ETIMEDOUT;
}

static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
			    void *arg, bool check_size)
{
	struct pci_vpd *vpd = &dev->vpd;
	unsigned int max_len;
	int ret = 0;
	loff_t end = pos + count;
	u8 *buf = arg;

	if (!pci_vpd_available(dev, check_size))
		return -ENODEV;

	if (pos < 0)
		return -EINVAL;

	max_len = check_size ? vpd->len : PCI_VPD_MAX_SIZE;

	if (pos >= max_len)
		return 0;

	if (end > max_len) {
		end = max_len;
		count = end - pos;
	}

	if (mutex_lock_killable(&vpd->lock))
		return -EINTR;

	while (pos < end) {
		u32 val;
		unsigned int i, skip;

		if (fatal_signal_pending(current)) {
			ret = -EINTR;
			break;
		}

		ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						 pos & ~3);
		if (ret < 0)
			break;
		ret = pci_vpd_wait(dev, true);
		if (ret < 0)
			break;

		ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
		if (ret < 0)
			break;

		skip = pos & 3;
		for (i = 0;  i < sizeof(u32); i++) {
			if (i >= skip) {
				*buf++ = val;
				if (++pos == end)
					break;
			}
			val >>= 8;
		}
	}

	mutex_unlock(&vpd->lock);
	return ret ? ret : count;
}

static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
			     const void *arg, bool check_size)
{
	struct pci_vpd *vpd = &dev->vpd;
	unsigned int max_len;
	const u8 *buf = arg;
	loff_t end = pos + count;
	int ret = 0;

	if (!pci_vpd_available(dev, check_size))
		return -ENODEV;

	if (pos < 0 || (pos & 3) || (count & 3))
		return -EINVAL;

	max_len = check_size ? vpd->len : PCI_VPD_MAX_SIZE;

	if (end > max_len)
		return -EINVAL;

	if (mutex_lock_killable(&vpd->lock))
		return -EINTR;

	while (pos < end) {
		ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA,
						  get_unaligned_le32(buf));
		if (ret < 0)
			break;
		ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
						 pos | PCI_VPD_ADDR_F);
		if (ret < 0)
			break;

		ret = pci_vpd_wait(dev, false);
		if (ret < 0)
			break;

		buf += sizeof(u32);
		pos += sizeof(u32);
	}

	mutex_unlock(&vpd->lock);
	return ret ? ret : count;
}

void pci_vpd_init(struct pci_dev *dev)
{
	if (dev->vpd.len == PCI_VPD_SZ_INVALID)
		return;

	dev->vpd.cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
	mutex_init(&dev->vpd.lock);
}

static ssize_t vpd_read(struct file *filp, struct kobject *kobj,
			struct bin_attribute *bin_attr, char *buf, loff_t off,
			size_t count)
{
	struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
	struct pci_dev *vpd_dev = dev;
	ssize_t ret;

	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
		vpd_dev = pci_get_func0_dev(dev);
		if (!vpd_dev)
			return -ENODEV;
	}

	pci_config_pm_runtime_get(vpd_dev);
	ret = pci_read_vpd(vpd_dev, off, count, buf);
	pci_config_pm_runtime_put(vpd_dev);

	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
		pci_dev_put(vpd_dev);

	return ret;
}

static ssize_t vpd_write(struct file *filp, struct kobject *kobj,
			 struct bin_attribute *bin_attr, char *buf, loff_t off,
			 size_t count)
{
	struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
	struct pci_dev *vpd_dev = dev;
	ssize_t ret;

	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
		vpd_dev = pci_get_func0_dev(dev);
		if (!vpd_dev)
			return -ENODEV;
	}

	pci_config_pm_runtime_get(vpd_dev);
	ret = pci_write_vpd(vpd_dev, off, count, buf);
	pci_config_pm_runtime_put(vpd_dev);

	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
		pci_dev_put(vpd_dev);

	return ret;
}
static BIN_ATTR(vpd, 0600, vpd_read, vpd_write, 0);

static struct bin_attribute *vpd_attrs[] = {
	&bin_attr_vpd,
	NULL,
};

static umode_t vpd_attr_is_visible(struct kobject *kobj,
				   struct bin_attribute *a, int n)
{
	struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));

	if (!pdev->vpd.cap)
		return 0;

	return a->attr.mode;
}

const struct attribute_group pci_dev_vpd_attr_group = {
	.bin_attrs = vpd_attrs,
	.is_bin_visible = vpd_attr_is_visible,
};

void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size)
{
	unsigned int len;
	void *buf;
	int cnt;

	if (!pci_vpd_available(dev, true))
		return ERR_PTR(-ENODEV);

	len = dev->vpd.len;
	buf = kmalloc(len, GFP_KERNEL);
	if (!buf)
		return ERR_PTR(-ENOMEM);

	cnt = pci_read_vpd(dev, 0, len, buf);
	if (cnt != len) {
		kfree(buf);
		return ERR_PTR(-EIO);
	}

	if (size)
		*size = len;

	return buf;
}
EXPORT_SYMBOL_GPL(pci_vpd_alloc);

static int pci_vpd_find_tag(const u8 *buf, unsigned int len, u8 rdt, unsigned int *size)
{
	int i = 0;

	/* look for LRDT tags only, end tag is the only SRDT tag */
	while (i + PCI_VPD_LRDT_TAG_SIZE <= len && buf[i] & PCI_VPD_LRDT) {
		unsigned int lrdt_len = pci_vpd_lrdt_size(buf + i);
		u8 tag = buf[i];

		i += PCI_VPD_LRDT_TAG_SIZE;
		if (tag == rdt) {
			if (i + lrdt_len > len)
				lrdt_len = len - i;
			if (size)
				*size = lrdt_len;
			return i;
		}

		i += lrdt_len;
	}

	return -ENOENT;
}

int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size)
{
	return pci_vpd_find_tag(buf, len, PCI_VPD_LRDT_ID_STRING, size);
}
EXPORT_SYMBOL_GPL(pci_vpd_find_id_string);

static int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
			      unsigned int len, const char *kw)
{
	int i;

	for (i = off; i + PCI_VPD_INFO_FLD_HDR_SIZE <= off + len;) {
		if (buf[i + 0] == kw[0] &&
		    buf[i + 1] == kw[1])
			return i;

		i += PCI_VPD_INFO_FLD_HDR_SIZE +
		     pci_vpd_info_field_size(&buf[i]);
	}

	return -ENOENT;
}

static ssize_t __pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf,
			      bool check_size)
{
	ssize_t ret;

	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
		dev = pci_get_func0_dev(dev);
		if (!dev)
			return -ENODEV;

		ret = pci_vpd_read(dev, pos, count, buf, check_size);
		pci_dev_put(dev);
		return ret;
	}

	return pci_vpd_read(dev, pos, count, buf, check_size);
}

/**
 * pci_read_vpd - Read one entry from Vital Product Data
 * @dev:	PCI device struct
 * @pos:	offset in VPD space
 * @count:	number of bytes to read
 * @buf:	pointer to where to store result
 */
ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
{
	return __pci_read_vpd(dev, pos, count, buf, true);
}
EXPORT_SYMBOL(pci_read_vpd);

/* Same, but allow to access any address */
ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
{
	return __pci_read_vpd(dev, pos, count, buf, false);
}
EXPORT_SYMBOL(pci_read_vpd_any);

static ssize_t __pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count,
			       const void *buf, bool check_size)
{
	ssize_t ret;

	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
		dev = pci_get_func0_dev(dev);
		if (!dev)
			return -ENODEV;

		ret = pci_vpd_write(dev, pos, count, buf, check_size);
		pci_dev_put(dev);
		return ret;
	}

	return pci_vpd_write(dev, pos, count, buf, check_size);
}

/**
 * pci_write_vpd - Write entry to Vital Product Data
 * @dev:	PCI device struct
 * @pos:	offset in VPD space
 * @count:	number of bytes to write
 * @buf:	buffer containing write data
 */
ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
{
	return __pci_write_vpd(dev, pos, count, buf, true);
}
EXPORT_SYMBOL(pci_write_vpd);

/* Same, but allow to access any address */
ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
{
	return __pci_write_vpd(dev, pos, count, buf, false);
}
EXPORT_SYMBOL(pci_write_vpd_any);

int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
				 const char *kw, unsigned int *size)
{
	int ro_start, infokw_start;
	unsigned int ro_len, infokw_size;

	ro_start = pci_vpd_find_tag(buf, len, PCI_VPD_LRDT_RO_DATA, &ro_len);
	if (ro_start < 0)
		return ro_start;

	infokw_start = pci_vpd_find_info_keyword(buf, ro_start, ro_len, kw);
	if (infokw_start < 0)
		return infokw_start;

	infokw_size = pci_vpd_info_field_size(buf + infokw_start);
	infokw_start += PCI_VPD_INFO_FLD_HDR_SIZE;

	if (infokw_start + infokw_size > len)
		return -EINVAL;

	if (size)
		*size = infokw_size;

	return infokw_start;
}
EXPORT_SYMBOL_GPL(pci_vpd_find_ro_info_keyword);

int pci_vpd_check_csum(const void *buf, unsigned int len)
{
	const u8 *vpd = buf;
	unsigned int size;
	u8 csum = 0;
	int rv_start;

	rv_start = pci_vpd_find_ro_info_keyword(buf, len, PCI_VPD_RO_KEYWORD_CHKSUM, &size);
	if (rv_start == -ENOENT) /* no checksum in VPD */
		return 1;
	else if (rv_start < 0)
		return rv_start;

	if (!size)
		return -EINVAL;

	while (rv_start >= 0)
		csum += vpd[rv_start--];

	return csum ? -EILSEQ : 0;
}
EXPORT_SYMBOL_GPL(pci_vpd_check_csum);

#ifdef CONFIG_PCI_QUIRKS
/*
 * Quirk non-zero PCI functions to route VPD access through function 0 for
 * devices that share VPD resources between functions.  The functions are
 * expected to be identical devices.
 */
static void quirk_f0_vpd_link(struct pci_dev *dev)
{
	struct pci_dev *f0;

	if (!PCI_FUNC(dev->devfn))
		return;

	f0 = pci_get_func0_dev(dev);
	if (!f0)
		return;

	if (f0->vpd.cap && dev->class == f0->class &&
	    dev->vendor == f0->vendor && dev->device == f0->device)
		dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;

	pci_dev_put(f0);
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
			      PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);

/*
 * If a device follows the VPD format spec, the PCI core will not read or
 * write past the VPD End Tag.  But some vendors do not follow the VPD
 * format spec, so we can't tell how much data is safe to access.  Devices
 * may behave unpredictably if we access too much.  Blacklist these devices
 * so we don't touch VPD at all.
 */
static void quirk_blacklist_vpd(struct pci_dev *dev)
{
	dev->vpd.len = PCI_VPD_SZ_INVALID;
	pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID, quirk_blacklist_vpd);
/*
 * The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
 * device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
 */
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
			       PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);

static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
{
	int chip = (dev->device & 0xf000) >> 12;
	int func = (dev->device & 0x0f00) >>  8;
	int prod = (dev->device & 0x00ff) >>  0;

	/*
	 * If this is a T3-based adapter, there's a 1KB VPD area at offset
	 * 0xc00 which contains the preferred VPD values.  If this is a T4 or
	 * later based adapter, the special VPD is at offset 0x400 for the
	 * Physical Functions (the SR-IOV Virtual Functions have no VPD
	 * Capabilities).  The PCI VPD Access core routines will normally
	 * compute the size of the VPD by parsing the VPD Data Structure at
	 * offset 0x000.  This will result in silent failures when attempting
	 * to accesses these other VPD areas which are beyond those computed
	 * limits.
	 */
	if (chip == 0x0 && prod >= 0x20)
		dev->vpd.len = 8192;
	else if (chip >= 0x4 && func < 0x8)
		dev->vpd.len = 2048;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
			 quirk_chelsio_extend_vpd);

#endif
Commit	Line	Data
7328c8f4	1	// SPDX-License-Identifier: GPL-2.0
b55ac1b2	2	/*
df62ab5e	3	* PCI VPD support
b55ac1b2 MC	4	*
	5	* Copyright (C) 2010 Broadcom Corporation.
	6	*/
	7
	8	#include <linux/pci.h>
f0eb77ae	9	#include <linux/delay.h>
363c75db	10	#include <linux/export.h>
f0eb77ae	11	#include <linux/sched/signal.h>
2c208abd	12	#include <asm/unaligned.h>
f0eb77ae BH	13	#include "pci.h"
f0eb77ae BH	14
06e1913d HK	15	#define PCI_VPD_LRDT_TAG_SIZE 3
	16	#define PCI_VPD_SRDT_LEN_MASK 0x07
	17	#define PCI_VPD_SRDT_TAG_SIZE 1
	18	#define PCI_VPD_STIN_END 0x0f
	19	#define PCI_VPD_INFO_FLD_HDR_SIZE 3
	20
	21	static u16 pci_vpd_lrdt_size(const u8 *lrdt)
	22	{
2c208abd	23	return get_unaligned_le16(lrdt + 1);
06e1913d HK	24	}
	25
	26	static u8 pci_vpd_srdt_tag(const u8 *srdt)
	27	{
	28	return *srdt >> 3;
	29	}
	30
	31	static u8 pci_vpd_srdt_size(const u8 *srdt)
	32	{
	33	return *srdt & PCI_VPD_SRDT_LEN_MASK;
	34	}
	35
	36	static u8 pci_vpd_info_field_size(const u8 *info_field)
	37	{
	38	return info_field[2];
	39	}
	40
f0eb77ae BH	41	/* VPD access through PCI 2.2+ VPD capability */
f0eb77ae BH	42
5881b389 HK	43	static struct pci_dev pci_get_func0_dev(struct pci_dev dev)
	44	{
	45	return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
	46	}
	47
22ff2bce HK	48	#define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
22ff2bce HK	49	#define PCI_VPD_SZ_INVALID UINT_MAX
f0eb77ae BH	50
	51	/**
	52	* pci_vpd_size - determine actual size of Vital Product Data
	53	* @dev: pci device struct
f0eb77ae	54	*/
1285762c	55	static size_t pci_vpd_size(struct pci_dev *dev)
f0eb77ae	56	{
6303049d BH	57	size_t off = 0, size;
6303049d BH	58	unsigned char tag, header[1+2]; /* 1 byte tag, 2 bytes length */
f0eb77ae	59
3331325c	60	while (pci_read_vpd_any(dev, off, 1, header) == 1) {
6303049d	61	size = 0;
f0eb77ae	62
4e0d77f8 HK	63	if (off == 0 && (header[0] == 0x00 \|\| header[0] == 0xff))
4e0d77f8 HK	64	goto error;
d1df5f3f	65
f0eb77ae BH	66	if (header[0] & PCI_VPD_LRDT) {
f0eb77ae BH	67	/* Large Resource Data Type Tag */
3331325c	68	if (pci_read_vpd_any(dev, off + 1, 2, &header[1]) != 2) {
7fa75dd8 BH	69	pci_warn(dev, "failed VPD read at offset %zu\n",
7fa75dd8 BH	70	off + 1);
22ff2bce	71	return off ?: PCI_VPD_SZ_INVALID;
f0eb77ae	72	}
7fa75dd8 BH	73	size = pci_vpd_lrdt_size(header);
	74	if (off + size > PCI_VPD_MAX_SIZE)
	75	goto error;
	76
	77	off += PCI_VPD_LRDT_TAG_SIZE + size;
f0eb77ae BH	78	} else {
f0eb77ae BH	79	/* Short Resource Data Type Tag */
f0eb77ae	80	tag = pci_vpd_srdt_tag(header);
6303049d BH	81	size = pci_vpd_srdt_size(header);
	82	if (off + size > PCI_VPD_MAX_SIZE)
	83	goto error;
	84
	85	off += PCI_VPD_SRDT_TAG_SIZE + size;
70730db0 BH	86	if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
70730db0 BH	87	return off;
f0eb77ae BH	88	}
f0eb77ae BH	89	}
5fe204ea	90	return off;
4e0d77f8 HK	91
4e0d77f8 HK	92	error:
6303049d BH	93	pci_info(dev, "invalid VPD tag %#04x (size %zu) at offset %zu%s\n",
6303049d BH	94	header[0], size, off, off == 0 ?
4e0d77f8	95	"; assume missing optional EEPROM" : "");
22ff2bce	96	return off ?: PCI_VPD_SZ_INVALID;
f0eb77ae BH	97	}
f0eb77ae BH	98
3331325c	99	static bool pci_vpd_available(struct pci_dev *dev, bool check_size)
00e1a5d2 BH	100	{
	101	struct pci_vpd *vpd = &dev->vpd;
	102
	103	if (!vpd->cap)
	104	return false;
	105
3331325c	106	if (vpd->len == 0 && check_size) {
00e1a5d2 BH	107	vpd->len = pci_vpd_size(dev);
	108	if (vpd->len == PCI_VPD_SZ_INVALID) {
	109	vpd->cap = 0;
	110	return false;
	111	}
	112	}
	113
	114	return true;
	115	}
	116
f0eb77ae BH	117	/*
	118	* Wait for last operation to complete.
	119	* This code has to spin since there is no other notification from the PCI
	120	* hardware. Since the VPD is often implemented by serial attachment to an
	121	* EEPROM, it may take many milliseconds to complete.
fe943bd8	122	* @set: if true wait for flag to be set, else wait for it to be cleared
f0eb77ae BH	123	*
	124	* Returns 0 on success, negative values indicate error.
	125	*/
fe943bd8	126	static int pci_vpd_wait(struct pci_dev *dev, bool set)
f0eb77ae	127	{
fd00faa3	128	struct pci_vpd *vpd = &dev->vpd;
f0eb77ae BH	129	unsigned long timeout = jiffies + msecs_to_jiffies(125);
	130	unsigned long max_sleep = 16;
	131	u16 status;
	132	int ret;
	133
6eaf2781	134	do {
f0eb77ae BH	135	ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
	136	&status);
	137	if (ret < 0)
	138	return ret;
	139
fe943bd8	140	if (!!(status & PCI_VPD_ADDR_F) == set)
f0eb77ae	141	return 0;
f0eb77ae	142
6eaf2781 BK	143	if (time_after(jiffies, timeout))
	144	break;
	145
f0eb77ae BH	146	usleep_range(10, max_sleep);
	147	if (max_sleep < 1024)
	148	max_sleep *= 2;
6eaf2781	149	} while (true);
f0eb77ae BH	150
	151	pci_warn(dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
	152	return -ETIMEDOUT;
	153	}
	154
	155	static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
bf2928c7	156	void *arg, bool check_size)
f0eb77ae	157	{
fd00faa3	158	struct pci_vpd *vpd = &dev->vpd;
3331325c	159	unsigned int max_len;
91ab5d9d	160	int ret = 0;
f0eb77ae BH	161	loff_t end = pos + count;
	162	u8 *buf = arg;
	163
3331325c	164	if (!pci_vpd_available(dev, check_size))
a38fccdb HK	165	return -ENODEV;
a38fccdb HK	166
f0eb77ae BH	167	if (pos < 0)
	168	return -EINVAL;
	169
3331325c HK	170	max_len = check_size ? vpd->len : PCI_VPD_MAX_SIZE;
3331325c HK	171
bf2928c7	172	if (pos >= max_len)
f0eb77ae BH	173	return 0;
f0eb77ae BH	174
bf2928c7 HK	175	if (end > max_len) {
bf2928c7 HK	176	end = max_len;
f0eb77ae BH	177	count = end - pos;
	178	}
	179
	180	if (mutex_lock_killable(&vpd->lock))
	181	return -EINTR;
	182
f0eb77ae BH	183	while (pos < end) {
	184	u32 val;
	185	unsigned int i, skip;
	186
91ab5d9d HK	187	if (fatal_signal_pending(current)) {
	188	ret = -EINTR;
	189	break;
	190	}
	191
f0eb77ae BH	192	ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
	193	pos & ~3);
	194	if (ret < 0)
	195	break;
fe943bd8	196	ret = pci_vpd_wait(dev, true);
f0eb77ae BH	197	if (ret < 0)
	198	break;
	199
	200	ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
	201	if (ret < 0)
	202	break;
	203
	204	skip = pos & 3;
	205	for (i = 0; i < sizeof(u32); i++) {
	206	if (i >= skip) {
	207	*buf++ = val;
	208	if (++pos == end)
	209	break;
	210	}
	211	val >>= 8;
	212	}
	213	}
91ab5d9d	214
f0eb77ae BH	215	mutex_unlock(&vpd->lock);
	216	return ret ? ret : count;
	217	}
	218
	219	static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
bf2928c7	220	const void *arg, bool check_size)
f0eb77ae	221	{
fd00faa3	222	struct pci_vpd *vpd = &dev->vpd;
3331325c	223	unsigned int max_len;
f0eb77ae BH	224	const u8 *buf = arg;
	225	loff_t end = pos + count;
	226	int ret = 0;
	227
3331325c	228	if (!pci_vpd_available(dev, check_size))
a38fccdb HK	229	return -ENODEV;
a38fccdb HK	230
f0eb77ae BH	231	if (pos < 0 \|\| (pos & 3) \|\| (count & 3))
	232	return -EINVAL;
	233
3331325c HK	234	max_len = check_size ? vpd->len : PCI_VPD_MAX_SIZE;
3331325c HK	235
bf2928c7	236	if (end > max_len)
f0eb77ae BH	237	return -EINVAL;
	238
	239	if (mutex_lock_killable(&vpd->lock))
	240	return -EINTR;
	241
f0eb77ae	242	while (pos < end) {
2c208abd HK	243	ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA,
2c208abd HK	244	get_unaligned_le32(buf));
f0eb77ae BH	245	if (ret < 0)
	246	break;
	247	ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
	248	pos \| PCI_VPD_ADDR_F);
	249	if (ret < 0)
	250	break;
	251
fe943bd8	252	ret = pci_vpd_wait(dev, false);
f0eb77ae BH	253	if (ret < 0)
	254	break;
	255
2c208abd	256	buf += sizeof(u32);
f0eb77ae BH	257	pos += sizeof(u32);
f0eb77ae BH	258	}
91ab5d9d	259
f0eb77ae BH	260	mutex_unlock(&vpd->lock);
	261	return ret ? ret : count;
	262	}
	263
e947e7b1	264	void pci_vpd_init(struct pci_dev *dev)
f0eb77ae	265	{
00e1a5d2 BH	266	if (dev->vpd.len == PCI_VPD_SZ_INVALID)
	267	return;
	268
fd00faa3 HK	269	dev->vpd.cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
fd00faa3 HK	270	mutex_init(&dev->vpd.lock);
f0eb77ae	271	}
b55ac1b2	272
07b4523e BH	273	static ssize_t vpd_read(struct file filp, struct kobject kobj,
	274	struct bin_attribute bin_attr, char buf, loff_t off,
	275	size_t count)
b1c615c4 BH	276	{
b1c615c4 BH	277	struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
5cd903bc AW	278	struct pci_dev *vpd_dev = dev;
5cd903bc AW	279	ssize_t ret;
b1c615c4	280
5cd903bc AW	281	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
	282	vpd_dev = pci_get_func0_dev(dev);
	283	if (!vpd_dev)
	284	return -ENODEV;
	285	}
	286
	287	pci_config_pm_runtime_get(vpd_dev);
	288	ret = pci_read_vpd(vpd_dev, off, count, buf);
	289	pci_config_pm_runtime_put(vpd_dev);
	290
	291	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
	292	pci_dev_put(vpd_dev);
	293
	294	return ret;
b1c615c4 BH	295	}
b1c615c4 BH	296
07b4523e BH	297	static ssize_t vpd_write(struct file filp, struct kobject kobj,
	298	struct bin_attribute bin_attr, char buf, loff_t off,
	299	size_t count)
b1c615c4 BH	300	{
b1c615c4 BH	301	struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
5cd903bc AW	302	struct pci_dev *vpd_dev = dev;
	303	ssize_t ret;
	304
	305	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
	306	vpd_dev = pci_get_func0_dev(dev);
	307	if (!vpd_dev)
	308	return -ENODEV;
	309	}
	310
	311	pci_config_pm_runtime_get(vpd_dev);
	312	ret = pci_write_vpd(vpd_dev, off, count, buf);
	313	pci_config_pm_runtime_put(vpd_dev);
	314
	315	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
	316	pci_dev_put(vpd_dev);
b1c615c4	317
5cd903bc	318	return ret;
b1c615c4	319	}
d93f8399	320	static BIN_ATTR(vpd, 0600, vpd_read, vpd_write, 0);
b1c615c4	321
d93f8399 KW	322	static struct bin_attribute *vpd_attrs[] = {
	323	&bin_attr_vpd,
	324	NULL,
	325	};
b1c615c4	326
d93f8399 KW	327	static umode_t vpd_attr_is_visible(struct kobject *kobj,
d93f8399 KW	328	struct bin_attribute *a, int n)
b1c615c4	329	{
d93f8399	330	struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
b1c615c4	331
fd00faa3	332	if (!pdev->vpd.cap)
d93f8399	333	return 0;
b1c615c4	334
d93f8399	335	return a->attr.mode;
b1c615c4 BH	336	}
b1c615c4 BH	337
d93f8399 KW	338	const struct attribute_group pci_dev_vpd_attr_group = {
	339	.bin_attrs = vpd_attrs,
	340	.is_bin_visible = vpd_attr_is_visible,
	341	};
b55ac1b2	342
76f3c032 HK	343	void pci_vpd_alloc(struct pci_dev dev, unsigned int *size)
76f3c032 HK	344	{
00e1a5d2	345	unsigned int len;
76f3c032 HK	346	void *buf;
	347	int cnt;
	348
3331325c	349	if (!pci_vpd_available(dev, true))
76f3c032 HK	350	return ERR_PTR(-ENODEV);
76f3c032 HK	351
00e1a5d2	352	len = dev->vpd.len;
76f3c032 HK	353	buf = kmalloc(len, GFP_KERNEL);
	354	if (!buf)
	355	return ERR_PTR(-ENOMEM);
	356
	357	cnt = pci_read_vpd(dev, 0, len, buf);
	358	if (cnt != len) {
	359	kfree(buf);
	360	return ERR_PTR(-EIO);
	361	}
	362
	363	if (size)
	364	*size = len;
	365
	366	return buf;
	367	}
	368	EXPORT_SYMBOL_GPL(pci_vpd_alloc);
	369
46a34783	370	static int pci_vpd_find_tag(const u8 buf, unsigned int len, u8 rdt, unsigned int size)
b55ac1b2	371	{
0a08bc07	372	int i = 0;
b55ac1b2	373
0a08bc07 HK	374	/* look for LRDT tags only, end tag is the only SRDT tag */
0a08bc07 HK	375	while (i + PCI_VPD_LRDT_TAG_SIZE <= len && buf[i] & PCI_VPD_LRDT) {
46a34783 HK	376	unsigned int lrdt_len = pci_vpd_lrdt_size(buf + i);
	377	u8 tag = buf[i];
	378
	379	i += PCI_VPD_LRDT_TAG_SIZE;
	380	if (tag == rdt) {
	381	if (i + lrdt_len > len)
	382	lrdt_len = len - i;
	383	if (size)
	384	*size = lrdt_len;
0a08bc07	385	return i;
46a34783	386	}
b55ac1b2	387
46a34783	388	i += lrdt_len;
b55ac1b2 MC	389	}
	390
	391	return -ENOENT;
	392	}
4067a854	393
acfbb1b8 HK	394	int pci_vpd_find_id_string(const u8 buf, unsigned int len, unsigned int size)
	395	{
	396	return pci_vpd_find_tag(buf, len, PCI_VPD_LRDT_ID_STRING, size);
	397	}
	398	EXPORT_SYMBOL_GPL(pci_vpd_find_id_string);
	399
59b83b29	400	static int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
4067a854 MC	401	unsigned int len, const char *kw)
	402	{
	403	int i;
	404
	405	for (i = off; i + PCI_VPD_INFO_FLD_HDR_SIZE <= off + len;) {
	406	if (buf[i + 0] == kw[0] &&
	407	buf[i + 1] == kw[1])
	408	return i;
	409
	410	i += PCI_VPD_INFO_FLD_HDR_SIZE +
	411	pci_vpd_info_field_size(&buf[i]);
	412	}
	413
	414	return -ENOENT;
	415	}
99605857	416
bf2928c7 HK	417	static ssize_t __pci_read_vpd(struct pci_dev dev, loff_t pos, size_t count, void buf,
	418	bool check_size)
	419	{
	420	ssize_t ret;
	421
	422	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
	423	dev = pci_get_func0_dev(dev);
	424	if (!dev)
	425	return -ENODEV;
	426
	427	ret = pci_vpd_read(dev, pos, count, buf, check_size);
	428	pci_dev_put(dev);
	429	return ret;
	430	}
	431
	432	return pci_vpd_read(dev, pos, count, buf, check_size);
	433	}
	434
d27f7344 HK	435	/**
	436	* pci_read_vpd - Read one entry from Vital Product Data
	437	* @dev: PCI device struct
	438	* @pos: offset in VPD space
	439	* @count: number of bytes to read
	440	* @buf: pointer to where to store result
	441	*/
	442	ssize_t pci_read_vpd(struct pci_dev dev, loff_t pos, size_t count, void buf)
bf2928c7 HK	443	{
	444	return __pci_read_vpd(dev, pos, count, buf, true);
	445	}
	446	EXPORT_SYMBOL(pci_read_vpd);
	447
	448	/* Same, but allow to access any address */
	449	ssize_t pci_read_vpd_any(struct pci_dev dev, loff_t pos, size_t count, void buf)
	450	{
	451	return __pci_read_vpd(dev, pos, count, buf, false);
	452	}
	453	EXPORT_SYMBOL(pci_read_vpd_any);
	454
	455	static ssize_t __pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count,
	456	const void *buf, bool check_size)
d27f7344	457	{
a38fccdb HK	458	ssize_t ret;
	459
	460	if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
	461	dev = pci_get_func0_dev(dev);
	462	if (!dev)
	463	return -ENODEV;
	464
bf2928c7	465	ret = pci_vpd_write(dev, pos, count, buf, check_size);
a38fccdb HK	466	pci_dev_put(dev);
	467	return ret;
	468	}
	469
bf2928c7	470	return pci_vpd_write(dev, pos, count, buf, check_size);
d27f7344	471	}
d27f7344 HK	472
	473	/**
	474	* pci_write_vpd - Write entry to Vital Product Data
	475	* @dev: PCI device struct
	476	* @pos: offset in VPD space
	477	* @count: number of bytes to write
	478	* @buf: buffer containing write data
	479	*/
	480	ssize_t pci_write_vpd(struct pci_dev dev, loff_t pos, size_t count, const void buf)
	481	{
bf2928c7	482	return __pci_write_vpd(dev, pos, count, buf, true);
d27f7344 HK	483	}
	484	EXPORT_SYMBOL(pci_write_vpd);
	485
bf2928c7 HK	486	/* Same, but allow to access any address */
	487	ssize_t pci_write_vpd_any(struct pci_dev dev, loff_t pos, size_t count, const void buf)
	488	{
	489	return __pci_write_vpd(dev, pos, count, buf, false);
	490	}
	491	EXPORT_SYMBOL(pci_write_vpd_any);
	492
9e515c9f HK	493	int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
	494	const char kw, unsigned int size)
	495	{
	496	int ro_start, infokw_start;
	497	unsigned int ro_len, infokw_size;
	498
46a34783	499	ro_start = pci_vpd_find_tag(buf, len, PCI_VPD_LRDT_RO_DATA, &ro_len);
9e515c9f HK	500	if (ro_start < 0)
	501	return ro_start;
	502
9e515c9f HK	503	infokw_start = pci_vpd_find_info_keyword(buf, ro_start, ro_len, kw);
	504	if (infokw_start < 0)
	505	return infokw_start;
	506
	507	infokw_size = pci_vpd_info_field_size(buf + infokw_start);
	508	infokw_start += PCI_VPD_INFO_FLD_HDR_SIZE;
	509
	510	if (infokw_start + infokw_size > len)
	511	return -EINVAL;
	512
	513	if (size)
	514	*size = infokw_size;
	515
	516	return infokw_start;
	517	}
	518	EXPORT_SYMBOL_GPL(pci_vpd_find_ro_info_keyword);
	519
6107e5cb HK	520	int pci_vpd_check_csum(const void *buf, unsigned int len)
	521	{
	522	const u8 *vpd = buf;
	523	unsigned int size;
	524	u8 csum = 0;
	525	int rv_start;
	526
	527	rv_start = pci_vpd_find_ro_info_keyword(buf, len, PCI_VPD_RO_KEYWORD_CHKSUM, &size);
	528	if (rv_start == -ENOENT) /* no checksum in VPD */
	529	return 1;
	530	else if (rv_start < 0)
	531	return rv_start;
	532
	533	if (!size)
	534	return -EINVAL;
	535
	536	while (rv_start >= 0)
	537	csum += vpd[rv_start--];
	538
	539	return csum ? -EILSEQ : 0;
	540	}
	541	EXPORT_SYMBOL_GPL(pci_vpd_check_csum);
	542
99605857 BH	543	#ifdef CONFIG_PCI_QUIRKS
	544	/*
	545	* Quirk non-zero PCI functions to route VPD access through function 0 for
	546	* devices that share VPD resources between functions. The functions are
	547	* expected to be identical devices.
	548	*/
	549	static void quirk_f0_vpd_link(struct pci_dev *dev)
	550	{
	551	struct pci_dev *f0;
	552
	553	if (!PCI_FUNC(dev->devfn))
	554	return;
	555
5881b389	556	f0 = pci_get_func0_dev(dev);
99605857 BH	557	if (!f0)
	558	return;
	559
fd00faa3	560	if (f0->vpd.cap && dev->class == f0->class &&
99605857 BH	561	dev->vendor == f0->vendor && dev->device == f0->device)
	562	dev->dev_flags \|= PCI_DEV_FLAGS_VPD_REF_F0;
	563
	564	pci_dev_put(f0);
	565	}
	566	DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
	567	PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
	568
	569	/*
	570	* If a device follows the VPD format spec, the PCI core will not read or
	571	* write past the VPD End Tag. But some vendors do not follow the VPD
	572	* format spec, so we can't tell how much data is safe to access. Devices
	573	* may behave unpredictably if we access too much. Blacklist these devices
	574	* so we don't touch VPD at all.
	575	*/
	576	static void quirk_blacklist_vpd(struct pci_dev *dev)
	577	{
fd00faa3 HK	578	dev->vpd.len = PCI_VPD_SZ_INVALID;
fd00faa3 HK	579	pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
99605857	580	}
7bac5449 HK	581	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
	582	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
	583	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
	584	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
	585	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
	586	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
	587	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
	588	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
	589	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
	590	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
	591	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
	592	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID, quirk_blacklist_vpd);
a638b5de JC	593	/*
	594	* The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
	595	* device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
	596	*/
7bac5449 HK	597	DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
7bac5449 HK	598	PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);
99605857	599
99605857 BH	600	static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
99605857 BH	601	{
3c0d551e LT	602	int chip = (dev->device & 0xf000) >> 12;
	603	int func = (dev->device & 0x0f00) >> 8;
	604	int prod = (dev->device & 0x00ff) >> 0;
	605
	606	/*
	607	* If this is a T3-based adapter, there's a 1KB VPD area at offset
	608	* 0xc00 which contains the preferred VPD values. If this is a T4 or
	609	* later based adapter, the special VPD is at offset 0x400 for the
	610	* Physical Functions (the SR-IOV Virtual Functions have no VPD
	611	* Capabilities). The PCI VPD Access core routines will normally
	612	* compute the size of the VPD by parsing the VPD Data Structure at
	613	* offset 0x000. This will result in silent failures when attempting
	614	* to accesses these other VPD areas which are beyond those computed
	615	* limits.
	616	*/
	617	if (chip == 0x0 && prod >= 0x20)
fd00faa3	618	dev->vpd.len = 8192;
3c0d551e	619	else if (chip >= 0x4 && func < 0x8)
fd00faa3	620	dev->vpd.len = 2048;
99605857	621	}
3c0d551e	622
7bac5449 HK	623	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
7bac5449 HK	624	quirk_chelsio_extend_vpd);
3c0d551e	625
99605857	626	#endif