[linux-block.git] / drivers / pci / setup-res.c

/*
 *	drivers/pci/setup-res.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Resource sorting
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"


void pci_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	u32 new, check, mask;
	int reg;
	enum pci_bar_type type;
	struct resource *res = dev->resource + resno;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev, &region, res);

	new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
	if (res->flags & IORESOURCE_IO)
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	else
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;

	reg = pci_resource_bar(dev, resno, &type);
	if (!reg)
		return;
	if (type != pci_bar_unknown) {
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;
		new |= PCI_ROM_ADDRESS_ENABLE;
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if (res->flags & IORESOURCE_MEM_64) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			dev_err(&dev->dev, "BAR %d: error updating "
			       "(high %#08x != %#08x)\n", resno, new, check);
		}
	}
	res->flags &= ~IORESOURCE_UNSET;
	dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
		 resno, res, (unsigned long long)region.start,
		 (unsigned long long)region.end);
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root, *conflict;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		dev_info(&dev->dev, "no compatible bridge window for %pR\n",
			 res);
		return -EINVAL;
	}

	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev,
			 "address space collision: %pR conflicts with %s %pR\n",
			 res, conflict->name, conflict);
		return -EBUSY;
	}

	return 0;
}
EXPORT_SYMBOL(pci_claim_resource);

#ifdef CONFIG_PCI_QUIRKS
void pci_disable_bridge_window(struct pci_dev *dev)
{
	dev_info(&dev->dev, "disabling bridge mem windows\n");

	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}
#endif	/* CONFIG_PCI_QUIRKS */


static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
		int resno, resource_size_t size, resource_size_t align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t min;
	int ret;

	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;

	/* First, try exact prefetching match.. */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH,
				     pcibios_align_resource, dev);

	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
		/*
		 * That failed.
		 *
		 * But a prefetching area can handle a non-prefetching
		 * window (it will just not perform as well).
		 */
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);
	}
	return ret;
}

static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 
		int resno, resource_size_t size)
{
	struct resource *root, *conflict;
	resource_size_t start, end;
	int ret = 0;

	if (res->flags & IORESOURCE_IO)
		root = &ioport_resource;
	else
		root = &iomem_resource;

	start = res->start;
	end = res->end;
	res->start = dev->fw_addr[resno];
	res->end = res->start + size - 1;
	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
		 resno, res);
	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev,
			 "BAR %d: %pR conflicts with %s %pR\n", resno,
			 res, conflict->name, conflict);
		res->start = start;
		res->end = end;
		ret = 1;
	}
	return ret;
}

static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	struct pci_bus *bus;
	int ret;
	char *type;

	bus = dev->bus;
	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
		if (!bus->parent || !bus->self->transparent)
			break;
		bus = bus->parent;
	}

	if (ret) {
		if (res->flags & IORESOURCE_MEM)
			if (res->flags & IORESOURCE_PREFETCH)
				type = "mem pref";
			else
				type = "mem";
		else if (res->flags & IORESOURCE_IO)
			type = "io";
		else
			type = "unknown";
		dev_info(&dev->dev,
			 "BAR %d: can't assign %s (size %#llx)\n",
			 resno, type, (unsigned long long) resource_size(res));
	}

	return ret;
}

int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
			resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t new_size;
	int ret;

	if (!res->parent) {
		dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resouce %pR "
			 "\n", resno, res);
		return -EINVAL;
	}

	new_size = resource_size(res) + addsize + min_align;
	ret = _pci_assign_resource(dev, resno, new_size, min_align);
	if (!ret) {
		res->flags &= ~IORESOURCE_STARTALIGN;
		dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}
	return ret;
}

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t align, size;
	struct pci_bus *bus;
	int ret;

	align = pci_resource_alignment(dev, res);
	if (!align) {
		dev_info(&dev->dev, "BAR %d: can't assign %pR "
			 "(bogus alignment)\n", resno, res);
		return -EINVAL;
	}

	bus = dev->bus;
	size = resource_size(res);
	ret = _pci_assign_resource(dev, resno, size, align);

	/*
	 * If we failed to assign anything, let's try the address
	 * where firmware left it.  That at least has a chance of
	 * working, which is better than just leaving it disabled.
	 */
	if (ret < 0 && dev->fw_addr[resno])
		ret = pci_revert_fw_address(res, dev, resno, size);

	if (!ret) {
		res->flags &= ~IORESOURCE_STARTALIGN;
		dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}
	return ret;
}


/* Sort resources by alignment */
void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
{
	int i;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		struct resource *r;
		struct resource_list *list, *tmp;
		resource_size_t r_align;

		r = &dev->resource[i];

		if (r->flags & IORESOURCE_PCI_FIXED)
			continue;

		if (!(r->flags) || r->parent)
			continue;

		r_align = pci_resource_alignment(dev, r);
		if (!r_align) {
			dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
				 i, r);
			continue;
		}
		for (list = head; ; list = list->next) {
			resource_size_t align = 0;
			struct resource_list *ln = list->next;

			if (ln)
				align = pci_resource_alignment(ln->dev, ln->res);

			if (r_align > align) {
				tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
				if (!tmp)
					panic("pdev_sort_resources(): "
					      "kmalloc() failed!\n");
				tmp->next = ln;
				tmp->res = r;
				tmp->dev = dev;
				list->next = tmp;
				break;
			}
		}
	}
}

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (!r->parent) {
			dev_err(&dev->dev, "device not available "
				"(can't reserve %pR)\n", r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
			 old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-res.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	* David Miller (davem@redhat.com)
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
	13
	14	/*
	15	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	16	* Resource sorting
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
	21	#include <linux/pci.h>
	22	#include <linux/errno.h>
	23	#include <linux/ioport.h>
	24	#include <linux/cache.h>
	25	#include <linux/slab.h>
	26	#include "pci.h"
	27
	28
14add80b	29	void pci_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	30	{
	31	struct pci_bus_region region;
	32	u32 new, check, mask;
	33	int reg;
613e7ed6	34	enum pci_bar_type type;
14add80b	35	struct resource *res = dev->resource + resno;
1da177e4	36
fb0f2b40 RB	37	/*
	38	* Ignore resources for unimplemented BARs and unused resource slots
	39	* for 64 bit BARs.
	40	*/
cf7bee5a IK	41	if (!res->flags)
	42	return;
	43
fb0f2b40 RB	44	/*
	45	* Ignore non-moveable resources. This might be legacy resources for
	46	* which no functional BAR register exists or another important
80ccba11	47	* system resource we shouldn't move around.
fb0f2b40 RB	48	*/
	49	if (res->flags & IORESOURCE_PCI_FIXED)
	50	return;
	51
1da177e4 LT	52	pcibios_resource_to_bus(dev, &region, res);
1da177e4 LT	53
1da177e4 LT	54	new = region.start \| (res->flags & PCI_REGION_FLAG_MASK);
	55	if (res->flags & IORESOURCE_IO)
	56	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	57	else
	58	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
	59
613e7ed6 YZ	60	reg = pci_resource_bar(dev, resno, &type);
	61	if (!reg)
	62	return;
	63	if (type != pci_bar_unknown) {
755528c8 LT	64	if (!(res->flags & IORESOURCE_ROM_ENABLE))
	65	return;
	66	new \|= PCI_ROM_ADDRESS_ENABLE;
1da177e4 LT	67	}
	68
	69	pci_write_config_dword(dev, reg, new);
	70	pci_read_config_dword(dev, reg, &check);
	71
	72	if ((new ^ check) & mask) {
80ccba11 BH	73	dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11 BH	74	resno, new, check);
1da177e4 LT	75	}
1da177e4 LT	76
28c6821a	77	if (res->flags & IORESOURCE_MEM_64) {
cf7bee5a	78	new = region.start >> 16 >> 16;
1da177e4 LT	79	pci_write_config_dword(dev, reg + 4, new);
	80	pci_read_config_dword(dev, reg + 4, &check);
	81	if (check != new) {
80ccba11 BH	82	dev_err(&dev->dev, "BAR %d: error updating "
80ccba11 BH	83	"(high %#08x != %#08x)\n", resno, new, check);
1da177e4 LT	84	}
	85	}
	86	res->flags &= ~IORESOURCE_UNSET;
1bcd495b	87	dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
865df576 BH	88	resno, res, (unsigned long long)region.start,
865df576 BH	89	(unsigned long long)region.end);
1da177e4 LT	90	}
1da177e4 LT	91
96bde06a	92	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	93	{
1da177e4 LT	94	struct resource *res = &dev->resource[resource];
966f3a75	95	struct resource root, conflict;
1da177e4	96
cebd78a8	97	root = pci_find_parent_resource(dev, res);
865df576	98	if (!root) {
f6d440da BH	99	dev_info(&dev->dev, "no compatible bridge window for %pR\n",
f6d440da BH	100	res);
865df576	101	return -EINVAL;
1da177e4 LT	102	}
1da177e4 LT	103
966f3a75 BH	104	conflict = request_resource_conflict(root, res);
966f3a75 BH	105	if (conflict) {
f6d440da BH	106	dev_info(&dev->dev,
	107	"address space collision: %pR conflicts with %s %pR\n",
	108	res, conflict->name, conflict);
966f3a75 BH	109	return -EBUSY;
966f3a75 BH	110	}
865df576	111
966f3a75	112	return 0;
1da177e4	113	}
eaa959df	114	EXPORT_SYMBOL(pci_claim_resource);
1da177e4	115
32a9a682 YS	116	#ifdef CONFIG_PCI_QUIRKS
	117	void pci_disable_bridge_window(struct pci_dev *dev)
	118	{
865df576	119	dev_info(&dev->dev, "disabling bridge mem windows\n");
32a9a682 YS	120
	121	/* MMIO Base/Limit */
	122	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	123
	124	/* Prefetchable MMIO Base/Limit */
	125	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	126	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	127	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	128	}
	129	#endif /* CONFIG_PCI_QUIRKS */
	130
2bbc6942 RP	131
2bbc6942 RP	132
d09ee968	133	static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
2bbc6942	134	int resno, resource_size_t size, resource_size_t align)
1da177e4	135	{
1da177e4	136	struct resource *res = dev->resource + resno;
2bbc6942	137	resource_size_t min;
1da177e4 LT	138	int ret;
1da177e4 LT	139
1da177e4	140	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
1da177e4 LT	141
	142	/* First, try exact prefetching match.. */
	143	ret = pci_bus_alloc_resource(bus, res, size, align, min,
	144	IORESOURCE_PREFETCH,
	145	pcibios_align_resource, dev);
	146
	147	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
	148	/*
	149	* That failed.
	150	*
	151	* But a prefetching area can handle a non-prefetching
	152	* window (it will just not perform as well).
	153	*/
	154	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
	155	pcibios_align_resource, dev);
	156	}
2bbc6942 RP	157	return ret;
2bbc6942 RP	158	}
1da177e4	159
2bbc6942 RP	160	static int pci_revert_fw_address(struct resource res, struct pci_dev dev,
	161	int resno, resource_size_t size)
	162	{
	163	struct resource root, conflict;
	164	resource_size_t start, end;
	165	int ret = 0;
58c84eda	166
2bbc6942 RP	167	if (res->flags & IORESOURCE_IO)
	168	root = &ioport_resource;
	169	else
	170	root = &iomem_resource;
	171
	172	start = res->start;
	173	end = res->end;
	174	res->start = dev->fw_addr[resno];
	175	res->end = res->start + size - 1;
	176	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
	177	resno, res);
	178	conflict = request_resource_conflict(root, res);
	179	if (conflict) {
	180	dev_info(&dev->dev,
	181	"BAR %d: %pR conflicts with %s %pR\n", resno,
	182	res, conflict->name, conflict);
	183	res->start = start;
	184	res->end = end;
	185	ret = 1;
	186	}
	187	return ret;
	188	}
	189
	190	static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
	191	{
	192	struct resource *res = dev->resource + resno;
	193	struct pci_bus *bus;
	194	int ret;
	195	char *type;
58c84eda	196
2bbc6942 RP	197	bus = dev->bus;
	198	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
	199	if (!bus->parent \|\| !bus->self->transparent)
	200	break;
	201	bus = bus->parent;
	202	}
	203
	204	if (ret) {
	205	if (res->flags & IORESOURCE_MEM)
	206	if (res->flags & IORESOURCE_PREFETCH)
	207	type = "mem pref";
	208	else
	209	type = "mem";
	210	else if (res->flags & IORESOURCE_IO)
	211	type = "io";
58c84eda	212	else
2bbc6942 RP	213	type = "unknown";
	214	dev_info(&dev->dev,
	215	"BAR %d: can't assign %s (size %#llx)\n",
	216	resno, type, (unsigned long long) resource_size(res));
58c84eda BH	217	}
58c84eda BH	218
2bbc6942 RP	219	return ret;
	220	}
	221
	222	int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
	223	resource_size_t min_align)
	224	{
	225	struct resource *res = dev->resource + resno;
	226	resource_size_t new_size;
	227	int ret;
	228
	229	if (!res->parent) {
	230	dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resouce %pR "
	231	"\n", resno, res);
	232	return -EINVAL;
	233	}
	234
	235	new_size = resource_size(res) + addsize + min_align;
	236	ret = _pci_assign_resource(dev, resno, new_size, min_align);
d09ee968	237	if (!ret) {
88452565	238	res->flags &= ~IORESOURCE_STARTALIGN;
865df576	239	dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
88452565	240	if (resno < PCI_BRIDGE_RESOURCES)
14add80b	241	pci_update_resource(dev, resno);
1da177e4	242	}
1da177e4 LT	243	return ret;
	244	}
	245
d09ee968 YL	246	int pci_assign_resource(struct pci_dev *dev, int resno)
	247	{
	248	struct resource *res = dev->resource + resno;
2bbc6942	249	resource_size_t align, size;
d09ee968 YL	250	struct pci_bus *bus;
	251	int ret;
	252
6faf17f6	253	align = pci_resource_alignment(dev, res);
d09ee968	254	if (!align) {
865df576	255	dev_info(&dev->dev, "BAR %d: can't assign %pR "
a369c791	256	"(bogus alignment)\n", resno, res);
d09ee968 YL	257	return -EINVAL;
	258	}
	259
	260	bus = dev->bus;
2bbc6942 RP	261	size = resource_size(res);
2bbc6942 RP	262	ret = _pci_assign_resource(dev, resno, size, align);
d09ee968	263
2bbc6942 RP	264	/*
	265	* If we failed to assign anything, let's try the address
	266	* where firmware left it. That at least has a chance of
	267	* working, which is better than just leaving it disabled.
	268	*/
	269	if (ret < 0 && dev->fw_addr[resno])
	270	ret = pci_revert_fw_address(res, dev, resno, size);
d09ee968	271
2bbc6942 RP	272	if (!ret) {
	273	res->flags &= ~IORESOURCE_STARTALIGN;
	274	dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
	275	if (resno < PCI_BRIDGE_RESOURCES)
	276	pci_update_resource(dev, resno);
	277	}
d09ee968 YL	278	return ret;
	279	}
	280
2bbc6942	281
1da177e4	282	/* Sort resources by alignment */
96bde06a	283	void pdev_sort_resources(struct pci_dev dev, struct resource_list head)
1da177e4 LT	284	{
	285	int i;
	286
	287	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	288	struct resource *r;
	289	struct resource_list list, tmp;
e31dd6e4	290	resource_size_t r_align;
1da177e4 LT	291
1da177e4 LT	292	r = &dev->resource[i];
fb0f2b40 RB	293
	294	if (r->flags & IORESOURCE_PCI_FIXED)
	295	continue;
	296
1da177e4 LT	297	if (!(r->flags) \|\| r->parent)
1da177e4 LT	298	continue;
88452565	299
6faf17f6	300	r_align = pci_resource_alignment(dev, r);
1da177e4	301	if (!r_align) {
c7dabef8	302	dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
a369c791	303	i, r);
1da177e4 LT	304	continue;
1da177e4 LT	305	}
1da177e4	306	for (list = head; ; list = list->next) {
e31dd6e4	307	resource_size_t align = 0;
1da177e4	308	struct resource_list *ln = list->next;
88452565 IK	309
88452565 IK	310	if (ln)
6faf17f6	311	align = pci_resource_alignment(ln->dev, ln->res);
88452565	312
1da177e4 LT	313	if (r_align > align) {
	314	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
	315	if (!tmp)
	316	panic("pdev_sort_resources(): "
	317	"kmalloc() failed!\n");
	318	tmp->next = ln;
	319	tmp->res = r;
	320	tmp->dev = dev;
	321	list->next = tmp;
	322	break;
	323	}
	324	}
	325	}
	326	}
842de40d BH	327
	328	int pci_enable_resources(struct pci_dev *dev, int mask)
	329	{
	330	u16 cmd, old_cmd;
	331	int i;
	332	struct resource *r;
	333
	334	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	335	old_cmd = cmd;
	336
	337	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	338	if (!(mask & (1 << i)))
	339	continue;
	340
	341	r = &dev->resource[i];
	342
	343	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	344	continue;
	345	if ((i == PCI_ROM_RESOURCE) &&
	346	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	347	continue;
	348
	349	if (!r->parent) {
865df576 BH	350	dev_err(&dev->dev, "device not available "
865df576 BH	351	"(can't reserve %pR)\n", r);
842de40d BH	352	return -EINVAL;
	353	}
	354
	355	if (r->flags & IORESOURCE_IO)
	356	cmd \|= PCI_COMMAND_IO;
	357	if (r->flags & IORESOURCE_MEM)
	358	cmd \|= PCI_COMMAND_MEMORY;
	359	}
	360
	361	if (cmd != old_cmd) {
	362	dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
	363	old_cmd, cmd);
	364	pci_write_config_word(dev, PCI_COMMAND, cmd);
	365	}
	366	return 0;
	367	}