Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-res.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */ | |
13 | ||
14 | /* | |
15 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Resource sorting | |
17 | */ | |
18 | ||
1da177e4 | 19 | #include <linux/kernel.h> |
363c75db | 20 | #include <linux/export.h> |
1da177e4 LT |
21 | #include <linux/pci.h> |
22 | #include <linux/errno.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/cache.h> | |
25 | #include <linux/slab.h> | |
26 | #include "pci.h" | |
27 | ||
28 | ||
14add80b | 29 | void pci_update_resource(struct pci_dev *dev, int resno) |
1da177e4 LT |
30 | { |
31 | struct pci_bus_region region; | |
9aac537e BH |
32 | bool disable; |
33 | u16 cmd; | |
1da177e4 LT |
34 | u32 new, check, mask; |
35 | int reg; | |
613e7ed6 | 36 | enum pci_bar_type type; |
14add80b | 37 | struct resource *res = dev->resource + resno; |
1da177e4 | 38 | |
fb0f2b40 RB |
39 | /* |
40 | * Ignore resources for unimplemented BARs and unused resource slots | |
41 | * for 64 bit BARs. | |
42 | */ | |
cf7bee5a IK |
43 | if (!res->flags) |
44 | return; | |
45 | ||
cd8a4d36 BH |
46 | if (res->flags & IORESOURCE_UNSET) |
47 | return; | |
48 | ||
fb0f2b40 RB |
49 | /* |
50 | * Ignore non-moveable resources. This might be legacy resources for | |
51 | * which no functional BAR register exists or another important | |
80ccba11 | 52 | * system resource we shouldn't move around. |
fb0f2b40 RB |
53 | */ |
54 | if (res->flags & IORESOURCE_PCI_FIXED) | |
55 | return; | |
56 | ||
fc279850 | 57 | pcibios_resource_to_bus(dev->bus, ®ion, res); |
1da177e4 | 58 | |
1da177e4 LT |
59 | new = region.start | (res->flags & PCI_REGION_FLAG_MASK); |
60 | if (res->flags & IORESOURCE_IO) | |
61 | mask = (u32)PCI_BASE_ADDRESS_IO_MASK; | |
62 | else | |
63 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
64 | ||
613e7ed6 YZ |
65 | reg = pci_resource_bar(dev, resno, &type); |
66 | if (!reg) | |
67 | return; | |
68 | if (type != pci_bar_unknown) { | |
755528c8 LT |
69 | if (!(res->flags & IORESOURCE_ROM_ENABLE)) |
70 | return; | |
71 | new |= PCI_ROM_ADDRESS_ENABLE; | |
1da177e4 LT |
72 | } |
73 | ||
9aac537e BH |
74 | /* |
75 | * We can't update a 64-bit BAR atomically, so when possible, | |
76 | * disable decoding so that a half-updated BAR won't conflict | |
77 | * with another device. | |
78 | */ | |
79 | disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on; | |
80 | if (disable) { | |
81 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
82 | pci_write_config_word(dev, PCI_COMMAND, | |
83 | cmd & ~PCI_COMMAND_MEMORY); | |
84 | } | |
85 | ||
1da177e4 LT |
86 | pci_write_config_dword(dev, reg, new); |
87 | pci_read_config_dword(dev, reg, &check); | |
88 | ||
89 | if ((new ^ check) & mask) { | |
80ccba11 BH |
90 | dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", |
91 | resno, new, check); | |
1da177e4 LT |
92 | } |
93 | ||
28c6821a | 94 | if (res->flags & IORESOURCE_MEM_64) { |
cf7bee5a | 95 | new = region.start >> 16 >> 16; |
1da177e4 LT |
96 | pci_write_config_dword(dev, reg + 4, new); |
97 | pci_read_config_dword(dev, reg + 4, &check); | |
98 | if (check != new) { | |
227f0647 RD |
99 | dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n", |
100 | resno, new, check); | |
1da177e4 LT |
101 | } |
102 | } | |
9aac537e BH |
103 | |
104 | if (disable) | |
105 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1da177e4 LT |
106 | } |
107 | ||
96bde06a | 108 | int pci_claim_resource(struct pci_dev *dev, int resource) |
1da177e4 LT |
109 | { |
110 | struct resource *res = &dev->resource[resource]; | |
966f3a75 | 111 | struct resource *root, *conflict; |
1da177e4 | 112 | |
29003beb BH |
113 | if (res->flags & IORESOURCE_UNSET) { |
114 | dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n", | |
115 | resource, res); | |
116 | return -EINVAL; | |
117 | } | |
118 | ||
cebd78a8 | 119 | root = pci_find_parent_resource(dev, res); |
865df576 | 120 | if (!root) { |
29003beb BH |
121 | dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n", |
122 | resource, res); | |
865df576 | 123 | return -EINVAL; |
1da177e4 LT |
124 | } |
125 | ||
966f3a75 BH |
126 | conflict = request_resource_conflict(root, res); |
127 | if (conflict) { | |
29003beb BH |
128 | dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n", |
129 | resource, res, conflict->name, conflict); | |
966f3a75 BH |
130 | return -EBUSY; |
131 | } | |
865df576 | 132 | |
966f3a75 | 133 | return 0; |
1da177e4 | 134 | } |
eaa959df | 135 | EXPORT_SYMBOL(pci_claim_resource); |
1da177e4 | 136 | |
32a9a682 YS |
137 | void pci_disable_bridge_window(struct pci_dev *dev) |
138 | { | |
865df576 | 139 | dev_info(&dev->dev, "disabling bridge mem windows\n"); |
32a9a682 YS |
140 | |
141 | /* MMIO Base/Limit */ | |
142 | pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); | |
143 | ||
144 | /* Prefetchable MMIO Base/Limit */ | |
145 | pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); | |
146 | pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); | |
147 | pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); | |
148 | } | |
2bbc6942 | 149 | |
6535943f MS |
150 | /* |
151 | * Generic function that returns a value indicating that the device's | |
152 | * original BIOS BAR address was not saved and so is not available for | |
153 | * reinstatement. | |
154 | * | |
155 | * Can be over-ridden by architecture specific code that implements | |
156 | * reinstatement functionality rather than leaving it disabled when | |
157 | * normal allocation attempts fail. | |
158 | */ | |
159 | resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx) | |
160 | { | |
161 | return 0; | |
162 | } | |
163 | ||
f7625980 | 164 | static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, |
2bbc6942 RP |
165 | int resno, resource_size_t size) |
166 | { | |
167 | struct resource *root, *conflict; | |
6535943f | 168 | resource_size_t fw_addr, start, end; |
58c84eda | 169 | |
6535943f MS |
170 | fw_addr = pcibios_retrieve_fw_addr(dev, resno); |
171 | if (!fw_addr) | |
94778835 | 172 | return -ENOMEM; |
6535943f | 173 | |
2bbc6942 RP |
174 | start = res->start; |
175 | end = res->end; | |
6535943f | 176 | res->start = fw_addr; |
2bbc6942 | 177 | res->end = res->start + size - 1; |
351fc6d1 MS |
178 | |
179 | root = pci_find_parent_resource(dev, res); | |
180 | if (!root) { | |
181 | if (res->flags & IORESOURCE_IO) | |
182 | root = &ioport_resource; | |
183 | else | |
184 | root = &iomem_resource; | |
185 | } | |
186 | ||
2bbc6942 RP |
187 | dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n", |
188 | resno, res); | |
189 | conflict = request_resource_conflict(root, res); | |
190 | if (conflict) { | |
94778835 BH |
191 | dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n", |
192 | resno, res, conflict->name, conflict); | |
2bbc6942 RP |
193 | res->start = start; |
194 | res->end = end; | |
94778835 | 195 | return -EBUSY; |
2bbc6942 | 196 | } |
94778835 | 197 | return 0; |
2bbc6942 RP |
198 | } |
199 | ||
fe6dacdb BH |
200 | static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, |
201 | int resno, resource_size_t size, resource_size_t align) | |
202 | { | |
203 | struct resource *res = dev->resource + resno; | |
204 | resource_size_t min; | |
205 | int ret; | |
206 | ||
207 | min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; | |
208 | ||
67d29b5c BH |
209 | /* |
210 | * First, try exact prefetching match. Even if a 64-bit | |
211 | * prefetchable bridge window is below 4GB, we can't put a 32-bit | |
212 | * prefetchable resource in it because pbus_size_mem() assumes a | |
213 | * 64-bit window will contain no 32-bit resources. If we assign | |
214 | * things differently than they were sized, not everything will fit. | |
215 | */ | |
fe6dacdb | 216 | ret = pci_bus_alloc_resource(bus, res, size, align, min, |
5b285415 | 217 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64, |
fe6dacdb | 218 | pcibios_align_resource, dev); |
d3689df0 BH |
219 | if (ret == 0) |
220 | return 0; | |
fe6dacdb | 221 | |
67d29b5c BH |
222 | /* |
223 | * If the prefetchable window is only 32 bits wide, we can put | |
224 | * 64-bit prefetchable resources in it. | |
225 | */ | |
d3689df0 | 226 | if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == |
5b285415 | 227 | (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { |
5b285415 YL |
228 | ret = pci_bus_alloc_resource(bus, res, size, align, min, |
229 | IORESOURCE_PREFETCH, | |
fe6dacdb | 230 | pcibios_align_resource, dev); |
d3689df0 BH |
231 | if (ret == 0) |
232 | return 0; | |
fe6dacdb | 233 | } |
5b285415 | 234 | |
67d29b5c BH |
235 | /* |
236 | * If we didn't find a better match, we can put any memory resource | |
237 | * in a non-prefetchable window. If this resource is 32 bits and | |
238 | * non-prefetchable, the first call already tried the only possibility | |
239 | * so we don't need to try again. | |
240 | */ | |
241 | if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) | |
fe6dacdb BH |
242 | ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, |
243 | pcibios_align_resource, dev); | |
67d29b5c | 244 | |
fe6dacdb BH |
245 | return ret; |
246 | } | |
247 | ||
d6776e6d NR |
248 | static int _pci_assign_resource(struct pci_dev *dev, int resno, |
249 | resource_size_t size, resource_size_t min_align) | |
2bbc6942 RP |
250 | { |
251 | struct resource *res = dev->resource + resno; | |
252 | struct pci_bus *bus; | |
253 | int ret; | |
254 | char *type; | |
58c84eda | 255 | |
2bbc6942 RP |
256 | bus = dev->bus; |
257 | while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { | |
258 | if (!bus->parent || !bus->self->transparent) | |
259 | break; | |
260 | bus = bus->parent; | |
261 | } | |
262 | ||
263 | if (ret) { | |
264 | if (res->flags & IORESOURCE_MEM) | |
265 | if (res->flags & IORESOURCE_PREFETCH) | |
266 | type = "mem pref"; | |
267 | else | |
268 | type = "mem"; | |
269 | else if (res->flags & IORESOURCE_IO) | |
270 | type = "io"; | |
58c84eda | 271 | else |
2bbc6942 RP |
272 | type = "unknown"; |
273 | dev_info(&dev->dev, | |
274 | "BAR %d: can't assign %s (size %#llx)\n", | |
275 | resno, type, (unsigned long long) resource_size(res)); | |
58c84eda BH |
276 | } |
277 | ||
2bbc6942 RP |
278 | return ret; |
279 | } | |
280 | ||
d09ee968 YL |
281 | int pci_assign_resource(struct pci_dev *dev, int resno) |
282 | { | |
283 | struct resource *res = dev->resource + resno; | |
2bbc6942 | 284 | resource_size_t align, size; |
d09ee968 YL |
285 | int ret; |
286 | ||
bd064f0a | 287 | res->flags |= IORESOURCE_UNSET; |
6faf17f6 | 288 | align = pci_resource_alignment(dev, res); |
d09ee968 | 289 | if (!align) { |
227f0647 RD |
290 | dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n", |
291 | resno, res); | |
d09ee968 YL |
292 | return -EINVAL; |
293 | } | |
294 | ||
2bbc6942 RP |
295 | size = resource_size(res); |
296 | ret = _pci_assign_resource(dev, resno, size, align); | |
d09ee968 | 297 | |
2bbc6942 RP |
298 | /* |
299 | * If we failed to assign anything, let's try the address | |
300 | * where firmware left it. That at least has a chance of | |
301 | * working, which is better than just leaving it disabled. | |
302 | */ | |
6535943f | 303 | if (ret < 0) |
2bbc6942 | 304 | ret = pci_revert_fw_address(res, dev, resno, size); |
d09ee968 | 305 | |
94778835 | 306 | if (ret < 0) |
28f6dbe2 BH |
307 | return ret; |
308 | ||
309 | res->flags &= ~IORESOURCE_UNSET; | |
310 | res->flags &= ~IORESOURCE_STARTALIGN; | |
311 | dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); | |
312 | if (resno < PCI_BRIDGE_RESOURCES) | |
313 | pci_update_resource(dev, resno); | |
314 | ||
315 | return 0; | |
d09ee968 | 316 | } |
b7fe9434 | 317 | EXPORT_SYMBOL(pci_assign_resource); |
d09ee968 | 318 | |
fe6dacdb BH |
319 | int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize, |
320 | resource_size_t min_align) | |
321 | { | |
322 | struct resource *res = dev->resource + resno; | |
c3337708 | 323 | unsigned long flags; |
fe6dacdb BH |
324 | resource_size_t new_size; |
325 | int ret; | |
326 | ||
c3337708 | 327 | flags = res->flags; |
bd064f0a | 328 | res->flags |= IORESOURCE_UNSET; |
fe6dacdb | 329 | if (!res->parent) { |
227f0647 RD |
330 | dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n", |
331 | resno, res); | |
fe6dacdb BH |
332 | return -EINVAL; |
333 | } | |
334 | ||
335 | /* already aligned with min_align */ | |
336 | new_size = resource_size(res) + addsize; | |
337 | ret = _pci_assign_resource(dev, resno, new_size, min_align); | |
28f6dbe2 | 338 | if (ret) { |
c3337708 GC |
339 | res->flags = flags; |
340 | dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n", | |
341 | resno, res, (unsigned long long) addsize); | |
28f6dbe2 | 342 | return ret; |
fe6dacdb | 343 | } |
c3337708 | 344 | |
28f6dbe2 BH |
345 | res->flags &= ~IORESOURCE_UNSET; |
346 | res->flags &= ~IORESOURCE_STARTALIGN; | |
347 | dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res); | |
348 | if (resno < PCI_BRIDGE_RESOURCES) | |
349 | pci_update_resource(dev, resno); | |
350 | ||
351 | return 0; | |
fe6dacdb BH |
352 | } |
353 | ||
842de40d BH |
354 | int pci_enable_resources(struct pci_dev *dev, int mask) |
355 | { | |
356 | u16 cmd, old_cmd; | |
357 | int i; | |
358 | struct resource *r; | |
359 | ||
360 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
361 | old_cmd = cmd; | |
362 | ||
363 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
364 | if (!(mask & (1 << i))) | |
365 | continue; | |
366 | ||
367 | r = &dev->resource[i]; | |
368 | ||
369 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
370 | continue; | |
371 | if ((i == PCI_ROM_RESOURCE) && | |
372 | (!(r->flags & IORESOURCE_ROM_ENABLE))) | |
373 | continue; | |
374 | ||
3cedcc36 BH |
375 | if (r->flags & IORESOURCE_UNSET) { |
376 | dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n", | |
377 | i, r); | |
378 | return -EINVAL; | |
379 | } | |
380 | ||
842de40d | 381 | if (!r->parent) { |
3cedcc36 BH |
382 | dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n", |
383 | i, r); | |
842de40d BH |
384 | return -EINVAL; |
385 | } | |
386 | ||
387 | if (r->flags & IORESOURCE_IO) | |
388 | cmd |= PCI_COMMAND_IO; | |
389 | if (r->flags & IORESOURCE_MEM) | |
390 | cmd |= PCI_COMMAND_MEMORY; | |
391 | } | |
392 | ||
393 | if (cmd != old_cmd) { | |
394 | dev_info(&dev->dev, "enabling device (%04x -> %04x)\n", | |
395 | old_cmd, cmd); | |
396 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
397 | } | |
398 | return 0; | |
399 | } |