Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-res.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */ | |
13 | ||
14 | /* | |
15 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Resource sorting | |
17 | */ | |
18 | ||
1da177e4 | 19 | #include <linux/kernel.h> |
363c75db | 20 | #include <linux/export.h> |
1da177e4 LT |
21 | #include <linux/pci.h> |
22 | #include <linux/errno.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/cache.h> | |
25 | #include <linux/slab.h> | |
26 | #include "pci.h" | |
27 | ||
28 | ||
14add80b | 29 | void pci_update_resource(struct pci_dev *dev, int resno) |
1da177e4 LT |
30 | { |
31 | struct pci_bus_region region; | |
9aac537e BH |
32 | bool disable; |
33 | u16 cmd; | |
1da177e4 LT |
34 | u32 new, check, mask; |
35 | int reg; | |
613e7ed6 | 36 | enum pci_bar_type type; |
14add80b | 37 | struct resource *res = dev->resource + resno; |
1da177e4 | 38 | |
fb0f2b40 RB |
39 | /* |
40 | * Ignore resources for unimplemented BARs and unused resource slots | |
41 | * for 64 bit BARs. | |
42 | */ | |
cf7bee5a IK |
43 | if (!res->flags) |
44 | return; | |
45 | ||
cd8a4d36 BH |
46 | if (res->flags & IORESOURCE_UNSET) |
47 | return; | |
48 | ||
fb0f2b40 RB |
49 | /* |
50 | * Ignore non-moveable resources. This might be legacy resources for | |
51 | * which no functional BAR register exists or another important | |
80ccba11 | 52 | * system resource we shouldn't move around. |
fb0f2b40 RB |
53 | */ |
54 | if (res->flags & IORESOURCE_PCI_FIXED) | |
55 | return; | |
56 | ||
fc279850 | 57 | pcibios_resource_to_bus(dev->bus, ®ion, res); |
1da177e4 | 58 | |
1da177e4 LT |
59 | new = region.start | (res->flags & PCI_REGION_FLAG_MASK); |
60 | if (res->flags & IORESOURCE_IO) | |
61 | mask = (u32)PCI_BASE_ADDRESS_IO_MASK; | |
62 | else | |
63 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
64 | ||
613e7ed6 YZ |
65 | reg = pci_resource_bar(dev, resno, &type); |
66 | if (!reg) | |
67 | return; | |
68 | if (type != pci_bar_unknown) { | |
755528c8 LT |
69 | if (!(res->flags & IORESOURCE_ROM_ENABLE)) |
70 | return; | |
71 | new |= PCI_ROM_ADDRESS_ENABLE; | |
1da177e4 LT |
72 | } |
73 | ||
9aac537e BH |
74 | /* |
75 | * We can't update a 64-bit BAR atomically, so when possible, | |
76 | * disable decoding so that a half-updated BAR won't conflict | |
77 | * with another device. | |
78 | */ | |
79 | disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on; | |
80 | if (disable) { | |
81 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
82 | pci_write_config_word(dev, PCI_COMMAND, | |
83 | cmd & ~PCI_COMMAND_MEMORY); | |
84 | } | |
85 | ||
1da177e4 LT |
86 | pci_write_config_dword(dev, reg, new); |
87 | pci_read_config_dword(dev, reg, &check); | |
88 | ||
89 | if ((new ^ check) & mask) { | |
80ccba11 BH |
90 | dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", |
91 | resno, new, check); | |
1da177e4 LT |
92 | } |
93 | ||
28c6821a | 94 | if (res->flags & IORESOURCE_MEM_64) { |
cf7bee5a | 95 | new = region.start >> 16 >> 16; |
1da177e4 LT |
96 | pci_write_config_dword(dev, reg + 4, new); |
97 | pci_read_config_dword(dev, reg + 4, &check); | |
98 | if (check != new) { | |
227f0647 RD |
99 | dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n", |
100 | resno, new, check); | |
1da177e4 LT |
101 | } |
102 | } | |
9aac537e BH |
103 | |
104 | if (disable) | |
105 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1da177e4 LT |
106 | } |
107 | ||
96bde06a | 108 | int pci_claim_resource(struct pci_dev *dev, int resource) |
1da177e4 LT |
109 | { |
110 | struct resource *res = &dev->resource[resource]; | |
966f3a75 | 111 | struct resource *root, *conflict; |
1da177e4 | 112 | |
29003beb BH |
113 | if (res->flags & IORESOURCE_UNSET) { |
114 | dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n", | |
115 | resource, res); | |
116 | return -EINVAL; | |
117 | } | |
118 | ||
cebd78a8 | 119 | root = pci_find_parent_resource(dev, res); |
865df576 | 120 | if (!root) { |
29003beb BH |
121 | dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n", |
122 | resource, res); | |
c770cb4c | 123 | res->flags |= IORESOURCE_UNSET; |
865df576 | 124 | return -EINVAL; |
1da177e4 LT |
125 | } |
126 | ||
966f3a75 BH |
127 | conflict = request_resource_conflict(root, res); |
128 | if (conflict) { | |
29003beb BH |
129 | dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n", |
130 | resource, res, conflict->name, conflict); | |
c770cb4c | 131 | res->flags |= IORESOURCE_UNSET; |
966f3a75 BH |
132 | return -EBUSY; |
133 | } | |
865df576 | 134 | |
966f3a75 | 135 | return 0; |
1da177e4 | 136 | } |
eaa959df | 137 | EXPORT_SYMBOL(pci_claim_resource); |
1da177e4 | 138 | |
32a9a682 YS |
139 | void pci_disable_bridge_window(struct pci_dev *dev) |
140 | { | |
865df576 | 141 | dev_info(&dev->dev, "disabling bridge mem windows\n"); |
32a9a682 YS |
142 | |
143 | /* MMIO Base/Limit */ | |
144 | pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); | |
145 | ||
146 | /* Prefetchable MMIO Base/Limit */ | |
147 | pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); | |
148 | pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); | |
149 | pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); | |
150 | } | |
2bbc6942 | 151 | |
6535943f MS |
152 | /* |
153 | * Generic function that returns a value indicating that the device's | |
154 | * original BIOS BAR address was not saved and so is not available for | |
155 | * reinstatement. | |
156 | * | |
157 | * Can be over-ridden by architecture specific code that implements | |
158 | * reinstatement functionality rather than leaving it disabled when | |
159 | * normal allocation attempts fail. | |
160 | */ | |
161 | resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx) | |
162 | { | |
163 | return 0; | |
164 | } | |
165 | ||
f7625980 | 166 | static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, |
2bbc6942 RP |
167 | int resno, resource_size_t size) |
168 | { | |
169 | struct resource *root, *conflict; | |
6535943f | 170 | resource_size_t fw_addr, start, end; |
58c84eda | 171 | |
6535943f MS |
172 | fw_addr = pcibios_retrieve_fw_addr(dev, resno); |
173 | if (!fw_addr) | |
94778835 | 174 | return -ENOMEM; |
6535943f | 175 | |
2bbc6942 RP |
176 | start = res->start; |
177 | end = res->end; | |
6535943f | 178 | res->start = fw_addr; |
2bbc6942 | 179 | res->end = res->start + size - 1; |
351fc6d1 MS |
180 | |
181 | root = pci_find_parent_resource(dev, res); | |
182 | if (!root) { | |
183 | if (res->flags & IORESOURCE_IO) | |
184 | root = &ioport_resource; | |
185 | else | |
186 | root = &iomem_resource; | |
187 | } | |
188 | ||
2bbc6942 RP |
189 | dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n", |
190 | resno, res); | |
191 | conflict = request_resource_conflict(root, res); | |
192 | if (conflict) { | |
94778835 BH |
193 | dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n", |
194 | resno, res, conflict->name, conflict); | |
2bbc6942 RP |
195 | res->start = start; |
196 | res->end = end; | |
94778835 | 197 | return -EBUSY; |
2bbc6942 | 198 | } |
94778835 | 199 | return 0; |
2bbc6942 RP |
200 | } |
201 | ||
fe6dacdb BH |
202 | static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, |
203 | int resno, resource_size_t size, resource_size_t align) | |
204 | { | |
205 | struct resource *res = dev->resource + resno; | |
206 | resource_size_t min; | |
207 | int ret; | |
208 | ||
209 | min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; | |
210 | ||
67d29b5c BH |
211 | /* |
212 | * First, try exact prefetching match. Even if a 64-bit | |
213 | * prefetchable bridge window is below 4GB, we can't put a 32-bit | |
214 | * prefetchable resource in it because pbus_size_mem() assumes a | |
215 | * 64-bit window will contain no 32-bit resources. If we assign | |
216 | * things differently than they were sized, not everything will fit. | |
217 | */ | |
fe6dacdb | 218 | ret = pci_bus_alloc_resource(bus, res, size, align, min, |
5b285415 | 219 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64, |
fe6dacdb | 220 | pcibios_align_resource, dev); |
d3689df0 BH |
221 | if (ret == 0) |
222 | return 0; | |
fe6dacdb | 223 | |
67d29b5c BH |
224 | /* |
225 | * If the prefetchable window is only 32 bits wide, we can put | |
226 | * 64-bit prefetchable resources in it. | |
227 | */ | |
d3689df0 | 228 | if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == |
5b285415 | 229 | (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { |
5b285415 YL |
230 | ret = pci_bus_alloc_resource(bus, res, size, align, min, |
231 | IORESOURCE_PREFETCH, | |
fe6dacdb | 232 | pcibios_align_resource, dev); |
d3689df0 BH |
233 | if (ret == 0) |
234 | return 0; | |
fe6dacdb | 235 | } |
5b285415 | 236 | |
67d29b5c BH |
237 | /* |
238 | * If we didn't find a better match, we can put any memory resource | |
239 | * in a non-prefetchable window. If this resource is 32 bits and | |
240 | * non-prefetchable, the first call already tried the only possibility | |
241 | * so we don't need to try again. | |
242 | */ | |
243 | if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) | |
fe6dacdb BH |
244 | ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, |
245 | pcibios_align_resource, dev); | |
67d29b5c | 246 | |
fe6dacdb BH |
247 | return ret; |
248 | } | |
249 | ||
d6776e6d NR |
250 | static int _pci_assign_resource(struct pci_dev *dev, int resno, |
251 | resource_size_t size, resource_size_t min_align) | |
2bbc6942 | 252 | { |
2bbc6942 RP |
253 | struct pci_bus *bus; |
254 | int ret; | |
58c84eda | 255 | |
2bbc6942 RP |
256 | bus = dev->bus; |
257 | while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { | |
258 | if (!bus->parent || !bus->self->transparent) | |
259 | break; | |
260 | bus = bus->parent; | |
261 | } | |
262 | ||
2bbc6942 RP |
263 | return ret; |
264 | } | |
265 | ||
d09ee968 YL |
266 | int pci_assign_resource(struct pci_dev *dev, int resno) |
267 | { | |
268 | struct resource *res = dev->resource + resno; | |
2bbc6942 | 269 | resource_size_t align, size; |
d09ee968 YL |
270 | int ret; |
271 | ||
bd064f0a | 272 | res->flags |= IORESOURCE_UNSET; |
6faf17f6 | 273 | align = pci_resource_alignment(dev, res); |
d09ee968 | 274 | if (!align) { |
227f0647 RD |
275 | dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n", |
276 | resno, res); | |
d09ee968 YL |
277 | return -EINVAL; |
278 | } | |
279 | ||
2bbc6942 RP |
280 | size = resource_size(res); |
281 | ret = _pci_assign_resource(dev, resno, size, align); | |
d09ee968 | 282 | |
2bbc6942 RP |
283 | /* |
284 | * If we failed to assign anything, let's try the address | |
285 | * where firmware left it. That at least has a chance of | |
286 | * working, which is better than just leaving it disabled. | |
287 | */ | |
64da465e BH |
288 | if (ret < 0) { |
289 | dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res); | |
2bbc6942 | 290 | ret = pci_revert_fw_address(res, dev, resno, size); |
64da465e | 291 | } |
d09ee968 | 292 | |
64da465e BH |
293 | if (ret < 0) { |
294 | dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno, | |
295 | res); | |
28f6dbe2 | 296 | return ret; |
64da465e | 297 | } |
28f6dbe2 BH |
298 | |
299 | res->flags &= ~IORESOURCE_UNSET; | |
300 | res->flags &= ~IORESOURCE_STARTALIGN; | |
301 | dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); | |
302 | if (resno < PCI_BRIDGE_RESOURCES) | |
303 | pci_update_resource(dev, resno); | |
304 | ||
305 | return 0; | |
d09ee968 | 306 | } |
b7fe9434 | 307 | EXPORT_SYMBOL(pci_assign_resource); |
d09ee968 | 308 | |
fe6dacdb BH |
309 | int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize, |
310 | resource_size_t min_align) | |
311 | { | |
312 | struct resource *res = dev->resource + resno; | |
c3337708 | 313 | unsigned long flags; |
fe6dacdb BH |
314 | resource_size_t new_size; |
315 | int ret; | |
316 | ||
c3337708 | 317 | flags = res->flags; |
bd064f0a | 318 | res->flags |= IORESOURCE_UNSET; |
fe6dacdb | 319 | if (!res->parent) { |
227f0647 RD |
320 | dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n", |
321 | resno, res); | |
fe6dacdb BH |
322 | return -EINVAL; |
323 | } | |
324 | ||
325 | /* already aligned with min_align */ | |
326 | new_size = resource_size(res) + addsize; | |
327 | ret = _pci_assign_resource(dev, resno, new_size, min_align); | |
28f6dbe2 | 328 | if (ret) { |
c3337708 GC |
329 | res->flags = flags; |
330 | dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n", | |
331 | resno, res, (unsigned long long) addsize); | |
28f6dbe2 | 332 | return ret; |
fe6dacdb | 333 | } |
c3337708 | 334 | |
28f6dbe2 BH |
335 | res->flags &= ~IORESOURCE_UNSET; |
336 | res->flags &= ~IORESOURCE_STARTALIGN; | |
64da465e BH |
337 | dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n", |
338 | resno, res, (unsigned long long) addsize); | |
28f6dbe2 BH |
339 | if (resno < PCI_BRIDGE_RESOURCES) |
340 | pci_update_resource(dev, resno); | |
341 | ||
342 | return 0; | |
fe6dacdb BH |
343 | } |
344 | ||
842de40d BH |
345 | int pci_enable_resources(struct pci_dev *dev, int mask) |
346 | { | |
347 | u16 cmd, old_cmd; | |
348 | int i; | |
349 | struct resource *r; | |
350 | ||
351 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
352 | old_cmd = cmd; | |
353 | ||
354 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
355 | if (!(mask & (1 << i))) | |
356 | continue; | |
357 | ||
358 | r = &dev->resource[i]; | |
359 | ||
360 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
361 | continue; | |
362 | if ((i == PCI_ROM_RESOURCE) && | |
363 | (!(r->flags & IORESOURCE_ROM_ENABLE))) | |
364 | continue; | |
365 | ||
3cedcc36 BH |
366 | if (r->flags & IORESOURCE_UNSET) { |
367 | dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n", | |
368 | i, r); | |
369 | return -EINVAL; | |
370 | } | |
371 | ||
842de40d | 372 | if (!r->parent) { |
3cedcc36 BH |
373 | dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n", |
374 | i, r); | |
842de40d BH |
375 | return -EINVAL; |
376 | } | |
377 | ||
378 | if (r->flags & IORESOURCE_IO) | |
379 | cmd |= PCI_COMMAND_IO; | |
380 | if (r->flags & IORESOURCE_MEM) | |
381 | cmd |= PCI_COMMAND_MEMORY; | |
382 | } | |
383 | ||
384 | if (cmd != old_cmd) { | |
385 | dev_info(&dev->dev, "enabling device (%04x -> %04x)\n", | |
386 | old_cmd, cmd); | |
387 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
388 | } | |
389 | return 0; | |
390 | } |