[linux-2.6-block.git] / drivers / pci / setup-res.c

/*
 *	drivers/pci/setup-res.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Resource sorting
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"


void pci_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	u32 new, check, mask;
	int reg;
	enum pci_bar_type type;
	struct resource *res = dev->resource + resno;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev, &region, res);

	new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
	if (res->flags & IORESOURCE_IO)
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	else
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;

	reg = pci_resource_bar(dev, resno, &type);
	if (!reg)
		return;
	if (type != pci_bar_unknown) {
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;
		new |= PCI_ROM_ADDRESS_ENABLE;
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if (res->flags & IORESOURCE_MEM_64) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			dev_err(&dev->dev, "BAR %d: error updating "
			       "(high %#08x != %#08x)\n", resno, new, check);
		}
	}
	res->flags &= ~IORESOURCE_UNSET;
	dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
		resno, res, (unsigned long long)region.start,
		(unsigned long long)region.end);
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root, *conflict;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		dev_info(&dev->dev, "no compatible bridge window for %pR\n",
			 res);
		return -EINVAL;
	}

	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev,
			 "address space collision: %pR conflicts with %s %pR\n",
			 res, conflict->name, conflict);
		return -EBUSY;
	}

	return 0;
}
EXPORT_SYMBOL(pci_claim_resource);

void pci_disable_bridge_window(struct pci_dev *dev)
{
	dev_info(&dev->dev, "disabling bridge mem windows\n");

	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}

static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
		int resno, resource_size_t size, resource_size_t align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t min;
	int ret;

	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;

	/* First, try exact prefetching match.. */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH,
				     pcibios_align_resource, dev);

	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
		/*
		 * That failed.
		 *
		 * But a prefetching area can handle a non-prefetching
		 * window (it will just not perform as well).
		 */
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);
	}
	return ret;
}

/*
 * Generic function that returns a value indicating that the device's
 * original BIOS BAR address was not saved and so is not available for
 * reinstatement.
 *
 * Can be over-ridden by architecture specific code that implements
 * reinstatement functionality rather than leaving it disabled when
 * normal allocation attempts fail.
 */
resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
{
	return 0;
}

static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 
		int resno, resource_size_t size)
{
	struct resource *root, *conflict;
	resource_size_t fw_addr, start, end;
	int ret = 0;

	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
	if (!fw_addr)
		return 1;

	start = res->start;
	end = res->end;
	res->start = fw_addr;
	res->end = res->start + size - 1;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		if (res->flags & IORESOURCE_IO)
			root = &ioport_resource;
		else
			root = &iomem_resource;
	}

	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
		 resno, res);
	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev,
			 "BAR %d: %pR conflicts with %s %pR\n", resno,
			 res, conflict->name, conflict);
		res->start = start;
		res->end = end;
		ret = 1;
	}
	return ret;
}

static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	struct pci_bus *bus;
	int ret;
	char *type;

	bus = dev->bus;
	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
		if (!bus->parent || !bus->self->transparent)
			break;
		bus = bus->parent;
	}

	if (ret) {
		if (res->flags & IORESOURCE_MEM)
			if (res->flags & IORESOURCE_PREFETCH)
				type = "mem pref";
			else
				type = "mem";
		else if (res->flags & IORESOURCE_IO)
			type = "io";
		else
			type = "unknown";
		dev_info(&dev->dev,
			 "BAR %d: can't assign %s (size %#llx)\n",
			 resno, type, (unsigned long long) resource_size(res));
	}

	return ret;
}

int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
			resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t new_size;
	int ret;

	if (!res->parent) {
		dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR "
			 "\n", resno, res);
		return -EINVAL;
	}

	/* already aligned with min_align */
	new_size = resource_size(res) + addsize;
	ret = _pci_assign_resource(dev, resno, new_size, min_align);
	if (!ret) {
		res->flags &= ~IORESOURCE_STARTALIGN;
		dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}
	return ret;
}

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t align, size;
	struct pci_bus *bus;
	int ret;

	align = pci_resource_alignment(dev, res);
	if (!align) {
		dev_info(&dev->dev, "BAR %d: can't assign %pR "
			 "(bogus alignment)\n", resno, res);
		return -EINVAL;
	}

	bus = dev->bus;
	size = resource_size(res);
	ret = _pci_assign_resource(dev, resno, size, align);

	/*
	 * If we failed to assign anything, let's try the address
	 * where firmware left it.  That at least has a chance of
	 * working, which is better than just leaving it disabled.
	 */
	if (ret < 0)
		ret = pci_revert_fw_address(res, dev, resno, size);

	if (!ret) {
		res->flags &= ~IORESOURCE_STARTALIGN;
		dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}
	return ret;
}

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (!r->parent) {
			dev_err(&dev->dev, "device not available "
				"(can't reserve %pR)\n", r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
			 old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-res.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	* David Miller (davem@redhat.com)
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
	13
	14	/*
	15	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	16	* Resource sorting
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
363c75db	21	#include <linux/export.h>
1da177e4 LT	22	#include <linux/pci.h>
	23	#include <linux/errno.h>
	24	#include <linux/ioport.h>
	25	#include <linux/cache.h>
	26	#include <linux/slab.h>
	27	#include "pci.h"
	28
	29
14add80b	30	void pci_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	31	{
	32	struct pci_bus_region region;
	33	u32 new, check, mask;
	34	int reg;
613e7ed6	35	enum pci_bar_type type;
14add80b	36	struct resource *res = dev->resource + resno;
1da177e4	37
fb0f2b40 RB	38	/*
	39	* Ignore resources for unimplemented BARs and unused resource slots
	40	* for 64 bit BARs.
	41	*/
cf7bee5a IK	42	if (!res->flags)
	43	return;
	44
fb0f2b40 RB	45	/*
	46	* Ignore non-moveable resources. This might be legacy resources for
	47	* which no functional BAR register exists or another important
80ccba11	48	* system resource we shouldn't move around.
fb0f2b40 RB	49	*/
	50	if (res->flags & IORESOURCE_PCI_FIXED)
	51	return;
	52
1da177e4 LT	53	pcibios_resource_to_bus(dev, &region, res);
1da177e4 LT	54
1da177e4 LT	55	new = region.start \| (res->flags & PCI_REGION_FLAG_MASK);
	56	if (res->flags & IORESOURCE_IO)
	57	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	58	else
	59	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
	60
613e7ed6 YZ	61	reg = pci_resource_bar(dev, resno, &type);
	62	if (!reg)
	63	return;
	64	if (type != pci_bar_unknown) {
755528c8 LT	65	if (!(res->flags & IORESOURCE_ROM_ENABLE))
	66	return;
	67	new \|= PCI_ROM_ADDRESS_ENABLE;
1da177e4 LT	68	}
	69
	70	pci_write_config_dword(dev, reg, new);
	71	pci_read_config_dword(dev, reg, &check);
	72
	73	if ((new ^ check) & mask) {
80ccba11 BH	74	dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11 BH	75	resno, new, check);
1da177e4 LT	76	}
1da177e4 LT	77
28c6821a	78	if (res->flags & IORESOURCE_MEM_64) {
cf7bee5a	79	new = region.start >> 16 >> 16;
1da177e4 LT	80	pci_write_config_dword(dev, reg + 4, new);
	81	pci_read_config_dword(dev, reg + 4, &check);
	82	if (check != new) {
80ccba11 BH	83	dev_err(&dev->dev, "BAR %d: error updating "
80ccba11 BH	84	"(high %#08x != %#08x)\n", resno, new, check);
1da177e4 LT	85	}
	86	}
	87	res->flags &= ~IORESOURCE_UNSET;
85b8582d VP	88	dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
	89	resno, res, (unsigned long long)region.start,
	90	(unsigned long long)region.end);
1da177e4 LT	91	}
1da177e4 LT	92
96bde06a	93	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	94	{
1da177e4 LT	95	struct resource *res = &dev->resource[resource];
966f3a75	96	struct resource root, conflict;
1da177e4	97
cebd78a8	98	root = pci_find_parent_resource(dev, res);
865df576	99	if (!root) {
f6d440da BH	100	dev_info(&dev->dev, "no compatible bridge window for %pR\n",
f6d440da BH	101	res);
865df576	102	return -EINVAL;
1da177e4 LT	103	}
1da177e4 LT	104
966f3a75 BH	105	conflict = request_resource_conflict(root, res);
966f3a75 BH	106	if (conflict) {
f6d440da BH	107	dev_info(&dev->dev,
	108	"address space collision: %pR conflicts with %s %pR\n",
	109	res, conflict->name, conflict);
966f3a75 BH	110	return -EBUSY;
966f3a75 BH	111	}
865df576	112
966f3a75	113	return 0;
1da177e4	114	}
eaa959df	115	EXPORT_SYMBOL(pci_claim_resource);
1da177e4	116
32a9a682 YS	117	void pci_disable_bridge_window(struct pci_dev *dev)
32a9a682 YS	118	{
865df576	119	dev_info(&dev->dev, "disabling bridge mem windows\n");
32a9a682 YS	120
	121	/* MMIO Base/Limit */
	122	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	123
	124	/* Prefetchable MMIO Base/Limit */
	125	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	126	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	127	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	128	}
2bbc6942	129
d09ee968	130	static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
2bbc6942	131	int resno, resource_size_t size, resource_size_t align)
1da177e4	132	{
1da177e4	133	struct resource *res = dev->resource + resno;
2bbc6942	134	resource_size_t min;
1da177e4 LT	135	int ret;
1da177e4 LT	136
1da177e4	137	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
1da177e4 LT	138
	139	/* First, try exact prefetching match.. */
	140	ret = pci_bus_alloc_resource(bus, res, size, align, min,
	141	IORESOURCE_PREFETCH,
	142	pcibios_align_resource, dev);
	143
	144	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
	145	/*
	146	* That failed.
	147	*
	148	* But a prefetching area can handle a non-prefetching
	149	* window (it will just not perform as well).
	150	*/
	151	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
	152	pcibios_align_resource, dev);
	153	}
2bbc6942 RP	154	return ret;
2bbc6942 RP	155	}
1da177e4	156
6535943f MS	157	/*
	158	* Generic function that returns a value indicating that the device's
	159	* original BIOS BAR address was not saved and so is not available for
	160	* reinstatement.
	161	*
	162	* Can be over-ridden by architecture specific code that implements
	163	* reinstatement functionality rather than leaving it disabled when
	164	* normal allocation attempts fail.
	165	*/
	166	resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
	167	{
	168	return 0;
	169	}
	170
2bbc6942 RP	171	static int pci_revert_fw_address(struct resource res, struct pci_dev dev,
	172	int resno, resource_size_t size)
	173	{
	174	struct resource root, conflict;
6535943f	175	resource_size_t fw_addr, start, end;
2bbc6942	176	int ret = 0;
58c84eda	177
6535943f MS	178	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
	179	if (!fw_addr)
	180	return 1;
	181
2bbc6942 RP	182	start = res->start;
2bbc6942 RP	183	end = res->end;
6535943f	184	res->start = fw_addr;
2bbc6942	185	res->end = res->start + size - 1;
351fc6d1 MS	186
	187	root = pci_find_parent_resource(dev, res);
	188	if (!root) {
	189	if (res->flags & IORESOURCE_IO)
	190	root = &ioport_resource;
	191	else
	192	root = &iomem_resource;
	193	}
	194
2bbc6942 RP	195	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
	196	resno, res);
	197	conflict = request_resource_conflict(root, res);
	198	if (conflict) {
	199	dev_info(&dev->dev,
	200	"BAR %d: %pR conflicts with %s %pR\n", resno,
	201	res, conflict->name, conflict);
	202	res->start = start;
	203	res->end = end;
	204	ret = 1;
	205	}
	206	return ret;
	207	}
	208
	209	static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
	210	{
	211	struct resource *res = dev->resource + resno;
	212	struct pci_bus *bus;
	213	int ret;
	214	char *type;
58c84eda	215
2bbc6942 RP	216	bus = dev->bus;
	217	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
	218	if (!bus->parent \|\| !bus->self->transparent)
	219	break;
	220	bus = bus->parent;
	221	}
	222
	223	if (ret) {
	224	if (res->flags & IORESOURCE_MEM)
	225	if (res->flags & IORESOURCE_PREFETCH)
	226	type = "mem pref";
	227	else
	228	type = "mem";
	229	else if (res->flags & IORESOURCE_IO)
	230	type = "io";
58c84eda	231	else
2bbc6942 RP	232	type = "unknown";
	233	dev_info(&dev->dev,
	234	"BAR %d: can't assign %s (size %#llx)\n",
	235	resno, type, (unsigned long long) resource_size(res));
58c84eda BH	236	}
58c84eda BH	237
2bbc6942 RP	238	return ret;
	239	}
	240
	241	int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
	242	resource_size_t min_align)
	243	{
	244	struct resource *res = dev->resource + resno;
	245	resource_size_t new_size;
	246	int ret;
	247
	248	if (!res->parent) {
0dea210b	249	dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR "
2bbc6942 RP	250	"\n", resno, res);
	251	return -EINVAL;
	252	}
	253
a4ac9fea YL	254	/* already aligned with min_align */
a4ac9fea YL	255	new_size = resource_size(res) + addsize;
2bbc6942	256	ret = _pci_assign_resource(dev, resno, new_size, min_align);
d09ee968	257	if (!ret) {
88452565	258	res->flags &= ~IORESOURCE_STARTALIGN;
a4ac9fea	259	dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
88452565	260	if (resno < PCI_BRIDGE_RESOURCES)
14add80b	261	pci_update_resource(dev, resno);
1da177e4	262	}
1da177e4 LT	263	return ret;
	264	}
	265
d09ee968 YL	266	int pci_assign_resource(struct pci_dev *dev, int resno)
	267	{
	268	struct resource *res = dev->resource + resno;
2bbc6942	269	resource_size_t align, size;
d09ee968 YL	270	struct pci_bus *bus;
	271	int ret;
	272
6faf17f6	273	align = pci_resource_alignment(dev, res);
d09ee968	274	if (!align) {
865df576	275	dev_info(&dev->dev, "BAR %d: can't assign %pR "
a369c791	276	"(bogus alignment)\n", resno, res);
d09ee968 YL	277	return -EINVAL;
	278	}
	279
	280	bus = dev->bus;
2bbc6942 RP	281	size = resource_size(res);
2bbc6942 RP	282	ret = _pci_assign_resource(dev, resno, size, align);
d09ee968	283
2bbc6942 RP	284	/*
	285	* If we failed to assign anything, let's try the address
	286	* where firmware left it. That at least has a chance of
	287	* working, which is better than just leaving it disabled.
	288	*/
6535943f	289	if (ret < 0)
2bbc6942	290	ret = pci_revert_fw_address(res, dev, resno, size);
d09ee968	291
2bbc6942 RP	292	if (!ret) {
	293	res->flags &= ~IORESOURCE_STARTALIGN;
	294	dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
	295	if (resno < PCI_BRIDGE_RESOURCES)
	296	pci_update_resource(dev, resno);
	297	}
d09ee968 YL	298	return ret;
	299	}
	300
842de40d BH	301	int pci_enable_resources(struct pci_dev *dev, int mask)
	302	{
	303	u16 cmd, old_cmd;
	304	int i;
	305	struct resource *r;
	306
	307	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	308	old_cmd = cmd;
	309
	310	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	311	if (!(mask & (1 << i)))
	312	continue;
	313
	314	r = &dev->resource[i];
	315
	316	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	317	continue;
	318	if ((i == PCI_ROM_RESOURCE) &&
	319	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	320	continue;
	321
	322	if (!r->parent) {
865df576 BH	323	dev_err(&dev->dev, "device not available "
865df576 BH	324	"(can't reserve %pR)\n", r);
842de40d BH	325	return -EINVAL;
	326	}
	327
	328	if (r->flags & IORESOURCE_IO)
	329	cmd \|= PCI_COMMAND_IO;
	330	if (r->flags & IORESOURCE_MEM)
	331	cmd \|= PCI_COMMAND_MEMORY;
	332	}
	333
	334	if (cmd != old_cmd) {
	335	dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
	336	old_cmd, cmd);
	337	pci_write_config_word(dev, PCI_COMMAND, cmd);
	338	}
	339	return 0;
	340	}