[linux-2.6-block.git] / drivers / pci / setup-res.c

/*
 *	drivers/pci/setup-res.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Resource sorting
 */

#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"


void pci_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	bool disable;
	u16 cmd;
	u32 new, check, mask;
	int reg;
	enum pci_bar_type type;
	struct resource *res = dev->resource + resno;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	if (res->flags & IORESOURCE_UNSET)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev->bus, &region, res);

	new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
	if (res->flags & IORESOURCE_IO)
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	else
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;

	reg = pci_resource_bar(dev, resno, &type);
	if (!reg)
		return;
	if (type != pci_bar_unknown) {
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;
		new |= PCI_ROM_ADDRESS_ENABLE;
	}

	/*
	 * We can't update a 64-bit BAR atomically, so when possible,
	 * disable decoding so that a half-updated BAR won't conflict
	 * with another device.
	 */
	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	if (disable) {
		pci_read_config_word(dev, PCI_COMMAND, &cmd);
		pci_write_config_word(dev, PCI_COMMAND,
				      cmd & ~PCI_COMMAND_MEMORY);
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if (res->flags & IORESOURCE_MEM_64) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
				resno, new, check);
		}
	}

	if (disable)
		pci_write_config_word(dev, PCI_COMMAND, cmd);
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root, *conflict;

	if (res->flags & IORESOURCE_UNSET) {
		dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
			 resource, res);
		return -EINVAL;
	}

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
			 resource, res);
		return -EINVAL;
	}

	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
			 resource, res, conflict->name, conflict);
		return -EBUSY;
	}

	return 0;
}
EXPORT_SYMBOL(pci_claim_resource);

void pci_disable_bridge_window(struct pci_dev *dev)
{
	dev_info(&dev->dev, "disabling bridge mem windows\n");

	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}

/*
 * Generic function that returns a value indicating that the device's
 * original BIOS BAR address was not saved and so is not available for
 * reinstatement.
 *
 * Can be over-ridden by architecture specific code that implements
 * reinstatement functionality rather than leaving it disabled when
 * normal allocation attempts fail.
 */
resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
{
	return 0;
}

static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
		int resno, resource_size_t size)
{
	struct resource *root, *conflict;
	resource_size_t fw_addr, start, end;

	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
	if (!fw_addr)
		return -ENOMEM;

	start = res->start;
	end = res->end;
	res->start = fw_addr;
	res->end = res->start + size - 1;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		if (res->flags & IORESOURCE_IO)
			root = &ioport_resource;
		else
			root = &iomem_resource;
	}

	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
		 resno, res);
	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
			 resno, res, conflict->name, conflict);
		res->start = start;
		res->end = end;
		return -EBUSY;
	}
	return 0;
}

static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
		int resno, resource_size_t size, resource_size_t align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t min;
	int ret;

	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;

	/*
	 * First, try exact prefetching match.  Even if a 64-bit
	 * prefetchable bridge window is below 4GB, we can't put a 32-bit
	 * prefetchable resource in it because pbus_size_mem() assumes a
	 * 64-bit window will contain no 32-bit resources.  If we assign
	 * things differently than they were sized, not everything will fit.
	 */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
				     pcibios_align_resource, dev);
	if (ret == 0)
		return 0;

	/*
	 * If the prefetchable window is only 32 bits wide, we can put
	 * 64-bit prefetchable resources in it.
	 */
	if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
		ret = pci_bus_alloc_resource(bus, res, size, align, min,
					     IORESOURCE_PREFETCH,
					     pcibios_align_resource, dev);
		if (ret == 0)
			return 0;
	}

	/*
	 * If we didn't find a better match, we can put any memory resource
	 * in a non-prefetchable window.  If this resource is 32 bits and
	 * non-prefetchable, the first call already tried the only possibility
	 * so we don't need to try again.
	 */
	if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);

	return ret;
}

static int _pci_assign_resource(struct pci_dev *dev, int resno,
				resource_size_t size, resource_size_t min_align)
{
	struct pci_bus *bus;
	int ret;

	bus = dev->bus;
	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
		if (!bus->parent || !bus->self->transparent)
			break;
		bus = bus->parent;
	}

	return ret;
}

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t align, size;
	int ret;

	res->flags |= IORESOURCE_UNSET;
	align = pci_resource_alignment(dev, res);
	if (!align) {
		dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
			 resno, res);
		return -EINVAL;
	}

	size = resource_size(res);
	ret = _pci_assign_resource(dev, resno, size, align);

	/*
	 * If we failed to assign anything, let's try the address
	 * where firmware left it.  That at least has a chance of
	 * working, which is better than just leaving it disabled.
	 */
	if (ret < 0) {
		dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
		ret = pci_revert_fw_address(res, dev, resno, size);
	}

	if (ret < 0) {
		dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
			 res);
		return ret;
	}

	res->flags &= ~IORESOURCE_UNSET;
	res->flags &= ~IORESOURCE_STARTALIGN;
	dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
	if (resno < PCI_BRIDGE_RESOURCES)
		pci_update_resource(dev, resno);

	return 0;
}
EXPORT_SYMBOL(pci_assign_resource);

int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
			resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	unsigned long flags;
	resource_size_t new_size;
	int ret;

	flags = res->flags;
	res->flags |= IORESOURCE_UNSET;
	if (!res->parent) {
		dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
			 resno, res);
		return -EINVAL;
	}

	/* already aligned with min_align */
	new_size = resource_size(res) + addsize;
	ret = _pci_assign_resource(dev, resno, new_size, min_align);
	if (ret) {
		res->flags = flags;
		dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
			 resno, res, (unsigned long long) addsize);
		return ret;
	}

	res->flags &= ~IORESOURCE_UNSET;
	res->flags &= ~IORESOURCE_STARTALIGN;
	dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
		 resno, res, (unsigned long long) addsize);
	if (resno < PCI_BRIDGE_RESOURCES)
		pci_update_resource(dev, resno);

	return 0;
}

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (r->flags & IORESOURCE_UNSET) {
			dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
				i, r);
			return -EINVAL;
		}

		if (!r->parent) {
			dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
				i, r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
			 old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-res.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	* David Miller (davem@redhat.com)
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
	13
	14	/*
	15	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	16	* Resource sorting
	17	*/
	18
1da177e4	19	#include <linux/kernel.h>
363c75db	20	#include <linux/export.h>
1da177e4 LT	21	#include <linux/pci.h>
	22	#include <linux/errno.h>
	23	#include <linux/ioport.h>
	24	#include <linux/cache.h>
	25	#include <linux/slab.h>
	26	#include "pci.h"
	27
	28
14add80b	29	void pci_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	30	{
1da177e4 LT	31	struct pci_bus_region region;
9aac537e BH	32	bool disable;
9aac537e BH	33	u16 cmd;
1da177e4 LT	34	u32 new, check, mask;
1da177e4 LT	35	int reg;
613e7ed6	36	enum pci_bar_type type;
14add80b	37	struct resource *res = dev->resource + resno;
1da177e4	38
fb0f2b40 RB	39	/*
	40	* Ignore resources for unimplemented BARs and unused resource slots
	41	* for 64 bit BARs.
	42	*/
cf7bee5a IK	43	if (!res->flags)
	44	return;
	45
cd8a4d36 BH	46	if (res->flags & IORESOURCE_UNSET)
	47	return;
	48
fb0f2b40 RB	49	/*
	50	* Ignore non-moveable resources. This might be legacy resources for
	51	* which no functional BAR register exists or another important
80ccba11	52	* system resource we shouldn't move around.
fb0f2b40 RB	53	*/
	54	if (res->flags & IORESOURCE_PCI_FIXED)
	55	return;
	56
fc279850	57	pcibios_resource_to_bus(dev->bus, &region, res);
1da177e4	58
1da177e4 LT	59	new = region.start \| (res->flags & PCI_REGION_FLAG_MASK);
	60	if (res->flags & IORESOURCE_IO)
	61	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	62	else
	63	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
	64
613e7ed6 YZ	65	reg = pci_resource_bar(dev, resno, &type);
	66	if (!reg)
	67	return;
	68	if (type != pci_bar_unknown) {
755528c8 LT	69	if (!(res->flags & IORESOURCE_ROM_ENABLE))
	70	return;
	71	new \|= PCI_ROM_ADDRESS_ENABLE;
1da177e4 LT	72	}
1da177e4 LT	73
9aac537e BH	74	/*
	75	* We can't update a 64-bit BAR atomically, so when possible,
	76	* disable decoding so that a half-updated BAR won't conflict
	77	* with another device.
	78	*/
	79	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	80	if (disable) {
	81	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	82	pci_write_config_word(dev, PCI_COMMAND,
	83	cmd & ~PCI_COMMAND_MEMORY);
	84	}
	85
1da177e4 LT	86	pci_write_config_dword(dev, reg, new);
	87	pci_read_config_dword(dev, reg, &check);
	88
	89	if ((new ^ check) & mask) {
80ccba11 BH	90	dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11 BH	91	resno, new, check);
1da177e4 LT	92	}
1da177e4 LT	93
28c6821a	94	if (res->flags & IORESOURCE_MEM_64) {
cf7bee5a	95	new = region.start >> 16 >> 16;
1da177e4 LT	96	pci_write_config_dword(dev, reg + 4, new);
	97	pci_read_config_dword(dev, reg + 4, &check);
	98	if (check != new) {
227f0647 RD	99	dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
227f0647 RD	100	resno, new, check);
1da177e4 LT	101	}
1da177e4 LT	102	}
9aac537e BH	103
	104	if (disable)
	105	pci_write_config_word(dev, PCI_COMMAND, cmd);
1da177e4 LT	106	}
1da177e4 LT	107
96bde06a	108	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	109	{
1da177e4 LT	110	struct resource *res = &dev->resource[resource];
966f3a75	111	struct resource root, conflict;
1da177e4	112
29003beb BH	113	if (res->flags & IORESOURCE_UNSET) {
	114	dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
	115	resource, res);
	116	return -EINVAL;
	117	}
	118
cebd78a8	119	root = pci_find_parent_resource(dev, res);
865df576	120	if (!root) {
29003beb BH	121	dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
29003beb BH	122	resource, res);
865df576	123	return -EINVAL;
1da177e4 LT	124	}
1da177e4 LT	125
966f3a75 BH	126	conflict = request_resource_conflict(root, res);
966f3a75 BH	127	if (conflict) {
29003beb BH	128	dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
29003beb BH	129	resource, res, conflict->name, conflict);
966f3a75 BH	130	return -EBUSY;
966f3a75 BH	131	}
865df576	132
966f3a75	133	return 0;
1da177e4	134	}
eaa959df	135	EXPORT_SYMBOL(pci_claim_resource);
1da177e4	136
32a9a682 YS	137	void pci_disable_bridge_window(struct pci_dev *dev)
32a9a682 YS	138	{
865df576	139	dev_info(&dev->dev, "disabling bridge mem windows\n");
32a9a682 YS	140
	141	/* MMIO Base/Limit */
	142	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	143
	144	/* Prefetchable MMIO Base/Limit */
	145	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	146	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	147	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	148	}
2bbc6942	149
6535943f MS	150	/*
	151	* Generic function that returns a value indicating that the device's
	152	* original BIOS BAR address was not saved and so is not available for
	153	* reinstatement.
	154	*
	155	* Can be over-ridden by architecture specific code that implements
	156	* reinstatement functionality rather than leaving it disabled when
	157	* normal allocation attempts fail.
	158	*/
	159	resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
	160	{
	161	return 0;
	162	}
	163
f7625980	164	static int pci_revert_fw_address(struct resource res, struct pci_dev dev,
2bbc6942 RP	165	int resno, resource_size_t size)
	166	{
	167	struct resource root, conflict;
6535943f	168	resource_size_t fw_addr, start, end;
58c84eda	169
6535943f MS	170	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
6535943f MS	171	if (!fw_addr)
94778835	172	return -ENOMEM;
6535943f	173
2bbc6942 RP	174	start = res->start;
2bbc6942 RP	175	end = res->end;
6535943f	176	res->start = fw_addr;
2bbc6942	177	res->end = res->start + size - 1;
351fc6d1 MS	178
	179	root = pci_find_parent_resource(dev, res);
	180	if (!root) {
	181	if (res->flags & IORESOURCE_IO)
	182	root = &ioport_resource;
	183	else
	184	root = &iomem_resource;
	185	}
	186
2bbc6942 RP	187	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
	188	resno, res);
	189	conflict = request_resource_conflict(root, res);
	190	if (conflict) {
94778835 BH	191	dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
94778835 BH	192	resno, res, conflict->name, conflict);
2bbc6942 RP	193	res->start = start;
2bbc6942 RP	194	res->end = end;
94778835	195	return -EBUSY;
2bbc6942	196	}
94778835	197	return 0;
2bbc6942 RP	198	}
2bbc6942 RP	199
fe6dacdb BH	200	static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
	201	int resno, resource_size_t size, resource_size_t align)
	202	{
	203	struct resource *res = dev->resource + resno;
	204	resource_size_t min;
	205	int ret;
	206
	207	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
	208
67d29b5c BH	209	/*
	210	* First, try exact prefetching match. Even if a 64-bit
	211	* prefetchable bridge window is below 4GB, we can't put a 32-bit
	212	* prefetchable resource in it because pbus_size_mem() assumes a
	213	* 64-bit window will contain no 32-bit resources. If we assign
	214	* things differently than they were sized, not everything will fit.
	215	*/
fe6dacdb	216	ret = pci_bus_alloc_resource(bus, res, size, align, min,
5b285415	217	IORESOURCE_PREFETCH \| IORESOURCE_MEM_64,
fe6dacdb	218	pcibios_align_resource, dev);
d3689df0 BH	219	if (ret == 0)
d3689df0 BH	220	return 0;
fe6dacdb	221
67d29b5c BH	222	/*
	223	* If the prefetchable window is only 32 bits wide, we can put
	224	* 64-bit prefetchable resources in it.
	225	*/
d3689df0	226	if ((res->flags & (IORESOURCE_PREFETCH \| IORESOURCE_MEM_64)) ==
5b285415	227	(IORESOURCE_PREFETCH \| IORESOURCE_MEM_64)) {
5b285415 YL	228	ret = pci_bus_alloc_resource(bus, res, size, align, min,
5b285415 YL	229	IORESOURCE_PREFETCH,
fe6dacdb	230	pcibios_align_resource, dev);
d3689df0 BH	231	if (ret == 0)
d3689df0 BH	232	return 0;
fe6dacdb	233	}
5b285415	234
67d29b5c BH	235	/*
	236	* If we didn't find a better match, we can put any memory resource
	237	* in a non-prefetchable window. If this resource is 32 bits and
	238	* non-prefetchable, the first call already tried the only possibility
	239	* so we don't need to try again.
	240	*/
	241	if (res->flags & (IORESOURCE_PREFETCH \| IORESOURCE_MEM_64))
fe6dacdb BH	242	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
fe6dacdb BH	243	pcibios_align_resource, dev);
67d29b5c	244
fe6dacdb BH	245	return ret;
	246	}
	247
d6776e6d NR	248	static int _pci_assign_resource(struct pci_dev *dev, int resno,
d6776e6d NR	249	resource_size_t size, resource_size_t min_align)
2bbc6942	250	{
2bbc6942 RP	251	struct pci_bus *bus;
2bbc6942 RP	252	int ret;
58c84eda	253
2bbc6942 RP	254	bus = dev->bus;
	255	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
	256	if (!bus->parent \|\| !bus->self->transparent)
	257	break;
	258	bus = bus->parent;
	259	}
	260
2bbc6942 RP	261	return ret;
	262	}
	263
d09ee968 YL	264	int pci_assign_resource(struct pci_dev *dev, int resno)
	265	{
	266	struct resource *res = dev->resource + resno;
2bbc6942	267	resource_size_t align, size;
d09ee968 YL	268	int ret;
d09ee968 YL	269
bd064f0a	270	res->flags \|= IORESOURCE_UNSET;
6faf17f6	271	align = pci_resource_alignment(dev, res);
d09ee968	272	if (!align) {
227f0647 RD	273	dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
227f0647 RD	274	resno, res);
d09ee968 YL	275	return -EINVAL;
	276	}
	277
2bbc6942 RP	278	size = resource_size(res);
2bbc6942 RP	279	ret = _pci_assign_resource(dev, resno, size, align);
d09ee968	280
2bbc6942 RP	281	/*
	282	* If we failed to assign anything, let's try the address
	283	* where firmware left it. That at least has a chance of
	284	* working, which is better than just leaving it disabled.
	285	*/
64da465e BH	286	if (ret < 0) {
64da465e BH	287	dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
2bbc6942	288	ret = pci_revert_fw_address(res, dev, resno, size);
64da465e	289	}
d09ee968	290
64da465e BH	291	if (ret < 0) {
	292	dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
	293	res);
28f6dbe2	294	return ret;
64da465e	295	}
28f6dbe2 BH	296
	297	res->flags &= ~IORESOURCE_UNSET;
	298	res->flags &= ~IORESOURCE_STARTALIGN;
	299	dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
	300	if (resno < PCI_BRIDGE_RESOURCES)
	301	pci_update_resource(dev, resno);
	302
	303	return 0;
d09ee968	304	}
b7fe9434	305	EXPORT_SYMBOL(pci_assign_resource);
d09ee968	306
fe6dacdb BH	307	int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
	308	resource_size_t min_align)
	309	{
	310	struct resource *res = dev->resource + resno;
c3337708	311	unsigned long flags;
fe6dacdb BH	312	resource_size_t new_size;
	313	int ret;
	314
c3337708	315	flags = res->flags;
bd064f0a	316	res->flags \|= IORESOURCE_UNSET;
fe6dacdb	317	if (!res->parent) {
227f0647 RD	318	dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
227f0647 RD	319	resno, res);
fe6dacdb BH	320	return -EINVAL;
	321	}
	322
	323	/* already aligned with min_align */
	324	new_size = resource_size(res) + addsize;
	325	ret = _pci_assign_resource(dev, resno, new_size, min_align);
28f6dbe2	326	if (ret) {
c3337708 GC	327	res->flags = flags;
	328	dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
	329	resno, res, (unsigned long long) addsize);
28f6dbe2	330	return ret;
fe6dacdb	331	}
c3337708	332
28f6dbe2 BH	333	res->flags &= ~IORESOURCE_UNSET;
28f6dbe2 BH	334	res->flags &= ~IORESOURCE_STARTALIGN;
64da465e BH	335	dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
64da465e BH	336	resno, res, (unsigned long long) addsize);
28f6dbe2 BH	337	if (resno < PCI_BRIDGE_RESOURCES)
	338	pci_update_resource(dev, resno);
	339
	340	return 0;
fe6dacdb BH	341	}
fe6dacdb BH	342
842de40d BH	343	int pci_enable_resources(struct pci_dev *dev, int mask)
	344	{
	345	u16 cmd, old_cmd;
	346	int i;
	347	struct resource *r;
	348
	349	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	350	old_cmd = cmd;
	351
	352	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	353	if (!(mask & (1 << i)))
	354	continue;
	355
	356	r = &dev->resource[i];
	357
	358	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	359	continue;
	360	if ((i == PCI_ROM_RESOURCE) &&
	361	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	362	continue;
	363
3cedcc36 BH	364	if (r->flags & IORESOURCE_UNSET) {
	365	dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
	366	i, r);
	367	return -EINVAL;
	368	}
	369
842de40d	370	if (!r->parent) {
3cedcc36 BH	371	dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
3cedcc36 BH	372	i, r);
842de40d BH	373	return -EINVAL;
	374	}
	375
	376	if (r->flags & IORESOURCE_IO)
	377	cmd \|= PCI_COMMAND_IO;
	378	if (r->flags & IORESOURCE_MEM)
	379	cmd \|= PCI_COMMAND_MEMORY;
	380	}
	381
	382	if (cmd != old_cmd) {
	383	dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
	384	old_cmd, cmd);
	385	pci_write_config_word(dev, PCI_COMMAND, cmd);
	386	}
	387	return 0;
	388	}