Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
6faf17f6 | 28 | #include "pci.h" |
1da177e4 | 29 | |
bdc4abec YL |
30 | struct pci_dev_resource { |
31 | struct list_head list; | |
2934a0de YL |
32 | struct resource *res; |
33 | struct pci_dev *dev; | |
568ddef8 YL |
34 | resource_size_t start; |
35 | resource_size_t end; | |
c8adf9a3 | 36 | resource_size_t add_size; |
2bbc6942 | 37 | resource_size_t min_align; |
568ddef8 YL |
38 | unsigned long flags; |
39 | }; | |
40 | ||
bffc56d4 YL |
41 | static void free_list(struct list_head *head) |
42 | { | |
43 | struct pci_dev_resource *dev_res, *tmp; | |
44 | ||
45 | list_for_each_entry_safe(dev_res, tmp, head, list) { | |
46 | list_del(&dev_res->list); | |
47 | kfree(dev_res); | |
48 | } | |
49 | } | |
094732a5 | 50 | |
f483d392 RP |
51 | int pci_realloc_enable = 0; |
52 | #define pci_realloc_enabled() pci_realloc_enable | |
53 | void pci_realloc(void) | |
54 | { | |
55 | pci_realloc_enable = 1; | |
56 | } | |
57 | ||
c8adf9a3 RP |
58 | /** |
59 | * add_to_list() - add a new resource tracker to the list | |
60 | * @head: Head of the list | |
61 | * @dev: device corresponding to which the resource | |
62 | * belongs | |
63 | * @res: The resource to be tracked | |
64 | * @add_size: additional size to be optionally added | |
65 | * to the resource | |
66 | */ | |
bdc4abec | 67 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 68 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 69 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 70 | { |
764242a0 | 71 | struct pci_dev_resource *tmp; |
568ddef8 | 72 | |
bdc4abec | 73 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
568ddef8 | 74 | if (!tmp) { |
c8adf9a3 | 75 | pr_warning("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 76 | return -ENOMEM; |
568ddef8 YL |
77 | } |
78 | ||
568ddef8 YL |
79 | tmp->res = res; |
80 | tmp->dev = dev; | |
81 | tmp->start = res->start; | |
82 | tmp->end = res->end; | |
83 | tmp->flags = res->flags; | |
c8adf9a3 | 84 | tmp->add_size = add_size; |
2bbc6942 | 85 | tmp->min_align = min_align; |
bdc4abec YL |
86 | |
87 | list_add(&tmp->list, head); | |
ef62dfef YL |
88 | |
89 | return 0; | |
568ddef8 YL |
90 | } |
91 | ||
bdc4abec | 92 | static void add_to_failed_list(struct list_head *head, |
c8adf9a3 RP |
93 | struct pci_dev *dev, struct resource *res) |
94 | { | |
2bbc6942 RP |
95 | add_to_list(head, dev, res, |
96 | 0 /* dont care */, | |
97 | 0 /* dont care */); | |
c8adf9a3 RP |
98 | } |
99 | ||
b9b0bba9 | 100 | static void remove_from_list(struct list_head *head, |
3e6e0d80 YL |
101 | struct resource *res) |
102 | { | |
b9b0bba9 | 103 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 104 | |
b9b0bba9 YL |
105 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
106 | if (dev_res->res == res) { | |
107 | list_del(&dev_res->list); | |
108 | kfree(dev_res); | |
bdc4abec | 109 | break; |
3e6e0d80 | 110 | } |
3e6e0d80 YL |
111 | } |
112 | } | |
113 | ||
b9b0bba9 | 114 | static resource_size_t get_res_add_size(struct list_head *head, |
1c372353 YL |
115 | struct resource *res) |
116 | { | |
b9b0bba9 | 117 | struct pci_dev_resource *dev_res; |
bdc4abec | 118 | |
b9b0bba9 YL |
119 | list_for_each_entry(dev_res, head, list) { |
120 | if (dev_res->res == res) { | |
121 | dev_printk(KERN_DEBUG, &dev_res->dev->dev, | |
bdc4abec | 122 | "%pR get_res_add_size add_size %llx\n", |
b9b0bba9 YL |
123 | dev_res->res, |
124 | (unsigned long long)dev_res->add_size); | |
125 | return dev_res->add_size; | |
bdc4abec | 126 | } |
3e6e0d80 | 127 | } |
1c372353 YL |
128 | |
129 | return 0; | |
130 | } | |
131 | ||
78c3b329 | 132 | /* Sort resources by alignment */ |
bdc4abec | 133 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
134 | { |
135 | int i; | |
136 | ||
137 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
138 | struct resource *r; | |
bdc4abec | 139 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 140 | resource_size_t r_align; |
bdc4abec | 141 | struct list_head *n; |
78c3b329 YL |
142 | |
143 | r = &dev->resource[i]; | |
144 | ||
145 | if (r->flags & IORESOURCE_PCI_FIXED) | |
146 | continue; | |
147 | ||
148 | if (!(r->flags) || r->parent) | |
149 | continue; | |
150 | ||
151 | r_align = pci_resource_alignment(dev, r); | |
152 | if (!r_align) { | |
153 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
154 | i, r); | |
155 | continue; | |
156 | } | |
78c3b329 | 157 | |
bdc4abec YL |
158 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
159 | if (!tmp) | |
160 | panic("pdev_sort_resources(): " | |
161 | "kmalloc() failed!\n"); | |
162 | tmp->res = r; | |
163 | tmp->dev = dev; | |
164 | ||
165 | /* fallback is smallest one or list is empty*/ | |
166 | n = head; | |
167 | list_for_each_entry(dev_res, head, list) { | |
168 | resource_size_t align; | |
169 | ||
170 | align = pci_resource_alignment(dev_res->dev, | |
171 | dev_res->res); | |
78c3b329 YL |
172 | |
173 | if (r_align > align) { | |
bdc4abec | 174 | n = &dev_res->list; |
78c3b329 YL |
175 | break; |
176 | } | |
177 | } | |
bdc4abec YL |
178 | /* Insert it just before n*/ |
179 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
180 | } |
181 | } | |
182 | ||
6841ec68 | 183 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 184 | struct list_head *head) |
1da177e4 | 185 | { |
6841ec68 | 186 | u16 class = dev->class >> 8; |
1da177e4 | 187 | |
6841ec68 YL |
188 | /* Don't touch classless devices or host bridges or ioapics. */ |
189 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
190 | return; | |
1da177e4 | 191 | |
6841ec68 YL |
192 | /* Don't touch ioapic devices already enabled by firmware */ |
193 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
194 | u16 command; | |
195 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
196 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
197 | return; | |
198 | } | |
1da177e4 | 199 | |
6841ec68 YL |
200 | pdev_sort_resources(dev, head); |
201 | } | |
23186279 | 202 | |
fc075e1d RP |
203 | static inline void reset_resource(struct resource *res) |
204 | { | |
205 | res->start = 0; | |
206 | res->end = 0; | |
207 | res->flags = 0; | |
208 | } | |
209 | ||
c8adf9a3 | 210 | /** |
9e8bf93a | 211 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 212 | * |
9e8bf93a | 213 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
214 | * resources |
215 | * @head : head of the list tracking requests with allocated | |
216 | * resources | |
217 | * | |
9e8bf93a | 218 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
219 | * additional resources for the element, provided the element |
220 | * is in the head list. | |
221 | */ | |
bdc4abec YL |
222 | static void reassign_resources_sorted(struct list_head *realloc_head, |
223 | struct list_head *head) | |
6841ec68 YL |
224 | { |
225 | struct resource *res; | |
b9b0bba9 | 226 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 227 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 228 | resource_size_t add_size; |
6841ec68 | 229 | int idx; |
1da177e4 | 230 | |
b9b0bba9 | 231 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
232 | bool found_match = false; |
233 | ||
b9b0bba9 | 234 | res = add_res->res; |
c8adf9a3 RP |
235 | /* skip resource that has been reset */ |
236 | if (!res->flags) | |
237 | goto out; | |
238 | ||
239 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
240 | list_for_each_entry(dev_res, head, list) { |
241 | if (dev_res->res == res) { | |
242 | found_match = true; | |
243 | break; | |
244 | } | |
c8adf9a3 | 245 | } |
bdc4abec YL |
246 | if (!found_match)/* just skip */ |
247 | continue; | |
c8adf9a3 | 248 | |
b9b0bba9 YL |
249 | idx = res - &add_res->dev->resource[0]; |
250 | add_size = add_res->add_size; | |
2bbc6942 | 251 | if (!resource_size(res)) { |
b9b0bba9 | 252 | res->start = add_res->start; |
2bbc6942 | 253 | res->end = res->start + add_size - 1; |
b9b0bba9 | 254 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 255 | reset_resource(res); |
2bbc6942 | 256 | } else { |
b9b0bba9 YL |
257 | resource_size_t align = add_res->min_align; |
258 | res->flags |= add_res->flags & | |
bdc4abec | 259 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 260 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 261 | add_size, align)) |
b9b0bba9 | 262 | dev_printk(KERN_DEBUG, &add_res->dev->dev, |
bdc4abec | 263 | "failed to add optional resources res=%pR\n", |
2bbc6942 | 264 | res); |
c8adf9a3 RP |
265 | } |
266 | out: | |
b9b0bba9 YL |
267 | list_del(&add_res->list); |
268 | kfree(add_res); | |
c8adf9a3 RP |
269 | } |
270 | } | |
271 | ||
272 | /** | |
273 | * assign_requested_resources_sorted() - satisfy resource requests | |
274 | * | |
275 | * @head : head of the list tracking requests for resources | |
276 | * @failed_list : head of the list tracking requests that could | |
277 | * not be allocated | |
278 | * | |
279 | * Satisfy resource requests of each element in the list. Add | |
280 | * requests that could not satisfied to the failed_list. | |
281 | */ | |
bdc4abec YL |
282 | static void assign_requested_resources_sorted(struct list_head *head, |
283 | struct list_head *fail_head) | |
c8adf9a3 RP |
284 | { |
285 | struct resource *res; | |
bdc4abec | 286 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 287 | int idx; |
9a928660 | 288 | |
bdc4abec YL |
289 | list_for_each_entry(dev_res, head, list) { |
290 | res = dev_res->res; | |
291 | idx = res - &dev_res->dev->resource[0]; | |
292 | if (resource_size(res) && | |
293 | pci_assign_resource(dev_res->dev, idx)) { | |
294 | if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) { | |
9a928660 YL |
295 | /* |
296 | * if the failed res is for ROM BAR, and it will | |
297 | * be enabled later, don't add it to the list | |
298 | */ | |
299 | if (!((idx == PCI_ROM_RESOURCE) && | |
300 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
bdc4abec YL |
301 | add_to_failed_list(fail_head, |
302 | dev_res->dev, res); | |
9a928660 | 303 | } |
fc075e1d | 304 | reset_resource(res); |
542df5de | 305 | } |
1da177e4 LT |
306 | } |
307 | } | |
308 | ||
bdc4abec YL |
309 | static void __assign_resources_sorted(struct list_head *head, |
310 | struct list_head *realloc_head, | |
311 | struct list_head *fail_head) | |
c8adf9a3 | 312 | { |
3e6e0d80 YL |
313 | /* |
314 | * Should not assign requested resources at first. | |
315 | * they could be adjacent, so later reassign can not reallocate | |
316 | * them one by one in parent resource window. | |
317 | * Try to assign requested + add_size at begining | |
318 | * if could do that, could get out early. | |
319 | * if could not do that, we still try to assign requested at first, | |
320 | * then try to reassign add_size for some resources. | |
321 | */ | |
bdc4abec YL |
322 | LIST_HEAD(save_head); |
323 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 324 | struct pci_dev_resource *save_res; |
bdc4abec | 325 | struct pci_dev_resource *dev_res; |
3e6e0d80 YL |
326 | |
327 | /* Check if optional add_size is there */ | |
bdc4abec | 328 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
329 | goto requested_and_reassign; |
330 | ||
331 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
332 | list_for_each_entry(dev_res, head, list) { |
333 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
bffc56d4 | 334 | free_list(&save_head); |
3e6e0d80 YL |
335 | goto requested_and_reassign; |
336 | } | |
bdc4abec | 337 | } |
3e6e0d80 YL |
338 | |
339 | /* Update res in head list with add_size in realloc_head list */ | |
bdc4abec YL |
340 | list_for_each_entry(dev_res, head, list) |
341 | dev_res->res->end += get_res_add_size(realloc_head, | |
342 | dev_res->res); | |
3e6e0d80 YL |
343 | |
344 | /* Try updated head list with add_size added */ | |
3e6e0d80 YL |
345 | assign_requested_resources_sorted(head, &local_fail_head); |
346 | ||
347 | /* all assigned with add_size ? */ | |
bdc4abec | 348 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 349 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
350 | list_for_each_entry(dev_res, head, list) |
351 | remove_from_list(realloc_head, dev_res->res); | |
bffc56d4 YL |
352 | free_list(&save_head); |
353 | free_list(head); | |
3e6e0d80 YL |
354 | return; |
355 | } | |
356 | ||
bffc56d4 | 357 | free_list(&local_fail_head); |
3e6e0d80 | 358 | /* Release assigned resource */ |
bdc4abec YL |
359 | list_for_each_entry(dev_res, head, list) |
360 | if (dev_res->res->parent) | |
361 | release_resource(dev_res->res); | |
3e6e0d80 | 362 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
363 | list_for_each_entry(save_res, &save_head, list) { |
364 | struct resource *res = save_res->res; | |
3e6e0d80 | 365 | |
b9b0bba9 YL |
366 | res->start = save_res->start; |
367 | res->end = save_res->end; | |
368 | res->flags = save_res->flags; | |
3e6e0d80 | 369 | } |
bffc56d4 | 370 | free_list(&save_head); |
3e6e0d80 YL |
371 | |
372 | requested_and_reassign: | |
c8adf9a3 RP |
373 | /* Satisfy the must-have resource requests */ |
374 | assign_requested_resources_sorted(head, fail_head); | |
375 | ||
0a2daa1c | 376 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 377 | requests */ |
9e8bf93a RP |
378 | if (realloc_head) |
379 | reassign_resources_sorted(realloc_head, head); | |
bffc56d4 | 380 | free_list(head); |
c8adf9a3 RP |
381 | } |
382 | ||
6841ec68 | 383 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
384 | struct list_head *add_head, |
385 | struct list_head *fail_head) | |
6841ec68 | 386 | { |
bdc4abec | 387 | LIST_HEAD(head); |
6841ec68 | 388 | |
6841ec68 | 389 | __dev_sort_resources(dev, &head); |
8424d759 | 390 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
391 | |
392 | } | |
393 | ||
394 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
395 | struct list_head *realloc_head, |
396 | struct list_head *fail_head) | |
6841ec68 YL |
397 | { |
398 | struct pci_dev *dev; | |
bdc4abec | 399 | LIST_HEAD(head); |
6841ec68 | 400 | |
6841ec68 YL |
401 | list_for_each_entry(dev, &bus->devices, bus_list) |
402 | __dev_sort_resources(dev, &head); | |
403 | ||
9e8bf93a | 404 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
405 | } |
406 | ||
b3743fa4 | 407 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
408 | { |
409 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 410 | struct resource *res; |
1da177e4 LT |
411 | struct pci_bus_region region; |
412 | ||
865df576 BH |
413 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
414 | bus->secondary, bus->subordinate); | |
1da177e4 | 415 | |
c7dabef8 BH |
416 | res = bus->resource[0]; |
417 | pcibios_resource_to_bus(bridge, ®ion, res); | |
418 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
419 | /* |
420 | * The IO resource is allocated a range twice as large as it | |
421 | * would normally need. This allows us to set both IO regs. | |
422 | */ | |
c7dabef8 | 423 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
424 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
425 | region.start); | |
426 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
427 | region.end); | |
428 | } | |
429 | ||
c7dabef8 BH |
430 | res = bus->resource[1]; |
431 | pcibios_resource_to_bus(bridge, ®ion, res); | |
432 | if (res->flags & IORESOURCE_IO) { | |
433 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
434 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
435 | region.start); | |
436 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
437 | region.end); | |
438 | } | |
439 | ||
c7dabef8 BH |
440 | res = bus->resource[2]; |
441 | pcibios_resource_to_bus(bridge, ®ion, res); | |
442 | if (res->flags & IORESOURCE_MEM) { | |
443 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
444 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
445 | region.start); | |
446 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
447 | region.end); | |
448 | } | |
449 | ||
c7dabef8 BH |
450 | res = bus->resource[3]; |
451 | pcibios_resource_to_bus(bridge, ®ion, res); | |
452 | if (res->flags & IORESOURCE_MEM) { | |
453 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
454 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
455 | region.start); | |
456 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
457 | region.end); | |
458 | } | |
459 | } | |
b3743fa4 | 460 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
461 | |
462 | /* Initialize bridges with base/limit values we have collected. | |
463 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
464 | requires that if there is no I/O ports or memory behind the | |
465 | bridge, corresponding range must be turned off by writing base | |
466 | value greater than limit to the bridge's base/limit registers. | |
467 | ||
468 | Note: care must be taken when updating I/O base/limit registers | |
469 | of bridges which support 32-bit I/O. This update requires two | |
470 | config space writes, so it's quite possible that an I/O window of | |
471 | the bridge will have some undesirable address (e.g. 0) after the | |
472 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 473 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
474 | { |
475 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 476 | struct resource *res; |
1da177e4 | 477 | struct pci_bus_region region; |
7cc5997d | 478 | u32 l, io_upper16; |
1da177e4 LT |
479 | |
480 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
481 | res = bus->resource[0]; |
482 | pcibios_resource_to_bus(bridge, ®ion, res); | |
483 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
484 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
485 | l &= 0xffff0000; | |
486 | l |= (region.start >> 8) & 0x00f0; | |
487 | l |= region.end & 0xf000; | |
488 | /* Set up upper 16 bits of I/O base/limit. */ | |
489 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 490 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 491 | } else { |
1da177e4 LT |
492 | /* Clear upper 16 bits of I/O base/limit. */ |
493 | io_upper16 = 0; | |
494 | l = 0x00f0; | |
1da177e4 LT |
495 | } |
496 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
497 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
498 | /* Update lower 16 bits of I/O base/limit. */ | |
499 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
500 | /* Update upper 16 bits of I/O base/limit. */ | |
501 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
502 | } |
503 | ||
504 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
505 | { | |
506 | struct pci_dev *bridge = bus->self; | |
507 | struct resource *res; | |
508 | struct pci_bus_region region; | |
509 | u32 l; | |
1da177e4 | 510 | |
7cc5997d | 511 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 BH |
512 | res = bus->resource[1]; |
513 | pcibios_resource_to_bus(bridge, ®ion, res); | |
514 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
515 | l = (region.start >> 16) & 0xfff0; |
516 | l |= region.end & 0xfff00000; | |
c7dabef8 | 517 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 518 | } else { |
1da177e4 | 519 | l = 0x0000fff0; |
1da177e4 LT |
520 | } |
521 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
522 | } |
523 | ||
524 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
525 | { | |
526 | struct pci_dev *bridge = bus->self; | |
527 | struct resource *res; | |
528 | struct pci_bus_region region; | |
529 | u32 l, bu, lu; | |
1da177e4 LT |
530 | |
531 | /* Clear out the upper 32 bits of PREF limit. | |
532 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
533 | disables PREF range, which is ok. */ | |
534 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
535 | ||
536 | /* Set up PREF base/limit. */ | |
c40a22e0 | 537 | bu = lu = 0; |
c7dabef8 BH |
538 | res = bus->resource[2]; |
539 | pcibios_resource_to_bus(bridge, ®ion, res); | |
540 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
541 | l = (region.start >> 16) & 0xfff0; |
542 | l |= region.end & 0xfff00000; | |
c7dabef8 | 543 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
544 | bu = upper_32_bits(region.start); |
545 | lu = upper_32_bits(region.end); | |
1f82de10 | 546 | } |
c7dabef8 | 547 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 548 | } else { |
1da177e4 | 549 | l = 0x0000fff0; |
1da177e4 LT |
550 | } |
551 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
552 | ||
59353ea3 AW |
553 | /* Set the upper 32 bits of PREF base & limit. */ |
554 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
555 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
556 | } |
557 | ||
558 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
559 | { | |
560 | struct pci_dev *bridge = bus->self; | |
561 | ||
7cc5997d YL |
562 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
563 | bus->secondary, bus->subordinate); | |
564 | ||
565 | if (type & IORESOURCE_IO) | |
566 | pci_setup_bridge_io(bus); | |
567 | ||
568 | if (type & IORESOURCE_MEM) | |
569 | pci_setup_bridge_mmio(bus); | |
570 | ||
571 | if (type & IORESOURCE_PREFETCH) | |
572 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
573 | |
574 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
575 | } | |
576 | ||
e2444273 | 577 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
578 | { |
579 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
580 | IORESOURCE_PREFETCH; | |
581 | ||
582 | __pci_setup_bridge(bus, type); | |
583 | } | |
584 | ||
1da177e4 LT |
585 | /* Check whether the bridge supports optional I/O and |
586 | prefetchable memory ranges. If not, the respective | |
587 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 588 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
589 | { |
590 | u16 io; | |
591 | u32 pmem; | |
592 | struct pci_dev *bridge = bus->self; | |
593 | struct resource *b_res; | |
594 | ||
595 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
596 | b_res[1].flags |= IORESOURCE_MEM; | |
597 | ||
598 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
599 | if (!io) { | |
600 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
601 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
602 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
603 | } | |
604 | if (io) | |
605 | b_res[0].flags |= IORESOURCE_IO; | |
606 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
607 | disconnect boundary by one PCI data phase. | |
608 | Workaround: do not use prefetching on this device. */ | |
609 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
610 | return; | |
611 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
612 | if (!pmem) { | |
613 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
614 | 0xfff0fff0); | |
615 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
616 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
617 | } | |
1f82de10 | 618 | if (pmem) { |
1da177e4 | 619 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
620 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
621 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 622 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
623 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
624 | } | |
1f82de10 YL |
625 | } |
626 | ||
627 | /* double check if bridge does support 64 bit pref */ | |
628 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
629 | u32 mem_base_hi, tmp; | |
630 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
631 | &mem_base_hi); | |
632 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
633 | 0xffffffff); | |
634 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
635 | if (!tmp) | |
636 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
637 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
638 | mem_base_hi); | |
639 | } | |
1da177e4 LT |
640 | } |
641 | ||
642 | /* Helper function for sizing routines: find first available | |
643 | bus resource of a given type. Note: we intentionally skip | |
644 | the bus resources which have already been assigned (that is, | |
645 | have non-NULL parent resource). */ | |
96bde06a | 646 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
647 | { |
648 | int i; | |
649 | struct resource *r; | |
650 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
651 | IORESOURCE_PREFETCH; | |
652 | ||
89a74ecc | 653 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
654 | if (r == &ioport_resource || r == &iomem_resource) |
655 | continue; | |
55a10984 JB |
656 | if (r && (r->flags & type_mask) == type && !r->parent) |
657 | return r; | |
1da177e4 LT |
658 | } |
659 | return NULL; | |
660 | } | |
661 | ||
13583b16 RP |
662 | static resource_size_t calculate_iosize(resource_size_t size, |
663 | resource_size_t min_size, | |
664 | resource_size_t size1, | |
665 | resource_size_t old_size, | |
666 | resource_size_t align) | |
667 | { | |
668 | if (size < min_size) | |
669 | size = min_size; | |
670 | if (old_size == 1 ) | |
671 | old_size = 0; | |
672 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
673 | flag in the struct pci_bus. */ | |
674 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
675 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
676 | #endif | |
677 | size = ALIGN(size + size1, align); | |
678 | if (size < old_size) | |
679 | size = old_size; | |
680 | return size; | |
681 | } | |
682 | ||
683 | static resource_size_t calculate_memsize(resource_size_t size, | |
684 | resource_size_t min_size, | |
685 | resource_size_t size1, | |
686 | resource_size_t old_size, | |
687 | resource_size_t align) | |
688 | { | |
689 | if (size < min_size) | |
690 | size = min_size; | |
691 | if (old_size == 1 ) | |
692 | old_size = 0; | |
693 | if (size < old_size) | |
694 | size = old_size; | |
695 | size = ALIGN(size + size1, align); | |
696 | return size; | |
697 | } | |
698 | ||
c8adf9a3 RP |
699 | /** |
700 | * pbus_size_io() - size the io window of a given bus | |
701 | * | |
702 | * @bus : the bus | |
703 | * @min_size : the minimum io window that must to be allocated | |
704 | * @add_size : additional optional io window | |
9e8bf93a | 705 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
706 | * |
707 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
708 | * since these windows have 4K granularity and the IO ranges | |
709 | * of non-bridge PCI devices are limited to 256 bytes. | |
710 | * We must be careful with the ISA aliasing though. | |
711 | */ | |
712 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 713 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
714 | { |
715 | struct pci_dev *dev; | |
716 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
c8adf9a3 | 717 | unsigned long size = 0, size0 = 0, size1 = 0; |
be768912 | 718 | resource_size_t children_add_size = 0; |
1da177e4 LT |
719 | |
720 | if (!b_res) | |
721 | return; | |
722 | ||
723 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
724 | int i; | |
725 | ||
726 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
727 | struct resource *r = &dev->resource[i]; | |
728 | unsigned long r_size; | |
729 | ||
730 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
731 | continue; | |
022edd86 | 732 | r_size = resource_size(r); |
1da177e4 LT |
733 | |
734 | if (r_size < 0x400) | |
735 | /* Might be re-aligned for ISA */ | |
736 | size += r_size; | |
737 | else | |
738 | size1 += r_size; | |
be768912 | 739 | |
9e8bf93a RP |
740 | if (realloc_head) |
741 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
742 | } |
743 | } | |
c8adf9a3 RP |
744 | size0 = calculate_iosize(size, min_size, size1, |
745 | resource_size(b_res), 4096); | |
be768912 YL |
746 | if (children_add_size > add_size) |
747 | add_size = children_add_size; | |
9e8bf93a | 748 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 749 | calculate_iosize(size, min_size, add_size + size1, |
13583b16 | 750 | resource_size(b_res), 4096); |
c8adf9a3 | 751 | if (!size0 && !size1) { |
865df576 BH |
752 | if (b_res->start || b_res->end) |
753 | dev_info(&bus->self->dev, "disabling bridge window " | |
754 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
755 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
756 | b_res->flags = 0; |
757 | return; | |
758 | } | |
759 | /* Alignment of the IO window is always 4K */ | |
760 | b_res->start = 4096; | |
c8adf9a3 | 761 | b_res->end = b_res->start + size0 - 1; |
88452565 | 762 | b_res->flags |= IORESOURCE_STARTALIGN; |
9e8bf93a RP |
763 | if (size1 > size0 && realloc_head) |
764 | add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096); | |
1da177e4 LT |
765 | } |
766 | ||
c8adf9a3 RP |
767 | /** |
768 | * pbus_size_mem() - size the memory window of a given bus | |
769 | * | |
770 | * @bus : the bus | |
771 | * @min_size : the minimum memory window that must to be allocated | |
772 | * @add_size : additional optional memory window | |
9e8bf93a | 773 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
774 | * |
775 | * Calculate the size of the bus and minimal alignment which | |
776 | * guarantees that all child resources fit in this size. | |
777 | */ | |
28760489 | 778 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
c8adf9a3 RP |
779 | unsigned long type, resource_size_t min_size, |
780 | resource_size_t add_size, | |
bdc4abec | 781 | struct list_head *realloc_head) |
1da177e4 LT |
782 | { |
783 | struct pci_dev *dev; | |
c8adf9a3 | 784 | resource_size_t min_align, align, size, size0, size1; |
c40a22e0 | 785 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
786 | int order, max_order; |
787 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 788 | unsigned int mem64_mask = 0; |
be768912 | 789 | resource_size_t children_add_size = 0; |
1da177e4 LT |
790 | |
791 | if (!b_res) | |
792 | return 0; | |
793 | ||
794 | memset(aligns, 0, sizeof(aligns)); | |
795 | max_order = 0; | |
796 | size = 0; | |
797 | ||
1f82de10 YL |
798 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
799 | b_res->flags &= ~IORESOURCE_MEM_64; | |
800 | ||
1da177e4 LT |
801 | list_for_each_entry(dev, &bus->devices, bus_list) { |
802 | int i; | |
1f82de10 | 803 | |
1da177e4 LT |
804 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
805 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 806 | resource_size_t r_size; |
1da177e4 LT |
807 | |
808 | if (r->parent || (r->flags & mask) != type) | |
809 | continue; | |
022edd86 | 810 | r_size = resource_size(r); |
2aceefcb YL |
811 | #ifdef CONFIG_PCI_IOV |
812 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 813 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb YL |
814 | i <= PCI_IOV_RESOURCE_END) { |
815 | r->end = r->start - 1; | |
9e8bf93a | 816 | add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); |
2aceefcb YL |
817 | children_add_size += r_size; |
818 | continue; | |
819 | } | |
820 | #endif | |
1da177e4 | 821 | /* For bridges size != alignment */ |
6faf17f6 | 822 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
823 | order = __ffs(align) - 20; |
824 | if (order > 11) { | |
865df576 BH |
825 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
826 | "(bad alignment %#llx)\n", i, r, | |
827 | (unsigned long long) align); | |
1da177e4 LT |
828 | r->flags = 0; |
829 | continue; | |
830 | } | |
831 | size += r_size; | |
832 | if (order < 0) | |
833 | order = 0; | |
834 | /* Exclude ranges with size > align from | |
835 | calculation of the alignment. */ | |
836 | if (r_size == align) | |
837 | aligns[order] += align; | |
838 | if (order > max_order) | |
839 | max_order = order; | |
1f82de10 | 840 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
be768912 | 841 | |
9e8bf93a RP |
842 | if (realloc_head) |
843 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
844 | } |
845 | } | |
1da177e4 LT |
846 | align = 0; |
847 | min_align = 0; | |
848 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
849 | resource_size_t align1 = 1; |
850 | ||
851 | align1 <<= (order + 20); | |
852 | ||
1da177e4 LT |
853 | if (!align) |
854 | min_align = align1; | |
6f6f8c2f | 855 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
856 | min_align = align1 >> 1; |
857 | align += aligns[order]; | |
858 | } | |
b42282e5 | 859 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
be768912 YL |
860 | if (children_add_size > add_size) |
861 | add_size = children_add_size; | |
9e8bf93a | 862 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 863 | calculate_memsize(size, min_size, add_size, |
b42282e5 | 864 | resource_size(b_res), min_align); |
c8adf9a3 | 865 | if (!size0 && !size1) { |
865df576 BH |
866 | if (b_res->start || b_res->end) |
867 | dev_info(&bus->self->dev, "disabling bridge window " | |
868 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
869 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
870 | b_res->flags = 0; |
871 | return 1; | |
872 | } | |
873 | b_res->start = min_align; | |
c8adf9a3 RP |
874 | b_res->end = size0 + min_align - 1; |
875 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; | |
9e8bf93a RP |
876 | if (size1 > size0 && realloc_head) |
877 | add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); | |
1da177e4 LT |
878 | return 1; |
879 | } | |
880 | ||
0a2daa1c RP |
881 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
882 | { | |
883 | if (res->flags & IORESOURCE_IO) | |
884 | return pci_cardbus_io_size; | |
885 | if (res->flags & IORESOURCE_MEM) | |
886 | return pci_cardbus_mem_size; | |
887 | return 0; | |
888 | } | |
889 | ||
890 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 891 | struct list_head *realloc_head) |
1da177e4 LT |
892 | { |
893 | struct pci_dev *bridge = bus->self; | |
894 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
895 | u16 ctrl; | |
896 | ||
897 | /* | |
898 | * Reserve some resources for CardBus. We reserve | |
899 | * a fixed amount of bus space for CardBus bridges. | |
900 | */ | |
934b7024 | 901 | b_res[0].start = 0; |
934b7024 | 902 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
903 | if (realloc_head) |
904 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 0 /* dont care */); | |
1da177e4 | 905 | |
934b7024 | 906 | b_res[1].start = 0; |
934b7024 | 907 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
908 | if (realloc_head) |
909 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */); | |
1da177e4 LT |
910 | |
911 | /* | |
912 | * Check whether prefetchable memory is supported | |
913 | * by this bridge. | |
914 | */ | |
915 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
916 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
917 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
918 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
919 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
920 | } | |
921 | ||
922 | /* | |
923 | * If we have prefetchable memory support, allocate | |
924 | * two regions. Otherwise, allocate one region of | |
925 | * twice the size. | |
926 | */ | |
927 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
934b7024 | 928 | b_res[2].start = 0; |
934b7024 | 929 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
930 | if (realloc_head) |
931 | add_to_list(realloc_head, bridge, b_res+2, pci_cardbus_mem_size, 0 /* dont care */); | |
1da177e4 | 932 | |
934b7024 | 933 | b_res[3].start = 0; |
934b7024 | 934 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
935 | if (realloc_head) |
936 | add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size, 0 /* dont care */); | |
1da177e4 | 937 | } else { |
934b7024 | 938 | b_res[3].start = 0; |
934b7024 | 939 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
940 | if (realloc_head) |
941 | add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size * 2, 0 /* dont care */); | |
1da177e4 | 942 | } |
0a2daa1c RP |
943 | |
944 | /* set the size of the resource to zero, so that the resource does not | |
945 | * get assigned during required-resource allocation cycle but gets assigned | |
946 | * during the optional-resource allocation cycle. | |
947 | */ | |
948 | b_res[0].start = b_res[1].start = b_res[2].start = b_res[3].start = 1; | |
949 | b_res[0].end = b_res[1].end = b_res[2].end = b_res[3].end = 0; | |
1da177e4 LT |
950 | } |
951 | ||
c8adf9a3 | 952 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
bdc4abec | 953 | struct list_head *realloc_head) |
1da177e4 LT |
954 | { |
955 | struct pci_dev *dev; | |
956 | unsigned long mask, prefmask; | |
c8adf9a3 | 957 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
1da177e4 LT |
958 | |
959 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
960 | struct pci_bus *b = dev->subordinate; | |
961 | if (!b) | |
962 | continue; | |
963 | ||
964 | switch (dev->class >> 8) { | |
965 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 966 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
967 | break; |
968 | ||
969 | case PCI_CLASS_BRIDGE_PCI: | |
970 | default: | |
9e8bf93a | 971 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
972 | break; |
973 | } | |
974 | } | |
975 | ||
976 | /* The root bus? */ | |
977 | if (!bus->self) | |
978 | return; | |
979 | ||
980 | switch (bus->self->class >> 8) { | |
981 | case PCI_CLASS_BRIDGE_CARDBUS: | |
982 | /* don't size cardbuses yet. */ | |
983 | break; | |
984 | ||
985 | case PCI_CLASS_BRIDGE_PCI: | |
986 | pci_bridge_check_ranges(bus); | |
28760489 | 987 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
988 | additional_io_size = pci_hotplug_io_size; |
989 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 990 | } |
c8adf9a3 RP |
991 | /* |
992 | * Follow thru | |
993 | */ | |
1da177e4 | 994 | default: |
19aa7ee4 YL |
995 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
996 | additional_io_size, realloc_head); | |
1da177e4 LT |
997 | /* If the bridge supports prefetchable range, size it |
998 | separately. If it doesn't, or its prefetchable window | |
999 | has already been allocated by arch code, try | |
1000 | non-prefetchable range for both types of PCI memory | |
1001 | resources. */ | |
1002 | mask = IORESOURCE_MEM; | |
1003 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
19aa7ee4 YL |
1004 | if (pbus_size_mem(bus, prefmask, prefmask, |
1005 | realloc_head ? 0 : additional_mem_size, | |
1006 | additional_mem_size, realloc_head)) | |
1da177e4 | 1007 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 | 1008 | else |
c8adf9a3 | 1009 | additional_mem_size += additional_mem_size; |
19aa7ee4 YL |
1010 | pbus_size_mem(bus, mask, IORESOURCE_MEM, |
1011 | realloc_head ? 0 : additional_mem_size, | |
1012 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1013 | break; |
1014 | } | |
1015 | } | |
c8adf9a3 RP |
1016 | |
1017 | void __ref pci_bus_size_bridges(struct pci_bus *bus) | |
1018 | { | |
1019 | __pci_bus_size_bridges(bus, NULL); | |
1020 | } | |
1da177e4 LT |
1021 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1022 | ||
568ddef8 | 1023 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
bdc4abec YL |
1024 | struct list_head *realloc_head, |
1025 | struct list_head *fail_head) | |
1da177e4 LT |
1026 | { |
1027 | struct pci_bus *b; | |
1028 | struct pci_dev *dev; | |
1029 | ||
9e8bf93a | 1030 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1031 | |
1da177e4 LT |
1032 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1033 | b = dev->subordinate; | |
1034 | if (!b) | |
1035 | continue; | |
1036 | ||
9e8bf93a | 1037 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1038 | |
1039 | switch (dev->class >> 8) { | |
1040 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1041 | if (!pci_is_enabled(dev)) |
1042 | pci_setup_bridge(b); | |
1da177e4 LT |
1043 | break; |
1044 | ||
1045 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1046 | pci_setup_cardbus(b); | |
1047 | break; | |
1048 | ||
1049 | default: | |
80ccba11 BH |
1050 | dev_info(&dev->dev, "not setting up bridge for bus " |
1051 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
1052 | break; |
1053 | } | |
1054 | } | |
1055 | } | |
568ddef8 YL |
1056 | |
1057 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
1058 | { | |
c8adf9a3 | 1059 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1060 | } |
1da177e4 LT |
1061 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1062 | ||
6841ec68 | 1063 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
bdc4abec YL |
1064 | struct list_head *add_head, |
1065 | struct list_head *fail_head) | |
6841ec68 YL |
1066 | { |
1067 | struct pci_bus *b; | |
1068 | ||
8424d759 YL |
1069 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1070 | add_head, fail_head); | |
6841ec68 YL |
1071 | |
1072 | b = bridge->subordinate; | |
1073 | if (!b) | |
1074 | return; | |
1075 | ||
8424d759 | 1076 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1077 | |
1078 | switch (bridge->class >> 8) { | |
1079 | case PCI_CLASS_BRIDGE_PCI: | |
1080 | pci_setup_bridge(b); | |
1081 | break; | |
1082 | ||
1083 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1084 | pci_setup_cardbus(b); | |
1085 | break; | |
1086 | ||
1087 | default: | |
1088 | dev_info(&bridge->dev, "not setting up bridge for bus " | |
1089 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1090 | break; | |
1091 | } | |
1092 | } | |
5009b460 YL |
1093 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1094 | unsigned long type) | |
1095 | { | |
1096 | int idx; | |
1097 | bool changed = false; | |
1098 | struct pci_dev *dev; | |
1099 | struct resource *r; | |
1100 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1101 | IORESOURCE_PREFETCH; | |
1102 | ||
1103 | dev = bus->self; | |
1104 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
1105 | idx++) { | |
1106 | r = &dev->resource[idx]; | |
1107 | if ((r->flags & type_mask) != type) | |
1108 | continue; | |
1109 | if (!r->parent) | |
1110 | continue; | |
1111 | /* | |
1112 | * if there are children under that, we should release them | |
1113 | * all | |
1114 | */ | |
1115 | release_child_resources(r); | |
1116 | if (!release_resource(r)) { | |
1117 | dev_printk(KERN_DEBUG, &dev->dev, | |
1118 | "resource %d %pR released\n", idx, r); | |
1119 | /* keep the old size */ | |
1120 | r->end = resource_size(r) - 1; | |
1121 | r->start = 0; | |
1122 | r->flags = 0; | |
1123 | changed = true; | |
1124 | } | |
1125 | } | |
1126 | ||
1127 | if (changed) { | |
1128 | /* avoiding touch the one without PREF */ | |
1129 | if (type & IORESOURCE_PREFETCH) | |
1130 | type = IORESOURCE_PREFETCH; | |
1131 | __pci_setup_bridge(bus, type); | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | enum release_type { | |
1136 | leaf_only, | |
1137 | whole_subtree, | |
1138 | }; | |
1139 | /* | |
1140 | * try to release pci bridge resources that is from leaf bridge, | |
1141 | * so we can allocate big new one later | |
1142 | */ | |
1143 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
1144 | unsigned long type, | |
1145 | enum release_type rel_type) | |
1146 | { | |
1147 | struct pci_dev *dev; | |
1148 | bool is_leaf_bridge = true; | |
1149 | ||
1150 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1151 | struct pci_bus *b = dev->subordinate; | |
1152 | if (!b) | |
1153 | continue; | |
1154 | ||
1155 | is_leaf_bridge = false; | |
1156 | ||
1157 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1158 | continue; | |
1159 | ||
1160 | if (rel_type == whole_subtree) | |
1161 | pci_bus_release_bridge_resources(b, type, | |
1162 | whole_subtree); | |
1163 | } | |
1164 | ||
1165 | if (pci_is_root_bus(bus)) | |
1166 | return; | |
1167 | ||
1168 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1169 | return; | |
1170 | ||
1171 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1172 | pci_bridge_release_resources(bus, type); | |
1173 | } | |
1174 | ||
76fbc263 YL |
1175 | static void pci_bus_dump_res(struct pci_bus *bus) |
1176 | { | |
89a74ecc BH |
1177 | struct resource *res; |
1178 | int i; | |
7c9342b8 | 1179 | |
89a74ecc | 1180 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1181 | if (!res || !res->end || !res->flags) |
76fbc263 YL |
1182 | continue; |
1183 | ||
c7dabef8 | 1184 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
1185 | } |
1186 | } | |
1187 | ||
1188 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1189 | { | |
1190 | struct pci_bus *b; | |
1191 | struct pci_dev *dev; | |
1192 | ||
1193 | ||
1194 | pci_bus_dump_res(bus); | |
1195 | ||
1196 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1197 | b = dev->subordinate; | |
1198 | if (!b) | |
1199 | continue; | |
1200 | ||
1201 | pci_bus_dump_resources(b); | |
1202 | } | |
1203 | } | |
1204 | ||
da7822e5 YL |
1205 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
1206 | { | |
1207 | int depth = 0; | |
1208 | struct pci_dev *dev; | |
1209 | ||
1210 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1211 | int ret; | |
1212 | struct pci_bus *b = dev->subordinate; | |
1213 | if (!b) | |
1214 | continue; | |
1215 | ||
1216 | ret = pci_bus_get_depth(b); | |
1217 | if (ret + 1 > depth) | |
1218 | depth = ret + 1; | |
1219 | } | |
1220 | ||
1221 | return depth; | |
1222 | } | |
1223 | static int __init pci_get_max_depth(void) | |
1224 | { | |
1225 | int depth = 0; | |
1226 | struct pci_bus *bus; | |
1227 | ||
1228 | list_for_each_entry(bus, &pci_root_buses, node) { | |
1229 | int ret; | |
1230 | ||
1231 | ret = pci_bus_get_depth(bus); | |
1232 | if (ret > depth) | |
1233 | depth = ret; | |
1234 | } | |
1235 | ||
1236 | return depth; | |
1237 | } | |
1238 | ||
f483d392 | 1239 | |
da7822e5 YL |
1240 | /* |
1241 | * first try will not touch pci bridge res | |
1242 | * second and later try will clear small leaf bridge res | |
1243 | * will stop till to the max deepth if can not find good one | |
1244 | */ | |
1da177e4 LT |
1245 | void __init |
1246 | pci_assign_unassigned_resources(void) | |
1247 | { | |
1248 | struct pci_bus *bus; | |
bdc4abec | 1249 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1250 | want additional resources */ |
bdc4abec | 1251 | struct list_head *add_list = NULL; |
da7822e5 YL |
1252 | int tried_times = 0; |
1253 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1254 | LIST_HEAD(fail_head); |
b9b0bba9 | 1255 | struct pci_dev_resource *fail_res; |
da7822e5 YL |
1256 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1257 | IORESOURCE_PREFETCH; | |
1258 | unsigned long failed_type; | |
19aa7ee4 | 1259 | int pci_try_num = 1; |
da7822e5 | 1260 | |
19aa7ee4 YL |
1261 | /* don't realloc if asked to do so */ |
1262 | if (pci_realloc_enabled()) { | |
1263 | int max_depth = pci_get_max_depth(); | |
1264 | ||
1265 | pci_try_num = max_depth + 1; | |
1266 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", | |
1267 | max_depth, pci_try_num); | |
1268 | } | |
da7822e5 YL |
1269 | |
1270 | again: | |
19aa7ee4 YL |
1271 | /* |
1272 | * last try will use add_list, otherwise will try good to have as | |
1273 | * must have, so can realloc parent bridge resource | |
1274 | */ | |
1275 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1276 | add_list = &realloc_head; |
1da177e4 LT |
1277 | /* Depth first, calculate sizes and alignments of all |
1278 | subordinate buses. */ | |
da7822e5 | 1279 | list_for_each_entry(bus, &pci_root_buses, node) |
19aa7ee4 | 1280 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1281 | |
1da177e4 | 1282 | /* Depth last, allocate resources and update the hardware. */ |
da7822e5 | 1283 | list_for_each_entry(bus, &pci_root_buses, node) |
bdc4abec | 1284 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1285 | if (add_list) |
bdc4abec | 1286 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1287 | tried_times++; |
1288 | ||
1289 | /* any device complain? */ | |
bdc4abec | 1290 | if (list_empty(&fail_head)) |
da7822e5 | 1291 | goto enable_and_dump; |
f483d392 | 1292 | |
da7822e5 | 1293 | failed_type = 0; |
b9b0bba9 YL |
1294 | list_for_each_entry(fail_res, &fail_head, list) |
1295 | failed_type |= fail_res->flags; | |
bdc4abec | 1296 | |
da7822e5 YL |
1297 | /* |
1298 | * io port are tight, don't try extra | |
1299 | * or if reach the limit, don't want to try more | |
1300 | */ | |
1301 | failed_type &= type_mask; | |
1302 | if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) { | |
bffc56d4 | 1303 | free_list(&fail_head); |
da7822e5 YL |
1304 | goto enable_and_dump; |
1305 | } | |
1306 | ||
1307 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1308 | tried_times + 1); | |
1309 | ||
1310 | /* third times and later will not check if it is leaf */ | |
1311 | if ((tried_times + 1) > 2) | |
1312 | rel_type = whole_subtree; | |
1313 | ||
1314 | /* | |
1315 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1316 | * child device under that bridge | |
1317 | */ | |
b9b0bba9 YL |
1318 | list_for_each_entry(fail_res, &fail_head, list) { |
1319 | bus = fail_res->dev->bus; | |
bdc4abec | 1320 | pci_bus_release_bridge_resources(bus, |
b9b0bba9 | 1321 | fail_res->flags & type_mask, |
bdc4abec | 1322 | rel_type); |
da7822e5 YL |
1323 | } |
1324 | /* restore size and flags */ | |
b9b0bba9 YL |
1325 | list_for_each_entry(fail_res, &fail_head, list) { |
1326 | struct resource *res = fail_res->res; | |
da7822e5 | 1327 | |
b9b0bba9 YL |
1328 | res->start = fail_res->start; |
1329 | res->end = fail_res->end; | |
1330 | res->flags = fail_res->flags; | |
1331 | if (fail_res->dev->subordinate) | |
da7822e5 | 1332 | res->flags = 0; |
da7822e5 | 1333 | } |
bffc56d4 | 1334 | free_list(&fail_head); |
da7822e5 YL |
1335 | |
1336 | goto again; | |
1337 | ||
1338 | enable_and_dump: | |
1339 | /* Depth last, update the hardware. */ | |
1340 | list_for_each_entry(bus, &pci_root_buses, node) | |
1341 | pci_enable_bridges(bus); | |
76fbc263 YL |
1342 | |
1343 | /* dump the resource on buses */ | |
da7822e5 | 1344 | list_for_each_entry(bus, &pci_root_buses, node) |
76fbc263 | 1345 | pci_bus_dump_resources(bus); |
1da177e4 | 1346 | } |
6841ec68 YL |
1347 | |
1348 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1349 | { | |
1350 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 1351 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 1352 | want additional resources */ |
32180e40 | 1353 | int tried_times = 0; |
bdc4abec | 1354 | LIST_HEAD(fail_head); |
b9b0bba9 | 1355 | struct pci_dev_resource *fail_res; |
6841ec68 | 1356 | int retval; |
32180e40 YL |
1357 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1358 | IORESOURCE_PREFETCH; | |
1359 | ||
32180e40 | 1360 | again: |
8424d759 | 1361 | __pci_bus_size_bridges(parent, &add_list); |
bdc4abec YL |
1362 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
1363 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
1364 | tried_times++; |
1365 | ||
bdc4abec | 1366 | if (list_empty(&fail_head)) |
3f579c34 | 1367 | goto enable_all; |
32180e40 YL |
1368 | |
1369 | if (tried_times >= 2) { | |
1370 | /* still fail, don't need to try more */ | |
bffc56d4 | 1371 | free_list(&fail_head); |
3f579c34 | 1372 | goto enable_all; |
32180e40 YL |
1373 | } |
1374 | ||
1375 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1376 | tried_times + 1); | |
1377 | ||
1378 | /* | |
1379 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1380 | * child device under that bridge | |
1381 | */ | |
b9b0bba9 YL |
1382 | list_for_each_entry(fail_res, &fail_head, list) { |
1383 | struct pci_bus *bus = fail_res->dev->bus; | |
1384 | unsigned long flags = fail_res->flags; | |
32180e40 YL |
1385 | |
1386 | pci_bus_release_bridge_resources(bus, flags & type_mask, | |
1387 | whole_subtree); | |
32180e40 YL |
1388 | } |
1389 | /* restore size and flags */ | |
b9b0bba9 YL |
1390 | list_for_each_entry(fail_res, &fail_head, list) { |
1391 | struct resource *res = fail_res->res; | |
32180e40 | 1392 | |
b9b0bba9 YL |
1393 | res->start = fail_res->start; |
1394 | res->end = fail_res->end; | |
1395 | res->flags = fail_res->flags; | |
1396 | if (fail_res->dev->subordinate) | |
32180e40 | 1397 | res->flags = 0; |
32180e40 | 1398 | } |
bffc56d4 | 1399 | free_list(&fail_head); |
32180e40 YL |
1400 | |
1401 | goto again; | |
3f579c34 YL |
1402 | |
1403 | enable_all: | |
1404 | retval = pci_reenable_device(bridge); | |
1405 | pci_set_master(bridge); | |
1406 | pci_enable_bridges(parent); | |
6841ec68 YL |
1407 | } |
1408 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f YL |
1409 | |
1410 | #ifdef CONFIG_HOTPLUG | |
1411 | /** | |
1412 | * pci_rescan_bus - scan a PCI bus for devices. | |
1413 | * @bus: PCI bus to scan | |
1414 | * | |
1415 | * Scan a PCI bus and child buses for new devices, adds them, | |
1416 | * and enables them. | |
1417 | * | |
1418 | * Returns the max number of subordinate bus discovered. | |
1419 | */ | |
1420 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) | |
1421 | { | |
1422 | unsigned int max; | |
1423 | struct pci_dev *dev; | |
bdc4abec | 1424 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
1425 | want additional resources */ |
1426 | ||
1427 | max = pci_scan_child_bus(bus); | |
1428 | ||
9b03088f YL |
1429 | down_read(&pci_bus_sem); |
1430 | list_for_each_entry(dev, &bus->devices, bus_list) | |
1431 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1432 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1433 | if (dev->subordinate) | |
1434 | __pci_bus_size_bridges(dev->subordinate, | |
1435 | &add_list); | |
1436 | up_read(&pci_bus_sem); | |
1437 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 1438 | BUG_ON(!list_empty(&add_list)); |
9b03088f YL |
1439 | |
1440 | pci_enable_bridges(bus); | |
1441 | pci_bus_add_devices(bus); | |
1442 | ||
1443 | return max; | |
1444 | } | |
1445 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
1446 | #endif |